arch/arm/mach-s5pv310/mach-smdkv310.c

   1 /* linux/arch/arm/mach-s5pv310/mach-smdkv310.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/serial_core.h>
  13 #include <linux/delay.h>
  14 #include <linux/usb/ch9.h>
  15 #include <linux/i2c.h>
  16 #include <linux/gpio.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/smsc911x.h>
  20 #include <linux/io.h>
  21 #include <linux/clk.h>
  22 #include <linux/videodev2.h>
  23 #if defined(CONFIG_S5P_MEM_CMA)
  24 #include <linux/cma.h>
  25 #endif
  26 #include <linux/regulator/machine.h>
  27 #include <linux/regulator/max8649.h>
  28 #include <linux/regulator/fixed.h>
  29
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach-types.h>
  32 #include <plat/regs-serial.h>
  33 #include <plat/s5pv310.h>
  34 #include <plat/clock.h>
  35 #include <plat/cpu.h>
  36 #include <plat/fb.h>
  37 #include <plat/iic.h>
  38 #include <plat/devs.h>
  39 #include <plat/adc.h>
  40 #include <plat/ts.h>
  41 #include <plat/fimg2d.h>
  42 #include <plat/sdhci.h>
  43 #include <plat/mshci.h>
  44 #include <plat/regs-otg.h>
  45 #include <plat/pm.h>
  46 #include <plat/tvout.h>
  47
  48 #include <plat/csis.h>
  49 #include <plat/fimc.h>
  50 #include <plat/fimc-core.h>
  51 #include <plat/gpio-cfg.h>
  52 #include <plat/media.h>
  53
  54 #include <plat/s3c64xx-spi.h>
  55 #include <plat/gpio-cfg.h>
  56 #include <plat/pd.h>
  57
  58 #include <media/s5k3ba_platform.h>
  59 #include <media/s5k4ba_platform.h>
  60 #include <media/s5k4ea_platform.h>
  61 #include <media/s5k6aa_platform.h>
  62
  63 #include <mach/regs-gpio.h>
  64 #include <mach/regs-srom.h>
  65
  66 #include <mach/map.h>
  67 #include <mach/regs-mem.h>
  68 #include <mach/regs-clock.h>
  69 #include <mach/media.h>
  70 #include <mach/gpio.h>
  71
  72 #include <mach/spi-clocks.h>
  73
  74 #if defined(CONFIG_SND_SOC_WM8994) || defined(CONFIG_SND_SOC_WM8994_MODULE)
  75 #include <linux/mfd/wm8994/pdata.h>
  76 #endif
  77
  78 #if defined(CONFIG_S5P_THERMAL)
  79 #include <plat/s5p-tmu.h>
  80 #include <mach/regs-tmu.h>
  81 #endif
  82
  83 /* Following are default values for UCON, ULCON and UFCON UART registers */
  84 #define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
  85                                  S3C2410_UCON_RXILEVEL |        \
  86                                  S3C2410_UCON_TXIRQMODE |       \
  87                                  S3C2410_UCON_RXIRQMODE |       \
  88                                  S3C2410_UCON_RXFIFO_TOI |      \
  89                                  S3C2443_UCON_RXERR_IRQEN)
  90
  91 #define SMDKV310_ULCON_DEFAULT  S3C2410_LCON_CS8
  92
  93 #define SMDKV310_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
  94                                  S5PV210_UFCON_TXTRIG4 |        \
  95                                  S5PV210_UFCON_RXTRIG4)
  96
  97 static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
  98         [0] = {
  99                 .hwport         = 0,
 100                 .flags          = 0,
 101                 .ucon           = SMDKV310_UCON_DEFAULT,
 102                 .ulcon          = SMDKV310_ULCON_DEFAULT,
 103                 .ufcon          = SMDKV310_UFCON_DEFAULT,
 104         },
 105         [1] = {
 106                 .hwport         = 1,
 107                 .flags          = 0,
 108                 .ucon           = SMDKV310_UCON_DEFAULT,
 109                 .ulcon          = SMDKV310_ULCON_DEFAULT,
 110                 .ufcon          = SMDKV310_UFCON_DEFAULT,
 111         },
 112         [2] = {
 113                 .hwport         = 2,
 114                 .flags          = 0,
 115                 .ucon           = SMDKV310_UCON_DEFAULT,
 116                 .ulcon          = SMDKV310_ULCON_DEFAULT,
 117                 .ufcon          = SMDKV310_UFCON_DEFAULT,
 118         },
 119         [3] = {
 120                 .hwport         = 3,
 121                 .flags          = 0,
 122                 .ucon           = SMDKV310_UCON_DEFAULT,
 123                 .ulcon          = SMDKV310_ULCON_DEFAULT,
 124                 .ufcon          = SMDKV310_UFCON_DEFAULT,
 125         },
 126         [4] = {
 127                 .hwport         = 4,
 128                 .flags          = 0,
 129                 .ucon           = SMDKV310_UCON_DEFAULT,
 130                 .ulcon          = SMDKV310_ULCON_DEFAULT,
 131                 .ufcon          = SMDKV310_UFCON_DEFAULT,
 132         },
 133 };
 134
 135 //#undef WRITEBACK_ENABLED
 136 #define WRITEBACK_ENABLED
 137
 138 #ifdef CONFIG_VIDEO_FIMC
 139 /*
 140  * External camera reset
 141  * Because the most of cameras take i2c bus signal, so that
 142  * you have to reset at the boot time for other i2c slave devices.
 143  * This function also called at fimc_init_camera()
 144  * Do optimization for cameras on your platform.
 145 */
 146 #ifdef CONFIG_ITU_A
 147 static int smdkv310_cam0_reset(int dummy)
 148 {
 149         int err;
 150         /* Camera A */
 151         err = gpio_request(S5PV310_GPX1(2), "GPX1");
 152         if (err)
 153                 printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
 154
 155         s3c_gpio_setpull(S5PV310_GPX1(2), S3C_GPIO_PULL_NONE);
 156         gpio_direction_output(S5PV310_GPX1(2), 0);
 157         gpio_direction_output(S5PV310_GPX1(2), 1);
 158         gpio_free(S5PV310_GPX1(2));
 159
 160         return 0;
 161 }
 162 #endif
 163 #ifdef CONFIG_ITU_B
 164 static int smdkv310_cam1_reset(int dummy)
 165 {
 166         int err;
 167
 168         /* Camera B */
 169         err = gpio_request(S5PV310_GPX1(0), "GPX1");
 170         if (err)
 171                 printk(KERN_ERR "#### failed to request GPX1_0 ####\n");
 172
 173         s3c_gpio_setpull(S5PV310_GPX1(0), S3C_GPIO_PULL_NONE);
 174         gpio_direction_output(S5PV310_GPX1(0), 0);
 175         gpio_direction_output(S5PV310_GPX1(0), 1);
 176         gpio_free(S5PV310_GPX1(0));
 177
 178         return 0;
 179 }
 180 #endif
 181 /* for 12M camera */
 182 #ifdef CE143_MONACO
 183 static int smdkv310_cam0_standby(void)
 184 {
 185         int err;
 186         /* Camera A */
 187         err = gpio_request(S5PV310_GPX3(3), "GPX3");
 188         if (err)
 189                 printk(KERN_ERR "#### failed to request GPX3_3 ####\n");
 190         s3c_gpio_setpull(S5PV310_GPX3(3), S3C_GPIO_PULL_NONE);
 191         gpio_direction_output(S5PV310_GPX3(3), 0);
 192         gpio_direction_output(S5PV310_GPX3(3), 1);
 193         gpio_free(S5PV310_GPX3(3));
 194
 195         return 0;
 196 }
 197
 198 static int smdkv310_cam1_standby(void)
 199 {
 200         int err;
 201
 202         /* Camera B */
 203         err = gpio_request(S5PV310_GPX1(1), "GPX1");
 204         if (err)
 205                 printk(KERN_ERR "#### failed to request GPX1_1 ####\n");
 206         s3c_gpio_setpull(S5PV310_GPX1(1), S3C_GPIO_PULL_NONE);
 207         gpio_direction_output(S5PV310_GPX1(1), 0);
 208         gpio_direction_output(S5PV310_GPX1(1), 1);
 209         gpio_free(S5PV310_GPX1(1));
 210
 211         return 0;
 212 }
 213 #endif
 214
 215 /* Set for MIPI-CSI Camera module Reset */
 216 #ifdef CONFIG_CSI_C
 217 static int smdkv310_mipi_cam0_reset(int dummy)
 218 {
 219         int err;
 220
 221         err = gpio_request(S5PV310_GPX1(2), "GPX1");
 222         if (err)
 223                 printk(KERN_ERR "#### failed to reset(GPX1_2) MIPI CAM\n");
 224
 225         s3c_gpio_setpull(S5PV310_GPX1(2), S3C_GPIO_PULL_NONE);
 226         gpio_direction_output(S5PV310_GPX1(2), 0);
 227         gpio_direction_output(S5PV310_GPX1(2), 1);
 228         gpio_free(S5PV310_GPX1(2));
 229
 230         return 0;
 231 }
 232 #endif
 233 #ifdef CONFIG_CSI_D
 234 static int smdkv310_mipi_cam1_reset(int dummy)
 235 {
 236         int err;
 237
 238         err = gpio_request(S5PV310_GPX1(0), "GPX1");
 239         if (err)
 240                 printk(KERN_ERR "#### failed to reset(GPX1_0) MIPI CAM\n");
 241
 242         s3c_gpio_setpull(S5PV310_GPX1(0), S3C_GPIO_PULL_NONE);
 243         gpio_direction_output(S5PV310_GPX1(0), 0);
 244         gpio_direction_output(S5PV310_GPX1(0), 1);
 245         gpio_free(S5PV310_GPX1(0));
 246
 247         return 0;
 248 }
 249 #endif
 250
 251 #ifdef CONFIG_VIDEO_S5K3BA
 252 static struct s5k3ba_platform_data s5k3ba_plat = {
 253         .default_width = 640,
 254         .default_height = 480,
 255         .pixelformat = V4L2_PIX_FMT_VYUY,
 256         .freq = 24000000,
 257         .is_mipi = 0,
 258 };
 259
 260 static struct i2c_board_info  s5k3ba_i2c_info = {
 261         I2C_BOARD_INFO("S5K3BA", 0x2d),
 262         .platform_data = &s5k3ba_plat,
 263 };
 264
 265 static struct s3c_platform_camera s5k3ba = {
 266 #ifdef CONFIG_ITU_A
 267         .id             = CAMERA_PAR_A,
 268         .clk_name       = "sclk_cam0",
 269         .i2c_busnum     = 0,
 270         .cam_power      = smdkv310_cam0_reset,
 271 #endif
 272 #ifdef CONFIG_ITU_B
 273         .id             = CAMERA_PAR_B,
 274         .clk_name       = "sclk_cam1",
 275         .i2c_busnum     = 1,
 276         .cam_power      = smdkv310_cam1_reset,
 277 #endif
 278         .type           = CAM_TYPE_ITU,
 279         .fmt            = ITU_601_YCBCR422_8BIT,
 280         .order422       = CAM_ORDER422_8BIT_CRYCBY,
 281         .info           = &s5k3ba_i2c_info,
 282         .pixelformat    = V4L2_PIX_FMT_VYUY,
 283         .srclk_name     = "xusbxti",
 284         .clk_rate       = 24000000,
 285         .line_length    = 1920,
 286         .width          = 640,
 287         .height         = 480,
 288         .window         = {
 289                 .left   = 0,
 290                 .top    = 0,
 291                 .width  = 640,
 292                 .height = 480,
 293         },
 294
 295         /* Polarity */
 296         .inv_pclk       = 0,
 297         .inv_vsync      = 1,
 298         .inv_href       = 0,
 299         .inv_hsync      = 0,
 300
 301         .initialized    = 0,
 302 };
 303 #endif
 304
 305 #ifdef CONFIG_VIDEO_S5K4BA
 306 static struct s5k4ba_platform_data s5k4ba_plat = {
 307         .default_width = 800,
 308         .default_height = 600,
 309         .pixelformat = V4L2_PIX_FMT_UYVY,
 310         .freq = 24000000,
 311         .is_mipi = 0,
 312 };
 313
 314 static struct i2c_board_info  s5k4ba_i2c_info = {
 315         I2C_BOARD_INFO("S5K4BA", 0x2d),
 316         .platform_data = &s5k4ba_plat,
 317 };
 318
 319 static struct s3c_platform_camera s5k4ba = {
 320 #ifdef CONFIG_ITU_A
 321         .id             = CAMERA_PAR_A,
 322         .clk_name       = "sclk_cam0",
 323         .i2c_busnum     = 0,
 324         .cam_power      = smdkv310_cam0_reset,
 325 #endif
 326 #ifdef CONFIG_ITU_B
 327         .id             = CAMERA_PAR_B,
 328         .clk_name       = "sclk_cam1",
 329         .i2c_busnum     = 1,
 330         .cam_power      = smdkv310_cam1_reset,
 331 #endif
 332         .type           = CAM_TYPE_ITU,
 333         .fmt            = ITU_601_YCBCR422_8BIT,
 334         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 335         .info           = &s5k4ba_i2c_info,
 336         .pixelformat    = V4L2_PIX_FMT_UYVY,
 337         .srclk_name     = "xusbxti",
 338         .clk_rate       = 24000000,
 339         .line_length    = 1920,
 340         .width          = 1600,
 341         .height         = 1200,
 342         .window         = {
 343                 .left   = 0,
 344                 .top    = 0,
 345                 .width  = 800,
 346                 .height = 600,
 347         },
 348
 349         /* Polarity */
 350         .inv_pclk       = 0,
 351         .inv_vsync      = 1,
 352         .inv_href       = 0,
 353         .inv_hsync      = 0,
 354
 355         .initialized    = 0,
 356 };
 357 #endif
 358
 359 /* 2 MIPI Cameras */
 360 #ifdef CONFIG_VIDEO_S5K4EA
 361 static struct s5k4ea_platform_data s5k4ea_plat = {
 362         .default_width = 1920,
 363         .default_height = 1080,
 364         .pixelformat = V4L2_PIX_FMT_UYVY,
 365         .freq = 24000000,
 366         .is_mipi = 1,
 367 };
 368
 369 static struct i2c_board_info  s5k4ea_i2c_info = {
 370         I2C_BOARD_INFO("S5K4EA", 0x2d),
 371         .platform_data = &s5k4ea_plat,
 372 };
 373
 374 static struct s3c_platform_camera s5k4ea = {
 375 #ifdef CONFIG_CSI_C
 376         .id             = CAMERA_CSI_C,
 377         .clk_name       = "sclk_cam0",
 378         .i2c_busnum     = 0,
 379         .cam_power      = smdkv310_mipi_cam0_reset,
 380 #endif
 381 #ifdef CONFIG_CSI_D
 382         .id             = CAMERA_CSI_D,
 383         .clk_name       = "sclk_cam1",
 384         .i2c_busnum     = 1,
 385         .cam_power      = smdkv310_mipi_cam1_reset,
 386 #endif
 387         .type           = CAM_TYPE_MIPI,
 388         .fmt            = MIPI_CSI_YCBCR422_8BIT,
 389         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 390         .info           = &s5k4ea_i2c_info,
 391         .pixelformat    = V4L2_PIX_FMT_UYVY,
 392         .srclk_name     = "xusbxti",
 393         .clk_rate       = 24000000,
 394         .line_length    = 1920,
 395         .width          = 1920,
 396         .height         = 1080,
 397         .window         = {
 398                 .left   = 0,
 399                 .top    = 0,
 400                 .width  = 1920,
 401                 .height = 1080,
 402         },
 403
 404         .mipi_lanes     = 2,
 405         .mipi_settle    = 12,
 406         .mipi_align     = 32,
 407
 408         /* Polarity */
 409         .inv_pclk       = 0,
 410         .inv_vsync      = 1,
 411         .inv_href       = 0,
 412         .inv_hsync      = 0,
 413
 414         .initialized    = 0,
 415 };
 416 #endif
 417
 418 #ifdef CONFIG_VIDEO_S5K6AA
 419 static struct s5k6aa_platform_data s5k6aa_plat = {
 420         .default_width = 640,
 421         .default_height = 480,
 422         .pixelformat = V4L2_PIX_FMT_UYVY,
 423         .freq = 24000000,
 424         .is_mipi = 1,
 425 };
 426
 427 static struct i2c_board_info  s5k6aa_i2c_info = {
 428         I2C_BOARD_INFO("S5K6AA", 0x3c),
 429         .platform_data = &s5k6aa_plat,
 430 };
 431
 432 static struct s3c_platform_camera s5k6aa = {
 433 #ifdef CONFIG_CSI_C
 434         .id             = CAMERA_CSI_C,
 435         .clk_name       = "sclk_cam0",
 436         .i2c_busnum     = 0,
 437         .cam_power      = smdkv310_mipi_cam0_reset,
 438 #endif
 439 #ifdef CONFIG_CSI_D
 440         .id             = CAMERA_CSI_D,
 441         .clk_name       = "sclk_cam1",
 442         .i2c_busnum     = 1,
 443         .cam_power      = smdkv310_mipi_cam1_reset,
 444 #endif
 445         .type           = CAM_TYPE_MIPI,
 446         .fmt            = MIPI_CSI_YCBCR422_8BIT,
 447         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 448         .info           = &s5k6aa_i2c_info,
 449         .pixelformat    = V4L2_PIX_FMT_UYVY,
 450         .srclk_name     = "xusbxti",
 451         .clk_rate       = 24000000,
 452         .line_length    = 1920,
 453         /* default resol for preview kind of thing */
 454         .width          = 640,
 455         .height         = 480,
 456         .window         = {
 457                 .left   = 0,
 458                 .top    = 0,
 459                 .width  = 640,
 460                 .height = 480,
 461         },
 462
 463         .mipi_lanes     = 1,
 464         .mipi_settle    = 6,
 465         .mipi_align     = 32,
 466
 467         /* Polarity */
 468         .inv_pclk       = 0,
 469         .inv_vsync      = 1,
 470         .inv_href       = 0,
 471         .inv_hsync      = 0,
 472
 473         .initialized    = 0,
 474 };
 475 #endif
 476
 477 #ifdef WRITEBACK_ENABLED
 478 static struct i2c_board_info  writeback_i2c_info = {
 479         I2C_BOARD_INFO("WriteBack", 0x0),
 480 };
 481
 482 static struct s3c_platform_camera writeback = {
 483         .id             = CAMERA_WB,
 484         .fmt            = ITU_601_YCBCR422_8BIT,
 485         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 486         .i2c_busnum     = 0,
 487         .info           = &writeback_i2c_info,
 488         .pixelformat    = V4L2_PIX_FMT_YUV444,
 489         .line_length    = 800,
 490         .width          = 480,
 491         .height         = 800,
 492         .window         = {
 493                 .left   = 0,
 494                 .top    = 0,
 495                 .width  = 480,
 496                 .height = 800,
 497         },
 498
 499         .initialized    = 0,
 500 };
 501 #endif
 502
 503 /* Interface setting */
 504 static struct s3c_platform_fimc fimc_plat = {
 505 #ifdef CONFIG_ITU_A
 506         .default_cam    = CAMERA_PAR_A,
 507 #endif
 508 #ifdef CONFIG_ITU_B
 509         .default_cam    = CAMERA_PAR_B,
 510 #endif
 511 #ifdef CONFIG_CSI_C
 512         .default_cam    = CAMERA_CSI_C,
 513 #endif
 514 #ifdef CONFIG_CSI_D
 515         .default_cam    = CAMERA_CSI_D,
 516 #endif
 517 #ifdef WRITEBACK_ENABLED
 518         .default_cam    = CAMERA_WB,
 519 #endif
 520         .camera         = {
 521 #ifdef CONFIG_VIDEO_S5K3BA
 522                 &s5k3ba,
 523 #endif
 524 #ifdef CONFIG_VIDEO_S5K4BA
 525                 &s5k4ba,
 526 #endif
 527 #ifdef CONFIG_VIDEO_S5K4EA
 528                 &s5k4ea,
 529 #endif
 530 #ifdef CONFIG_VIDEO_S5K6AA
 531                 &s5k6aa,
 532 #endif
 533 #ifdef WRITEBACK_ENABLED
 534                 &writeback,
 535 #endif
 536         },
 537 #ifdef CONFIG_CPU_S5PV310_EVT1
 538         .hw_ver         = 0x52,
 539 #else
 540         .hw_ver         = 0x51,
 541 #endif
 542 };
 543 #endif
 544
 545 static struct resource smdkv310_smsc911x_resources[] = {
 546         [0] = {
 547                 .start = S5PV310_PA_SROM1,
 548                 .end   = S5PV310_PA_SROM1 + SZ_64K - 1,
 549                 .flags = IORESOURCE_MEM,
 550         },
 551         [1] = {
 552                 .start = IRQ_EINT(5),
 553                 .end   = IRQ_EINT(5),
 554                 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
 555         },
 556 };
 557
 558 static struct smsc911x_platform_config smsc9215 = {
 559         .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 560         .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
 561         .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
 562         .phy_interface = PHY_INTERFACE_MODE_MII,
 563         .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
 564 };
 565
 566 static struct platform_device smdkv310_smsc911x = {
 567         .name          = "smsc911x",
 568         .id            = -1,
 569         .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
 570         .resource      = smdkv310_smsc911x_resources,
 571         .dev = {
 572                 .platform_data = &smsc9215,
 573         },
 574 };
 575
 576 #ifdef CONFIG_DRM_MALI
 577 static struct platform_device s5p_device_mali_drm = {
 578         .name = "mali_drm",
 579         .id   = -1,
 580 };
 581 #endif
 582
 583
 584 static struct regulator_consumer_supply max8952_supply[] = {
 585         REGULATOR_SUPPLY("vdd_arm", NULL),
 586 };
 587
 588 static struct regulator_consumer_supply max8649_supply[] = {
 589         REGULATOR_SUPPLY("vdd_int", NULL),
 590 };
 591
 592 static struct regulator_consumer_supply max8649a_supply[] = {
 593         REGULATOR_SUPPLY("vdd_g3d", NULL),
 594 };
 595
 596 static struct regulator_init_data max8952_init_data = {
 597         .constraints    = {
 598                 .name           = "vdd_arm range",
 599                 .min_uV         = 770000,
 600                 .max_uV         = 1400000,
 601                 .always_on      = 1,
 602                 .boot_on        = 1,
 603                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
 604                 .state_mem      = {
 605                         .uV             = 1200000,
 606                         .disabled       = 1,
 607                 },
 608         },
 609         .num_consumer_supplies  = 1,
 610         .consumer_supplies      = &max8952_supply[0],
 611 };
 612
 613 static struct regulator_init_data max8649_init_data = {
 614         .constraints    = {
 615                 .name           = "vdd_int range",
 616                 .min_uV         = 750000,
 617                 .max_uV         = 1380000,
 618                 .always_on      = 1,
 619                 .boot_on        = 1,
 620                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
 621                 .state_mem      = {
 622                         .uV             = 1100000,
 623                         .disabled       = 1,
 624                 },
 625         },
 626         .num_consumer_supplies  = 1,
 627         .consumer_supplies      = &max8649_supply[0],
 628 };
 629
 630 static struct regulator_init_data max8649a_init_data = {
 631         .constraints    = {
 632                 .name           = "vdd_g3d range",
 633                 .min_uV         = 750000,
 634                 .max_uV         = 1380000,
 635                 .always_on      = 0,
 636                 .boot_on        = 0,
 637                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
 638                 .state_mem      = {
 639                         .uV             = 1200000,
 640                         .disabled       = 1,
 641                 },
 642         },
 643         .num_consumer_supplies  = 1,
 644         .consumer_supplies      = &max8649a_supply[0],
 645 };
 646
 647 static struct max8649_platform_data s5pv310_max8952_info = {
 648         .mode           = 3,    /* VID1 = 1, VID0 = 1 */
 649         .extclk         = 0,
 650         .ramp_timing    = MAX8649_RAMP_32MV,
 651         .regulator      = &max8952_init_data,
 652 };
 653
 654 static struct max8649_platform_data s5pv310_max8649_info = {
 655         .mode           = 2,    /* VID1 = 1, VID0 = 0 */
 656         .extclk         = 0,
 657         .ramp_timing    = MAX8649_RAMP_32MV,
 658         .regulator      = &max8649_init_data,
 659 };
 660
 661 static struct max8649_platform_data s5pv310_max8649a_info = {
 662         .mode           = 2,    /* VID1 = 1, VID0 = 0 */
 663         .extclk         = 0,
 664         .ramp_timing    = MAX8649_RAMP_32MV,
 665         .regulator      = &max8649a_init_data,
 666 };
 667
 668 #if defined(CONFIG_SND_SOC_WM8994) || defined(CONFIG_SND_SOC_WM8994_MODULE)
 669
 670 #ifdef CONFIG_REGULATOR_WM8994
 671 static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
 672         {
 673                 .dev_name       = "1-001a",
 674                 .supply         = "AVDD2",
 675         }, {
 676                 .dev_name       = "1-001a",
 677                 .supply         = "CPVDD",
 678         },
 679 };
 680
 681 static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
 682         {
 683                 .dev_name       = "1-001a",
 684                 .supply         = "SPKVDD1",
 685         }, {
 686                 .dev_name       = "1-001a",
 687                 .supply         = "SPKVDD2",
 688         },
 689 };
 690
 691 static struct regulator_consumer_supply wm8994_fixed_voltage2_supplies[] = {
 692         {
 693                 .dev_name       = "1-001a",
 694                 .supply         = "DBVDD",
 695         },
 696 };
 697
 698 static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
 699         .constraints = {
 700                 .always_on = 1,
 701         },
 702         .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
 703         .consumer_supplies      = wm8994_fixed_voltage0_supplies,
 704 };
 705
 706 static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
 707         .constraints = {
 708                 .always_on = 1,
 709         },
 710         .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
 711         .consumer_supplies      = wm8994_fixed_voltage1_supplies,
 712 };
 713
 714 static struct regulator_init_data wm8994_fixed_voltage2_init_data = {
 715         .constraints = {
 716                 .always_on = 1,
 717         },
 718         .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage2_supplies),
 719         .consumer_supplies      = wm8994_fixed_voltage2_supplies,
 720 };
 721
 722 static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
 723         .supply_name    = "VDD_1.8V",
 724         .microvolts     = 1800000,
 725         .gpio           = -EINVAL,
 726         .init_data      = &wm8994_fixed_voltage0_init_data,
 727 };
 728
 729 static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
 730         .supply_name    = "DC_5V",
 731         .microvolts     = 5000000,
 732         .gpio           = -EINVAL,
 733         .init_data      = &wm8994_fixed_voltage1_init_data,
 734 };
 735
 736 static struct fixed_voltage_config wm8994_fixed_voltage2_config = {
 737         .supply_name    = "VDD_3.3V",
 738         .microvolts     = 3300000,
 739         .gpio           = -EINVAL,
 740         .init_data      = &wm8994_fixed_voltage2_init_data,
 741 };
 742
 743 static struct platform_device wm8994_fixed_voltage0 = {
 744         .name           = "reg-fixed-voltage",
 745         .id             = 0,
 746         .dev            = {
 747                 .platform_data  = &wm8994_fixed_voltage0_config,
 748         },
 749 };
 750
 751 static struct platform_device wm8994_fixed_voltage1 = {
 752         .name           = "reg-fixed-voltage",
 753         .id             = 1,
 754         .dev            = {
 755                 .platform_data  = &wm8994_fixed_voltage1_config,
 756         },
 757 };
 758
 759 static struct platform_device wm8994_fixed_voltage2 = {
 760         .name           = "reg-fixed-voltage",
 761         .id             = 2,
 762         .dev            = {
 763                 .platform_data  = &wm8994_fixed_voltage2_config,
 764         },
 765 };
 766
 767 static struct regulator_consumer_supply wm8994_avdd1_supply = {
 768         .dev_name       = "1-001a",
 769         .supply         = "AVDD1",
 770 };
 771
 772 static struct regulator_consumer_supply wm8994_dcvdd_supply = {
 773         .dev_name       = "1-001a",
 774         .supply         = "DCVDD",
 775 };
 776
 777 static struct regulator_init_data wm8994_ldo1_data = {
 778         .constraints    = {
 779                 .name           = "AVDD1",
 780         },
 781         .num_consumer_supplies  = 1,
 782         .consumer_supplies      = &wm8994_avdd1_supply,
 783 };
 784
 785 static struct regulator_init_data wm8994_ldo2_data = {
 786         .constraints    = {
 787                 .name           = "DCVDD",
 788         },
 789         .num_consumer_supplies  = 1,
 790         .consumer_supplies      = &wm8994_dcvdd_supply,
 791 };
 792 #endif
 793
 794 static struct wm8994_pdata wm8994_platform_data = {
 795         /* configure gpio1 function: 0x0001(Logic level input/output) */
 796         .gpio_defaults[0] = 0x0001,
 797         /* configure gpio3/4/5/7 function for AIF2 voice */
 798         .gpio_defaults[2] = 0x8100,/*BCLK2 in*/
 799         .gpio_defaults[3] = 0x8100,/*LRCLK2 in*/
 800         .gpio_defaults[4] = 0x8100,/*DACDAT2 in*/
 801         /* configure gpio6 function: 0x0001(Logic level input/output) */
 802         .gpio_defaults[5] = 0x0001,
 803         .gpio_defaults[6] = 0x0100,/*ADCDAT2 out*/
 804 #ifdef CONFIG_REGULATOR_WM8994
 805         .ldo[0] = { 0, NULL, &wm8994_ldo1_data },
 806         .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
 807 #endif
 808 };
 809 #endif
 810
 811 #ifdef CONFIG_I2C_S3C2410
 812 /* I2C0 */
 813 static struct i2c_board_info i2c_devs0[] __initdata = {
 814         { I2C_BOARD_INFO("24c128", 0x50), },     /* Samsung S524AD0XD1 */
 815         { I2C_BOARD_INFO("24c128", 0x52), },     /* Samsung S524AD0XD1 */
 816         {
 817                 I2C_BOARD_INFO("max8952", 0x60),
 818                 .platform_data  = &s5pv310_max8952_info,
 819         }, {
 820                 I2C_BOARD_INFO("max8649", 0x62),
 821                 .platform_data  = &s5pv310_max8649a_info,
 822         },
 823 };
 824 #ifdef CONFIG_S3C_DEV_I2C1
 825 /* I2C1 */
 826 static struct i2c_board_info i2c_devs1[] __initdata = {
 827 #if defined(CONFIG_SND_SOC_WM8994) || defined(CONFIG_SND_SOC_WM8994_MODULE)
 828         {
 829                 I2C_BOARD_INFO("wm8994", 0x1a),
 830                 .platform_data  = &wm8994_platform_data,
 831         },
 832 #endif
 833
 834 #ifdef CONFIG_VIDEO_TVOUT
 835         {
 836                 I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)),
 837         },
 838 #endif
 839         {
 840                 I2C_BOARD_INFO("max8649", 0x60),
 841                 .platform_data  = &s5pv310_max8649_info,
 842         },
 843 };
 844 #endif
 845 #ifdef CONFIG_S3C_DEV_I2C2
 846 /* I2C2 */
 847 static struct i2c_board_info i2c_devs2[] __initdata = {
 848 };
 849 #endif
 850 #ifdef CONFIG_S3C_DEV_I2C3
 851 /* I2C3 */
 852 static struct i2c_board_info i2c_devs3[] __initdata = {
 853 };
 854 #endif
 855 #ifdef CONFIG_S3C_DEV_I2C4
 856 /* I2C4 */
 857 static struct i2c_board_info i2c_devs4[] __initdata = {
 858 };
 859 #endif
 860 #ifdef CONFIG_S3C_DEV_I2C5
 861 /* I2C5 */
 862 static struct i2c_board_info i2c_devs5[] __initdata = {
 863 };
 864 #endif
 865 #ifdef CONFIG_S3C_DEV_I2C6
 866 /* I2C6 */
 867 static struct i2c_board_info i2c_devs6[] __initdata = {
 868 };
 869 #endif
 870 #ifdef CONFIG_S3C_DEV_I2C7
 871 /* I2C7 */
 872 static struct i2c_board_info i2c_devs7[] __initdata = {
 873 };
 874 #endif
 875 #endif
 876
 877 #ifdef CONFIG_S3C_DEV_HSMMC
 878 static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
 879         .cd_type                = S3C_SDHCI_CD_INTERNAL,
 880 #if defined(CONFIG_S5PV310_SD_CH0_8BIT)
 881         .max_width              = 8,
 882         .host_caps              = MMC_CAP_8_BIT_DATA,
 883 #endif
 884 };
 885 #endif
 886 #ifdef CONFIG_S3C_DEV_HSMMC1
 887 static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
 888         .cd_type                = S3C_SDHCI_CD_INTERNAL,
 889 };
 890 #endif
 891 #ifdef CONFIG_S3C_DEV_HSMMC2
 892 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
 893         .cd_type                = S3C_SDHCI_CD_INTERNAL,
 894 #if defined(CONFIG_S5PV310_SD_CH2_8BIT)
 895         .max_width              = 8,
 896         .host_caps              = MMC_CAP_8_BIT_DATA,
 897 #endif
 898 };
 899 #endif
 900 #ifdef CONFIG_S3C_DEV_HSMMC3
 901 static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
 902         .cd_type                = S3C_SDHCI_CD_INTERNAL,
 903 };
 904 #endif
 905 #ifdef CONFIG_S5P_DEV_MSHC
 906 static struct s3c_mshci_platdata smdkv310_mshc_pdata __initdata = {
 907         .cd_type                = S3C_MSHCI_CD_INTERNAL,
 908         .has_wp_gpio            = true,
 909         .wp_gpio                = 0xffffffff,
 910 #if defined(CONFIG_S5PV310_MSHC_CH0_8BIT) && \
 911         defined(CONFIG_S5PV310_MSHC_CH0_DDR)
 912         .max_width              = 8,
 913         .host_caps              = MMC_CAP_8_BIT_DATA | MMC_CAP_DDR,
 914 #elif defined(CONFIG_S5PV310_MSHC_CH0_8BIT)
 915         .max_width              = 8,
 916         .host_caps              = MMC_CAP_8_BIT_DATA,
 917 #elif defined(CONFIG_S5PV310_MSHC_CH0_DDR)
 918         .host_caps              = MMC_CAP_DDR,
 919 #endif
 920 };
 921 #endif
 922
 923 #ifdef CONFIG_VIDEO_FIMG2D
 924 static struct fimg2d_platdata fimg2d_data __initdata = {
 925         .hw_ver = 30,
 926         .parent_clkname = "mout_mpll",
 927         .clkname = "sclk_fimg2d",
 928         .gate_clkname = "fimg2d",
 929         .clkrate = 250 * 1000000,
 930 };
 931 #endif
 932
 933 #if defined(CONFIG_S3C64XX_DEV_SPI)
 934 static struct s3c64xx_spi_csinfo spi0_csi[] = {
 935         [0] = {
 936                 .line = S5PV310_GPB(1),
 937                 .set_level = gpio_set_value,
 938         },
 939 };
 940
 941 static struct spi_board_info spi0_board_info[] __initdata = {
 942         {
 943                 .modalias = "spidev",
 944                 .platform_data = NULL,
 945                 .max_speed_hz = 10*1000*1000,
 946                 .bus_num = 0,
 947                 .chip_select = 0,
 948                 .mode = SPI_MODE_0,
 949                 .controller_data = &spi0_csi[0],
 950         }
 951 };
 952 #endif
 953
 954 #ifdef CONFIG_FB_S3C_AMS369FG06
 955
 956 static struct s3c_platform_fb ams369fg06_data __initdata = {
 957         .hw_ver = 0x70,
 958         .clk_name = "sclk_lcd",
 959         .nr_wins = 5,
 960         .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW,
 961         .swap = FB_SWAP_HWORD | FB_SWAP_WORD,
 962 };
 963
 964 #define         LCD_BUS_NUM     1
 965 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 966         [0] = {
 967                 .line = S5PV310_GPB(5),
 968                 .set_level = gpio_set_value,
 969         },
 970 };
 971
 972 static struct spi_board_info spi_board_info[] __initdata = {
 973         {
 974                 .modalias       = "ams369fg06",
 975                 .platform_data  = NULL,
 976                 .max_speed_hz   = 1200000,
 977                 .bus_num        = LCD_BUS_NUM,
 978                 .chip_select    = 0,
 979                 .mode           = SPI_MODE_3,
 980                 .controller_data = &spi1_csi[0],
 981         }
 982 };
 983
 984 #elif defined(CONFIG_S3C64XX_DEV_SPI)
 985 static struct s3c64xx_spi_csinfo spi1_csi[] = {
 986         [0] = {
 987                 .line = S5PV310_GPB(5),
 988                 .set_level = gpio_set_value,
 989         },
 990 };
 991
 992 static struct spi_board_info spi1_board_info[] __initdata = {
 993         {
 994                 .modalias = "spidev",
 995                 .platform_data = NULL,
 996                 .max_speed_hz = 1200000,
 997                 .bus_num = 1,
 998                 .chip_select = 0,
 999                 .mode = SPI_MODE_0,
1000                 .controller_data = &spi1_csi[0],
1001         }
1002 };
1003
1004 static struct s3c64xx_spi_csinfo spi2_csi[] = {
1005         [0] = {
1006                 .line = S5PV310_GPC1(2),
1007                 .set_level = gpio_set_value,
1008         },
1009 };
1010
1011 static struct spi_board_info spi2_board_info[] __initdata = {
1012         {
1013                 .modalias = "spidev",
1014                 .platform_data = NULL,
1015                 .max_speed_hz = 10*1000*1000,
1016                 .bus_num = 2,
1017                 .chip_select = 0,
1018                 .mode = SPI_MODE_0,
1019                 .controller_data = &spi2_csi[0],
1020         }
1021 };
1022 #endif
1023
1024 static struct platform_device *smdkc210_devices[] __initdata = {
1025 #ifdef CONFIG_S5PV310_DEV_PD
1026         &s5pv310_device_pd[PD_MFC],
1027         &s5pv310_device_pd[PD_G3D],
1028         &s5pv310_device_pd[PD_LCD0],
1029         &s5pv310_device_pd[PD_LCD1],
1030         &s5pv310_device_pd[PD_CAM],
1031         &s5pv310_device_pd[PD_TV],
1032         &s5pv310_device_pd[PD_GPS],
1033 #endif
1034
1035         &smdkv310_smsc911x,
1036 #ifdef CONFIG_DRM_MALI
1037         &s5p_device_mali_drm,
1038 #endif
1039 #ifdef CONFIG_FB_S3C
1040         &s3c_device_fb,
1041 #endif
1042 #ifdef CONFIG_I2C_S3C2410
1043         &s3c_device_i2c0,
1044 #ifdef CONFIG_S3C_DEV_I2C1
1045         &s3c_device_i2c1,
1046 #endif
1047 #ifdef CONFIG_S3C_DEV_I2C2
1048         &s3c_device_i2c2,
1049 #endif
1050 #ifdef CONFIG_S3C_DEV_I2C3
1051         &s3c_device_i2c3,
1052 #endif
1053 #ifdef CONFIG_S3C_DEV_I2C4
1054         &s3c_device_i2c4,
1055 #endif
1056 #ifdef CONFIG_S3C_DEV_I2C5
1057         &s3c_device_i2c5,
1058 #endif
1059 #ifdef CONFIG_S3C_DEV_I2C6
1060         &s3c_device_i2c6,
1061 #endif
1062 #ifdef CONFIG_S3C_DEV_I2C7
1063         &s3c_device_i2c7,
1064 #endif
1065 #endif
1066 #ifdef CONFIG_SND_S3C64XX_SOC_I2S_V4
1067         &s5pv310_device_iis0,
1068 #endif
1069 #ifdef CONFIG_SND_S3C_SOC_PCM
1070         &s5pv310_device_pcm0,
1071 #endif
1072 #if defined(CONFIG_SND_SOC_SMDK_WM9713)
1073         &s5pv310_device_ac97,
1074 #endif
1075 #ifdef CONFIG_SND_SAMSUNG_SOC_SPDIF
1076         &s5pv310_device_spdif,
1077 #endif
1078
1079 #ifdef CONFIG_MTD_ONENAND
1080         &s5p_device_onenand,
1081 #endif
1082
1083 #ifdef CONFIG_S3C_DEV_HSMMC
1084         &s3c_device_hsmmc0,
1085 #endif
1086 #ifdef CONFIG_S3C_DEV_HSMMC1
1087         &s3c_device_hsmmc1,
1088 #endif
1089 #ifdef CONFIG_S3C_DEV_HSMMC2
1090         &s3c_device_hsmmc2,
1091 #endif
1092 #ifdef CONFIG_S3C_DEV_HSMMC3
1093         &s3c_device_hsmmc3,
1094 #endif
1095 #ifdef CONFIG_S5P_DEV_MSHC
1096         &s3c_device_mshc,
1097 #endif
1098 #ifdef CONFIG_TOUCHSCREEN_S3C2410
1099 #ifdef CONFIG_S3C_DEV_ADC
1100         &s3c_device_ts,
1101 #endif
1102 #ifdef CONFIG_S3C_DEV_ADC1
1103         &s3c_device_ts1,
1104 #endif
1105 #endif
1106
1107 #ifdef CONFIG_S3C_ADC
1108         &s3c_device_adc,
1109 #endif
1110
1111 #ifdef CONFIG_VIDEO_TVOUT
1112         &s5p_device_tvout,
1113         &s5p_device_cec,
1114         &s5p_device_hpd,
1115 #endif
1116
1117 #ifdef CONFIG_S3C2410_WATCHDOG
1118         &s3c_device_wdt,
1119 #endif
1120
1121 #ifdef CONFIG_USB
1122         &s3c_device_usb_ehci,
1123         &s3c_device_usb_ohci,
1124 #endif
1125
1126 #ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
1127         &s5p_device_fimc0,
1128         &s5p_device_fimc1,
1129         &s5p_device_fimc2,
1130         &s5p_device_fimc3,
1131 #endif
1132
1133 #ifdef CONFIG_VIDEO_FIMC
1134         &s3c_device_fimc0,
1135         &s3c_device_fimc1,
1136         &s3c_device_fimc2,
1137         &s3c_device_fimc3,
1138 #ifdef CONFIG_VIDEO_FIMC_MIPI
1139         &s3c_device_csis0,
1140         &s3c_device_csis1,
1141 #endif
1142 #endif
1143 #ifdef CONFIG_VIDEO_JPEG
1144         &s5p_device_jpeg,
1145 #endif
1146 #ifdef CONFIG_VIDEO_MFC5X
1147         &s5p_device_mfc,
1148 #endif
1149
1150 #ifdef CONFIG_VIDEO_FIMG2D
1151         &s5p_device_fimg2d,
1152 #endif
1153
1154 #ifdef CONFIG_USB_GADGET
1155         &s3c_device_usbgadget,
1156 #endif
1157
1158 #if defined(CONFIG_S3C64XX_DEV_SPI)
1159         &s5pv310_device_spi0,
1160 #endif
1161 #ifdef CONFIG_FB_S3C_AMS369FG06
1162         &s5pv310_device_spi1,
1163 #elif defined(CONFIG_S3C64XX_DEV_SPI)
1164         &s5pv310_device_spi1,
1165         &s5pv310_device_spi2,
1166 #endif
1167
1168 #ifdef CONFIG_S5P_SYSMMU
1169         &s5p_device_sysmmu,
1170 #endif
1171
1172 #ifdef CONFIG_S3C_DEV_GIB
1173         &s3c_device_gib,
1174 #endif
1175
1176 #ifdef CONFIG_S3C_DEV_RTC
1177         &s3c_device_rtc,
1178 #endif
1179
1180 #if (defined(CONFIG_SND_SOC_WM8994) || \
1181                 defined(CONFIG_SND_SOC_WM8994_MODULE)) && \
1182                 defined(CONFIG_REGULATOR_WM8994)
1183         &wm8994_fixed_voltage0,
1184         &wm8994_fixed_voltage1,
1185         &wm8994_fixed_voltage2,
1186 #endif
1187
1188 #ifdef CONFIG_SATA_AHCI_PLATFORM
1189         &s5pv310_device_sata,
1190 #endif
1191
1192 #ifdef CONFIG_S5P_THERMAL
1193         &s5p_device_tmu,
1194 #endif
1195 };
1196
1197 #if defined(CONFIG_VIDEO_TVOUT)
1198 static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
1199
1200 };
1201 static struct s5p_platform_cec hdmi_cec_data __initdata = {
1202
1203 };
1204 #endif
1205
1206 static void __init smdkv310_smsc911x_init(void)
1207 {
1208         u32 cs1;
1209
1210         /* configure nCS1 width to 16 bits */
1211         cs1 = __raw_readl(S5PV310_SROM_BW) &
1212                     ~(S5PV310_SROM_BW__CS_MASK <<
1213                                     S5PV310_SROM_BW__NCS1__SHIFT);
1214         cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
1215                 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
1216                 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
1217                 S5PV310_SROM_BW__NCS1__SHIFT;
1218         __raw_writel(cs1, S5PV310_SROM_BW);
1219
1220         /* set timing for nCS1 suitable for ethernet chip */
1221         __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
1222                      (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
1223                      (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
1224                      (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
1225                      (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
1226                      (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
1227                      (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
1228 }
1229
1230 int __init s5pv310_fimc_setup_clks(void)
1231 {
1232         int err = 0;
1233         int i;
1234         struct clk *clk_fimc, *parent;
1235
1236         struct device *fimc_devs[] = {
1237                 &s5p_device_fimc0.dev,
1238                 &s5p_device_fimc1.dev,
1239                 &s5p_device_fimc2.dev,
1240                 &s5p_device_fimc3.dev
1241         };
1242
1243         parent = clk_get(NULL, "mout_epll");
1244         if (IS_ERR(parent))
1245                 return PTR_ERR(parent);
1246
1247         for (i = 0; err == 0 && i < ARRAY_SIZE(fimc_devs); i++) {
1248                 if (fimc_devs[i]) {
1249                         clk_fimc = clk_get(fimc_devs[i], "sclk_fimc");
1250                         if (IS_ERR(clk_fimc)) {
1251                                 err = PTR_ERR(clk_fimc);
1252                                 break;
1253                         }
1254                         clk_set_parent(clk_fimc, parent);
1255                         clk_put(clk_fimc);
1256                 }
1257         }
1258         clk_put(parent);
1259
1260         return err;
1261 }
1262
1263 static void __init smdkv310_map_io(void)
1264 {
1265         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
1266         s3c24xx_init_clocks(24000000);
1267         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
1268
1269         clk_xusbxti.rate = 24000000;
1270 }
1271
1272 #ifdef CONFIG_TOUCHSCREEN_S3C2410
1273 static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
1274         .delay                  = 10000,
1275         .presc                  = 49,
1276         .oversampling_shift     = 2,
1277 };
1278 #endif
1279
1280 static void __init smdkv310_machine_init(void)
1281 {
1282 #if defined(CONFIG_S3C64XX_DEV_SPI)
1283         struct device *spi0_dev = &s5pv310_device_spi0.dev;
1284 #endif
1285 #ifdef CONFIG_FB_S3C_AMS369FG06
1286         struct clk *sclk = NULL;
1287         struct clk *prnt = NULL;
1288         struct device *spi_dev = &s5pv310_device_spi1.dev;
1289 #elif defined(CONFIG_S3C64XX_DEV_SPI)
1290         struct clk *sclk = NULL;
1291         struct clk *prnt = NULL;
1292         struct device *spi1_dev = &s5pv310_device_spi1.dev;
1293         struct device *spi2_dev = &s5pv310_device_spi2.dev;
1294 #endif
1295
1296         s3c_pm_init();
1297
1298 #if defined(CONFIG_S5PV310_DEV_PD) && !defined(CONFIG_PM_RUNTIME)
1299         /*
1300          * These power domains should be always on
1301          * without runtime pm support.
1302          */
1303         s5pv310_pd_enable(&s5pv310_device_pd[PD_MFC].dev);
1304         s5pv310_pd_enable(&s5pv310_device_pd[PD_G3D].dev);
1305         s5pv310_pd_enable(&s5pv310_device_pd[PD_LCD0].dev);
1306         s5pv310_pd_enable(&s5pv310_device_pd[PD_LCD1].dev);
1307         s5pv310_pd_enable(&s5pv310_device_pd[PD_CAM].dev);
1308         s5pv310_pd_enable(&s5pv310_device_pd[PD_TV].dev);
1309         s5pv310_pd_enable(&s5pv310_device_pd[PD_GPS].dev);
1310 #endif
1311
1312         smdkv310_smsc911x_init();
1313 #ifdef CONFIG_I2C_S3C2410
1314         s3c_i2c0_set_platdata(NULL);
1315         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
1316 #ifdef CONFIG_S3C_DEV_I2C1
1317         s3c_i2c1_set_platdata(NULL);
1318         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
1319 #endif
1320 #ifdef CONFIG_S3C_DEV_I2C2
1321         s3c_i2c2_set_platdata(NULL);
1322         i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
1323 #endif
1324 #ifdef CONFIG_S3C_DEV_I2C3
1325         s3c_i2c3_set_platdata(NULL);
1326         i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
1327 #endif
1328 #ifdef CONFIG_S3C_DEV_I2C4
1329         s3c_i2c4_set_platdata(NULL);
1330         i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4));
1331 #endif
1332 #ifdef CONFIG_S3C_DEV_I2C5
1333         s3c_i2c5_set_platdata(NULL);
1334         i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5));
1335 #endif
1336 #ifdef CONFIG_S3C_DEV_I2C6
1337         s3c_i2c6_set_platdata(NULL);
1338         i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6));
1339 #endif
1340 #ifdef CONFIG_S3C_DEV_I2C7
1341         s3c_i2c7_set_platdata(NULL);
1342         i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
1343 #endif
1344 #endif
1345
1346 #ifdef CONFIG_FB_S3C
1347 #ifdef CONFIG_FB_S3C_AMS369FG06
1348 #else
1349         s3cfb_set_platdata(NULL);
1350 #endif
1351 #endif
1352
1353 #ifdef CONFIG_S5P_THERMAL
1354         s5p_tmu_set_platdata(NULL);
1355 #endif
1356
1357 #ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC
1358 //      smdkv310_camera_config();
1359 //      smdkv310_subdev_config();
1360
1361         s3c_fimc_setname(0, "s5pv310-fimc");
1362         s3c_fimc_setname(1, "s5pv310-fimc");
1363         s3c_fimc_setname(2, "s5pv310-fimc");
1364         s3c_fimc_setname(3, "s5pv310-fimc");
1365         /* FIMC */
1366         s3c_set_platdata(&s3c_fimc0_default_data,
1367                          sizeof(s3c_fimc0_default_data), &s5p_device_fimc0);
1368         s3c_set_platdata(&s3c_fimc1_default_data,
1369                          sizeof(s3c_fimc1_default_data), &s5p_device_fimc1);
1370         s3c_set_platdata(&s3c_fimc2_default_data,
1371                          sizeof(s3c_fimc2_default_data), &s5p_device_fimc2);
1372         s3c_set_platdata(&s3c_fimc3_default_data,
1373                          sizeof(s3c_fimc3_default_data), &s5p_device_fimc3);
1374 #endif
1375
1376 #ifdef CONFIG_VIDEO_FIMC
1377         /* fimc */
1378         s3c_fimc0_set_platdata(&fimc_plat);
1379         s3c_fimc1_set_platdata(&fimc_plat);
1380         s3c_fimc2_set_platdata(&fimc_plat);
1381         s3c_fimc3_set_platdata(&fimc_plat);
1382 #ifdef CONFIG_VIDEO_FIMC_MIPI
1383         s3c_csis0_set_platdata(NULL);
1384         s3c_csis1_set_platdata(NULL);
1385 #endif
1386 #endif
1387
1388 #ifdef CONFIG_VIDEO_MFC5X
1389 #ifdef CONFIG_S5PV310_DEV_PD
1390         s5p_device_mfc.dev.parent = &s5pv310_device_pd[PD_MFC].dev;
1391 #endif
1392 #endif
1393
1394 #ifdef CONFIG_VIDEO_FIMG2D
1395         s5p_fimg2d_set_platdata(&fimg2d_data);
1396 #ifdef CONFIG_S5PV310_DEV_PD
1397         s5p_device_fimg2d.dev.parent = &s5pv310_device_pd[PD_LCD0].dev;
1398 #endif
1399 #endif
1400 #ifdef CONFIG_S3C_DEV_HSMMC
1401         s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
1402 #endif
1403 #ifdef CONFIG_S3C_DEV_HSMMC1
1404         s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
1405 #endif
1406 #ifdef CONFIG_S3C_DEV_HSMMC2
1407         s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
1408 #endif
1409 #ifdef CONFIG_S3C_DEV_HSMMC3
1410         s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
1411 #endif
1412 #ifdef CONFIG_S5P_DEV_MSHC
1413         s3c_mshci_set_platdata(&smdkv310_mshc_pdata);
1414 #endif
1415
1416 #ifdef CONFIG_TOUCHSCREEN_S3C2410
1417 #ifdef CONFIG_S3C_DEV_ADC
1418         s3c24xx_ts_set_platdata(&s3c_ts_platform);
1419 #endif
1420 #ifdef CONFIG_S3C_DEV_ADC1
1421         s3c24xx_ts1_set_platdata(&s3c_ts_platform);
1422 #endif
1423 #endif
1424
1425 #if defined(CONFIG_VIDEO_TVOUT)
1426         s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
1427         s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
1428
1429 #ifdef CONFIG_S5PV310_DEV_PD
1430         s5p_device_tvout.dev.parent = &s5pv310_device_pd[PD_TV].dev;
1431 #endif
1432 #endif
1433
1434 #ifdef CONFIG_S5PV310_DEV_PD
1435 #ifdef CONFIG_FB_S3C
1436         s3c_device_fb.dev.parent = &s5pv310_device_pd[PD_LCD0].dev;
1437 #endif
1438 #endif
1439
1440 #ifdef CONFIG_S5PV310_DEV_PD
1441 #ifdef CONFIG_VIDEO_FIMC
1442         s3c_device_fimc0.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1443         s3c_device_fimc1.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1444         s3c_device_fimc2.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1445         s3c_device_fimc3.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1446 #endif
1447 #endif
1448
1449         platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
1450
1451 #if defined(CONFIG_S3C64XX_DEV_SPI)
1452         sclk = clk_get(spi0_dev, "sclk_spi");
1453         if (IS_ERR(sclk))
1454                 dev_err(spi0_dev, "failed to get sclk for SPI-0\n");
1455         prnt = clk_get(spi0_dev, "mout_mpll");
1456         if (IS_ERR(prnt))
1457                 dev_err(spi0_dev, "failed to get prnt\n");
1458         clk_set_parent(sclk, prnt);
1459         clk_put(prnt);
1460
1461         if (!gpio_request(S5PV310_GPB(1), "SPI_CS0")) {
1462                 gpio_direction_output(S5PV310_GPB(1), 1);
1463                 s3c_gpio_cfgpin(S5PV310_GPB(1), S3C_GPIO_SFN(1));
1464                 s3c_gpio_setpull(S5PV310_GPB(1), S3C_GPIO_PULL_UP);
1465                 s5pv310_spi_set_info(0, S5PV310_SPI_SRCCLK_SCLK,
1466                         ARRAY_SIZE(spi0_csi));
1467         }
1468         spi_register_board_info(spi0_board_info, ARRAY_SIZE(spi0_board_info));
1469 #endif
1470
1471 #ifdef CONFIG_FB_S3C_AMS369FG06
1472         sclk = clk_get(spi_dev, "sclk_spi");
1473         if (IS_ERR(sclk))
1474                 dev_err(spi_dev, "failed to get sclk for SPI-1\n");
1475         prnt = clk_get(spi_dev, "mout_mpll");
1476         if (IS_ERR(prnt))
1477                 dev_err(spi_dev, "failed to get prnt\n");
1478         clk_set_parent(sclk, prnt);
1479         clk_put(prnt);
1480
1481         if (!gpio_request(S5PV310_GPB(5), "LCD_CS")) {
1482                 gpio_direction_output(S5PV310_GPB(5), 1);
1483                 s3c_gpio_cfgpin(S5PV310_GPB(5), S3C_GPIO_SFN(1));
1484                 s3c_gpio_setpull(S5PV310_GPB(5), S3C_GPIO_PULL_UP);
1485                 s5pv310_spi_set_info(LCD_BUS_NUM, S5PV310_SPI_SRCCLK_SCLK,
1486                         ARRAY_SIZE(spi1_csi));
1487         }
1488         spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
1489         s3cfb_set_platdata(&ams369fg06_data);
1490 #elif defined(CONFIG_S3C64XX_DEV_SPI)
1491         sclk = clk_get(spi1_dev, "sclk_spi");
1492         if (IS_ERR(sclk))
1493                 dev_err(spi1_dev, "failed to get sclk for SPI-1\n");
1494         prnt = clk_get(spi1_dev, "mout_mpll");
1495         if (IS_ERR(prnt))
1496                 dev_err(spi1_dev, "failed to get prnt\n");
1497         clk_set_parent(sclk, prnt);
1498         clk_put(prnt);
1499
1500         if (!gpio_request(S5PV310_GPB(5), "SPI_CS1")) {
1501                 gpio_direction_output(S5PV310_GPB(5), 1);
1502                 s3c_gpio_cfgpin(S5PV310_GPB(5), S3C_GPIO_SFN(1));
1503                 s3c_gpio_setpull(S5PV310_GPB(5), S3C_GPIO_PULL_UP);
1504                 s5pv310_spi_set_info(1, S5PV310_SPI_SRCCLK_SCLK,
1505                         ARRAY_SIZE(spi1_csi));
1506         }
1507         spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info));
1508
1509         sclk = clk_get(spi2_dev, "sclk_spi");
1510         if (IS_ERR(sclk))
1511                 dev_err(spi2_dev, "failed to get sclk for SPI-2\n");
1512         prnt = clk_get(spi2_dev, "mout_mpll");
1513         if (IS_ERR(prnt))
1514                 dev_err(spi2_dev, "failed to get prnt\n");
1515         clk_set_parent(sclk, prnt);
1516         clk_put(prnt);
1517
1518         if (!gpio_request(S5PV310_GPC1(2), "SPI_CS2")) {
1519                 gpio_direction_output(S5PV310_GPC1(2), 1);
1520                 s3c_gpio_cfgpin(S5PV310_GPC1(2), S3C_GPIO_SFN(1));
1521                 s3c_gpio_setpull(S5PV310_GPC1(2), S3C_GPIO_PULL_UP);
1522                 s5pv310_spi_set_info(2, S5PV310_SPI_SRCCLK_SCLK,
1523                         ARRAY_SIZE(spi2_csi));
1524         }
1525         spi_register_board_info(spi2_board_info, ARRAY_SIZE(spi2_board_info));
1526 #endif
1527         s5pv310_fimc_setup_clks();
1528 }
1529
1530 #if defined(CONFIG_S5P_MEM_CMA)
1531 static void __init s5pv310_reserve(void)
1532 {
1533         static struct cma_region regions[] = {
1534 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD0
1535                 {
1536                         .name = "fimd",
1537                         .size = (CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD0
1538 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD1
1539                                 + CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD1
1540 #endif
1541                                 ) * SZ_1K,
1542                 },
1543 #endif
1544 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0
1545                 {
1546                         .name = "fimc0",
1547                         .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K,
1548                 },
1549 #endif
1550 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1
1551                 {
1552                         .name = "fimc1",
1553                         .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K,
1554                 },
1555 #endif
1556 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2
1557                 {
1558                         .name = "fimc2",
1559                         .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 * SZ_1K,
1560                 },
1561 #endif
1562 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3
1563                 {
1564                         .name = "fimc3",
1565                         .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC3 * SZ_1K,
1566                 },
1567 #endif
1568 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC
1569                 {
1570                         .name = "mfc",
1571                         .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K,
1572                 },
1573 #endif
1574 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0
1575                 {
1576                         .name = "mfc0",
1577                         .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K,
1578                         {
1579                                 .alignment = 1 << 17,
1580                         },
1581                 },
1582 #endif
1583 #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1
1584                 {
1585                         .name = "mfc1",
1586                         .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K,
1587                         {
1588                                 .alignment = 1 << 17,
1589                         },
1590                 },
1591 #endif
1592                 {}
1593         };
1594
1595         static const char map[] __initconst =
1596                 "s3cfb=fimd;s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;mfc=mfc,mfc0,mfc1";
1597
1598         cma_set_defaults(regions, map);
1599         cma_early_regions_reserve(NULL);
1600 }
1601 #endif
1602
1603 MACHINE_START(SMDKV310, "SMDKV310")
1604         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
1605         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
1606         .phys_io        = S3C_PA_UART & 0xfff00000,
1607         .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
1608         .boot_params    = S5P_PA_SDRAM + 0x100,
1609         .init_irq       = s5pv310_init_irq,
1610         .map_io         = smdkv310_map_io,
1611         .init_machine   = smdkv310_machine_init,
1612         .timer          = &s5pv310_timer,
1613 #if defined(CONFIG_S5P_MEM_CMA)
1614         .reserve        = &s5pv310_reserve,
1615 #elif defined(CONFIG_S5P_MEM_BOOTMEM)
1616         .reserve        = &s5p_reserve_bootmem,
1617 #endif
1618 MACHINE_END