arch/arm/mach-s5pv310/mach-smdkc210.c

   1 /* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/serial_core.h>
  13 #include <linux/i2c.h>
  14 #include <linux/gpio.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/smsc911x.h>
  17 #include <linux/io.h>
  18 #include <linux/regulator/machine.h>
  19 #include <linux/regulator/max8649.h>
  20 #include <linux/clk.h>
  21
  22 #include <asm/mach/arch.h>
  23 #include <asm/mach-types.h>
  24
  25 #include <plat/regs-serial.h>
  26 #include <plat/s5pv310.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/iic.h>
  30 #include <plat/devs.h>
  31 #include <plat/adc.h>
  32 #include <plat/ts.h>
  33 #include <plat/fimg2d.h>
  34 #include <plat/sdhci.h>
  35 #include <plat/mshci.h>
  36 #include <plat/pm.h>
  37 #include <plat/tvout.h>
  38
  39 #include <plat/csis.h>
  40 #include <plat/fimc.h>
  41 #include <plat/gpio-cfg.h>
  42 #include <plat/pd.h>
  43
  44 #include <media/s5k3ba_platform.h>
  45 #include <media/s5k4ba_platform.h>
  46 #include <media/s5k4ea_platform.h>
  47 #include <media/s5k6aa_platform.h>
  48
  49 #include <mach/regs-gpio.h>
  50
  51 #include <mach/map.h>
  52 #include <mach/regs-mem.h>
  53 #include <mach/media.h>
  54
  55 /* Following are default values for UCON, ULCON and UFCON UART registers */
  56 #define SMDKC210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
  57                                  S3C2410_UCON_RXILEVEL |        \
  58                                  S3C2410_UCON_TXIRQMODE |       \
  59                                  S3C2410_UCON_RXIRQMODE |       \
  60                                  S3C2410_UCON_RXFIFO_TOI |      \
  61                                  S3C2443_UCON_RXERR_IRQEN)
  62
  63 #define SMDKC210_ULCON_DEFAULT  S3C2410_LCON_CS8
  64
  65 #define SMDKC210_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
  66                                  S5PV210_UFCON_TXTRIG4 |        \
  67                                  S5PV210_UFCON_RXTRIG4)
  68
  69 static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
  70         [0] = {
  71                 .hwport         = 0,
  72                 .flags          = 0,
  73                 .ucon           = SMDKC210_UCON_DEFAULT,
  74                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  75                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  76         },
  77         [1] = {
  78                 .hwport         = 1,
  79                 .flags          = 0,
  80                 .ucon           = SMDKC210_UCON_DEFAULT,
  81                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  82                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  83         },
  84         [2] = {
  85                 .hwport         = 2,
  86                 .flags          = 0,
  87                 .ucon           = SMDKC210_UCON_DEFAULT,
  88                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  89                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  90         },
  91         [3] = {
  92                 .hwport         = 3,
  93                 .flags          = 0,
  94                 .ucon           = SMDKC210_UCON_DEFAULT,
  95                 .ulcon          = SMDKC210_ULCON_DEFAULT,
  96                 .ufcon          = SMDKC210_UFCON_DEFAULT,
  97         },
  98         [4] = {
  99                 .hwport         = 4,
 100                 .flags          = 0,
 101                 .ucon           = SMDKC210_UCON_DEFAULT,
 102                 .ulcon          = SMDKC210_ULCON_DEFAULT,
 103                 .ufcon          = SMDKC210_UFCON_DEFAULT,
 104         },
 105 };
 106
 107 #undef WRITEBACK_ENABLED
 108 //#define WRITEBACK_ENABLED
 109
 110 #ifdef CONFIG_VIDEO_FIMC
 111 /*
 112  * External camera reset
 113  * Because the most of cameras take i2c bus signal, so that
 114  * you have to reset at the boot time for other i2c slave devices.
 115  * This function also called at fimc_init_camera()
 116  * Do optimization for cameras on your platform.
 117 */
 118 #ifdef CONFIG_ITU_A
 119 static int smdkv310_cam0_reset(int dummy)
 120 {
 121         int err;
 122         /* Camera A */
 123         err = gpio_request(S5PV310_GPX1(2), "GPX1");
 124         if (err)
 125                 printk(KERN_ERR "#### failed to request GPX1_2 ####\n");
 126
 127         s3c_gpio_setpull(S5PV310_GPX1(2), S3C_GPIO_PULL_NONE);
 128         gpio_direction_output(S5PV310_GPX1(2), 0);
 129         gpio_direction_output(S5PV310_GPX1(2), 1);
 130         gpio_free(S5PV310_GPX1(2));
 131
 132         return 0;
 133 }
 134 #endif
 135 #ifdef CONFIG_ITU_B
 136 static int smdkv310_cam1_reset(int dummy)
 137 {
 138         int err;
 139
 140         /* Camera B */
 141         err = gpio_request(S5PV310_GPX1(0), "GPX1");
 142         if (err)
 143                 printk(KERN_ERR "#### failed to request GPX1_0 ####\n");
 144
 145         s3c_gpio_setpull(S5PV310_GPX1(0), S3C_GPIO_PULL_NONE);
 146         gpio_direction_output(S5PV310_GPX1(0), 0);
 147         gpio_direction_output(S5PV310_GPX1(0), 1);
 148         gpio_free(S5PV310_GPX1(0));
 149
 150         return 0;
 151 }
 152 #endif
 153 /* for 12M camera */
 154 #ifdef CE143_MONACO
 155 static int smdkv310_cam0_standby(void)
 156 {
 157         int err;
 158         /* Camera A */
 159         err = gpio_request(S5PV310_GPX3(3), "GPX3");
 160         if (err)
 161                 printk(KERN_ERR "#### failed to request GPX3_3 ####\n");
 162         s3c_gpio_setpull(S5PV310_GPX3(3), S3C_GPIO_PULL_NONE);
 163         gpio_direction_output(S5PV310_GPX3(3), 0);
 164         gpio_direction_output(S5PV310_GPX3(3), 1);
 165         gpio_free(S5PV310_GPX3(3));
 166
 167         return 0;
 168 }
 169
 170 static int smdkv310_cam1_standby(void)
 171 {
 172         int err;
 173
 174         /* Camera B */
 175         err = gpio_request(S5PV310_GPX1(1), "GPX1");
 176         if (err)
 177                 printk(KERN_ERR "#### failed to request GPX1_1 ####\n");
 178         s3c_gpio_setpull(S5PV310_GPX1(1), S3C_GPIO_PULL_NONE);
 179         gpio_direction_output(S5PV310_GPX1(1), 0);
 180         gpio_direction_output(S5PV310_GPX1(1), 1);
 181         gpio_free(S5PV310_GPX1(1));
 182
 183         return 0;
 184 }
 185 #endif
 186
 187 /* Set for MIPI-CSI Camera module Reset */
 188 #ifdef CONFIG_CSI_C
 189 static int smdkv310_mipi_cam0_reset(int dummy)
 190 {
 191         int err;
 192
 193         err = gpio_request(S5PV310_GPX1(2), "GPX1");
 194         if (err)
 195                 printk(KERN_ERR "#### failed to reset(GPX1_2) MIPI CAM\n");
 196
 197         s3c_gpio_setpull(S5PV310_GPX1(2), S3C_GPIO_PULL_NONE);
 198         gpio_direction_output(S5PV310_GPX1(2), 0);
 199         gpio_direction_output(S5PV310_GPX1(2), 1);
 200         gpio_free(S5PV310_GPX1(2));
 201
 202         return 0;
 203 }
 204 #endif
 205 #ifdef CONFIG_CSI_D
 206 static int smdkv310_mipi_cam1_reset(int dummy)
 207 {
 208         int err;
 209
 210         err = gpio_request(S5PV310_GPX1(0), "GPX1");
 211         if (err)
 212                 printk(KERN_ERR "#### failed to reset(GPX1_0) MIPI CAM\n");
 213
 214         s3c_gpio_setpull(S5PV310_GPX1(0), S3C_GPIO_PULL_NONE);
 215         gpio_direction_output(S5PV310_GPX1(0), 0);
 216         gpio_direction_output(S5PV310_GPX1(0), 1);
 217         gpio_free(S5PV310_GPX1(0));
 218
 219         return 0;
 220 }
 221 #endif
 222
 223 #ifdef CONFIG_VIDEO_S5K3BA
 224 static struct s5k3ba_platform_data s5k3ba_plat = {
 225         .default_width = 640,
 226         .default_height = 480,
 227         .pixelformat = V4L2_PIX_FMT_VYUY,
 228         .freq = 24000000,
 229         .is_mipi = 0,
 230 };
 231
 232 static struct i2c_board_info  s5k3ba_i2c_info = {
 233         I2C_BOARD_INFO("S5K3BA", 0x2d),
 234         .platform_data = &s5k3ba_plat,
 235 };
 236
 237 static struct s3c_platform_camera s5k3ba = {
 238 #ifdef CONFIG_ITU_A
 239         .id             = CAMERA_PAR_A,
 240         .clk_name       = "sclk_cam0",
 241         .i2c_busnum     = 0,
 242         .cam_power      = smdkv310_cam0_reset,
 243 #endif
 244 #ifdef CONFIG_ITU_B
 245         .id             = CAMERA_PAR_B,
 246         .clk_name       = "sclk_cam1",
 247         .i2c_busnum     = 1,
 248         .cam_power      = smdkv310_cam1_reset,
 249 #endif
 250         .type           = CAM_TYPE_ITU,
 251         .fmt            = ITU_601_YCBCR422_8BIT,
 252         .order422       = CAM_ORDER422_8BIT_CRYCBY,
 253         .info           = &s5k3ba_i2c_info,
 254         .pixelformat    = V4L2_PIX_FMT_VYUY,
 255         .srclk_name     = "xusbxti",
 256         .clk_rate       = 24000000,
 257         .line_length    = 1920,
 258         .width          = 640,
 259         .height         = 480,
 260         .window         = {
 261                 .left   = 0,
 262                 .top    = 0,
 263                 .width  = 640,
 264                 .height = 480,
 265         },
 266
 267         /* Polarity */
 268         .inv_pclk       = 0,
 269         .inv_vsync      = 1,
 270         .inv_href       = 0,
 271         .inv_hsync      = 0,
 272
 273         .initialized    = 0,
 274 };
 275 #endif
 276
 277 #ifdef CONFIG_VIDEO_S5K4BA
 278 static struct s5k4ba_platform_data s5k4ba_plat = {
 279         .default_width = 800,
 280         .default_height = 600,
 281         .pixelformat = V4L2_PIX_FMT_UYVY,
 282         .freq = 24000000,
 283         .is_mipi = 0,
 284 };
 285
 286 static struct i2c_board_info  s5k4ba_i2c_info = {
 287         I2C_BOARD_INFO("S5K4BA", 0x2d),
 288         .platform_data = &s5k4ba_plat,
 289 };
 290
 291 static struct s3c_platform_camera s5k4ba = {
 292 #ifdef CONFIG_ITU_A
 293         .id             = CAMERA_PAR_A,
 294         .clk_name       = "sclk_cam0",
 295         .i2c_busnum     = 0,
 296         .cam_power      = smdkv310_cam0_reset,
 297 #endif
 298 #ifdef CONFIG_ITU_B
 299         .id             = CAMERA_PAR_B,
 300         .clk_name       = "sclk_cam1",
 301         .i2c_busnum     = 1,
 302         .cam_power      = smdkv310_cam1_reset,
 303 #endif
 304         .type           = CAM_TYPE_ITU,
 305         .fmt            = ITU_601_YCBCR422_8BIT,
 306         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 307         .info           = &s5k4ba_i2c_info,
 308         .pixelformat    = V4L2_PIX_FMT_UYVY,
 309         .srclk_name     = "xusbxti",
 310         .clk_rate       = 24000000,
 311         .line_length    = 1920,
 312         .width          = 1600,
 313         .height         = 1200,
 314         .window         = {
 315                 .left   = 0,
 316                 .top    = 0,
 317                 .width  = 800,
 318                 .height = 600,
 319         },
 320
 321         /* Polarity */
 322         .inv_pclk       = 0,
 323         .inv_vsync      = 1,
 324         .inv_href       = 0,
 325         .inv_hsync      = 0,
 326
 327         .initialized    = 0,
 328 };
 329 #endif
 330
 331 /* 2 MIPI Cameras */
 332 #ifdef CONFIG_VIDEO_S5K4EA
 333 static struct s5k4ea_platform_data s5k4ea_plat = {
 334         .default_width = 1920,
 335         .default_height = 1080,
 336         .pixelformat = V4L2_PIX_FMT_UYVY,
 337         .freq = 24000000,
 338         .is_mipi = 1,
 339 };
 340
 341 static struct i2c_board_info  s5k4ea_i2c_info = {
 342         I2C_BOARD_INFO("S5K4EA", 0x2d),
 343         .platform_data = &s5k4ea_plat,
 344 };
 345
 346 static struct s3c_platform_camera s5k4ea = {
 347 #ifdef CONFIG_CSI_C
 348         .id             = CAMERA_CSI_C,
 349         .clk_name       = "sclk_cam0",
 350         .i2c_busnum     = 0,
 351         .cam_power      = smdkv310_mipi_cam0_reset,
 352 #endif
 353 #ifdef CONFIG_CSI_D
 354         .id             = CAMERA_CSI_D,
 355         .clk_name       = "sclk_cam1",
 356         .i2c_busnum     = 1,
 357         .cam_power      = smdkv310_mipi_cam1_reset,
 358 #endif
 359         .type           = CAM_TYPE_MIPI,
 360         .fmt            = MIPI_CSI_YCBCR422_8BIT,
 361         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 362         .info           = &s5k4ea_i2c_info,
 363         .pixelformat    = V4L2_PIX_FMT_UYVY,
 364         .srclk_name     = "mout_mpll",
 365         .clk_rate       = 48000000,
 366         .line_length    = 1920,
 367         .width          = 1920,
 368         .height         = 1080,
 369         .window         = {
 370                 .left   = 0,
 371                 .top    = 0,
 372                 .width  = 1920,
 373                 .height = 1080,
 374         },
 375
 376         .mipi_lanes     = 2,
 377         .mipi_settle    = 12,
 378         .mipi_align     = 32,
 379
 380         /* Polarity */
 381         .inv_pclk       = 0,
 382         .inv_vsync      = 1,
 383         .inv_href       = 0,
 384         .inv_hsync      = 0,
 385
 386         .initialized    = 0,
 387 };
 388 #endif
 389
 390 #ifdef CONFIG_VIDEO_S5K6AA
 391 static struct s5k6aa_platform_data s5k6aa_plat = {
 392         .default_width = 640,
 393         .default_height = 480,
 394         .pixelformat = V4L2_PIX_FMT_UYVY,
 395         .freq = 24000000,
 396         .is_mipi = 1,
 397 };
 398
 399 static struct i2c_board_info  s5k6aa_i2c_info = {
 400         I2C_BOARD_INFO("S5K6AA", 0x3c),
 401         .platform_data = &s5k6aa_plat,
 402 };
 403
 404 static struct s3c_platform_camera s5k6aa = {
 405 #ifdef CONFIG_CSI_C
 406         .id             = CAMERA_CSI_C,
 407         .clk_name       = "sclk_cam0",
 408         .i2c_busnum     = 0,
 409         .cam_power      = smdkv310_mipi_cam0_reset,
 410 #endif
 411 #ifdef CONFIG_CSI_D
 412         .id             = CAMERA_CSI_D,
 413         .clk_name       = "sclk_cam1",
 414         .i2c_busnum     = 1,
 415         .cam_power      = smdkv310_mipi_cam1_reset,
 416 #endif
 417         .type           = CAM_TYPE_MIPI,
 418         .fmt            = MIPI_CSI_YCBCR422_8BIT,
 419         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 420         .info           = &s5k6aa_i2c_info,
 421         .pixelformat    = V4L2_PIX_FMT_UYVY,
 422         .srclk_name     = "xusbxti",
 423         .clk_rate       = 24000000,
 424         .line_length    = 1920,
 425         /* default resol for preview kind of thing */
 426         .width          = 640,
 427         .height         = 480,
 428         .window         = {
 429                 .left   = 0,
 430                 .top    = 0,
 431                 .width  = 640,
 432                 .height = 480,
 433         },
 434
 435         .mipi_lanes     = 1,
 436         .mipi_settle    = 6,
 437         .mipi_align     = 32,
 438
 439         /* Polarity */
 440         .inv_pclk       = 0,
 441         .inv_vsync      = 1,
 442         .inv_href       = 0,
 443         .inv_hsync      = 0,
 444
 445         .initialized    = 0,
 446 };
 447 #endif
 448
 449 #ifdef WRITEBACK_ENABLED
 450 static struct i2c_board_info  writeback_i2c_info = {
 451         I2C_BOARD_INFO("WriteBack", 0x0),
 452 };
 453
 454 static struct s3c_platform_camera writeback = {
 455         .id             = CAMERA_WB,
 456         .fmt            = ITU_601_YCBCR422_8BIT,
 457         .order422       = CAM_ORDER422_8BIT_CBYCRY,
 458         .i2c_busnum     = 0,
 459         .info           = &writeback_i2c_info,
 460         .pixelformat    = V4L2_PIX_FMT_YUV444,
 461         .line_length    = 800,
 462         .width          = 480,
 463         .height         = 800,
 464         .window         = {
 465                 .left   = 0,
 466                 .top    = 0,
 467                 .width  = 480,
 468                 .height = 800,
 469         },
 470
 471         .initialized    = 0,
 472 };
 473 #endif
 474
 475 /* Interface setting */
 476 static struct s3c_platform_fimc fimc_plat = {
 477 #ifdef CONFIG_ITU_A
 478         .default_cam    = CAMERA_PAR_A,
 479 #endif
 480 #ifdef CONFIG_ITU_B
 481         .default_cam    = CAMERA_PAR_B,
 482 #endif
 483 #ifdef CONFIG_CSI_C
 484         .default_cam    = CAMERA_CSI_C,
 485 #endif
 486 #ifdef CONFIG_CSI_D
 487         .default_cam    = CAMERA_CSI_D,
 488 #endif
 489 #ifdef WRITEBACK_ENABLED
 490         .default_cam    = CAMERA_WB,
 491 #endif
 492         .camera         = {
 493 #ifdef CONFIG_VIDEO_S5K3BA
 494                 &s5k3ba,
 495 #endif
 496 #ifdef CONFIG_VIDEO_S5K4BA
 497                 &s5k4ba,
 498 #endif
 499 #ifdef CONFIG_VIDEO_S5K4EA
 500                 &s5k4ea,
 501 #endif
 502 #ifdef CONFIG_VIDEO_S5K6AA
 503                 &s5k6aa,
 504 #endif
 505 #ifdef WRITEBACK_ENABLED
 506                 &writeback,
 507 #endif
 508         },
 509 #ifdef CONFIG_CPU_S5PV310_EVT1
 510         .hw_ver         = 0x52,
 511 #else
 512         .hw_ver         = 0x51,
 513 #endif
 514 };
 515 #endif
 516 static struct resource smdkc210_smsc911x_resources[] = {
 517         [0] = {
 518                 .start = S5PV310_PA_SROM1,
 519                 .end   = S5PV310_PA_SROM1 + SZ_64K - 1,
 520                 .flags = IORESOURCE_MEM,
 521         },
 522         [1] = {
 523                 .start = IRQ_EINT(5),
 524                 .end   = IRQ_EINT(5),
 525                 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 526         },
 527 };
 528
 529 static struct smsc911x_platform_config smsc9215 = {
 530         .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 531         .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
 532         .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
 533         .phy_interface = PHY_INTERFACE_MODE_MII,
 534         .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
 535 };
 536
 537 static struct platform_device smdkc210_smsc911x = {
 538         .name          = "smsc911x",
 539         .id            = -1,
 540         .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
 541         .resource      = &smdkc210_smsc911x_resources,
 542         .dev = {
 543                 .platform_data = &smsc9215,
 544         },
 545 };
 546
 547 static struct regulator_consumer_supply max8952_supply[] = {
 548         REGULATOR_SUPPLY("vdd_arm", NULL),
 549 };
 550
 551 static struct regulator_consumer_supply max8649_supply[] = {
 552         REGULATOR_SUPPLY("vdd_int", NULL),
 553 };
 554
 555 static struct regulator_consumer_supply max8649a_supply[] = {
 556         REGULATOR_SUPPLY("vdd_g3d", NULL),
 557 };
 558
 559 static struct regulator_init_data max8952_init_data = {
 560         .constraints    = {
 561                 .name           = "vdd_arm range",
 562                 .min_uV         = 770000,
 563                 .max_uV         = 1400000,
 564                 .always_on      = 1,
 565                 .boot_on        = 1,
 566                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
 567         },
 568         .num_consumer_supplies  = 1,
 569         .consumer_supplies      = &max8952_supply[0],
 570 };
 571
 572 static struct regulator_init_data max8649_init_data = {
 573         .constraints    = {
 574                 .name           = "vdd_int range",
 575                 .min_uV         = 750000,
 576                 .max_uV         = 1380000,
 577                 .always_on      = 1,
 578                 .boot_on        = 1,
 579                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
 580         },
 581         .num_consumer_supplies  = 1,
 582         .consumer_supplies      = &max8649_supply[0],
 583 };
 584 static struct regulator_init_data max8649a_init_data = {
 585         .constraints    = {
 586                 .name           = "vdd_g3d range",
 587                 .min_uV         = 750000,
 588                 .max_uV         = 1380000,
 589                 .always_on      = 0,
 590                 .boot_on        = 0,
 591                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
 592         },
 593         .num_consumer_supplies  = 1,
 594         .consumer_supplies      = &max8649a_supply[0],
 595 };
 596
 597 static struct max8649_platform_data s5pv310_max8952_info = {
 598         .mode           = 3,    /* VID1 = 1, VID0 = 1 */
 599         .extclk         = 0,
 600         .ramp_timing    = MAX8649_RAMP_32MV,
 601         .regulator      = &max8952_init_data,
 602 };
 603
 604 static struct max8649_platform_data s5pv310_max8649_info = {
 605         .mode           = 2,    /* VID1 = 1, VID0 = 0 */
 606         .extclk         = 0,
 607         .ramp_timing    = MAX8649_RAMP_32MV,
 608         .regulator      = &max8649_init_data,
 609 };
 610 static struct max8649_platform_data s5pv310_max8649a_info = {
 611         .mode           = 2,    /* VID1 = 1, VID0 = 0 */
 612         .extclk         = 0,
 613         .ramp_timing    = MAX8649_RAMP_32MV,
 614         .regulator      = &max8649a_init_data,
 615 };
 616
 617 #ifdef CONFIG_I2C_S3C2410
 618 /* I2C0 */
 619 static struct i2c_board_info i2c_devs0[] __initdata = {
 620         {
 621                 I2C_BOARD_INFO("24c128", 0x50),         /* Samsung S524AD0XD1 */
 622         }, {
 623                 I2C_BOARD_INFO("24c128", 0x52),         /* Samsung S524AD0XD1 */
 624         }, {
 625                 I2C_BOARD_INFO("max8952", 0x60),
 626                 .platform_data  = &s5pv310_max8952_info,
 627         }, {
 628                 I2C_BOARD_INFO("max8649", 0x62),
 629                 .platform_data  = &s5pv310_max8649a_info,
 630         },
 631 };
 632 #ifdef CONFIG_S3C_DEV_I2C1
 633 /* I2C1 */
 634 static struct i2c_board_info i2c_devs1[] __initdata = {
 635         {
 636                 I2C_BOARD_INFO("max8649", 0x60),
 637                 .platform_data  = &s5pv310_max8649_info,
 638         },
 639 };
 640 #endif
 641 #ifdef CONFIG_S3C_DEV_I2C2
 642 /* I2C2 */
 643 static struct i2c_board_info i2c_devs2[] __initdata = {
 644 };
 645 #endif
 646 #ifdef CONFIG_S3C_DEV_I2C3
 647 /* I2C3 */
 648 static struct i2c_board_info i2c_devs3[] __initdata = {
 649 };
 650 #endif
 651 #ifdef CONFIG_S3C_DEV_I2C4
 652 /* I2C4 */
 653 static struct i2c_board_info i2c_devs4[] __initdata = {
 654 };
 655 #endif
 656 #ifdef CONFIG_S3C_DEV_I2C5
 657 /* I2C5 */
 658 static struct i2c_board_info i2c_devs5[] __initdata = {
 659 };
 660 #endif
 661 #ifdef CONFIG_S3C_DEV_I2C6
 662 /* I2C6 */
 663 static struct i2c_board_info i2c_devs6[] __initdata = {
 664 };
 665 #endif
 666 #ifdef CONFIG_S3C_DEV_I2C7
 667 /* I2C7 */
 668 static struct i2c_board_info i2c_devs7[] __initdata = {
 669 };
 670 #endif
 671 #endif
 672
 673 #ifdef CONFIG_S3C_DEV_HSMMC
 674 static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
 675         .cd_type                = S3C_SDHCI_CD_GPIO,
 676         .ext_cd_gpio            = S5PV310_GPK0(2),
 677         .ext_cd_gpio_invert     = 1,
 678 #if defined(CONFIG_S5PV310_SD_CH0_8BIT)
 679         .max_width              = 8,
 680         .host_caps              = MMC_CAP_8_BIT_DATA,
 681 #endif
 682 };
 683 #endif
 684 #ifdef CONFIG_S3C_DEV_HSMMC1
 685 static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
 686         .cd_type                = S3C_SDHCI_CD_GPIO,
 687         .ext_cd_gpio            = S5PV310_GPK0(2),
 688         .ext_cd_gpio_invert     = 1,
 689 };
 690 #endif
 691 #ifdef CONFIG_S3C_DEV_HSMMC2
 692 static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
 693         .cd_type                = S3C_SDHCI_CD_GPIO,
 694         .ext_cd_gpio            = S5PV310_GPK2(2),
 695         .ext_cd_gpio_invert     = 1,
 696 #if defined(CONFIG_S5PV310_SD_CH2_8BIT)
 697         .max_width              = 8,
 698         .host_caps              = MMC_CAP_8_BIT_DATA,
 699 #endif
 700 };
 701 #endif
 702 #ifdef CONFIG_S3C_DEV_HSMMC3
 703 static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
 704         .cd_type                = S3C_SDHCI_CD_GPIO,
 705         .ext_cd_gpio            = S5PV310_GPK2(2),
 706         .ext_cd_gpio_invert     = 1,
 707 };
 708 #endif
 709 #ifdef CONFIG_S5P_DEV_MSHC
 710 static struct s3c_mshci_platdata smdkc210_mshc_pdata __initdata = {
 711         .cd_type                = S3C_MSHCI_CD_INTERNAL,
 712         .has_wp_gpio            = true,
 713         .wp_gpio                = 0xffffffff,
 714 #if defined(CONFIG_S5PV310_MSHC_CH0_8BIT)
 715         .max_width              = 8,
 716         .host_caps              = MMC_CAP_8_BIT_DATA,
 717 #endif
 718 };
 719 #endif
 720
 721 #ifdef CONFIG_VIDEO_FIMG2D
 722 static struct fimg2d_platdata fimg2d_data __initdata = {
 723     .hw_ver = 30,
 724     .parent_clkname = "mout_mpll",
 725     .clkname = "sclk_fimg2d",
 726     .gate_clkname = "fimg2d",
 727     .clkrate = 250 * 1000000,
 728 };
 729 #endif
 730
 731 static struct platform_device *smdkc210_devices[] __initdata = {
 732 #ifdef CONFIG_S5PV310_DEV_PD
 733         &s5pv310_device_pd[PD_MFC],
 734         &s5pv310_device_pd[PD_G3D],
 735         &s5pv310_device_pd[PD_LCD0],
 736         &s5pv310_device_pd[PD_LCD1],
 737         &s5pv310_device_pd[PD_CAM],
 738         &s5pv310_device_pd[PD_TV],
 739         &s5pv310_device_pd[PD_GPS],
 740 #endif
 741
 742         &smdkc210_smsc911x,
 743 #ifdef CONFIG_I2C_S3C2410
 744         &s3c_device_i2c0,
 745 #if defined(CONFIG_S3C_DEV_I2C1)
 746         &s3c_device_i2c1,
 747 #endif
 748 #if defined(CONFIG_S3C_DEV_I2C2)
 749         &s3c_device_i2c2,
 750 #endif
 751 #if defined(CONFIG_S3C_DEV_I2C3)
 752         &s3c_device_i2c3,
 753 #endif
 754 #if defined(CONFIG_S3C_DEV_I2C4)
 755         &s3c_device_i2c4,
 756 #endif
 757 #if defined(CONFIG_S3C_DEV_I2C5)
 758         &s3c_device_i2c5,
 759 #endif
 760 #if defined(CONFIG_S3C_DEV_I2C6)
 761         &s3c_device_i2c6,
 762 #endif
 763 #if defined(CONFIG_S3C_DEV_I2C7)
 764         &s3c_device_i2c7,
 765 #endif
 766 #endif
 767 #if defined(CONFIG_SND_SOC_SMDK_WM9713)
 768         &s5pv310_device_ac97,
 769 #endif
 770 #ifdef CONFIG_SND_SAMSUNG_SOC_SPDIF
 771         &s5pv310_device_spdif,
 772 #endif
 773 #ifdef CONFIG_S3C_DEV_HSMMC
 774         &s3c_device_hsmmc0,
 775 #endif
 776 #ifdef CONFIG_S3C_DEV_HSMMC1
 777         &s3c_device_hsmmc1,
 778 #endif
 779 #ifdef CONFIG_S3C_DEV_HSMMC2
 780         &s3c_device_hsmmc2,
 781 #endif
 782 #ifdef CONFIG_S3C_DEV_HSMMC3
 783         &s3c_device_hsmmc3,
 784 #endif
 785 #ifdef CONFIG_S5P_DEV_MSHC
 786         &s3c_device_mshc,
 787 #endif
 788 #ifdef CONFIG_TOUCHSCREEN_S3C2410
 789 #ifdef CONFIG_S3C_DEV_ADC
 790         &s3c_device_ts,
 791 #endif
 792 #ifdef CONFIG_S3C_DEV_ADC1
 793         &s3c_device_ts1,
 794 #endif
 795 #endif
 796
 797 #ifdef CONFIG_S3C_ADC
 798         &s3c_device_adc,
 799 #endif
 800
 801 #ifdef CONFIG_VIDEO_TVOUT
 802         &s5p_device_tvout,
 803         &s5p_device_cec,
 804         &s5p_device_hpd,
 805 #endif
 806
 807 #ifdef CONFIG_S3C2410_WATCHDOG
 808         &s3c_device_wdt,
 809 #endif
 810 #ifdef CONFIG_USB
 811         &s3c_device_usb_ehci,
 812         &s3c_device_usb_ohci,
 813 #endif
 814 #ifdef CONFIG_USB_GADGET
 815         &s3c_device_usbgadget,
 816 #endif
 817 #ifdef CONFIG_S3C_DEV_RTC
 818         &s3c_device_rtc,
 819 #endif
 820 #ifdef CONFIG_S3C_DEV_GIB
 821         &s3c_device_gib,
 822 #endif
 823
 824 #ifdef CONFIG_VIDEO_MFC5X
 825         &s5p_device_mfc,
 826 #endif
 827
 828 #ifdef CONFIG_VIDEO_JPEG
 829         &s5p_device_jpeg,
 830 #endif
 831
 832 #ifdef CONFIG_VIDEO_FIMG2D
 833     &s5p_device_fimg2d,
 834 #endif
 835
 836 #ifdef CONFIG_S5P_SYSMMU
 837         &s5p_device_sysmmu,
 838 #endif
 839
 840 #ifdef CONFIG_VIDEO_FIMC
 841         &s3c_device_fimc0,
 842         &s3c_device_fimc1,
 843         &s3c_device_fimc2,
 844         &s3c_device_fimc3,
 845 #ifdef CONFIG_VIDEO_FIMC_MIPI
 846         &s3c_device_csis0,
 847         &s3c_device_csis1,
 848 #endif
 849 #endif
 850 };
 851
 852 #if defined(CONFIG_VIDEO_TVOUT)
 853 static struct s5p_platform_hpd hdmi_hpd_data __initdata = {
 854
 855 };
 856 static struct s5p_platform_cec hdmi_cec_data __initdata = {
 857
 858 };
 859 #endif
 860
 861 static void __init smdkc210_map_io(void)
 862 {
 863         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
 864         s3c24xx_init_clocks(24000000);
 865         s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
 866
 867         clk_xusbxti.rate = 24000000;
 868 }
 869
 870 static void __init sromc_setup(void)
 871 {
 872         u32 tmp;
 873
 874         tmp = __raw_readl(S5P_SROM_BW);
 875         tmp &= ~(0xffff);
 876         tmp |= (0x9999);
 877         __raw_writel(tmp, S5P_SROM_BW);
 878
 879         __raw_writel(0xff1ffff1, S5P_SROM_BC1);
 880
 881         tmp = __raw_readl(S5P_VA_GPIO + 0x120);
 882         tmp &= ~(0xffffff);
 883         tmp |= (0x221121);
 884         __raw_writel(tmp, (S5P_VA_GPIO + 0x120));
 885
 886         __raw_writel(0x22222222, (S5P_VA_GPIO + 0x180));
 887         __raw_writel(0x22222222, (S5P_VA_GPIO + 0x1a0));
 888         __raw_writel(0x22222222, (S5P_VA_GPIO + 0x1c0));
 889         __raw_writel(0x22222222, (S5P_VA_GPIO + 0x1e0));
 890 }
 891
 892 #ifdef CONFIG_TOUCHSCREEN_S3C2410
 893 static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
 894         .delay                  = 10000,
 895         .presc                  = 49,
 896         .oversampling_shift     = 2,
 897 };
 898 #endif
 899
 900 static void __init smdkc210_machine_init(void)
 901 {
 902         s3c_pm_init();
 903
 904 #if defined(CONFIG_S5PV310_DEV_PD) && !defined(CONFIG_PM_RUNTIME)
 905         /*
 906          * These power domains should be always on
 907          * without runtime pm support.
 908          */
 909         s5pv310_pd_enable(&s5pv310_device_pd[PD_MFC].dev);
 910         s5pv310_pd_enable(&s5pv310_device_pd[PD_G3D].dev);
 911         s5pv310_pd_enable(&s5pv310_device_pd[PD_LCD0].dev);
 912         s5pv310_pd_enable(&s5pv310_device_pd[PD_LCD1].dev);
 913         s5pv310_pd_enable(&s5pv310_device_pd[PD_CAM].dev);
 914         s5pv310_pd_enable(&s5pv310_device_pd[PD_TV].dev);
 915         s5pv310_pd_enable(&s5pv310_device_pd[PD_GPS].dev);
 916 #endif
 917
 918         smdkc210_smsc911x_init();
 919 #ifdef CONFIG_I2C_S3C2410
 920         s3c_i2c0_set_platdata(NULL);
 921         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 922 #ifdef CONFIG_S3C_DEV_I2C1
 923         s3c_i2c1_set_platdata(NULL);
 924         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 925 #endif
 926 #ifdef CONFIG_S3C_DEV_I2C2
 927         s3c_i2c2_set_platdata(NULL);
 928         i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2));
 929 #endif
 930 #ifdef CONFIG_S3C_DEV_I2C3
 931         s3c_i2c3_set_platdata(NULL);
 932         i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3));
 933 #endif
 934 #ifdef CONFIG_S3C_DEV_I2C4
 935         s3c_i2c4_set_platdata(NULL);
 936         i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4));
 937 #endif
 938 #ifdef CONFIG_S3C_DEV_I2C5
 939         s3c_i2c5_set_platdata(NULL);
 940         i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5));
 941 #endif
 942 #ifdef CONFIG_S3C_DEV_I2C6
 943         s3c_i2c6_set_platdata(NULL);
 944         i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6));
 945 #endif
 946 #ifdef CONFIG_S3C_DEV_I2C7
 947         s3c_i2c7_set_platdata(NULL);
 948         i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7));
 949 #endif
 950 #endif
 951
 952 #ifdef CONFIG_VIDEO_FIMG2D
 953         s5p_fimg2d_set_platdata(&fimg2d_data);
 954 #endif
 955
 956 #ifdef CONFIG_S3C_DEV_HSMMC
 957         s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
 958 #endif
 959 #ifdef CONFIG_S3C_DEV_HSMMC1
 960         s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
 961 #endif
 962 #ifdef CONFIG_S3C_DEV_HSMMC2
 963         s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
 964 #endif
 965 #ifdef CONFIG_S3C_DEV_HSMMC3
 966         s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
 967 #endif
 968 #ifdef CONFIG_S5P_DEV_MSHC
 969         s3c_mshci_set_platdata(&smdkc210_mshc_pdata);
 970 #endif
 971
 972 #ifdef CONFIG_TOUCHSCREEN_S3C2410
 973 #ifdef CONFIG_S3C_DEV_ADC
 974         s3c24xx_ts_set_platdata(&s3c_ts_platform);
 975 #endif
 976 #ifdef CONFIG_S3C_DEV_ADC1
 977         s3c24xx_ts1_set_platdata(&s3c_ts_platform);
 978 #endif
 979 #endif
 980
 981 #ifdef CONFIG_VIDEO_FIMC
 982         /* fimc */
 983         s3c_fimc0_set_platdata(&fimc_plat);
 984         s3c_fimc1_set_platdata(&fimc_plat);
 985         s3c_fimc2_set_platdata(&fimc_plat);
 986         s3c_fimc3_set_platdata(&fimc_plat);
 987 #ifdef CONFIG_VIDEO_FIMC_MIPI
 988         s3c_csis0_set_platdata(NULL);
 989         s3c_csis1_set_platdata(NULL);
 990 #endif
 991 #endif
 992
 993 #if defined(CONFIG_VIDEO_TVOUT)
 994         s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data);
 995         s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
 996 #endif
 997
 998 #ifdef CONFIG_S5PV310_DEV_PD
 999 #ifdef CONFIG_FB_S3C
1000         s3c_device_fb.dev.parent = &s5pv310_device_pd[PD_LCD0].dev;
1001 #endif
1002 #endif
1003
1004 #ifdef CONFIG_S5PV310_DEV_PD
1005 #ifdef CONFIG_VIDEO_FIMC
1006         s3c_device_fimc0.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1007         s3c_device_fimc1.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1008         s3c_device_fimc2.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1009         s3c_device_fimc3.dev.parent = &s5pv310_device_pd[PD_CAM].dev;
1010 #endif
1011 #endif
1012
1013         platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
1014 }
1015
1016 MACHINE_START(SMDKC210, "SMDKC210")
1017         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
1018         .phys_io        = S3C_PA_UART & 0xfff00000,
1019         .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
1020         .boot_params    = S5P_PA_SDRAM + 0x100,
1021         .init_irq       = s5pv310_init_irq,
1022         .map_io         = smdkc210_map_io,
1023         .init_machine   = smdkc210_machine_init,
1024         .timer          = &s5pv310_timer,
1025 MACHINE_END