1 /* linux/arch/arm/mach-s5pv310/irq-eint.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5PV310 - IRQ EINT support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
17 #include <linux/sysdev.h>
18 #include <linux/gpio.h>
20 #include <plat/regs-irqtype.h>
23 #include <plat/gpio-cfg.h>
26 #include <mach/regs-gpio.h>
28 #include <asm/mach/irq.h>
30 static DEFINE_SPINLOCK(eint_lock);
32 static unsigned int s5pv310_get_irq_nr(unsigned int number)
38 ret = (number + IRQ_EINT0);
41 ret = (number + (IRQ_EINT4 - 4));
44 ret = (number + (IRQ_EINT8 - 8));
47 printk(KERN_ERR "[%s] input number is not available : %d\n",__func__,number);
53 static unsigned int s5pv310_irq_split(unsigned int number)
58 ret = do_div(test, IRQ_EINT_BASE);
65 static unsigned int s5pv310_irq_to_bit(unsigned int irq)
70 tmp = do_div(irq, IRQ_EINT_BASE);
77 static inline void s5pv310_irq_eint_mask(unsigned int irq)
81 spin_lock(&eint_lock);
82 mask = __raw_readl(S5P_EINT_MASK(s5pv310_irq_split(irq)));
83 mask |= s5pv310_irq_to_bit(irq);
84 __raw_writel(mask, S5P_EINT_MASK(s5pv310_irq_split(irq)));
85 spin_unlock(&eint_lock);
88 static void s5pv310_irq_eint_unmask(unsigned int irq)
92 spin_lock(&eint_lock);
93 mask = __raw_readl(S5P_EINT_MASK(s5pv310_irq_split(irq)));
94 mask &= ~(s5pv310_irq_to_bit(irq));
95 __raw_writel(mask, S5P_EINT_MASK(s5pv310_irq_split(irq)));
96 spin_unlock(&eint_lock);
99 static inline void s5pv310_irq_eint_ack(unsigned int irq)
101 spin_lock(&eint_lock);
102 __raw_writel(s5pv310_irq_to_bit(irq), S5P_EINT_PEND(s5pv310_irq_split(irq)));
103 spin_unlock(&eint_lock);
106 static void s5pv310_irq_eint_maskack(unsigned int irq)
108 s5pv310_irq_eint_mask(irq);
109 s5pv310_irq_eint_ack(irq);
112 static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
114 int offs = EINT_OFFSET(irq);
118 struct irq_desc *desc = irq_to_desc(irq);
121 case IRQ_TYPE_EDGE_RISING:
122 newvalue = S5P_EXTINT_RISEEDGE;
125 case IRQ_TYPE_EDGE_FALLING:
126 newvalue = S5P_EXTINT_FALLEDGE;
129 case IRQ_TYPE_EDGE_BOTH:
130 newvalue = S5P_EXTINT_BOTHEDGE;
133 case IRQ_TYPE_LEVEL_LOW:
134 newvalue = S5P_EXTINT_LOWLEV;
137 case IRQ_TYPE_LEVEL_HIGH:
138 newvalue = S5P_EXTINT_HILEV;
142 printk(KERN_ERR "No such irq type %d", type);
146 shift = (offs & 0x7) * 4;
149 spin_lock(&eint_lock);
150 ctrl = __raw_readl(S5P_EINT_CON(s5pv310_irq_split(irq)));
152 ctrl |= newvalue << shift;
153 __raw_writel(ctrl, S5P_EINT_CON(s5pv310_irq_split(irq)));
154 spin_unlock(&eint_lock);
156 if ((0 <= offs) && (offs < 8))
157 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
159 else if ((8 <= offs) && (offs < 16))
160 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
162 else if ((16 <= offs) && (offs < 24))
163 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
165 else if ((24 <= offs) && (offs < 32))
166 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
169 printk(KERN_ERR "No such irq number %d", offs);
171 if (type & IRQ_TYPE_EDGE_BOTH)
172 desc->handle_irq = handle_edge_irq;
174 desc->handle_irq = handle_level_irq;
179 static struct irq_chip s5pv310_irq_eint = {
180 .name = "s5pv310-eint",
181 .mask = s5pv310_irq_eint_mask,
182 .unmask = s5pv310_irq_eint_unmask,
183 .mask_ack = s5pv310_irq_eint_maskack,
184 .ack = s5pv310_irq_eint_ack,
185 .set_type = s5pv310_irq_eint_set_type,
187 .set_wake = s3c_irqext_wake,
191 /* s5pv310_irq_demux_eint
193 * This function demuxes the IRQ from the group0 external interrupts,
194 * from EINTs 16 to 31. It is designed to be inlined into the specific
195 * handler s5p_irq_demux_eintX_Y.
197 * Each EINT pend/mask registers handle eight of them.
199 static inline u32 s5pv310_irq_demux_eint(unsigned int irq, unsigned int start)
201 unsigned int cascade_irq;
203 u32 status = __raw_readl(S5P_EINT_PEND(s5pv310_irq_split(start)));
204 u32 mask = __raw_readl(S5P_EINT_MASK(s5pv310_irq_split(start)));
211 cascade_irq = fls(status) - 1;
212 generic_handle_irq(cascade_irq + start);
213 status &= ~(1 << cascade_irq);
220 static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
222 struct irq_chip *chip = get_irq_chip(irq);
228 a16_23 = s5pv310_irq_demux_eint(irq, IRQ_EINT(16));
229 a24_31 = s5pv310_irq_demux_eint(irq, IRQ_EINT(24));
231 if (!a16_23 && !a24_31)
232 do_bad_IRQ(irq, desc);
237 static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
240 struct irq_chip *chip = get_irq_chip(irq);
245 for (i = 0 ; i <= 15 ; i++) {
246 if (irq == s5pv310_get_irq_nr(i)) {
247 generic_handle_irq(IRQ_EINT(i));
252 do_bad_IRQ(irq, desc);
257 int __init s5pv310_init_irq_eint(void)
261 for (irq = 0 ; irq <= 31 ; irq++) {
262 set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
263 set_irq_handler(IRQ_EINT(irq), handle_level_irq);
264 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
267 set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
269 for (irq = 0 ; irq <= 15 ; irq++)
270 set_irq_chained_handler(s5pv310_get_irq_nr(irq), s5pv310_irq_eint0_15);
275 arch_initcall(s5pv310_init_irq_eint);