2 * Copyright (C) 2011 Samsung Electronics
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/init.h>
10 #include <mach/gpio.h>
15 #include "gpio-mobile.h"
16 #include "gpio-slp10.h"
19 * Please describe the how to setup the pins.
20 * E.g., what's the correct setings for I2C, PULL_UP or PULL_NONE?
30 /* UART 0 for BT & 1 for GPS */
31 static const struct s5p_gpio_group group_a0[] __initdata = {
32 /* XuRXD[0] BT_UART_RXD */
33 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
34 /* XuTXD[0] BT_UART_TXD */
35 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
36 /* XuCTSn[0] BT_UART_CTS */
37 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
38 /* XuRTSn[0] BT_UART_RTS */
39 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
40 /* XuRXD[1] GPS_UART_RXD */
41 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
42 /* XuTXD[1] GPS_UART_TXD */
43 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
44 /* XuCTSn[1] GPS_UART_CTS */
45 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
46 /* XuRTSn[1] GPS_UART_RTS */
47 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
50 /* UART 2 for debug & 3 for CP */
51 static const struct s5p_gpio_group group_a1[] __initdata = {
53 PIN(0, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
55 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
56 /* Xi2c2SDA TSP_SDA_2.8V (I2C3: TSP) PU by VTOUCH_VDD2.8V */
57 PIN(2, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
58 /* Xi2c2SCL TSP_SCL_2.8V (I2C3: TSP) PU by VTOUCH_VDD2.8V */
59 PIN(3, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
60 /* XuRXD[3] AP_FLM_RXD_2.8V */
61 PIN(4, SFN(0x2), NONE, NOP, DRV1X, INPUT, PULLDOWN),
62 /* XuTXD[3] AP_FLM_TXD_2.8V */
63 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
66 static const struct s5p_gpio_group group_b[] __initdata = {
75 /* XspiCLK[1] TP_IEM_CLK */
77 /* XspiCSn[1] TP_IEM_DAT */
79 /* XspiMISO[1] AP_PMIC_SDA (PU by VCC_2.8V_PDA */
80 PIN(6, SFN(0x3), NONE, NONE, DRV1X, INPUT, NOP),
81 /* XspiMOSI[1] AP_PMIC_SCLK (PU by VCC_2.8V_PDA */
82 PIN(7, SFN(0x3), NONE, NONE, DRV1X, INPUT, NOP),
85 static const struct s5p_gpio_group group_c0[] __initdata = {
86 /* XIIS1SCLK REC_PCM_CLK */
87 PIN(0, SFN(0x2), NONE, XXXXXX, DRV1X, OUTPUT0, NOP),
90 /* XIIS1LRCK REC_PCM_SYNC */
91 PIN(2, SFN(0x2), NONE, XXXXXX, DRV1X, OUTPUT0, NOP),
92 /* XIIS1SDI REC_PCM_IN */
93 PIN(3, SFN(0x2), NONE, NOP, DRV1X, INPUT, PULLDOWN),
94 /* XIIS1SDO REC_PCM_OUT */
95 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
98 static const struct s5p_gpio_group group_c1[] __initdata = {
101 /* Xpcm2EXTCLK CP_ON: Inefficient? */
102 PIN(1, SFN(0x1), LOW, NOP, DRV1X, KEEP, NOP),
105 /* Xpcm2SIN CODEC_VT_SDA_1.8V PU by VCC_1.8V_PDA */
106 PIN(3, SFN(0x4), NONE, NOP, DRV1X, INPUT, NOP),
107 /* Xpcm2SOUT CODEV_VT_SCLK_1.8V PU by VCC_1.8V_PDA */
108 PIN(4, SFN(0x4), NONE, NOP, DRV1X, INPUT, NOP),
111 static const struct s5p_gpio_group group_d0[] __initdata = {
112 /* XpwmTOUT[0] LED_BACKLIGHT_PWM */
113 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
114 /* XpwmTOUT[1] VIBTONE_PWM */
115 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
116 /* XpwmTOUT[2] MSENSOR_MHL_SDA_2.8V PU by VCC_2.8V_PDA */
117 PIN(2, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
118 /* XpwmTOUT[3] MSENSOR_MHL_SCL_2.8V PU by VCC_2.8V_PDA */
119 PIN(3, SFN(0x3), NONE, NOP, DRV1X, INPUT, NOP),
122 static const struct s5p_gpio_group group_d1[] __initdata = {
123 /* Xi2c0SDA MEGA_CAM_SDA_2.8V PU by VCC_2.8V_PDA */
124 PIN(0, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
125 /* Xi2c0SCL MEGA_CAM_SCL_2.8V PU by VCC_2.8V_PDA */
126 PIN(1, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
127 /* Xi2c1SDA SENSE_SDA_2.8V PU by VCC_2.8V_PDA */
128 PIN(2, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
129 /* Xi2c1SCL SENSE_SCL_2.8V PU by VCC_2.8V_PDA */
130 PIN(3, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
133 static const struct s5p_gpio_group group_e0[] __initdata = {
146 static const struct s5p_gpio_group group_e1[] __initdata = {
147 /* XmdmADDR[0] HW_REV0 PU by VCC_1.8V_PDA */
148 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at slp10_0105 */
149 /* XmdmADDR[1] HW_REV1 PU by VCC_1.8V_PDA */
150 PIN(1, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at slp10_0102 */
151 /* XmdmADDR[2] HW_REV2 PU by VCC_1.8V_PDA */
152 PIN(2, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* H at slp10_0102 */
153 /* XmdmADDR[3] HW_REV3 PU by VCC_1.8V_PDA */
154 PIN(3, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP), /* L at slp10_0102 */
155 /* XmdmADDR[4] MICBIAS_EN */
156 PIN(4, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
157 /* XmdmADDR[5] LVDS_nSHDN PD by Ground */
158 PIN(5, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
165 static const struct s5p_gpio_group group_e2[] __initdata = {
166 /* XmdmADDR[8] TA_nCHG PU by VCC_1.8V_PDA */
167 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
168 /* XmdmADDR[9] CAM_IO_EN */
169 PIN(1, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
170 /* XmdmADDR[10] NC */
172 /* XmdmADDR[11] LCD_LDO_EN */
173 PIN(3, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
174 /* XmdmADDR[12] EAR_MICBIAS_EN */
175 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
176 /* XmdmADDR[13] 8M_1.2V_EN */
177 PIN(5, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
180 static const struct s5p_gpio_group group_e3[] __initdata = {
183 /* XmdmDATA[1] USB_OTG_EN */
184 PIN(1, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
186 PIN(2, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
199 static const struct s5p_gpio_group group_e4[] __initdata = {
204 /* XmdmDATA[10] NC */
206 /* XmdmDATA[11] NC */
208 /* XmdmDATA[12] NC */
210 /* XmdmDATA[13] NC */
212 /* XmdmDATA[14] NC */
214 /* XmdmDATA[15] NC */
219 static const struct s5p_gpio_group group_f0[] __initdata = {
220 /* XvHSYNC LCD_HSYNC */
221 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
222 /* XvVSYNC LCD_VSYNC */
223 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
225 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
226 /* XvVCLK LCD_PCLK CAP-Ground */
227 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
229 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
231 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
233 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
235 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
238 static const struct s5p_gpio_group group_f1[] __initdata = {
240 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
242 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
244 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
246 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
248 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
250 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
252 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
254 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
257 static const struct s5p_gpio_group group_f2[] __initdata = {
259 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
261 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
263 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
265 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
267 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
269 PIN(5, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
271 PIN(6, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
273 PIN(7, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
276 static const struct s5p_gpio_group group_f3[] __initdata = {
278 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
280 PIN(1, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
282 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
284 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
285 /* XvVSYNC_LDI MHL_RST */
286 PIN(4, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
287 /* XvSYS_OE MHL_INT PD by Ground*/
288 PIN(5, SFN(0xF), NONE, NOP, DRV1X, INPUT, NOP),
292 static const struct s5p_gpio_group group_j0[] __initdata = {
293 /* XciPCLK CAM_PCLK */
294 PIN(0, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
295 /* XciVSYNC CAM_VSYNC */
296 PIN(1, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
297 /* XciHREF CAM_HSYNC */
298 PIN(2, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
299 /* XciDATA[0] CAM_D */
300 PIN(3, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
302 PIN(4, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
304 PIN(5, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
306 PIN(6, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
308 PIN(7, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
311 static const struct s5p_gpio_group group_j1[] __initdata = {
313 PIN(0, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
315 PIN(1, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
317 PIN(2, SFN(0x2), NONE, NOP, DRV4X, INPUT, PULLDOWN),
318 /* XciCLKenb CAM_MCLK */
319 PIN(3, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
320 /* XciFIELD MHL_WAKE_UP */
321 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
324 static const struct s5p_gpio_group group_k0[] __initdata = {
325 /* Xmmc0CLK NAND_CLK */
326 PIN(0, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
327 /* Xmmc0CMD NAND_CMD */
328 PIN(1, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
329 /* Xmmc0CDn GPS_EN */
330 PIN(2, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
331 /* Xmmc0DATA[0] NAND_D */
332 PIN(3, SFN(0x2), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
333 /* Xmmc0DATA[1] NAND_D */
334 PIN(4, SFN(0x2), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
335 /* Xmmc0DATA[2] NAND_D */
336 PIN(5, SFN(0x2), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
337 /* Xmmc0DATA[3] NAND_D */
338 PIN(6, SFN(0x2), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
341 static const struct s5p_gpio_group group_k1[] __initdata = {
342 /* Xmmc1CLK LED_SDA_2.8V */
343 PIN(0, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
344 /* Xmmc1CMD LDO_EN_1 Inefficient? Reconsider! */
345 PIN(1, SFN(0x1), HIGH, PULLUP, DRV1X, OUTPUT1, NOP),
346 /* Xmmc1CDn LED_SCL_2.8V */
347 PIN(2, SFN(0x2), NONE, NOP, DRV1X, INPUT, NOP),
348 /* Xmmc1DATA[0] NAND_D */
349 PIN(3, SFN(0x3), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
350 /* Xmmc1DATA[1] NAND_D */
351 PIN(4, SFN(0x3), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
352 /* Xmmc1DATA[2] NAND_D */
353 PIN(5, SFN(0x3), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
354 /* Xmmc1DATA[3] NAND_D */
355 PIN(6, SFN(0x3), NONE, PULLUP, DRV4X, OUTPUT0, NOP),
358 static const struct s5p_gpio_group group_k2[] __initdata = {
363 /* Xmmc2CDn LIGHT_SDA_2.8V PU by VCC_2.8V_PDA / Does this do SDA? */
364 PIN(2, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
365 /* Xmmc2DATA[0] T_FLASH_D PU by VTF_2.8V */
375 static const struct s5p_gpio_group group_k3[] __initdata = {
376 /* Xmmc3CLK WLAN_SDIO_CLK */
377 PIN(0, SFN(0x2), NONE, NOP, DRV4X, OUTPUT0, NOP),
378 /* Xmmc3CMD WLAN_SDIO_CMD PU by VCC_2.8V_PDA */
379 PIN(1, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
380 /* Xmmc3CDn LIGHT_SCL_2.8V PU by VCC_2.8V_PDA */
381 PIN(2, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
382 /* Xmmc3DATA[0] WLAN_SDIO_D PU by VCC_2.8V_PDA */
383 PIN(3, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
385 PIN(4, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
387 PIN(5, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
389 PIN(6, SFN(0x2), NONE, NOP, DRV4X, INPUT, NOP),
392 static const struct s5p_gpio_group group_l0[] __initdata = {
393 /* XGNSS_SYNC BUCK2_EN: MAX8997 SET3 */
394 PIN(0, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
395 /* XGNSS_ISIGN CURR_ADJ PD by Ground. Set HIGH if TA connected */
396 PIN(1, SFN(0x1), LOW, NOP, DRV1X, KEEP, NOP),
397 /* XGNSS_IMAG RGB_nRST */
398 PIN(2, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
399 /* XGNSS_QSIGN MENU_KEY */
400 PIN(3, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
401 /* XGNSS_QMAG BT_EN */
402 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
403 /* XGNSS_MCLK SEARCH_KEY */
404 PIN(5, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
405 /* XGNSS_RF_RSTN HOME_KEY */
406 PIN(6, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
407 /* XGNSS_CLKREQ CLEAR_KEY */
408 PIN(7, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
411 static const struct s5p_gpio_group group_l1[] __initdata = {
412 /* XGNSS_SCL BT_nRST */
413 PIN(0, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
414 /* XGNSS_SDA MASSMEMORY_EN */
415 PIN(1, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
416 /* XGNSS_EPOCH WLAN_EN */
417 PIN(2, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
420 static const struct s5p_gpio_group group_l2[] __initdata = {
421 /* XGNSS_GPIO_0 CAM_VT_nSTBY (active low) */
422 PIN(0, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
423 /* XGNSS_GPIO_1 CAM_VT_nRST (active low) */
424 PIN(1, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
425 /* XGNSS_GPIO_2 NC */
427 /* XGNSS_GPIO_3 ACCESSRORY_EN */
428 PIN(3, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
429 /* XGNSS_GPIO_4 TOUCH_RST */
430 PIN(4, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
431 /* XGNSS_GPIO_5 ISP_INT */
432 PIN(5, SFN(0xf), NONE, PULLUP, DRV1X, INPUT, PULLDOWN),
433 /* XGNSS_GPIO_6 NFC_EN */
434 PIN(6, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
435 /* XGNSS_GPIO_7 NFC_FIRMWARE */
436 PIN(7, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
440 static const struct s5p_gpio_group group_x0[] = {
441 /* XEINT[0] GYRO_INT */
442 EXTPIN(0, SFN(0x0), NONE, PULLDOWN, DRV1X),
443 /* XEINT[1] GYRO_FIFO_INT */
444 EXTPIN(1, SFN(0x0), NONE, PULLDOWN, DRV1X),
445 /* XEINT[2] LIGHT_nINT PD with Diode to Ground */
446 EXTPIN(2, SFN(0xf), NONE, NOP, DRV1X),
447 /* XEINT[3] BOOT_MODE */
448 EXTPIN(3, SFN(0x0), NONE, NOP, DRV1X),
449 /* XEINT[4] TOUCH_INT PU by VTOUCH_AVDD2.8V */
450 EXTPIN(4, SFN(0xf), NONE, NOP, DRV1X),
451 /* XEINT[5] BUCK1_EN_A */
452 EXTPIN(5, SFN(0x1), LOW, NOP, DRV1X),
453 /* XEINT[6] BUCK1_EN_B */
454 EXTPIN(6, SFN(0x1), LOW, NOP, DRV1X),
455 /* XEINT[7] AP_PMIC_IRQ PU by VCC_2.8V_PDA */
456 EXTPIN(7, SFN(0xf), NONE, NOP, DRV1X),
460 static const struct s5p_gpio_group group_x1[] = {
461 /* XEINT[8] IPC_SLAVE_WAKEUP */
462 EXTPIN(0, SFN(0x1), LOW, PULLDOWN, DRV1X),
463 /* XEINT[9] IPC_HOST_WAKEUP */
464 EXTPIN(1, SFN(0xf), NONE, NOP, DRV1X),
465 /* XEINT[10] CP_DUMP_INT : Don't know how to set up? */
466 EXTPIN(2, SFN(0x0), NONE, NOP, DRV1X),
467 /* XEINT[11] SUSPEND_REQUEST_HSIC */
468 EXTPIN(3, SFN(0xf), NONE, NOP, DRV1X),
469 /* XEINT[12] TA_nCONNECTED */
470 EXTPIN(4, SFN(0x0), NONE, NOP, DRV1X),
471 /* XEINT[13] DOCK_INT PD to Ground */
472 EXTPIN(5, SFN(0xf), NONE, NOP, DRV1X),
473 /* XEINT[14] PHONE_ACTIVE */
474 EXTPIN(6, SFN(0xf), NONE, PULLDOWN, DRV1X),
475 /* XEINT[15] SIM_DETECT PU by VCC_1.8V_PDA*/
476 EXTPIN(7, SFN(0x0), NONE, NOP, DRV1X),
480 static const struct s5p_gpio_group group_x2[] = {
481 /* XEINT[16] VOL_UP PU by VCC_2.8V_PDA */
482 EXTPIN(0, SFN(0xf), NONE, NOP, DRV1X),
483 /* XEINT[17] VOL_DOWN PU by VCC_2.8V_PDA */
484 EXTPIN(1, SFN(0xf), NONE, NOP, DRV1X),
485 /* XEINT[18] MSENSE_INT */
486 EXTPIN(2, SFN(0xf), NONE, NOP, DRV1X),
487 /* XEINT[19] FUEL_ALERT PU by VCC_2.8V_PDA */
488 EXTPIN(3, SFN(0xf), NONE, NOP, DRV1X),
489 /* XEINT[20] HDMI_EN */
490 EXTPIN(4, SFN(0x1), LOW, NOP, DRV1X),
491 /* XEINT[21] WLAN_HOST_WAKE */
492 EXTPIN(5, SFN(0xf), NONE, PULLDOWN, DRV1X),
493 /* XEINT[22] BT_HOST_WAKE */
494 EXTPIN(6, SFN(0xf), NONE, PULLDOWN, DRV1X),
495 /* XEINT[23] nPOWER */
496 EXTPIN(7, SFN(0xf), NONE, NOP, DRV1X),
500 static const struct s5p_gpio_group group_x3[] = {
501 /* XEINT[24] ACC_INT */
502 EXTPIN(0, SFN(0xf), NONE, PULLDOWN, DRV1X),
503 /* XEINT[25] BT_WAKE */
504 EXTPIN(1, SFN(0x1), LOW, NOP, DRV1X),
505 /* XEINT[26] DET_3.5 */
506 EXTPIN(2, SFN(0xf), NONE, NOP, DRV1X),
507 /* XEINT[27] GPS_nRST */
508 EXTPIN(3, SFN(0x1), LOW, NOP, DRV1X),
509 /* XEINT[28] REMOTE_SENSE_IRQ PD by Ground */
510 EXTPIN(4, SFN(0xf), NONE, NOP, DRV1X),
511 /* XEINT[29] ACCESSORY_INT PU by VADC_3.3V_C210 */
512 EXTPIN(5, SFN(0xf), NONE, NOP, DRV1X),
513 /* XEINT[30] EAR_SEND_END */
514 EXTPIN(6, SFN(0xf), NONE, PULLDOWN, DRV1X),
515 /* XEINT[31] HDMI_HPD */
516 EXTPIN(7, SFN(0x0), NONE, NOP, DRV1X),
519 static const struct s5p_gpio_group group_y0[] __initdata = {
520 /* Xm0CSn[0] NFC_SCL_1.8V */
521 PIN(0, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
522 /* Xm0CSn[1] NFC_SDA_1.8V */
523 PIN(1, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
525 PIN(2, SKIP_SFN, NONE, XXXXXX, DRV1X, OUTPUT1, NOP),
527 PIN(3, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
529 PIN(4, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
531 PIN(5, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
534 static const struct s5p_gpio_group group_y1[] __initdata = {
536 PIN(0, SFN(0x0), NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
538 PIN(1, SFN(0x0), NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
540 PIN(2, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
542 PIN(3, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
545 static const struct s5p_gpio_group group_y2[] __initdata = {
547 PIN(0, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
549 PIN(1, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
551 PIN(2, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, NOP),
553 PIN(3, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
555 PIN(4, SKIP_SFN, NONE, XXXXXX, DRV1X, OUTPUT1, NOP),
557 PIN(5, SKIP_SFN, NONE, XXXXXX, DRV1X, INPUT, PULLDOWN),
560 static const struct s5p_gpio_group group_y3[] __initdata = {
561 /* Xm0ADDR[0] MHL_SDA_1.8V PU by VCC_1.8V_MHL */
562 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
565 /* Xm0ADDR[2] MHL_SCL_1.8V PU by VCC_1.8V_MHL */
566 PIN(2, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
569 /* Xm0ADDR[4] CP_RST */
570 PIN(4, SFN(0x1), LOW, NOP, DRV1X, KEEP, NOP),
571 /* Xm0ADDR[5] ACTIVE_STATE_HSIC */
572 PIN(5, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
573 /* Xm0ADDR[6] GPS_CNTL */
574 PIN(6, SFN(0x1), LOW, NOP, DRV1X, OUTPUT0, NOP),
575 /* Xm0ADDR[7] ISP_RESET (active low) */
576 PIN(7, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
579 static const struct s5p_gpio_group group_y4[] __initdata = {
580 /* Xm0ADDR[8] FUEL_SDA_1.8V PU by VCC_1.8V_PDA */
581 PIN(0, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
582 /* Xm0ADDR[9] FUAL_SCL_1.8V PU by VCC_1.8V_PDA */
583 PIN(1, SFN(0x0), NONE, NOP, DRV1X, INPUT, NOP),
584 /* Xm0ADDR[10] PDA_ACTIVE */
585 PIN(2, SFN(0x1), HIGH, NOP, DRV1X, OUTPUT0, NOP),
586 /* Xm0ADDR[11] NFC_IRQ */
587 PIN(2, SFN(0xf), NONE, NOP, DRV1X, OUTPUT0, NOP),
590 /* Xm0ADDR[13] TA_EN */
591 PIN(5, SFN(0x1), LOW, NOP, DRV1X, KEEP, NOP),
592 /* Xm0ADDR[14] RESET_REQ_N */
593 PIN(6, SFN(0x1), LOW, NOP, DRV1X, KEEP, NOP),
594 /* Xm0ADDR[15] UART_SEL */
595 PIN(7, SKIP_SFN, NONE, NOP, DRV1X, KEEP, NOP),
599 static const struct s5p_gpio_group group_y5[] __initdata = {
618 static const struct s5p_gpio_group group_y6[] __initdata = {
637 static const struct s5p_gpio_group group_z[] __initdata = {
638 /* Xi2s0SCLK MM_I2S_CLK */
639 PIN(0, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
642 /* Xi2s0LRCK MM_I2S_SYNC */
643 PIN(2, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
644 /* Xi2s0SDI MM_I2S_DI */
645 PIN(3, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
646 /* Xi2s0SDO[0] MM_I2S_DO */
647 PIN(4, SFN(0x2), NONE, NOP, DRV1X, OUTPUT0, NOP),
654 /* Note: It contains the latest borad revision configuration */
655 static struct s5p_gpio_group_info slp10_gpios[] __refdata = {
657 GPIO_(GROUP_A0, S5P_VA_GPIO, 0x000, group_a0),
658 GPIO_(GROUP_A1, S5P_VA_GPIO, 0x020, group_a1),
659 GPIO_(GROUP_B, S5P_VA_GPIO, 0x040, group_b),
660 GPIO_(GROUP_C0, S5P_VA_GPIO, 0x060, group_c0),
661 GPIO_(GROUP_C1, S5P_VA_GPIO, 0x080, group_c1),
662 GPIO_(GROUP_D0, S5P_VA_GPIO, 0x0A0, group_d0),
663 GPIO_(GROUP_D1, S5P_VA_GPIO, 0x0C0, group_d1),
664 GPIO_(GROUP_E0, S5P_VA_GPIO, 0x0E0, group_e0),
665 GPIO_(GROUP_E1, S5P_VA_GPIO, 0x100, group_e1),
666 GPIO_(GROUP_E2, S5P_VA_GPIO, 0x120, group_e2),
667 GPIO_(GROUP_E3, S5P_VA_GPIO, 0x140, group_e3),
668 GPIO_(GROUP_E4, S5P_VA_GPIO, 0x160, group_e4),
669 GPIO_(GROUP_F0, S5P_VA_GPIO, 0x180, group_f0),
670 GPIO_(GROUP_F1, S5P_VA_GPIO, 0x1A0, group_f1),
671 GPIO_(GROUP_F2, S5P_VA_GPIO, 0x1C0, group_f2),
672 GPIO_(GROUP_F3, S5P_VA_GPIO, 0x1E0, group_f3),
674 GPIO_(GROUP_J0, S5P_VA_GPIO2, 0x000, group_j0),
675 GPIO_(GROUP_J1, S5P_VA_GPIO2, 0x020, group_j1),
676 GPIO_(GROUP_K0, S5P_VA_GPIO2, 0x040, group_k0),
677 GPIO_(GROUP_K1, S5P_VA_GPIO2, 0x060, group_k1),
678 GPIO_(GROUP_K2, S5P_VA_GPIO2, 0x080, group_k2),
679 GPIO_(GROUP_K3, S5P_VA_GPIO2, 0x0A0, group_k3),
680 GPIO_(GROUP_L0, S5P_VA_GPIO2, 0x0C0, group_l0),
681 GPIO_(GROUP_L1, S5P_VA_GPIO2, 0x0E0, group_l1),
682 GPIO_(GROUP_L2, S5P_VA_GPIO2, 0x100, group_l2),
683 GPIO_(GROUP_Y0, S5P_VA_GPIO2, 0x120, group_y0),
684 GPIO_(GROUP_Y1, S5P_VA_GPIO2, 0x140, group_y1),
685 GPIO_(GROUP_Y2, S5P_VA_GPIO2, 0x160, group_y2),
686 GPIO_(GROUP_Y3, S5P_VA_GPIO2, 0x180, group_y3),
687 GPIO_(GROUP_Y4, S5P_VA_GPIO2, 0x1A0, group_y4),
688 GPIO_(GROUP_Y5, S5P_VA_GPIO2, 0x1C0, group_y5),
689 GPIO_(GROUP_Y6, S5P_VA_GPIO2, 0x1E0, group_y6),
690 /* External GPIOs & Alive block */
691 GPIO_(GROUP_X0, S5P_VA_GPIO2, 0xC00, group_x0),
692 GPIO_(GROUP_X1, S5P_VA_GPIO2, 0xC20, group_x1),
693 GPIO_(GROUP_X2, S5P_VA_GPIO2, 0xC40, group_x2),
694 GPIO_(GROUP_X3, S5P_VA_GPIO2, 0xC60, group_x3),
696 GPIO_(GROUP_Z, S5P_VA_GPIO3, 0x000, group_z),
699 static int mobile_gpios[] = {
700 [GPIO_MICBIAS_EN] = S5PV310_GPE1(4),
701 [GPIO_DET_3_5] = S5PV310_GPX3(2),
702 [GPIO_EAR_MICBIAS_EN] = S5PV310_GPE2(4),
703 [GPIO_EAR_SEND_END] = S5PV310_GPX3(6),
705 [GPIO_CP_ON] = S5PV310_GPC1(1),
706 [GPIO_IPC_SLAVE_WAKEUP] = S5PV310_GPX1(0),
707 [GPIO_IPC_HOST_WAKEUP] = S5PV310_GPX1(1),
708 [GPIO_CP_DUMP_INT] = S5PV310_GPX1(2),
709 [GPIO_SUSPEND_REQUEST_HSIC] = S5PV310_GPX1(3),
710 [GPIO_PHONE_ACTIVE] = S5PV310_GPX1(6),
711 [GPIO_SIM_DETECT] = S5PV310_GPX1(7),
712 [GPIO_CP_RST] = S5PV310_GPY3(4),
713 [GPIO_ACTIVE_STATE_HSIC] = S5PV310_GPY3(5),
714 [GPIO_PDA_ACTIVE] = S5PV310_GPY4(2),
715 [GPIO_RESET_REQ_N] = S5PV310_GPY4(6),
716 [GPIO_USB_OTG_EN] = S5PV310_GPE3(1),
717 [GPIO_UART_SEL] = S5PV310_GPY4(7),
720 struct mobile_gpios_data slp10_data;
722 void __init mobile_gpios_init_slp10(void)
724 int hwrev = system_rev & 0xFF;
726 printk("Mobile GPIOs init - HW Rev %d\n", hwrev);
728 slp10_data.infos = slp10_gpios;
729 slp10_data.x0 = (struct s5p_gpio_group *)group_x0;
730 slp10_data.x1 = (struct s5p_gpio_group *)group_x1;
731 slp10_data.x2 = (struct s5p_gpio_group *)group_x2;
732 slp10_data.x3 = (struct s5p_gpio_group *)group_x3;
733 slp10_data.gpios = mobile_gpios;
735 slp10_data.infos_size = ARRAY_SIZE(slp10_gpios);
736 slp10_data.x0_size = ARRAY_SIZE(group_x0);
737 slp10_data.x1_size = ARRAY_SIZE(group_x1);
738 slp10_data.x2_size = ARRAY_SIZE(group_x2);
739 slp10_data.x3_size = ARRAY_SIZE(group_x3);
740 slp10_data.gpios_size = ARRAY_SIZE(mobile_gpios);
742 mobile_gpios_register(&slp10_data);