arch/arm/mach-s5pv310/dma.c

   1 /*
   2  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/platform_device.h>
  21 #include <linux/dma-mapping.h>
  22
  23 #include <plat/devs.h>
  24 #include <plat/irqs.h>
  25 #ifdef CONFIG_S5PV310_DEV_PD
  26 #include <plat/pd.h>
  27 #endif
  28
  29 #include <mach/map.h>
  30 #include <mach/irqs.h>
  31
  32 #include <plat/s3c-pl330-pdata.h>
  33
  34 static u64 dma_dmamask = DMA_BIT_MASK(32);
  35
  36 static struct resource s5pv310_mdma_resource[] = {
  37         [0] = {
  38                 .start  = S5PV310_PA_MDMA1,
  39                 .end    = S5PV310_PA_MDMA1 + SZ_4K,
  40                 .flags = IORESOURCE_MEM,
  41         },
  42         [1] = {
  43                 .start  = IRQ_MDMA1,
  44                 .end    = IRQ_MDMA1,
  45                 .flags  = IORESOURCE_IRQ,
  46         },
  47 };
  48
  49 struct s3c_pl330_platdata s5pv310_mdma_pdata = {
  50         .peri = {
  51                 /*
  52                  * The DMAC can have max 8 channel so there
  53                  * can be MAX 8 M<->M requests served at any time.
  54                  *
  55                  * Always keep the first 8 M->M channels on the
  56                  * DMAC dedicated for M->M transfers.
  57                  */
  58                 [0] = DMACH_MTOM_0,
  59                 [1] = DMACH_MTOM_1,
  60                 [2] = DMACH_MTOM_2,
  61                 [3] = DMACH_MTOM_3,
  62                 [4] = DMACH_MTOM_4,
  63                 [5] = DMACH_MTOM_5,
  64                 [6] = DMACH_MTOM_6,
  65                 [7] = DMACH_MTOM_7,
  66                 [8] = DMACH_MAX,
  67                 [9] = DMACH_MAX,
  68                 [10] = DMACH_MAX,
  69                 [11] = DMACH_MAX,
  70                 [12] = DMACH_MAX,
  71                 [13] = DMACH_MAX,
  72                 [14] = DMACH_MAX,
  73                 [15] = DMACH_MAX,
  74                 [16] = DMACH_MAX,
  75                 [17] = DMACH_MAX,
  76                 [18] = DMACH_MAX,
  77                 [19] = DMACH_MAX,
  78                 [20] = DMACH_MAX,
  79                 [21] = DMACH_MAX,
  80                 [22] = DMACH_MAX,
  81                 [23] = DMACH_MAX,
  82                 [24] = DMACH_MAX,
  83                 [25] = DMACH_MAX,
  84                 [26] = DMACH_MAX,
  85                 [27] = DMACH_MAX,
  86                 [28] = DMACH_MAX,
  87                 [29] = DMACH_MAX,
  88                 [30] = DMACH_MAX,
  89                 [31] = DMACH_MAX,
  90         },
  91         .va_mode = 0,
  92 };
  93
  94 struct platform_device s5pv310_device_mdma = {
  95         .name           = "s3c-pl330",
  96         .id             = 0,
  97         .num_resources  = ARRAY_SIZE(s5pv310_mdma_resource),
  98         .resource       = s5pv310_mdma_resource,
  99         .dev            = {
 100                 .dma_mask = &dma_dmamask,
 101                 .coherent_dma_mask = DMA_BIT_MASK(32),
 102                 .platform_data = &s5pv310_mdma_pdata,
 103         },
 104 };
 105 EXPORT_SYMBOL_GPL(s5pv310_device_mdma);
 106
 107 static struct resource s5pv310_pdma0_resource[] = {
 108         [0] = {
 109                 .start  = S5PV310_PA_PDMA0,
 110                 .end    = S5PV310_PA_PDMA0 + SZ_4K,
 111                 .flags = IORESOURCE_MEM,
 112         },
 113         [1] = {
 114                 .start  = IRQ_PDMA0,
 115                 .end    = IRQ_PDMA0,
 116                 .flags  = IORESOURCE_IRQ,
 117         },
 118 };
 119
 120 static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
 121         .peri = {
 122                 [0] = DMACH_PCM0_RX,
 123                 [1] = DMACH_PCM0_TX,
 124                 [2] = DMACH_PCM2_RX,
 125                 [3] = DMACH_PCM2_TX,
 126                 [4] = DMACH_MSM_REQ0,
 127                 [5] = DMACH_MSM_REQ2,
 128                 [6] = DMACH_SPI0_RX,
 129                 [7] = DMACH_SPI0_TX,
 130                 [8] = DMACH_SPI2_RX,
 131                 [9] = DMACH_SPI2_TX,
 132                 [10] = DMACH_I2S0S_TX,
 133                 [11] = DMACH_I2S0_RX,
 134                 [12] = DMACH_I2S0_TX,
 135                 [13] = DMACH_I2S2_RX,
 136                 [14] = DMACH_I2S2_TX,
 137                 [15] = DMACH_UART0_RX,
 138                 [16] = DMACH_UART0_TX,
 139                 [17] = DMACH_UART2_RX,
 140                 [18] = DMACH_UART2_TX,
 141                 [19] = DMACH_UART4_RX,
 142                 [20] = DMACH_UART4_TX,
 143                 [21] = DMACH_SLIMBUS0_RX,
 144                 [22] = DMACH_SLIMBUS0_TX,
 145                 [23] = DMACH_SLIMBUS2_RX,
 146                 [24] = DMACH_SLIMBUS2_TX,
 147                 [25] = DMACH_SLIMBUS4_RX,
 148                 [26] = DMACH_SLIMBUS4_TX,
 149                 [27] = DMACH_AC97_MICIN,
 150                 [28] = DMACH_AC97_PCMIN,
 151                 [29] = DMACH_AC97_PCMOUT,
 152                 [30] = DMACH_MAX,
 153                 [31] = DMACH_MAX,
 154         },
 155         .va_mode = 0,
 156 };
 157
 158 struct platform_device s5pv310_device_pdma0 = {
 159         .name           = "s3c-pl330",
 160         .id             = 1,
 161         .num_resources  = ARRAY_SIZE(s5pv310_pdma0_resource),
 162         .resource       = s5pv310_pdma0_resource,
 163         .dev            = {
 164                 .dma_mask = &dma_dmamask,
 165                 .coherent_dma_mask = DMA_BIT_MASK(32),
 166                 .platform_data = &s5pv310_pdma0_pdata,
 167         },
 168 };
 169 EXPORT_SYMBOL_GPL(s5pv310_device_pdma0);
 170
 171 static struct resource s5pv310_pdma1_resource[] = {
 172         [0] = {
 173                 .start  = S5PV310_PA_PDMA1,
 174                 .end    = S5PV310_PA_PDMA1 + SZ_4K,
 175                 .flags = IORESOURCE_MEM,
 176         },
 177         [1] = {
 178                 .start  = IRQ_PDMA1,
 179                 .end    = IRQ_PDMA1,
 180                 .flags  = IORESOURCE_IRQ,
 181         },
 182 };
 183
 184 static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
 185         .peri = {
 186                 [0] = DMACH_PCM0_RX,
 187                 [1] = DMACH_PCM0_TX,
 188                 [2] = DMACH_PCM1_RX,
 189                 [3] = DMACH_PCM1_TX,
 190                 [4] = DMACH_MSM_REQ1,
 191                 [5] = DMACH_MSM_REQ3,
 192                 [6] = DMACH_SPI1_RX,
 193                 [7] = DMACH_SPI1_TX,
 194                 [8] = DMACH_I2S0S_TX,
 195                 [9] = DMACH_I2S0_RX,
 196                 [10] = DMACH_I2S0_TX,
 197                 [11] = DMACH_I2S1_RX,
 198                 [12] = DMACH_I2S1_TX,
 199                 [13] = DMACH_UART0_RX,
 200                 [14] = DMACH_UART0_TX,
 201                 [15] = DMACH_UART1_RX,
 202                 [16] = DMACH_UART1_TX,
 203                 [17] = DMACH_UART3_RX,
 204                 [18] = DMACH_UART3_TX,
 205                 [19] = DMACH_SLIMBUS1_RX,
 206                 [20] = DMACH_SLIMBUS1_TX,
 207                 [21] = DMACH_SLIMBUS3_RX,
 208                 [22] = DMACH_SLIMBUS3_TX,
 209                 [23] = DMACH_SLIMBUS5_RX,
 210                 [24] = DMACH_SLIMBUS5_TX,
 211                 [25] = DMACH_SLIMBUS0AUX_RX,
 212                 [26] = DMACH_SLIMBUS0AUX_TX,
 213                 [27] = DMACH_SPDIF,
 214                 [28] = DMACH_MAX,
 215                 [29] = DMACH_MAX,
 216                 [30] = DMACH_MAX,
 217                 [31] = DMACH_MAX,
 218         },
 219         .va_mode = 0,
 220 };
 221
 222 struct platform_device s5pv310_device_pdma1 = {
 223         .name           = "s3c-pl330",
 224         .id             = 2,
 225         .num_resources  = ARRAY_SIZE(s5pv310_pdma1_resource),
 226         .resource       = s5pv310_pdma1_resource,
 227         .dev            = {
 228                 .dma_mask = &dma_dmamask,
 229                 .coherent_dma_mask = DMA_BIT_MASK(32),
 230                 .platform_data = &s5pv310_pdma1_pdata,
 231         },
 232 };
 233 EXPORT_SYMBOL_GPL(s5pv310_device_pdma1);
 234
 235 static struct platform_device *s5pv310_dmacs[] __initdata = {
 236         &s5pv310_device_mdma,
 237         &s5pv310_device_pdma0,
 238         &s5pv310_device_pdma1,
 239 };
 240
 241 static int __init s5pv310_dma_init(void)
 242 {
 243         platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
 244
 245         return 0;
 246 }
 247 arch_initcall(s5pv310_dma_init);