arch/arm/mach-s5pv310/clock.c

   1 /* linux/arch/arm/mach-s5pv310/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV310 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/devs.h>
  22 #include <plat/s5p-clock.h>
  23 #include <plat/clock-clksrc.h>
  24 #include <plat/sysmmu.h>
  25
  26 #include <mach/map.h>
  27 #include <mach/regs-clock.h>
  28 #include <mach/regs-audss.h>
  29
  30 static struct clk clk_sclk_hdmi27m = {
  31         .name           = "sclk_hdmi27m",
  32         .id             = -1,
  33         .rate           = 27000000,
  34 };
  35
  36 static struct clk clk_sclk_hdmiphy = {
  37         .name           = "sclk_hdmiphy",
  38         .id             = -1,
  39 };
  40
  41 static struct clk clk_sclk_usbphy0 = {
  42         .name           = "sclk_usbphy0",
  43         .id             = -1,
  44         .rate           = 27000000,
  45 };
  46
  47 static struct clk clk_sclk_usbphy1 = {
  48         .name           = "sclk_usbphy1",
  49         .id             = -1,
  50 };
  51
  52 static struct clk clk_audiocdclk0 = {
  53         .name           = "audiocdclk",
  54         .id             = 0,
  55 };
  56
  57 static struct clk clk_audiocdclk1 = {
  58         .name           = "audiocdclk",
  59         .id             = 0,
  60 };
  61
  62 static struct clk clk_audiocdclk2 = {
  63         .name           = "audiocdclk",
  64         .id             = -1,
  65 };
  66
  67 static struct clk clk_spdifcdclk = {
  68         .name           = "spdifcdclk",
  69         .id             = -1,
  70 };
  71
  72 static int s5pv310_clk_ip_g3d_ctrl(struct clk *clk, int enable)
  73 {
  74         return s5p_gatectrl(S5P_CLKGATE_IP_G3D, clk, enable);
  75 }
  76
  77 static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
  78 {
  79         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
  80 }
  81
  82 static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
  83 {
  84         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
  85 }
  86
  87 static int s5pv310_clk_ip_mfc_ctrl(struct clk *clk, int enable)
  88 {
  89         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
  90 }
  91
  92 static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
  93 {
  94         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
  95 }
  96
  97 static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  98 {
  99         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
 100 }
 101
 102 static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 103 {
 104         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 105 }
 106
 107 static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 108 {
 109         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 110 }
 111
 112 static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 113 {
 114         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
 115 }
 116
 117 static int s5pv310_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 118 {
 119         return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
 120 }
 121
 122 static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
 123 {
 124         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
 125 }
 126
 127 static int s5pv310_clk_ip_tv_ctrl(struct clk *clk, int enable)
 128 {
 129         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
 130 }
 131
 132 static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
 133 {
 134         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
 135 }
 136
 137 static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 138 {
 139         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 140 }
 141
 142 static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 143 {
 144         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 145 }
 146
 147 static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 148 {
 149         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 150 }
 151
 152 static int s5pv310_clk_ip_gps_ctrl(struct clk *clk, int enable)
 153 {
 154         return s5p_gatectrl(S5P_CLKGATE_IP_GPS, clk, enable);
 155 }
 156
 157 static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
 158 {
 159         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 160 }
 161
 162 static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
 163 {
 164         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 165 }
 166
 167 static int s5pv310_clk_ip_leftbus_ctrl(struct clk *clk, int enable)
 168 {
 169         return s5p_gatectrl(S5P_CLKGATE_IP_LEFTBUS, clk, enable);
 170 }
 171
 172 static int s5pv310_clk_ip_rightbus_ctrl(struct clk *clk, int enable)
 173 {
 174         return s5p_gatectrl(S5P_CLKGATE_IP_RIGHTBUS, clk, enable);
 175 }
 176
 177 static int s5pv310_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
 178 {
 179         return s5p_gatectrl(S5P_CLKSRC_MASK_MAUDIO, clk, enable);
 180 }
 181
 182 static int s5pv310_clk_audss_ctrl(struct clk *clk, int enable)
 183 {
 184         return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable);
 185 }
 186
 187 static int s5pv310_clk_epll_ctrl(struct clk *clk, int enable)
 188 {
 189         return s5p_gatectrl(S5P_EPLL_CON0, clk, enable);
 190 }
 191
 192 static int s5pv310_clk_vpll_ctrl(struct clk *clk, int enable)
 193 {
 194         return s5p_gatectrl(S5P_VPLL_CON0, clk, enable);
 195 }
 196
 197
 198 /* Core list of CMU_CPU side */
 199
 200 static struct clksrc_clk clk_mout_apll = {
 201         .clk    = {
 202                 .name           = "mout_apll",
 203                 .id             = -1,
 204         },
 205         .sources        = &clk_src_apll,
 206         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 207 };
 208
 209 static struct clksrc_clk clk_sclk_apll = {
 210         .clk    = {
 211                 .name           = "sclk_apll",
 212                 .id             = -1,
 213                 .parent         = &clk_mout_apll.clk,
 214         },
 215         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 216 };
 217
 218 static struct clksrc_clk clk_mout_epll = {
 219         .clk    = {
 220                 .name           = "mout_epll",
 221                 .id             = -1,
 222                 .parent = &clk_fout_epll,
 223         },
 224         .sources        = &clk_src_epll,
 225         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 226 };
 227
 228 static struct clksrc_clk clk_mout_mpll = {
 229         .clk = {
 230                 .name           = "mout_mpll",
 231                 .id             = -1,
 232         },
 233         .sources        = &clk_src_mpll,
 234         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
 235 };
 236
 237 static struct clk *clkset_moutcore_list[] = {
 238         [0] = &clk_mout_apll.clk,
 239         [1] = &clk_mout_mpll.clk,
 240 };
 241
 242 static struct clksrc_sources clkset_moutcore = {
 243         .sources        = clkset_moutcore_list,
 244         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 245 };
 246
 247 static struct clksrc_clk clk_moutcore = {
 248         .clk    = {
 249                 .name           = "moutcore",
 250                 .id             = -1,
 251         },
 252         .sources        = &clkset_moutcore,
 253         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 254 };
 255
 256 static struct clksrc_clk clk_coreclk = {
 257         .clk    = {
 258                 .name           = "core_clk",
 259                 .id             = -1,
 260                 .parent         = &clk_moutcore.clk,
 261         },
 262         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 263 };
 264
 265 static struct clksrc_clk clk_armclk = {
 266         .clk    = {
 267                 .name           = "armclk",
 268                 .id             = -1,
 269                 .parent         = &clk_coreclk.clk,
 270         },
 271 };
 272
 273 static struct clksrc_clk clk_aclk_corem0 = {
 274         .clk    = {
 275                 .name           = "aclk_corem0",
 276                 .id             = -1,
 277                 .parent         = &clk_coreclk.clk,
 278         },
 279         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 280 };
 281
 282 static struct clksrc_clk clk_aclk_cores = {
 283         .clk    = {
 284                 .name           = "aclk_cores",
 285                 .id             = -1,
 286                 .parent         = &clk_coreclk.clk,
 287         },
 288         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 289 };
 290
 291 static struct clksrc_clk clk_aclk_corem1 = {
 292         .clk    = {
 293                 .name           = "aclk_corem1",
 294                 .id             = -1,
 295                 .parent         = &clk_coreclk.clk,
 296         },
 297         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 298 };
 299
 300 static struct clksrc_clk clk_periphclk = {
 301         .clk    = {
 302                 .name           = "periphclk",
 303                 .id             = -1,
 304                 .parent         = &clk_coreclk.clk,
 305         },
 306         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 307 };
 308
 309 /* Core list of CMU_CORE side */
 310
 311 static struct clk *clkset_corebus_list[] = {
 312         [0] = &clk_mout_mpll.clk,
 313         [1] = &clk_sclk_apll.clk,
 314 };
 315
 316 static struct clksrc_sources clkset_mout_corebus = {
 317         .sources        = clkset_corebus_list,
 318         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 319 };
 320
 321 static struct clksrc_clk clk_mout_corebus = {
 322         .clk    = {
 323                 .name           = "mout_corebus",
 324                 .id             = -1,
 325         },
 326         .sources        = &clkset_mout_corebus,
 327         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 328 };
 329
 330 static struct clksrc_clk clk_sclk_dmc = {
 331         .clk    = {
 332                 .name           = "sclk_dmc",
 333                 .id             = -1,
 334                 .parent         = &clk_mout_corebus.clk,
 335         },
 336         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 337 };
 338
 339 static struct clksrc_clk clk_aclk_cored = {
 340         .clk    = {
 341                 .name           = "aclk_cored",
 342                 .id             = -1,
 343                 .parent         = &clk_sclk_dmc.clk,
 344         },
 345         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 346 };
 347
 348 static struct clksrc_clk clk_aclk_corep = {
 349         .clk    = {
 350                 .name           = "aclk_corep",
 351                 .id             = -1,
 352                 .parent         = &clk_aclk_cored.clk,
 353         },
 354         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 355 };
 356
 357 static struct clksrc_clk clk_aclk_acp = {
 358         .clk    = {
 359                 .name           = "aclk_acp",
 360                 .id             = -1,
 361                 .parent         = &clk_mout_corebus.clk,
 362         },
 363         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 364 };
 365
 366 static struct clksrc_clk clk_pclk_acp = {
 367         .clk    = {
 368                 .name           = "pclk_acp",
 369                 .id             = -1,
 370                 .parent         = &clk_aclk_acp.clk,
 371         },
 372         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 373 };
 374
 375 /* Core list of CMU_TOP side */
 376
 377 static struct clk *clkset_aclk_top_list[] = {
 378         [0] = &clk_mout_mpll.clk,
 379         [1] = &clk_sclk_apll.clk,
 380 };
 381
 382 static struct clksrc_sources clkset_aclk = {
 383         .sources        = clkset_aclk_top_list,
 384         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 385 };
 386
 387 static struct clksrc_clk clk_aclk_200 = {
 388         .clk    = {
 389                 .name           = "aclk_200",
 390                 .id             = -1,
 391         },
 392         .sources        = &clkset_aclk,
 393         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 394         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 395 };
 396
 397 static struct clksrc_clk clk_aclk_100 = {
 398         .clk    = {
 399                 .name           = "aclk_100",
 400                 .id             = -1,
 401         },
 402         .sources        = &clkset_aclk,
 403         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 404         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 405 };
 406
 407 static struct clksrc_clk clk_aclk_160 = {
 408         .clk    = {
 409                 .name           = "aclk_160",
 410                 .id             = -1,
 411         },
 412         .sources        = &clkset_aclk,
 413         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 414         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 415 };
 416
 417 static struct clksrc_clk clk_aclk_133 = {
 418         .clk    = {
 419                 .name           = "aclk_133",
 420                 .id             = -1,
 421         },
 422         .sources        = &clkset_aclk,
 423         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 424         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 425 };
 426
 427 /* CMU_LEFT/RIGHTBUS side */
 428 static struct clk *clkset_aclk_lrbus_list[] = {
 429         [0] = &clk_mout_mpll.clk,
 430         [1] = &clk_sclk_apll.clk,
 431 };
 432
 433 static struct clksrc_sources clkset_aclk_lrbus = {
 434         .sources        = clkset_aclk_lrbus_list,
 435         .nr_sources     = ARRAY_SIZE(clkset_aclk_lrbus_list),
 436 };
 437
 438 static struct clksrc_clk clk_aclk_gdl = {
 439         .clk    = {
 440                 .name           = "aclk_gdl",
 441                 .id             = -1,
 442         },
 443         .sources = &clkset_aclk_lrbus,
 444         .reg_src        = { .reg = S5P_CLKSRC_LEFTBUS, .shift = 0, .size = 1 },
 445         .reg_div        = { .reg = S5P_CLKDIV_LEFTBUS, .shift = 0, .size = 3 },
 446 };
 447
 448 static struct clksrc_clk clk_aclk_gdr = {
 449         .clk    = {
 450                 .name           = "aclk_gdr",
 451                 .id             = -1,
 452         },
 453         .sources = &clkset_aclk_lrbus,
 454         .reg_src        = { .reg = S5P_CLKSRC_RIGHTBUS, .shift = 0, .size = 1 },
 455         .reg_div        = { .reg = S5P_CLKDIV_RIGHTBUS, .shift = 0, .size = 3 },
 456 };
 457
 458 static struct clksrc_clk clk_aclk_gpl = {
 459         .clk            = {
 460                 .name           = "aclk_gpl",
 461                 .id             = -1,
 462                 .parent         = &clk_aclk_gdl.clk,
 463         },
 464         .reg_div = { .reg = S5P_CLKDIV_LEFTBUS, .shift = 4, .size = 3 },
 465 };
 466
 467 static struct clksrc_clk clk_aclk_gpr = {
 468         .clk            = {
 469                 .name           = "aclk_gpr",
 470                 .id             = -1,
 471                 .parent         = &clk_aclk_gdr.clk,
 472         },
 473         .reg_div = { .reg = S5P_CLKDIV_RIGHTBUS, .shift = 4, .size = 3 },
 474 };
 475
 476 static struct clk *clkset_vpllsrc_list[] = {
 477         [0] = &clk_fin_vpll,
 478         [1] = &clk_sclk_hdmi27m,
 479 };
 480
 481 static struct clksrc_sources clkset_vpllsrc = {
 482         .sources        = clkset_vpllsrc_list,
 483         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 484 };
 485
 486 static struct clksrc_clk clk_vpllsrc = {
 487         .clk    = {
 488                 .name           = "vpll_src",
 489                 .id             = -1,
 490                 .enable         = s5pv310_clksrc_mask_top_ctrl,
 491                 .ctrlbit        = (1 << 0),
 492         },
 493         .sources        = &clkset_vpllsrc,
 494         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 495 };
 496
 497 static struct clk *clkset_sclk_vpll_list[] = {
 498         [0] = &clk_vpllsrc.clk,
 499         [1] = &clk_fout_vpll,
 500 };
 501
 502 static struct clksrc_sources clkset_sclk_vpll = {
 503         .sources        = clkset_sclk_vpll_list,
 504         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 505 };
 506
 507 static struct clksrc_clk clk_sclk_vpll = {
 508         .clk    = {
 509                 .name           = "sclk_vpll",
 510                 .id             = -1,
 511         },
 512         .sources        = &clkset_sclk_vpll,
 513         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 514 };
 515
 516 /* --------------------------------------
 517  *         TV subsystem CLOCKS
 518  * --------------------------------------
 519  */
 520
 521 static struct clk *clkset_sclk_dac_list[] = {
 522         [0] = &clk_sclk_vpll.clk,
 523         [1] = &clk_sclk_hdmiphy,
 524 };
 525
 526 static struct clksrc_sources clkset_sclk_dac = {
 527         .sources        = clkset_sclk_dac_list,
 528         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 529 };
 530
 531 static struct clksrc_clk clk_sclk_dac = {
 532         .clk            = {
 533                 .name           = "sclk_dac",
 534                 .id             = -1,
 535                 .enable         = s5pv310_clksrc_mask_tv_ctrl,
 536                 .ctrlbit        = (1 << 8),
 537         },
 538         .sources = &clkset_sclk_dac,
 539         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
 540 };
 541
 542 static struct clksrc_clk clk_sclk_pixel  = {
 543         .clk            = {
 544                 .name           = "sclk_pixel",
 545                 .id             = -1,
 546                 .parent = &clk_sclk_vpll.clk,
 547         },
 548         .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
 549 };
 550
 551 static struct clk *clkset_sclk_hdmi_list[] = {
 552         [0] = &clk_sclk_pixel.clk,
 553         [1] = &clk_sclk_hdmiphy,
 554 };
 555
 556 static struct clksrc_sources clkset_sclk_hdmi = {
 557         .sources        = clkset_sclk_hdmi_list,
 558         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 559 };
 560
 561 static struct clksrc_clk clk_sclk_hdmi = {
 562         .clk            = {
 563                 .name           = "sclk_hdmi",
 564                 .id             = -1,
 565                 .enable         = s5pv310_clksrc_mask_tv_ctrl,
 566                 .ctrlbit        = (1 << 0),
 567         },
 568         .sources = &clkset_sclk_hdmi,
 569         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
 570 };
 571
 572 static struct clk *clkset_sclk_mixer_list[] = {
 573         [0] = &clk_sclk_dac.clk,
 574         [1] = &clk_sclk_hdmi.clk,
 575 };
 576
 577 static struct clksrc_sources clkset_sclk_mixer = {
 578         .sources        = clkset_sclk_mixer_list,
 579         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 580 };
 581
 582 static struct clksrc_clk clk_sclk_mixer = {
 583         .clk            = {
 584                 .name           = "sclk_mixer",
 585                 .id             = -1,
 586                 .enable         = s5pv310_clksrc_mask_tv_ctrl,
 587                 .ctrlbit        = (1 << 4),
 588         },
 589         .sources = &clkset_sclk_mixer,
 590         .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
 591 };
 592
 593 static struct clksrc_clk *sclk_tv[] = {
 594         &clk_sclk_dac,
 595         &clk_sclk_pixel,
 596         &clk_sclk_hdmi,
 597         &clk_sclk_mixer,
 598         NULL,
 599 };
 600
 601 /* -------------------------------------------- */
 602
 603 static struct clk *clkset_mout_hpm_list[] = {
 604         [0] = &clk_mout_apll.clk,
 605         [1] = &clk_mout_mpll.clk,
 606 };
 607
 608 static struct clksrc_sources clkset_sclk_hpm = {
 609         .sources        = clkset_mout_hpm_list,
 610         .nr_sources     = ARRAY_SIZE(clkset_mout_hpm_list),
 611 };
 612
 613 static struct clksrc_clk clk_dout_copy = {
 614         .clk    = {
 615                 .name           = "dout_copy",
 616                 .id             = -1,
 617         },
 618         .sources        = &clkset_sclk_hpm,
 619         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 20, .size = 1 },
 620         .reg_div        = { .reg = S5P_CLKDIV_CPU1, .shift = 0, .size = 3 },
 621 };
 622
 623 static struct clk *clkset_mout_g3d0_list[] = {
 624         [0] = &clk_mout_mpll.clk,
 625         [1] = &clk_sclk_apll.clk,
 626 };
 627
 628 static struct clksrc_sources clkset_mout_g3d0 = {
 629         .sources        = clkset_mout_g3d0_list,
 630         .nr_sources     = ARRAY_SIZE(clkset_mout_g3d0_list),
 631 };
 632
 633 static struct clksrc_clk clk_mout_g3d0 = {
 634         .clk    = {
 635                 .name           = "mout_g3d0",
 636                 .id             = -1,
 637         },
 638         .sources        = &clkset_mout_g3d0,
 639         .reg_src        = { .reg = S5P_CLKSRC_G3D, .shift = 0, .size = 1 },
 640 };
 641
 642 static struct clk *clkset_mout_g3d1_list[] = {
 643         [0] = &clk_mout_epll.clk,
 644         [1] = &clk_sclk_vpll.clk,
 645 };
 646
 647 static struct clksrc_sources clkset_mout_g3d1 = {
 648         .sources        = clkset_mout_g3d1_list,
 649         .nr_sources     = ARRAY_SIZE(clkset_mout_g3d1_list),
 650 };
 651
 652 static struct clksrc_clk clk_mout_g3d1 = {
 653         .clk    = {
 654                 .name           = "mout_g3d1",
 655                 .id             = -1,
 656         },
 657         .sources        = &clkset_mout_g3d1,
 658         .reg_src        = { .reg = S5P_CLKSRC_G3D, .shift = 4, .size = 1 },
 659 };
 660
 661 static struct clk *clkset_mout_g3d_list[] = {
 662         [0] = &clk_mout_g3d0.clk,
 663         [1] = &clk_mout_g3d1.clk,
 664 };
 665
 666 static struct clksrc_sources clkset_mout_g3d = {
 667         .sources        = clkset_mout_g3d_list,
 668         .nr_sources     = ARRAY_SIZE(clkset_mout_g3d_list),
 669 };
 670
 671 enum {CLK_SMMU_MDMA = 0};
 672 static struct clk init_clocks_disable[] = {
 673         [CLK_SMMU_MDMA] = {
 674                 .name           = "smmu_mdma",
 675                 .id             = -1,
 676                 .enable         = s5pv310_clk_ip_image_ctrl,
 677                 .ctrlbit        = (1 << 5),
 678         }, {
 679                 .name           = "ppmuleft",
 680                 .id             = -1,
 681                 .enable         = s5pv310_clk_ip_leftbus_ctrl,
 682                 .ctrlbit        = (1 << 1),
 683         }, {
 684                 .name           = "ppmuright",
 685                 .id             = -1,
 686                 .enable         = s5pv310_clk_ip_rightbus_ctrl,
 687                 .ctrlbit        = (1 << 1),
 688         }, {
 689                 .name           = "fimc",
 690                 .id             = 0,
 691                 .parent         = &clk_aclk_160.clk,
 692                 .enable         = s5pv310_clk_ip_cam_ctrl,
 693                 .ctrlbit        = (1 << 0),
 694         }, {
 695                 .name           = "fimc",
 696                 .id             = 1,
 697                 .parent         = &clk_aclk_160.clk,
 698                 .enable         = s5pv310_clk_ip_cam_ctrl,
 699                 .ctrlbit        = (1 << 1),
 700         }, {
 701                 .name           = "fimc",
 702                 .id             = 2,
 703                 .parent         = &clk_aclk_160.clk,
 704                 .enable         = s5pv310_clk_ip_cam_ctrl,
 705                 .ctrlbit        = (1 << 2),
 706         }, {
 707                 .name           = "fimc",
 708                 .id             = 3,
 709                 .parent         = &clk_aclk_160.clk,
 710                 .enable         = s5pv310_clk_ip_cam_ctrl,
 711                 .ctrlbit        = (1 << 3),
 712         }, {
 713                 .name           = "csis",
 714                 .id             = 0,
 715                 .enable         = s5pv310_clk_ip_cam_ctrl,
 716                 .ctrlbit        = (1 << 4),
 717         }, {
 718                 .name           = "csis",
 719                 .id             = 1,
 720                 .enable         = s5pv310_clk_ip_cam_ctrl,
 721                 .ctrlbit        = (1 << 5),
 722         }, {
 723                 .name           = "jpeg",
 724                 .id             = -1,
 725                 .enable         = s5pv310_clk_ip_cam_ctrl,
 726                 .ctrlbit        = (1 << 6),
 727         }, {
 728                 .name           = "smmu_fimc",
 729                 .id             = 0,
 730                 .enable         = s5pv310_clk_ip_cam_ctrl,
 731                 .ctrlbit        = (1 << 7),
 732         }, {
 733                 .name           = "smmu_fimc",
 734                 .id             = 1,
 735                 .enable         = s5pv310_clk_ip_cam_ctrl,
 736                 .ctrlbit        = (1 << 8),
 737         }, {
 738                 .name           = "smmu_fimc",
 739                 .id             = 2,
 740                 .enable         = s5pv310_clk_ip_cam_ctrl,
 741                 .ctrlbit        = (1 << 9),
 742         }, {
 743                 .name           = "smmu_fimc",
 744                 .id             = 3,
 745                 .enable         = s5pv310_clk_ip_cam_ctrl,
 746                 .ctrlbit        = (1 << 10),
 747         }, {
 748                 .name           = "smmu_jpeg",
 749                 .id             = -1,
 750                 .enable         = s5pv310_clk_ip_cam_ctrl,
 751                 .ctrlbit        = (1 << 11),
 752         }, {
 753                 .name           = "qe_fimc",
 754                 .id             = 0,
 755                 .enable         = s5pv310_clk_ip_cam_ctrl,
 756                 .ctrlbit        = (1 << 12),
 757         }, {
 758                 .name           = "qe_fimc",
 759                 .id             = 1,
 760                 .enable         = s5pv310_clk_ip_cam_ctrl,
 761                 .ctrlbit        = (1 << 13),
 762         }, {
 763                 .name           = "qe_fimc",
 764                 .id             = 2,
 765                 .enable         = s5pv310_clk_ip_cam_ctrl,
 766                 .ctrlbit        = (1 << 14),
 767         }, {
 768                 .name           = "qe_fimc",
 769                 .id             = 3,
 770                 .enable         = s5pv310_clk_ip_cam_ctrl,
 771                 .ctrlbit        = (1 << 15),
 772         }, {
 773                 .name           = "ppmucamif",
 774                 .id             = -1,
 775                 .enable         = s5pv310_clk_ip_cam_ctrl,
 776                 .ctrlbit        = (1 << 16),
 777         }, {
 778                 .name           = "pixelasync_m0",
 779                 .id             = -1,
 780                 .enable         = s5pv310_clk_ip_cam_ctrl,
 781                 .ctrlbit        = (1 << 17),
 782         }, {
 783                 .name           = "pixelasync_m1",
 784                 .id             = -1,
 785                 .enable         = s5pv310_clk_ip_cam_ctrl,
 786                 .ctrlbit        = (1 << 18),
 787         }, {
 788                 .name           = "mfc",
 789                 .id             = -1,
 790                 .enable         = s5pv310_clk_ip_mfc_ctrl,
 791                 .ctrlbit        = (1 << 0),
 792         }, {
 793                 .name           = "fimd1",
 794                 .id             = -1,
 795                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
 796                 .ctrlbit        = (1 << 0),
 797         }, {
 798                 .name           = "mie1",
 799                 .id             = -1,
 800                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
 801                 .ctrlbit        = (1 << 1),
 802         }, {
 803                 .name           = "mdnie1",
 804                 .id             = -1,
 805                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
 806                 .ctrlbit        = (1 << 2),
 807         }, {
 808                 .name           = "dsim1",
 809                 .id             = -1,
 810                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
 811                 .ctrlbit        = (1 << 3),
 812         }, {
 813                 .name           = "smmu_fimd1",
 814                 .id             = -1,
 815                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
 816                 .ctrlbit        = (1 << 4),
 817         }, {
 818                 .name           = "ppmu_fimd1",
 819                 .id             = -1,
 820                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
 821                 .ctrlbit        = (1 << 5),
 822         }, {
 823                 .name           = "iis",
 824                 .id             = 0,
 825                 .enable         = s5pv310_clk_ip_peril_ctrl,
 826                 .ctrlbit        = (1 << 20),
 827         }, {
 828                 .name           = "iis",
 829                 .id             = 1,
 830                 .enable         = s5pv310_clk_ip_peril_ctrl,
 831                 .ctrlbit        = (1 << 21),
 832         }, {
 833                 .name           = "pcm",
 834                 .id             = 1,
 835                 .enable         = s5pv310_clk_ip_peril_ctrl,
 836                 .ctrlbit        = (1 << 22),
 837         }, {
 838                 .name           = "pcm",
 839                 .id             = 2,
 840                 .enable         = s5pv310_clk_ip_peril_ctrl,
 841                 .ctrlbit        = (1 << 23),
 842         }, {
 843                 .name           = "pciephy",
 844                 .id             = -1,
 845                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 846                 .ctrlbit        = (1 << 2),
 847         }, {
 848                 .name           = "sataphy",
 849                 .id             = -1,
 850                 .parent         = &clk_aclk_133.clk,
 851                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 852                 .ctrlbit        = (1 << 3),
 853         }, {
 854                 .name           = "tsi",
 855                 .id             = -1,
 856                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 857                 .ctrlbit        = (1 << 4),
 858         }, {
 859                 .name           = "hsmmc",
 860                 .id             = 0,
 861                 .parent         = &clk_aclk_133.clk,
 862                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 863                 .ctrlbit        = (1 << 5),
 864         }, {
 865                 .name           = "hsmmc",
 866                 .id             = 1,
 867                 .parent         = &clk_aclk_133.clk,
 868                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 869                 .ctrlbit        = (1 << 6),
 870         }, {
 871                 .name           = "hsmmc",
 872                 .id             = 2,
 873                 .parent         = &clk_aclk_133.clk,
 874                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 875                 .ctrlbit        = (1 << 7),
 876         }, {
 877                 .name           = "hsmmc",
 878                 .id             = 3,
 879                 .parent         = &clk_aclk_133.clk,
 880                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 881                 .ctrlbit        = (1 << 8),
 882         }, {
 883                 .name           = "dw_mmc",
 884                 .id             = -1,
 885                 .parent         = &clk_aclk_133.clk,
 886                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 887                 .ctrlbit        = (1 << 9),
 888         }, {
 889                 .name           = "sata",
 890                 .id             = -1,
 891                 .parent         = &clk_aclk_133.clk,
 892                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 893                 .ctrlbit        = (1 << 10),
 894         }, {
 895                 .name           = "sromc",
 896                 .id             = -1,
 897                 .enable         = s5pv310_clk_ip_fsys_ctrl ,
 898                 .ctrlbit        = (1 << 11),
 899         }, {
 900                 .name           = "usbhost",
 901                 .id             = -1,
 902                 .enable         = s5pv310_clk_ip_fsys_ctrl ,
 903                 .ctrlbit        = (1 << 12),
 904         }, {
 905                 .name           = "usbotg",
 906                 .id             = -1,
 907                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 908                 .ctrlbit        = (1 << 13),
 909         }, {
 910                 .name           = "pcie",
 911                 .id             = -1,
 912                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 913                 .ctrlbit        = (1 << 14),
 914         }, {
 915                 .name           = "onenand",
 916                 .id             = -1,
 917                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 918                 .ctrlbit        = (1 << 15),
 919         }, {
 920                 .name           = "nand",
 921                 .id             = -1,
 922                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 923                 .ctrlbit        = (1 << 16),
 924         }, {
 925                 .name           = "ppmufile",
 926                 .id             = -1,
 927                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 928                 .ctrlbit        = (1 << 17),
 929         }, {
 930                 .name           = "smmu_pcie",
 931                 .id             = -1,
 932                 .enable         = s5pv310_clk_ip_fsys_ctrl,
 933                 .ctrlbit        = (1 << 18),
 934         }, {
 935                 .name           = "chipid",
 936                 .id             = -1,
 937                 .enable         = s5pv310_clk_ip_perir_ctrl,
 938                 .ctrlbit        = (1 << 0),
 939         }, {
 940 #if 0
 941                 .name           = "sysreg",
 942                 .id             = -1,
 943                 .enable         = s5pv310_clk_ip_perir_ctrl,
 944                 .ctrlbit        = (1 << 1),
 945         }, {
 946                 .name           = "pmu_apbif",
 947                 .id             = -1,
 948                 .enable         = s5pv310_clk_ip_perir_ctrl,
 949                 .ctrlbit        = (1 << 2),
 950         }, {
 951                 .name           = "cmu_dmcpart",
 952                 .id             = -1,
 953                 .enable         = s5pv310_clk_ip_perir_ctrl,
 954                 .ctrlbit        = (1 << 4),
 955         }, {
 956 #endif
 957                 .name           = "tzpc0",
 958                 .id             = -1,
 959                 .enable         = s5pv310_clk_ip_perir_ctrl,
 960                 .ctrlbit        = (1 << 5),
 961         }, {
 962                 .name           = "tzpc1",
 963                 .id             = -1,
 964                 .enable         = s5pv310_clk_ip_perir_ctrl,
 965                 .ctrlbit        = (1 << 6),
 966         }, {
 967                 .name           = "tzpc2",
 968                 .id             = -1,
 969                 .enable         = s5pv310_clk_ip_perir_ctrl,
 970                 .ctrlbit        = (1 << 7),
 971         }, {
 972                 .name           = "tzpc3",
 973                 .id             = -1,
 974                 .enable         = s5pv310_clk_ip_perir_ctrl,
 975                 .ctrlbit        = (1 << 8),
 976         }, {
 977                 .name           = "tzpc4",
 978                 .id             = -1,
 979                 .enable         = s5pv310_clk_ip_perir_ctrl,
 980                 .ctrlbit        = (1 << 9),
 981         }, {
 982                 .name           = "tzpc5",
 983                 .id             = -1,
 984                 .enable         = s5pv310_clk_ip_perir_ctrl,
 985                 .ctrlbit        = (1 << 10),
 986         }, {
 987                 .name           = "hdmi_cec",
 988                 .id             = -1,
 989                 .enable         = s5pv310_clk_ip_perir_ctrl,
 990                 .ctrlbit        = (1 << 11),
 991         }, {
 992                 .name           = "seckey",
 993                 .id             = -1,
 994                 .enable         = s5pv310_clk_ip_perir_ctrl,
 995                 .ctrlbit        = (1 << 12),
 996         }, {
 997                 .name           = "watchdog",
 998                 .id             = -1,
 999                 .parent         = &clk_aclk_100.clk,
1000                 .enable         = s5pv310_clk_ip_perir_ctrl,
1001                 .ctrlbit        = (1 << 14),
1002         }, {
1003                 .name           = "rtc",
1004                 .id             = -1,
1005                 .enable         = s5pv310_clk_ip_perir_ctrl,
1006                 .ctrlbit        = (1 << 15),
1007         }, {
1008                 .name           = "keypad",
1009                 .id             = -1,
1010                 .enable         = s5pv310_clk_ip_perir_ctrl,
1011                 .ctrlbit        = (1 << 16),
1012         }, {
1013                 .name           = "tmu_apbif",
1014                 .id             = -1,
1015                 .enable         = s5pv310_clk_ip_perir_ctrl,
1016                 .ctrlbit        = (1 << 17),
1017         }, {
1018                 .name           = "uart",
1019                 .id             = 4,
1020                 .enable         = s5pv310_clk_ip_peril_ctrl,
1021                 .ctrlbit        = (1 << 4),
1022         }, {
1023                 .name           = "uart",
1024                 .id             = 5,
1025                 .enable         = s5pv310_clk_ip_peril_ctrl,
1026                 .ctrlbit        = (1 << 5),
1027         }, {
1028                 .name           = "i2c",
1029                 .id             = 0,
1030                 .parent         = &clk_aclk_100.clk,
1031                 .enable         = s5pv310_clk_ip_peril_ctrl,
1032                 .ctrlbit        = (1 << 6),
1033         }, {
1034                 .name           = "i2c",
1035                 .id             = 1,
1036                 .parent         = &clk_aclk_100.clk,
1037                 .enable         = s5pv310_clk_ip_peril_ctrl,
1038                 .ctrlbit        = (1 << 7),
1039         }, {
1040                 .name           = "i2c",
1041                 .id             = 2,
1042                 .parent         = &clk_aclk_100.clk,
1043                 .enable         = s5pv310_clk_ip_peril_ctrl,
1044                 .ctrlbit        = (1 << 8),
1045         }, {
1046                 .name           = "i2c",
1047                 .id             = 3,
1048                 .parent         = &clk_aclk_100.clk,
1049                 .enable         = s5pv310_clk_ip_peril_ctrl,
1050                 .ctrlbit        = (1 << 9),
1051         }, {
1052                 .name           = "i2c",
1053                 .id             = 4,
1054                 .parent         = &clk_aclk_100.clk,
1055                 .enable         = s5pv310_clk_ip_peril_ctrl,
1056                 .ctrlbit        = (1 << 10),
1057         }, {
1058                 .name           = "i2c",
1059                 .id             = 5,
1060                 .parent         = &clk_aclk_100.clk,
1061                 .enable         = s5pv310_clk_ip_peril_ctrl,
1062                 .ctrlbit        = (1 << 11),
1063         }, {
1064                 .name           = "i2c",
1065                 .id             = 6,
1066                 .parent         = &clk_aclk_100.clk,
1067                 .enable         = s5pv310_clk_ip_peril_ctrl,
1068                 .ctrlbit        = (1 << 12),
1069         }, {
1070                 .name           = "i2c",
1071                 .id             = 7,
1072                 .parent         = &clk_aclk_100.clk,
1073                 .enable         = s5pv310_clk_ip_peril_ctrl,
1074                 .ctrlbit        = (1 << 13),
1075         }, {
1076                 .name           = "i2c",
1077                 .id             = 8,
1078                 .parent         = &clk_aclk_100.clk,
1079                 .enable         = s5pv310_clk_ip_peril_ctrl,
1080                 .ctrlbit        = (1 << 14),
1081         }, {
1082                 .name           = "adc",
1083                 .id             = -1,
1084                 .enable         = s5pv310_clk_ip_peril_ctrl,
1085                 .ctrlbit        = (1 << 15),
1086         }, {
1087                 .name           = "spi",
1088                 .id             = 0,
1089                 .enable         = s5pv310_clk_ip_peril_ctrl,
1090                 .ctrlbit        = (1 << 16),
1091         }, {
1092                 .name           = "spi",
1093                 .id             = 1,
1094                 .enable         = s5pv310_clk_ip_peril_ctrl,
1095                 .ctrlbit        = (1 << 17),
1096         }, {
1097                 .name           = "spi",
1098                 .id             = 2,
1099                 .enable         = s5pv310_clk_ip_peril_ctrl,
1100                 .ctrlbit        = (1 << 18),
1101         }, {
1102                 .name           = "slimbus",
1103                 .id             = -1,
1104                 .enable         = s5pv310_clk_ip_peril_ctrl,
1105                 .ctrlbit        = (1 << 25),
1106         }, {
1107                 .name           = "spdif",
1108                 .id             = -1,
1109                 .enable         = s5pv310_clk_ip_peril_ctrl,
1110                 .ctrlbit        = (1 << 26),
1111         }, {
1112                 .name           = "ac97",
1113                 .id             = -1,
1114                 .parent         = &clk_aclk_100.clk,
1115                 .enable         = s5pv310_clk_ip_peril_ctrl,
1116                 .ctrlbit        = (1 << 27),
1117         }, {
1118                 .name           = "modem",
1119                 .id             = -1,
1120                 .parent         = &clk_aclk_100.clk,
1121                 .enable         = s5pv310_clk_ip_peril_ctrl,
1122                 .ctrlbit        = (1 << 28),
1123         }, {
1124                 .name           = "gps",
1125                 .id             = -1,
1126                 .enable         = s5pv310_clk_ip_gps_ctrl,
1127                 .ctrlbit        = (1 << 0),
1128         }, {
1129                 .name           = "iis",
1130                 .id             = -1,
1131                 .enable         = s5pv310_clk_audss_ctrl,
1132                 .ctrlbit        = (1 << 3) | (1 << 2),
1133         }, {
1134                 .name           = "pcm",
1135                 .id             = 0,
1136                 .enable         = s5pv310_clk_audss_ctrl,
1137                 .ctrlbit        = (1 << 5) | (1 << 4),
1138         }, {
1139                 .name           = "srp",
1140                 .id             = -1,
1141                 .enable         = s5pv310_clk_audss_ctrl,
1142                 .ctrlbit        = (1 << 8) | (1 << 7) | (1 << 6) | (1 << 0),
1143         }, {
1144                 .name           = "smmu_gps",
1145                 .id             = -1,
1146                 .enable         = s5pv310_clk_ip_gps_ctrl,
1147                 .ctrlbit        = (1 << 1),
1148         }, {
1149                 .name           = "g3d",
1150                 .id             = -1,
1151                 .enable         = s5pv310_clk_ip_g3d_ctrl,
1152                 .ctrlbit        = (1 << 0),
1153         }, {
1154                 .name           = "ppmug3d",
1155                 .id             = -1,
1156                 .enable         = s5pv310_clk_ip_g3d_ctrl,
1157                 .ctrlbit        = (1 << 1), /* No more exist in EVT1 ? */
1158         }, {
1159                 .name           = "qe_g3d",
1160                 .id             = -1,
1161                 .enable         = s5pv310_clk_ip_g3d_ctrl,
1162                 .ctrlbit        = (1 << 2),
1163         }, {
1164                 .name           = "fimg2d",
1165                 .id             = -1,
1166                 .enable         = s5pv310_clk_ip_image_ctrl,
1167                 .ctrlbit        = (1 << 0),
1168         }, {
1169                 .name           = "rotator",
1170                 .id             = -1,
1171                 .enable         = s5pv310_clk_ip_image_ctrl,
1172                 .ctrlbit        = (1 << 1),
1173         }, {
1174                 .name           = "smmu_fimg2d",
1175                 .id             = -1,
1176                 .enable         = s5pv310_clk_ip_image_ctrl,
1177                 .ctrlbit        = (1 << 3),
1178         }, {
1179                 .name           = "smmu_rotator",
1180                 .id             = -1,
1181                 .enable         = s5pv310_clk_ip_image_ctrl,
1182                 .ctrlbit        = (1 << 4),
1183         }, {
1184                 .name           = "qe_g2d",
1185                 .id             = -1,
1186                 .enable         = s5pv310_clk_ip_image_ctrl,
1187                 .ctrlbit        = (1 << 6),
1188         }, {
1189                 .name           = "qe_rotator",
1190                 .id             = -1,
1191                 .enable         = s5pv310_clk_ip_image_ctrl,
1192                 .ctrlbit        = (1 << 7),
1193         }, {
1194 #if 0 /* Controlled by dma:0 clock */
1195                 .name           = "qe_mdma",
1196                 .id             = -1,
1197                 .enable         = s5pv310_clk_ip_image_ctrl,
1198                 .ctrlbit        = (1 << 8),
1199         }, {
1200 #endif
1201                 .name           = "ppmuimage",
1202                 .id             = -1,
1203                 .enable         = s5pv310_clk_ip_image_ctrl,
1204                 .ctrlbit        = (1 << 9),
1205         }, {
1206                 .name           = "ppmu_fimd0",
1207                 .id             = -1,
1208                 .enable         = s5pv310_clk_ip_lcd0_ctrl,
1209                 .ctrlbit        = (1 << 5),
1210         }, {
1211                 .name           = "sysmmu",
1212                 .id             = SYSMMU_FIMC0,
1213                 .enable         = s5pv310_clk_ip_cam_ctrl,
1214                 .ctrlbit        = (1 << 7),
1215         }, {
1216                 .name           = "sysmmu",
1217                 .id             = SYSMMU_FIMC1,
1218                 .enable         = s5pv310_clk_ip_cam_ctrl,
1219                 .ctrlbit        = (1 << 8),
1220         }, {
1221                 .name           = "sysmmu",
1222                 .id             = SYSMMU_FIMC2,
1223                 .enable         = s5pv310_clk_ip_cam_ctrl,
1224                 .ctrlbit        = (1 << 9),
1225         }, {
1226                 .name           = "sysmmu",
1227                 .id             = SYSMMU_FIMC3,
1228                 .enable         = s5pv310_clk_ip_cam_ctrl,
1229                 .ctrlbit        = (1 << 10),
1230         }, {
1231                 .name           = "sysmmu",
1232                 .id             = SYSMMU_JPEG,
1233                 .enable         = s5pv310_clk_ip_cam_ctrl,
1234                 .ctrlbit        = (1 << 11),
1235         }, {
1236                 .name           = "sysmmu",
1237                 .id             = SYSMMU_FIMD0,
1238                 .enable         = s5pv310_clk_ip_lcd0_ctrl,
1239                 .ctrlbit        = (1 << 4),
1240         }, {
1241                 .name           = "sysmmu",
1242                 .id             = SYSMMU_FIMD1,
1243                 .enable         = s5pv310_clk_ip_lcd1_ctrl,
1244                 .ctrlbit        = (1 << 4),
1245         }, {
1246                 .name           = "sysmmu",
1247                 .id             = SYSMMU_PCIe,
1248                 .enable         = s5pv310_clk_ip_fsys_ctrl,
1249                 .ctrlbit        = (1 << 18),
1250         }, {
1251                 .name           = "sysmmu",
1252                 .id             = SYSMMU_G2D,
1253                 .enable         = s5pv310_clk_ip_image_ctrl,
1254                 .ctrlbit        = (1 << 3),
1255         }, {
1256                 .name           = "sysmmu",
1257                 .id             = SYSMMU_ROTATOR,
1258                 .enable         = s5pv310_clk_ip_image_ctrl,
1259                 .ctrlbit        = (1 << 4),
1260         }, {
1261                 .name           = "sysmmu",
1262                 .id             = SYSMMU_TV,
1263                 .enable         = s5pv310_clk_ip_tv_ctrl,
1264                 .ctrlbit        = (1 << 4),
1265         }, {
1266                 .name           = "sysmmu",
1267                 .id             = SYSMMU_MFC_L,
1268                 .enable         = s5pv310_clk_ip_mfc_ctrl,
1269                 .ctrlbit        = (1 << 1),
1270         }, {
1271                 .name           = "sysmmu",
1272                 .id             = SYSMMU_MFC_R,
1273                 .enable         = s5pv310_clk_ip_mfc_ctrl,
1274                 .ctrlbit        = (1 << 2),
1275         }, {
1276                 .name           = "ppmumfc_l",
1277                 .id             = -1,
1278                 .enable         = s5pv310_clk_ip_mfc_ctrl,
1279                 .ctrlbit        = (1 << 3),
1280         }, {
1281                 .name           = "ppmumfc_r",
1282                 .id             = -1,
1283                 .enable         = s5pv310_clk_ip_mfc_ctrl,
1284                 .ctrlbit        = (1 << 4),
1285         }, {
1286                 .name           = "dsim0",
1287                 .id             = -1,
1288                 .enable         = s5pv310_clk_ip_lcd0_ctrl,
1289                 .ctrlbit        = (1 << 3),
1290         }, {
1291                 .name           = "fimd_lite0",
1292                 .id             = -1,
1293                 .enable         = s5pv310_clk_ip_lcd0_ctrl,
1294                 .ctrlbit        = (1 << 2),
1295         }, {
1296                 .name           = "mie0",
1297                 .id             = -1,
1298                 .enable         = s5pv310_clk_ip_lcd0_ctrl,
1299                 .ctrlbit        = (1 << 1),
1300         }, {
1301                 .name           = "vp",
1302                 .id             = -1,
1303                 .enable         = s5pv310_clk_ip_tv_ctrl,
1304                 .ctrlbit        = (1 << 0),
1305         }, {
1306                 .name           = "mixer",
1307                 .id             = -1,
1308                 .enable         = s5pv310_clk_ip_tv_ctrl,
1309                 .ctrlbit        = (1 << 1),
1310         }, {
1311                 .name           = "dac",
1312                 .id             = -1,
1313                 .enable         = s5pv310_clk_ip_tv_ctrl,
1314                 .ctrlbit        = (1 << 2),
1315         }, {
1316                 .name           = "hdmi",
1317                 .id             = -1,
1318                 .enable         = s5pv310_clk_ip_tv_ctrl,
1319                 .ctrlbit        = (1 << 3),
1320         }, {
1321                 .name           = "smmu_tv",
1322                 .id             = -1,
1323                 .enable         = s5pv310_clk_ip_tv_ctrl,
1324                 .ctrlbit        = (1 << 4),
1325         }, {
1326                 .name           = "ppmutv",
1327                 .id             = -1,
1328                 .enable         = s5pv310_clk_ip_tv_ctrl,
1329                 .ctrlbit        = (1 << 5),
1330         }
1331 };
1332
1333 static struct clk init_dmaclocks[] = {
1334         {
1335                 .name           = "dma",
1336                 .id             = 0,
1337                 .enable         = s5pv310_clk_ip_image_ctrl,
1338                 .parent         = &init_clocks_disable[CLK_SMMU_MDMA],
1339                 .ctrlbit        = ((1 << 8) | (1 << 2)),
1340         }, {
1341                 .name           = "dma",
1342                 .id             = 1,
1343                 .enable         = s5pv310_clk_ip_fsys_ctrl,
1344                 .ctrlbit        = (1 << 0),
1345         }, {
1346                 .name           = "dma",
1347                 .id             = 2,
1348                 .parent         = &init_dmaclocks[1],
1349                 .enable         = s5pv310_clk_ip_fsys_ctrl,
1350                 .ctrlbit        = (1 << 1),
1351         },
1352 };
1353
1354 static struct clk *clkset_sclk_audio0_list[] = {
1355         [0] = &clk_audiocdclk0,
1356         [1] = NULL,
1357         [2] = &clk_sclk_hdmi27m,
1358         [3] = &clk_sclk_usbphy0,
1359         [4] = &clk_xxti,
1360         [5] = &clk_xusbxti,
1361         [6] = &clk_mout_mpll.clk,
1362         [7] = &clk_mout_epll.clk,
1363         [8] = &clk_sclk_vpll.clk,
1364 };
1365
1366 static struct clksrc_sources clkset_sclk_audio0 = {
1367         .sources        = clkset_sclk_audio0_list,
1368         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
1369 };
1370
1371 static struct clksrc_clk clk_sclk_audio0 = {
1372         .clk            = {
1373                 .name           = "audio-bus",
1374                 .id             = 0,
1375                 .enable         = s5pv310_clksrc_mask_maudio_ctrl,
1376                 .ctrlbit        = (1 << 0),
1377         },
1378         .sources = &clkset_sclk_audio0,
1379         .reg_src = { .reg = S5P_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
1380         .reg_div = { .reg = S5P_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
1381 };
1382
1383 static struct clk *clkset_mout_audss_list[] = {
1384         NULL,
1385         &clk_fout_epll,
1386 };
1387
1388 static struct clksrc_sources clkset_mout_audss = {
1389         .sources        = clkset_mout_audss_list,
1390         .nr_sources     = ARRAY_SIZE(clkset_mout_audss_list),
1391 };
1392
1393 static struct clksrc_clk clk_mout_audss = {
1394         .clk            = {
1395                 .name           = "mout_audss",
1396                 .id             = -1,
1397         },
1398         .sources        = &clkset_mout_audss,
1399         .reg_src        = { .reg = S5P_CLKSRC_AUDSS, .shift = 0, .size = 1 },
1400 };
1401
1402 static struct clk *clkset_sclk_audss_list[] = {
1403         &clk_mout_audss.clk,
1404         &clk_audiocdclk0,
1405         &clk_sclk_audio0.clk,
1406 };
1407
1408 static struct clksrc_sources clkset_sclk_audss = {
1409         .sources        = clkset_sclk_audss_list,
1410         .nr_sources     = ARRAY_SIZE(clkset_sclk_audss_list),
1411 };
1412
1413 static struct clksrc_clk clk_sclk_audss = {
1414         .clk            = {
1415                 .name           = "audio-bus",
1416                 .id             = -1,
1417                 .enable         = s5pv310_clk_audss_ctrl,
1418                 .ctrlbit        = S5P_AUDSS_CLKGATE_I2SBUS,
1419         },
1420         .sources        = &clkset_sclk_audss,
1421         .reg_src        = { .reg = S5P_CLKSRC_AUDSS, .shift = 2, .size = 2 },
1422         .reg_div        = { .reg = S5P_CLKDIV_AUDSS, .shift = 4, .size = 8 },
1423 };
1424
1425 static struct clk *clkset_sclk_audio1_list[] = {
1426         [0] = &clk_audiocdclk1,
1427         [1] = NULL,
1428         [2] = &clk_sclk_hdmi27m,
1429         [3] = &clk_sclk_usbphy0,
1430         [4] = &clk_xxti,
1431         [5] = &clk_xusbxti,
1432         [6] = &clk_mout_mpll.clk,
1433         [7] = &clk_mout_epll.clk,
1434         [8] = &clk_sclk_vpll.clk,
1435 };
1436
1437 static struct clksrc_sources clkset_sclk_audio1 = {
1438         .sources        = clkset_sclk_audio1_list,
1439         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
1440 };
1441
1442 static struct clksrc_clk clk_sclk_audio1 = {
1443                 .clk            = {
1444                 .name           = "audio-bus",
1445                 .id             = 1,
1446                 .enable         = s5pv310_clksrc_mask_peril1_ctrl,
1447                 .ctrlbit        = (1 << 0),
1448         },
1449         .sources = &clkset_sclk_audio1,
1450         .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 0, .size = 4 },
1451         .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 4, .size = 8 },
1452 };
1453
1454 static struct clk *clkset_sclk_audio2_list[] = {
1455         [0] = &clk_audiocdclk2,
1456         [1] = NULL,
1457         [2] = &clk_sclk_hdmi27m,
1458         [3] = &clk_sclk_usbphy0,
1459         [4] = &clk_xxti,
1460         [5] = &clk_xusbxti,
1461         [6] = &clk_mout_mpll.clk,
1462         [7] = &clk_mout_epll.clk,
1463         [8] = &clk_sclk_vpll.clk,
1464 };
1465
1466 static struct clksrc_sources clkset_sclk_audio2 = {
1467         .sources        = clkset_sclk_audio2_list,
1468         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
1469 };
1470
1471 static struct clksrc_clk clk_sclk_audio2 = {
1472         .clk    = {
1473                 .name           = "audio-bus",
1474                 .id             = 2,
1475                 .enable         = s5pv310_clksrc_mask_peril1_ctrl,
1476                 .ctrlbit        = (1 << 4),
1477         },
1478         .sources = &clkset_sclk_audio2,
1479         .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 4, .size = 4 },
1480         .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 16, .size = 4 },
1481 };
1482
1483 static struct clk *clkset_sclk_spdif_list[] = {
1484         [0] = &clk_sclk_audio0.clk,
1485         [1] = &clk_sclk_audio1.clk,
1486         [2] = &clk_sclk_audio2.clk,
1487         [3] = &clk_spdifcdclk,
1488 };
1489
1490 static struct clksrc_sources clkset_sclk_spdif = {
1491         .sources        = clkset_sclk_spdif_list,
1492         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
1493 };
1494
1495 static struct clksrc_clk clk_sclk_spdif = {
1496         .clk    = {
1497                 .name           = "sclk_spdif",
1498                 .id             = -1,
1499                 .enable         = s5pv310_clksrc_mask_peril1_ctrl,
1500                 .ctrlbit        = (1 << 8),
1501         },
1502         .sources = &clkset_sclk_spdif,
1503         .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 8, .size = 2 },
1504 };
1505
1506 static struct clk init_clocks[] = {
1507         {
1508                 .name           = "uart",
1509                 .id             = 0,
1510                 .enable         = s5pv310_clk_ip_peril_ctrl,
1511                 .ctrlbit        = (1 << 0),
1512         }, {
1513                 .name           = "uart",
1514                 .id             = 1,
1515                 .enable         = s5pv310_clk_ip_peril_ctrl,
1516                 .ctrlbit        = (1 << 1),
1517         }, {
1518                 .name           = "uart",
1519                 .id             = 2,
1520                 .enable         = s5pv310_clk_ip_peril_ctrl,
1521                 .ctrlbit        = (1 << 2),
1522         }, {
1523                 .name           = "uart",
1524                 .id             = 3,
1525                 .enable         = s5pv310_clk_ip_peril_ctrl,
1526                 .ctrlbit        = (1 << 3),
1527         }, {
1528                 .name           = "mctimer",
1529                 .id             = -1,
1530                 .enable         = s5pv310_clk_ip_perir_ctrl,
1531                 .ctrlbit        = (1 << 13),
1532         }, {
1533                 .name           = "fimd0",
1534                 .id             = -1,
1535                 .enable         = s5pv310_clk_ip_lcd0_ctrl,
1536                 .ctrlbit        = (1 << 0),
1537         }, {
1538                 .name           = "timers",
1539                 .id             = -1,
1540                 .parent         = &clk_aclk_100.clk,
1541                 .enable         = s5pv310_clk_ip_peril_ctrl,
1542                 .ctrlbit        = (1 << 24),
1543         }
1544 };
1545
1546 static struct clk *clkset_group_list[] = {
1547         [0] = &clk_xxti,
1548         [1] = &clk_xusbxti,
1549         [2] = &clk_sclk_hdmi27m,
1550         [3] = &clk_sclk_usbphy0,
1551         [4] = &clk_sclk_usbphy1,
1552         [5] = &clk_sclk_hdmiphy,
1553         [6] = &clk_mout_mpll.clk,
1554         [7] = &clk_mout_epll.clk,
1555         [8] = &clk_sclk_vpll.clk,
1556 };
1557
1558 static struct clksrc_sources clkset_group = {
1559         .sources        = clkset_group_list,
1560         .nr_sources     = ARRAY_SIZE(clkset_group_list),
1561 };
1562
1563 static struct clk *clkset_mout_mfc0_list[] = {
1564         [0] = &clk_mout_mpll.clk,
1565         [1] = &clk_sclk_apll.clk,
1566 };
1567
1568 static struct clksrc_sources clkset_mout_mfc0 = {
1569         .sources        = clkset_mout_mfc0_list,
1570         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
1571 };
1572
1573 static struct clksrc_clk clk_mout_mfc0 = {
1574         .clk    = {
1575                 .name           = "mout_mfc0",
1576                 .id             = -1,
1577         },
1578         .sources        = &clkset_mout_mfc0,
1579         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
1580 };
1581
1582 static struct clk *clkset_mout_mfc1_list[] = {
1583         [0] = &clk_mout_epll.clk,
1584         [1] = &clk_sclk_vpll.clk,
1585 };
1586
1587 static struct clksrc_sources clkset_mout_mfc1 = {
1588         .sources        = clkset_mout_mfc1_list,
1589         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
1590 };
1591
1592 static struct clksrc_clk clk_mout_mfc1 = {
1593         .clk    = {
1594                 .name           = "mout_mfc1",
1595                 .id             = -1,
1596         },
1597         .sources        = &clkset_mout_mfc1,
1598         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
1599 };
1600
1601 static struct clk *clkset_mout_mfc_list[] = {
1602         [0] = &clk_mout_mfc0.clk,
1603         [1] = &clk_mout_mfc1.clk,
1604 };
1605
1606 static struct clksrc_sources clkset_mout_mfc = {
1607         .sources        = clkset_mout_mfc_list,
1608         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
1609 };
1610
1611 static struct clk *clkset_mout_g2d0_list[] = {
1612         [0] = &clk_mout_mpll.clk,
1613         [1] = &clk_sclk_apll.clk,
1614 };
1615
1616 static struct clksrc_sources clkset_mout_g2d0 = {
1617         .sources        = clkset_mout_g2d0_list,
1618         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
1619 };
1620
1621 static struct clksrc_clk clk_mout_g2d0 = {
1622         .clk    = {
1623                 .name           = "mout_g2d0",
1624                 .id             = -1,
1625         },
1626         .sources        = &clkset_mout_g2d0,
1627         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
1628 };
1629
1630 static struct clk *clkset_mout_g2d1_list[] = {
1631         [0] = &clk_mout_epll.clk,
1632         [1] = &clk_sclk_vpll.clk,
1633 };
1634
1635 static struct clksrc_sources clkset_mout_g2d1 = {
1636         .sources        = clkset_mout_g2d1_list,
1637         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
1638 };
1639
1640 static struct clksrc_clk clk_mout_g2d1 = {
1641         .clk    = {
1642                 .name           = "mout_g2d1",
1643                 .id             = -1,
1644         },
1645         .sources        = &clkset_mout_g2d1,
1646         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
1647 };
1648
1649 static struct clk *clkset_mout_g2d_list[] = {
1650         [0] = &clk_mout_g2d0.clk,
1651         [1] = &clk_mout_g2d1.clk,
1652 };
1653
1654 static struct clksrc_sources clkset_mout_g2d = {
1655         .sources        = clkset_mout_g2d_list,
1656         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
1657 };
1658
1659 static struct clksrc_clk clk_dout_mmc0 = {
1660         .clk            = {
1661                 .name           = "dout_mmc0",
1662                 .id             = -1,
1663         },
1664         .sources = &clkset_group,
1665         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
1666         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1667 };
1668
1669 static struct clksrc_clk clk_dout_mmc1 = {
1670         .clk            = {
1671                 .name           = "dout_mmc1",
1672                 .id             = -1,
1673         },
1674         .sources = &clkset_group,
1675         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
1676         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1677 };
1678
1679 static struct clksrc_clk clk_dout_mmc2 = {
1680         .clk            = {
1681                 .name           = "dout_mmc2",
1682                 .id             = -1,
1683         },
1684         .sources = &clkset_group,
1685         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
1686         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1687 };
1688
1689 static struct clksrc_clk clk_dout_mmc3 = {
1690         .clk            = {
1691                 .name           = "dout_mmc3",
1692                 .id             = -1,
1693         },
1694         .sources = &clkset_group,
1695         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1696         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1697 };
1698
1699 static struct clksrc_clk clk_dout_mmc4 = {
1700         .clk            = {
1701                 .name           = "dout_mmc4",
1702                 .id             = -1,
1703         },
1704         .sources = &clkset_group,
1705         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1706         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1707 };
1708
1709 static struct clksrc_clk clk_sclk_mfc = {
1710         .clk            = {
1711                 .name           = "sclk_mfc",
1712                 .id             = -1,
1713         },
1714         .sources = &clkset_mout_mfc,
1715         .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1716         .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1717 };
1718
1719 static struct clksrc_clk clk_sclk_g3d = {
1720         .clk            = {
1721                 .name           = "sclk_g3d",
1722                 .id             = -1,
1723         },
1724         .sources = &clkset_mout_g3d,
1725         .reg_src = { .reg = S5P_CLKSRC_G3D, .shift = 8, .size = 1 },
1726         .reg_div = { .reg = S5P_CLKDIV_G3D, .shift = 0, .size = 4 },
1727 };
1728
1729 static struct clksrc_clk clk_sclk_g2d = {
1730         .clk            = {
1731                 .name           = "sclk_fimg2d",
1732                 .id             = -1,
1733         },
1734         .sources = &clkset_mout_g2d,
1735         .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1736         .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1737 };
1738
1739 static struct clksrc_clk clk_cam_a_clk = {
1740         .clk            = {
1741                 .name           = "sclk_cam",
1742                 .id             = 0,
1743                 .enable         = s5pv310_clksrc_mask_cam_ctrl,
1744                 .ctrlbit        = (1 << 16),
1745         },
1746         .sources = &clkset_group,
1747         .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1748         .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1749 };
1750
1751 static struct clksrc_clk clk_cam_b_clk = {
1752         .clk            = {
1753                 .name           = "sclk_cam",
1754                 .id             = 1,
1755                 .enable         = s5pv310_clksrc_mask_cam_ctrl,
1756                 .ctrlbit        = (1 << 20),
1757         },
1758         .sources = &clkset_group,
1759         .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1760         .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1761 };
1762
1763
1764
1765 static struct clk *clkset_cmu_dmc_list[] = {
1766         [0] = &clk_aclk_cored.clk,
1767         [1] = &clk_aclk_corep.clk,
1768         [2] = &clk_aclk_acp.clk,
1769         [3] = &clk_pclk_acp.clk,
1770         [4] = &clk_sclk_dmc.clk,
1771         [5] = NULL, /* SCLK_DPHY */
1772         [6] = NULL, /* SCLK_CORE_TIMERS */
1773         [7] = NULL, /* SCLK_PWI */
1774 };
1775 static struct clksrc_sources clkset_cmu_dmc = {
1776         .sources        = clkset_cmu_dmc_list,
1777         .nr_sources     = ARRAY_SIZE(clkset_cmu_dmc_list),
1778 };
1779 static struct clksrc_clk clk_cmu_dmc = {
1780         .clk            = {
1781                 .name           = "cmu_dmc",
1782                 .id             = -1,
1783         },
1784         .sources = &clkset_cmu_dmc,
1785         .reg_src = { .reg = S5P_CLKOUT_CMU_DMC, .shift = 0, .size = 5 },
1786         .reg_div = { .reg = S5P_CLKOUT_CMU_DMC, .shift = 8, .size = 6 },
1787 };
1788
1789 static struct clk *clkset_cmu_top_list[] = {
1790         [0] = &clk_fout_epll,
1791         [1] = &clk_fout_vpll,
1792         [2] = &clk_sclk_hdmi27m,
1793         [3] = &clk_sclk_usbphy0,
1794         [4] = &clk_sclk_usbphy1,
1795         [5] = &clk_sclk_hdmiphy,
1796         [6] = &clk_audiocdclk0,
1797         [7] = &clk_audiocdclk1,
1798         [8] = &clk_audiocdclk2,
1799         [9] = &clk_spdifcdclk,
1800         [10] = &clk_aclk_160.clk,
1801         [11] = &clk_aclk_133.clk,
1802         [12] = &clk_aclk_200.clk,
1803         [13] = &clk_aclk_100.clk,
1804         [14] = &clk_sclk_mfc.clk,
1805         [15] = &clk_sclk_g3d.clk,
1806         [16] = &clk_sclk_g2d.clk,
1807         [17] = &clk_cam_a_clk.clk,
1808         [18] = &clk_cam_b_clk.clk,
1809         [19] = NULL, /* S_RXBYTECLKHS0_2L */
1810         [20] = NULL, /* S_RXBYTECLKHS0_4L */
1811         [21] = NULL, /* RX_HALF_BYTE_CLK_CSIS0 */
1812         [22] = NULL, /* RX_HALF_BYTE_CLK_CSIS1 */
1813 };
1814 static struct clksrc_sources clkset_cmu_top = {
1815         .sources        = clkset_cmu_top_list,
1816         .nr_sources     = ARRAY_SIZE(clkset_cmu_top_list),
1817 };
1818 static struct clksrc_clk clk_cmu_top = {
1819         .clk            = {
1820                 .name           = "cmu_top",
1821                 .id             = -1,
1822         },
1823         .sources = &clkset_cmu_top,
1824         .reg_src = { .reg = S5P_CLKOUT_CMU_TOP, .shift = 0, .size = 5 },
1825         .reg_div = { .reg = S5P_CLKOUT_CMU_TOP, .shift = 8, .size = 6 },
1826 };
1827
1828 static struct clk *clkset_cmu_leftbus_list[] = {
1829         [0] = NULL, /* SCLK_MPLL/2 */
1830         [1] = NULL, /* SCLK_APLL/2 */
1831         [2] = &clk_aclk_gdl.clk,
1832         [3] = &clk_aclk_gpl.clk,
1833 };
1834 static struct clksrc_sources clkset_cmu_leftbus = {
1835         .sources        = clkset_cmu_leftbus_list,
1836         .nr_sources     = ARRAY_SIZE(clkset_cmu_leftbus_list),
1837 };
1838 static struct clksrc_clk clk_cmu_leftbus = {
1839         .clk            = {
1840                 .name           = "cmu_leftbus",
1841                 .id             = -1,
1842         },
1843         .sources = &clkset_cmu_leftbus,
1844         .reg_src = { .reg = S5P_CLKOUT_CMU_LEFTBUS, .shift = 0, .size = 5 },
1845         .reg_div = { .reg = S5P_CLKOUT_CMU_LEFTBUS, .shift = 8, .size = 6 },
1846 };
1847
1848 static struct clk *clkset_cmu_rightbus_list[] = {
1849         [0] = NULL, /* SCLK_MPLL/2 */
1850         [1] = NULL, /* SCLK_APLL/2 */
1851         [2] = &clk_aclk_gdr.clk,
1852         [3] = &clk_aclk_gpr.clk,
1853 };
1854 static struct clksrc_sources clkset_cmu_rightbus = {
1855         .sources        = clkset_cmu_rightbus_list,
1856         .nr_sources     = ARRAY_SIZE(clkset_cmu_rightbus_list),
1857 };
1858 static struct clksrc_clk clk_cmu_rightbus = {
1859         .clk            = {
1860                 .name           = "cmu_rightbus",
1861                 .id             = -1,
1862         },
1863         .sources = &clkset_cmu_rightbus,
1864         .reg_src = { .reg = S5P_CLKOUT_CMU_RIGHTBUS, .shift = 0, .size = 5 },
1865         .reg_div = { .reg = S5P_CLKOUT_CMU_RIGHTBUS, .shift = 8, .size = 6 },
1866 };
1867
1868 static struct clk *clkset_cmu_cpu_list[] = {
1869         [0] = NULL, /* APLL_FOUT/2 */
1870         [1] = NULL, /* APLL_VCOOUT/4 */
1871         [2] = NULL, /* MPLL_FOUT/2 */
1872         [3] = NULL, /* MPLL_VCOOUT/4 */
1873         [4] = NULL, /* ARMCLK/2 */
1874         [5] = &clk_aclk_corem0.clk,
1875         [6] = &clk_aclk_corem1.clk,
1876         [7] = &clk_aclk_cores.clk,
1877         [8] = NULL, /* ATCLK (ATB) (CLKDIV_CPU) */
1878         [9] = &clk_periphclk.clk,
1879         [10] = NULL, /* PCLK_DBG (CLKDIV_CPU) */
1880         [11] = NULL, /* SCLK_HPM (CLKDIV_CPU) */
1881 };
1882 static struct clksrc_sources clkset_cmu_cpu = {
1883         .sources        = clkset_cmu_cpu_list,
1884         .nr_sources     = ARRAY_SIZE(clkset_cmu_cpu_list),
1885 };
1886 static struct clksrc_clk clk_cmu_cpu = {
1887         .clk            = {
1888                 .name           = "cmu_cpu",
1889                 .id             = -1,
1890         },
1891         .sources = &clkset_cmu_cpu,
1892         .reg_src = { .reg = S5P_CLKOUT_CMU_CPU, .shift = 0, .size = 5 },
1893         .reg_div = { .reg = S5P_CLKOUT_CMU_CPU, .shift = 8, .size = 6 },
1894 };
1895
1896 static struct clk *clkset_xclkout_list[] = {
1897         [0] = &clk_cmu_dmc.clk,
1898         [1] = &clk_cmu_top.clk,
1899         [2] = &clk_cmu_leftbus.clk,
1900         [3] = &clk_cmu_rightbus.clk,
1901         [4] = &clk_cmu_cpu.clk,
1902         [5] = NULL, /* N/A */
1903         [6] = NULL, /* N/A */
1904         [7] = NULL, /* N/A */
1905         [8] = NULL,     /* XXTI */
1906         [9] = &clk_xusbxti,
1907         [10] = NULL, /* N/A */
1908         [11] = NULL, /* N/A */
1909         [12] = NULL, /* RTC_TICK_SRC */
1910         [13] = NULL, /* RTCCLK */
1911 };
1912 static struct clksrc_sources clkset_xclkout = {
1913         .sources        = clkset_xclkout_list,
1914         .nr_sources     = ARRAY_SIZE(clkset_xclkout_list),
1915 };
1916 static struct clksrc_clk clk_xclkout = {
1917         .clk            = {
1918                 .name           = "xclkout",
1919                 .id             = -1,
1920         },
1921         .sources = &clkset_xclkout,
1922         .reg_src = { .reg = S5P_PMU_DEBUG, .shift = 8, .size = 4 },
1923 };
1924
1925 static struct clksrc_clk clksrcs[] = {
1926         {
1927                 .clk    = {
1928                         .name           = "uclk1",
1929                         .id             = 0,
1930                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
1931                         .ctrlbit        = (1 << 0),
1932                 },
1933                 .sources = &clkset_group,
1934                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1935                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1936         }, {
1937                 .clk            = {
1938                         .name           = "uclk1",
1939                         .id             = 1,
1940                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
1941                         .ctrlbit        = (1 << 4),
1942                 },
1943                 .sources = &clkset_group,
1944                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1945                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1946         }, {
1947                 .clk            = {
1948                         .name           = "uclk1",
1949                         .id             = 2,
1950                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
1951                         .ctrlbit        = (1 << 8),
1952                 },
1953                 .sources = &clkset_group,
1954                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1955                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1956         }, {
1957                 .clk            = {
1958                         .name           = "uclk1",
1959                         .id             = 3,
1960                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
1961                         .ctrlbit        = (1 << 12),
1962                 },
1963                 .sources = &clkset_group,
1964                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1965                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1966         }, {
1967                 .clk            = {
1968                         .name           = "uclk1",
1969                         .id             = 4,
1970                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
1971                         .ctrlbit        = (1 << 16),
1972                 },
1973                 .sources = &clkset_group,
1974                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 16, .size = 4 },
1975                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 16, .size = 4 },
1976         }, {
1977                 .clk            = {
1978                         .name           = "sclk_pwm",
1979                         .id             = -1,
1980                         .enable         = s5pv310_clksrc_mask_peril0_ctrl,
1981                         .ctrlbit        = (1 << 24),
1982                         /* All the three regs are not in the user manual. */
1983                 },
1984                 .sources = &clkset_group,
1985                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1986                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1987         }, {
1988                 .clk            = {
1989                         .name           = "sclk_csis",
1990                         .id             = 0,
1991                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
1992                         .ctrlbit        = (1 << 24),
1993                 },
1994                 .sources = &clkset_group,
1995                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1996                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1997         }, {
1998                 .clk            = {
1999                         .name           = "sclk_csis",
2000                         .id             = 1,
2001                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
2002                         .ctrlbit        = (1 << 28),
2003                 },
2004                 .sources = &clkset_group,
2005                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
2006                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
2007         }, {
2008                 .clk            = {
2009                         .name           = "sclk_cam0",
2010                         .id             = -1,
2011                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
2012                         .ctrlbit        = (1 << 16),
2013                 },
2014                 .sources = &clkset_group,
2015                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
2016                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
2017         }, {
2018                 .clk            = {
2019                         .name           = "sclk_fimc",
2020                         .id             = 0,
2021                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
2022                         .ctrlbit        = (1 << 0),
2023                 },
2024                 .sources = &clkset_group,
2025                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
2026                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
2027         }, {
2028                 .clk            = {
2029                         .name           = "sclk_fimc",
2030                         .id             = 1,
2031                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
2032                         .ctrlbit        = (1 << 4),
2033                 },
2034                 .sources = &clkset_group,
2035                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
2036                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
2037         }, {
2038                 .clk            = {
2039                         .name           = "sclk_fimc",
2040                         .id             = 2,
2041                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
2042                         .ctrlbit        = (1 << 8),
2043                 },
2044                 .sources = &clkset_group,
2045                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
2046                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
2047         }, {
2048                 .clk            = {
2049                         .name           = "sclk_fimc",
2050                         .id             = 3,
2051                         .enable         = s5pv310_clksrc_mask_cam_ctrl,
2052                         .ctrlbit        = (1 << 12),
2053                 },
2054                 .sources = &clkset_group,
2055                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
2056                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
2057         }, {
2058                 .clk            = {
2059                         .name           = "sclk_fimd0",
2060                         .id             = -1,
2061                         .enable         = s5pv310_clksrc_mask_lcd0_ctrl,
2062                         .ctrlbit        = (1 << 0),
2063                 },
2064                 .sources = &clkset_group,
2065                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
2066                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
2067         }, {
2068                 .clk            = {
2069                         .name           = "sclk_fimd1",
2070                         .id             = -1,
2071                         .enable         = s5pv310_clksrc_mask_lcd1_ctrl,
2072                         .ctrlbit        = (1 << 0),
2073                 },
2074                 .sources = &clkset_group,
2075                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
2076                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
2077         }, {
2078                 .clk            = {
2079                         .name           = "sclk_mdnie0",
2080                         .id             = -1,
2081                         .enable         = s5pv310_clksrc_mask_lcd0_ctrl,
2082                         .ctrlbit        = (1 << 2),
2083                 },
2084                 .sources = &clkset_group,
2085                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 4, .size = 4 },
2086                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 4, .size = 4 },
2087         }, {
2088                 .clk            = {
2089                         .name           = "sclk_sata",
2090                         .id             = -1,
2091                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
2092                         .ctrlbit        = (1 << 24),
2093                 },
2094                 .sources = &clkset_mout_corebus,
2095                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
2096                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
2097         }, {
2098                 .clk            = {
2099                         .name           = "sclk_spi",
2100                         .id             = 0,
2101                         .enable         = s5pv310_clksrc_mask_peril1_ctrl,
2102                         .ctrlbit        = (1 << 16),
2103                 },
2104                 .sources = &clkset_group,
2105                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
2106                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 8, .size = 8 },
2107         }, {
2108                 .clk            = {
2109                         .name           = "sclk_spi",
2110                         .id             = 1,
2111                         .enable         = s5pv310_clksrc_mask_peril1_ctrl,
2112                         .ctrlbit        = (1 << 20),
2113                 },
2114                 .sources = &clkset_group,
2115                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
2116                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 24, .size = 8 },
2117         }, {
2118                 .clk            = {
2119                         .name           = "sclk_spi",
2120                         .id             = 2,
2121                         .enable         = s5pv310_clksrc_mask_peril1_ctrl,
2122                         .ctrlbit        = (1 << 24),
2123                 },
2124                 .sources = &clkset_group,
2125                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
2126                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 8, .size = 8 },
2127         }, {
2128                 .clk            = {
2129                         .name           = "sclk_mmc",
2130                         .id             = 0,
2131                         .parent         = &clk_dout_mmc0.clk,
2132                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
2133                         .ctrlbit        = (1 << 0),
2134                 },
2135                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
2136         }, {
2137                 .clk            = {
2138                         .name           = "sclk_mmc",
2139                         .id             = 1,
2140                         .parent         = &clk_dout_mmc1.clk,
2141                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
2142                         .ctrlbit        = (1 << 4),
2143                 },
2144                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
2145         }, {
2146                 .clk            = {
2147                         .name           = "sclk_mmc",
2148                         .id             = 2,
2149                         .parent         = &clk_dout_mmc2.clk,
2150                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
2151                         .ctrlbit        = (1 << 8),
2152                 },
2153                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
2154         }, {
2155                 .clk            = {
2156                         .name           = "sclk_mmc",
2157                         .id             = 3,
2158                         .parent         = &clk_dout_mmc3.clk,
2159                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
2160                         .ctrlbit        = (1 << 12),
2161                 },
2162                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
2163         }, {
2164                 .clk            = {
2165                         .name           = "sclk_dw_mmc",
2166                         .id             = -1,
2167                         .parent         = &clk_dout_mmc4.clk,
2168                         .enable         = s5pv310_clksrc_mask_fsys_ctrl,
2169                         .ctrlbit        = (1 << 16),
2170                 },
2171                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
2172         }, {
2173                 .clk            = {
2174                         .name           = "sclk_pcm",
2175                         .id             = 0,
2176                         .parent         = &clk_sclk_audio0.clk,
2177                 },
2178                 .reg_div = { .reg = S5P_CLKDIV_MAUDIO, .shift = 4, .size = 8 },
2179         }, {
2180                 .clk            = {
2181                         .name           = "sclk_pcm",
2182                         .id             = 1,
2183                         .parent         = &clk_sclk_audio1.clk,
2184                 },
2185                 .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 4, .size = 8 },
2186         }, {
2187                 .clk            = {
2188                         .name           = "sclk_pcm",
2189                         .id             = 2,
2190                         .parent         = &clk_sclk_audio2.clk,
2191                 },
2192                 .reg_div = { .reg = S5P_CLKDIV_PERIL4, .shift = 20, .size = 8 },
2193         }, {
2194                 .clk            = {
2195                         .name           = "sclk_i2s",
2196                         .id             = 1,
2197                         .parent         = &clk_sclk_audio1.clk,
2198                 },
2199                 .reg_div = { .reg = S5P_CLKDIV_PERIL5, .shift = 0, .size = 6 },
2200         }, {
2201                 .clk            = {
2202                         .name           = "sclk_i2s",
2203                         .id             = 2,
2204                         .parent         = &clk_sclk_audio2.clk,
2205                 },
2206                 .reg_div = { .reg = S5P_CLKDIV_PERIL5, .shift = 8, .size = 6 },
2207         }, {
2208                 .clk            = {
2209                         .name           = "sclk_hpm",
2210                         .id             = -1,
2211                         .parent         = &clk_dout_copy.clk,
2212                 },
2213                 .reg_div = { .reg = S5P_CLKDIV_CPU1, .shift = 4, .size = 3 },
2214         }, {
2215                 .clk            = {
2216                         .name           = "sclk_pwi",
2217                         .id             = -1,
2218                 },
2219                 .sources = &clkset_group,
2220                 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 16, .size = 4 },
2221                 .reg_div = { .reg = S5P_CLKDIV_DMC1, .shift = 8, .size = 4 },
2222         },
2223 };
2224
2225 /* Clock initialization code */
2226 static struct clksrc_clk *sysclks[] = {
2227         &clk_mout_apll,
2228         &clk_sclk_apll,
2229         &clk_mout_epll,
2230         &clk_mout_mpll,
2231         &clk_moutcore,
2232         &clk_coreclk,
2233         &clk_armclk,
2234         &clk_aclk_corem0,
2235         &clk_aclk_cores,
2236         &clk_aclk_corem1,
2237         &clk_periphclk,
2238         &clk_mout_corebus,
2239         &clk_sclk_dmc,
2240         &clk_aclk_cored,
2241         &clk_aclk_corep,
2242         &clk_aclk_acp,
2243         &clk_pclk_acp,
2244         &clk_vpllsrc,
2245         &clk_sclk_vpll,
2246         &clk_aclk_200,
2247         &clk_aclk_100,
2248         &clk_aclk_160,
2249         &clk_aclk_133,
2250         &clk_aclk_gdl,
2251         &clk_aclk_gpl,
2252         &clk_aclk_gdr,
2253         &clk_aclk_gpr,
2254         &clk_dout_mmc0,
2255         &clk_dout_mmc1,
2256         &clk_dout_mmc2,
2257         &clk_dout_mmc3,
2258         &clk_dout_mmc4,
2259         &clk_mout_audss,
2260         &clk_sclk_audss,
2261         &clk_sclk_audio0,
2262         &clk_sclk_audio1,
2263         &clk_sclk_audio2,
2264         &clk_sclk_spdif,
2265         &clk_mout_g2d0,
2266         &clk_mout_g2d1,
2267         &clk_mout_g3d0,
2268         &clk_mout_g3d1,
2269         &clk_mout_mfc0,
2270         &clk_mout_mfc1,
2271         &clk_dout_copy,
2272         &clk_sclk_mfc,
2273         &clk_sclk_g3d,
2274         &clk_sclk_g2d,
2275         &clk_cam_a_clk,
2276         &clk_cam_b_clk,
2277         &clk_cmu_dmc,
2278         &clk_cmu_top,
2279         &clk_cmu_leftbus,
2280         &clk_cmu_rightbus,
2281         &clk_cmu_cpu,
2282         &clk_xclkout,
2283 };
2284
2285 static unsigned long s5pv310_epll_get_rate(struct clk *clk)
2286 {
2287         return clk->rate;
2288 }
2289
2290 static u32 epll_div[][6] = {
2291         {  48000000, 0, 48, 3, 3, 0 },
2292         {  96000000, 0, 48, 3, 2, 0 },
2293         { 144000000, 1, 72, 3, 2, 0 },
2294         { 192000000, 0, 48, 3, 1, 0 },
2295         { 288000000, 1, 72, 3, 1, 0 },
2296         {  84000000, 0, 42, 3, 2, 0 },
2297         {  50000000, 0, 50, 3, 3, 0 },
2298         {  80000000, 1, 80, 3, 3, 0 },
2299         {  32750000, 1, 65, 3, 4, 35127 },
2300         {  32768000, 1, 65, 3, 4, 35127 },
2301         {  49152000, 0, 49, 3, 3, 9961 },
2302         {  67737600, 1, 67, 3, 3, 48366 },
2303         {  73728000, 1, 73, 3, 3, 47710 },
2304         {  45158400, 0, 45, 3, 3, 10381 },
2305         {  45000000, 0, 45, 3, 3, 10355 },
2306         {  45158000, 0, 45, 3, 3, 10355 },
2307         {  49125000, 0, 49, 3, 3, 9961 },
2308         {  67738000, 1, 67, 3, 3, 48366 },
2309         {  73800000, 1, 73, 3, 3, 47710 },
2310         {  36000000, 1, 32, 3, 4, 0 },
2311         {  60000000, 1, 60, 3, 3, 0 },
2312         {  72000000, 1, 72, 3, 3, 0 },
2313 };
2314
2315 static int s5pv310_epll_set_rate(struct clk *clk, unsigned long rate)
2316 {
2317         unsigned int epll_con, epll_con_k;
2318         unsigned int i;
2319
2320         /* Return if nothing changed */
2321         if (clk->rate == rate)
2322                 return 0;
2323
2324         epll_con = __raw_readl(S5P_EPLL_CON0);
2325         epll_con &= ~(0x1 << 27 | \
2326                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
2327                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
2328                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
2329
2330         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
2331                 if (epll_div[i][0] == rate) {
2332                         epll_con_k = epll_div[i][5] << 0;
2333                         epll_con |= epll_div[i][1] << 27;
2334                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
2335                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
2336                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
2337                         break;
2338                 }
2339         }
2340
2341         if (i == ARRAY_SIZE(epll_div)) {
2342                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
2343                                 __func__);
2344                 return -EINVAL;
2345         }
2346
2347         __raw_writel(epll_con, S5P_EPLL_CON0);
2348         __raw_writel(epll_con_k, S5P_EPLL_CON1);
2349
2350         clk->rate = rate;
2351
2352         return 0;
2353 }
2354
2355 static struct clk_ops s5pv310_epll_ops = {
2356         .get_rate = s5pv310_epll_get_rate,
2357         .set_rate = s5pv310_epll_set_rate,
2358 };
2359
2360
2361 struct vpll_div_data {
2362         u32 rate;
2363         u32 pdiv;
2364         u32 mdiv;
2365         u32 sdiv;
2366         u32 k;
2367         u32 mfr;
2368         u32 mrr;
2369         u32 vsel;
2370
2371 };
2372
2373 static struct vpll_div_data vpll_div[] = {
2374         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
2375         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
2376 };
2377
2378 static unsigned long s5pv310_vpll_get_rate(struct clk *clk)
2379 {
2380         return clk->rate;
2381 }
2382
2383 static int s5pv310_vpll_set_rate(struct clk *clk, unsigned long rate)
2384 {
2385         unsigned int vpll_con0, vpll_con1;
2386         unsigned int i;
2387
2388         /* Return if nothing changed */
2389         if (clk->rate == rate)
2390                 return 0;
2391
2392         vpll_con0 = __raw_readl(S5P_VPLL_CON0);
2393         vpll_con0 &= ~(0x1 << 27 |                                      \
2394                         PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT |       \
2395                         PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT |       \
2396                         PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
2397
2398         vpll_con1 = __raw_readl(S5P_VPLL_CON1);
2399         vpll_con1 &= ~(0x1f << 24 |     \
2400                         0x3f << 16 |    \
2401                         0xfff << 0);
2402
2403         for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
2404                 if (vpll_div[i].rate == rate) {
2405                         vpll_con0 |= vpll_div[i].vsel << 27;
2406                         vpll_con0 |= vpll_div[i].pdiv << PLL90XX_PDIV_SHIFT;
2407                         vpll_con0 |= vpll_div[i].mdiv << PLL90XX_MDIV_SHIFT;
2408                         vpll_con0 |= vpll_div[i].sdiv << PLL90XX_SDIV_SHIFT;
2409
2410                         vpll_con1 |= vpll_div[i].mrr << 24;
2411                         vpll_con1 |= vpll_div[i].mfr << 16;
2412                         vpll_con1 |= vpll_div[i].k << 0;
2413                         break;
2414                 }
2415         }
2416
2417         if (i == ARRAY_SIZE(vpll_div)) {
2418                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
2419                                 __func__);
2420                 return -EINVAL;
2421         }
2422
2423         __raw_writel(vpll_con0, S5P_VPLL_CON0);
2424         __raw_writel(vpll_con1, S5P_VPLL_CON1);
2425
2426         clk->rate = rate;
2427
2428         return 0;
2429 }
2430
2431 static struct clk_ops s5pv310_vpll_ops = {
2432         .get_rate = s5pv310_vpll_get_rate,
2433         .set_rate = s5pv310_vpll_set_rate,
2434 };
2435
2436 static int xtal_rate;
2437
2438 static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
2439 {
2440         return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
2441 }
2442
2443 static struct clk_ops s5pv310_fout_apll_ops = {
2444         .get_rate = s5pv310_fout_apll_get_rate,
2445 };
2446
2447 void __init_or_cpufreq s5pv310_setup_clocks(void)
2448 {
2449         struct clk *xtal_clk;
2450         unsigned long apll;
2451         unsigned long mpll;
2452         unsigned long epll;
2453         unsigned long vpll;
2454         unsigned long vpllsrc;
2455         unsigned long xtal;
2456         unsigned long armclk;
2457         unsigned long sclk_dmc;
2458         unsigned long aclk_200;
2459         unsigned long aclk_100;
2460         unsigned long aclk_160;
2461         unsigned long aclk_133;
2462         unsigned int ptr;
2463
2464         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
2465
2466         xtal_clk = clk_get(NULL, "xtal");
2467         BUG_ON(IS_ERR(xtal_clk));
2468
2469         xtal = clk_get_rate(xtal_clk);
2470
2471         xtal_rate = xtal;
2472
2473         clk_put(xtal_clk);
2474
2475         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
2476
2477         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
2478         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
2479         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
2480                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
2481
2482         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
2483         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
2484                                 __raw_readl(S5P_VPLL_CON1), pll_4650);
2485
2486         clk_fout_apll.ops = &s5pv310_fout_apll_ops;
2487         clk_fout_mpll.rate = mpll;
2488         clk_fout_epll.rate = epll;
2489         clk_fout_vpll.rate = vpll;
2490
2491         printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
2492                         apll, mpll, epll, vpll);
2493
2494         armclk = clk_get_rate(&clk_armclk.clk);
2495         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
2496         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
2497         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
2498         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
2499         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
2500
2501         printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
2502                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
2503                         armclk, sclk_dmc, aclk_200,
2504                         aclk_100, aclk_160, aclk_133);
2505
2506         clk_f.rate = armclk;
2507         clk_h.rate = sclk_dmc;
2508         clk_p.rate = aclk_100;
2509
2510         clk_fout_epll.enable = s5pv310_clk_epll_ctrl;
2511         clk_fout_epll.ops = &s5pv310_epll_ops;
2512
2513         clk_set_parent(&clk_sclk_audss.clk, &clk_mout_audss.clk);
2514         clk_set_parent(&clk_mout_audss.clk, &clk_fout_epll);
2515         clk_set_parent(&clk_sclk_audio0.clk, &clk_mout_epll.clk);
2516         clk_set_parent(&clk_sclk_audio1.clk, &clk_mout_epll.clk);
2517         clk_set_parent(&clk_sclk_audio2.clk, &clk_mout_epll.clk);
2518         clk_set_parent(&clk_mout_epll.clk, &clk_fout_epll);
2519
2520         clk_fout_vpll.enable = s5pv310_clk_vpll_ctrl;
2521         clk_fout_vpll.ops = &s5pv310_vpll_ops;
2522
2523         clk_set_parent(&clk_cmu_dmc.clk, &clk_sclk_dmc.clk);
2524         clk_set_parent(&clk_cmu_top.clk, &clk_aclk_200.clk);
2525         clk_set_parent(&clk_cmu_leftbus.clk, &clk_aclk_gdl.clk);
2526         clk_set_parent(&clk_cmu_rightbus.clk, &clk_aclk_gdr.clk);
2527         clk_set_parent(&clk_cmu_cpu.clk, &clk_aclk_corem0.clk);
2528
2529         clk_set_parent(&clk_xclkout.clk, &clk_xusbxti);
2530
2531         clk_set_rate(&clk_sclk_apll.clk, 100000000);
2532
2533         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
2534                 s3c_set_clksrc(&clksrcs[ptr], true);
2535 }
2536
2537 static struct clk *clks[] __initdata = {
2538         &clk_sclk_hdmi27m,
2539         &clk_sclk_hdmiphy,
2540 };
2541
2542 void __init s5pv310_register_clocks(void)
2543 {
2544         struct clk *clkp;
2545         int ret;
2546         int ptr;
2547
2548         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
2549         if (ret > 0)
2550                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
2551
2552         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
2553                 s3c_register_clksrc(sysclks[ptr], 1);
2554
2555         /* register TV clocks */
2556         for (ptr = 0; sclk_tv[ptr]; ++ptr)
2557                 s3c_register_clksrc(sclk_tv[ptr], 1);
2558
2559         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
2560         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
2561
2562         clkp = init_clocks_disable;
2563         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
2564                 ret = s3c24xx_register_clock(clkp);
2565                 if (ret < 0) {
2566                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
2567                                clkp->name, ret);
2568                 }
2569                 (clkp->enable)(clkp, 0);
2570         }
2571
2572         /* Register DMA Clock */
2573         s3c_register_clocks(init_dmaclocks, ARRAY_SIZE(init_dmaclocks));
2574
2575         s3c_pwmclk_init();
2576 }