2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for S5P64X0 machines
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
20 #include <linux/device.h>
21 #include <linux/serial_core.h>
22 #include <clocksource/samsung_pwm.h>
23 #include <linux/platform_device.h>
24 #include <linux/sched.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/gpio.h>
27 #include <linux/irq.h>
28 #include <linux/reboot.h>
31 #include <asm/proc-fns.h>
32 #include <asm/system_misc.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/irq.h>
38 #include <mach/hardware.h>
39 #include <mach/regs-clock.h>
40 #include <mach/regs-gpio.h>
43 #include <plat/clock.h>
44 #include <plat/devs.h>
46 #include <plat/sdhci.h>
47 #include <plat/adc-core.h>
48 #include <plat/fb-core.h>
49 #include <plat/spi-core.h>
50 #include <plat/gpio-cfg.h>
51 #include <plat/pwm-core.h>
52 #include <plat/regs-irqtype.h>
53 #include <plat/regs-serial.h>
54 #include <plat/watchdog-reset.h>
58 static const char name_s5p6440[] = "S5P6440";
59 static const char name_s5p6450[] = "S5P6450";
61 static struct cpu_table cpu_ids[] __initdata = {
63 .idcode = S5P6440_CPU_ID,
64 .idmask = S5P64XX_CPU_MASK,
65 .map_io = s5p6440_map_io,
66 .init_clocks = s5p6440_init_clocks,
67 .init_uarts = s5p6440_init_uarts,
71 .idcode = S5P6450_CPU_ID,
72 .idmask = S5P64XX_CPU_MASK,
73 .map_io = s5p6450_map_io,
74 .init_clocks = s5p6450_init_clocks,
75 .init_uarts = s5p6450_init_uarts,
81 /* Initial IO mappings */
83 static struct map_desc s5p64x0_iodesc[] __initdata = {
85 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
95 .virtual = (unsigned long)S3C_VA_TIMER,
96 .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
100 .virtual = (unsigned long)S3C_VA_WATCHDOG,
101 .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
105 .virtual = (unsigned long)S5P_VA_SROMC,
106 .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
110 .virtual = (unsigned long)S5P_VA_GPIO,
111 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
115 .virtual = (unsigned long)VA_VIC0,
116 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
120 .virtual = (unsigned long)VA_VIC1,
121 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
127 static struct map_desc s5p6440_iodesc[] __initdata = {
129 .virtual = (unsigned long)S3C_VA_UART,
130 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
136 static struct map_desc s5p6450_iodesc[] __initdata = {
138 .virtual = (unsigned long)S3C_VA_UART,
139 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
143 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
144 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
150 static void s5p64x0_idle(void)
154 val = __raw_readl(S5P64X0_PWR_CFG);
157 __raw_writel(val, S5P64X0_PWR_CFG);
162 static struct samsung_pwm_variant s5p64x0_pwm_variant = {
165 .has_tint_cstat = true,
169 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
171 s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
172 s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
175 void __init samsung_timer_init(void)
177 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
178 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
179 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
182 samsung_pwm_clocksource_init(S3C_VA_TIMER,
183 timer_irqs, &s5p64x0_pwm_variant);
189 * register the standard CPU IO areas
192 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
194 /* initialize the io descriptors we need for initialization */
195 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
197 iotable_init(mach_desc, size);
199 /* detect cpu id and rev. */
200 s5p_init_cpu(S5P64X0_SYS_ID);
202 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
203 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
205 samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
208 void __init s5p6440_map_io(void)
210 /* initialize any device information early */
211 s3c_adc_setname("s3c64xx-adc");
212 s3c_fb_setname("s5p64x0-fb");
213 s3c64xx_spi_setname("s5p64x0-spi");
215 s5p64x0_default_sdhci0();
216 s5p64x0_default_sdhci1();
217 s5p6440_default_sdhci2();
219 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
222 void __init s5p6450_map_io(void)
224 /* initialize any device information early */
225 s3c_adc_setname("s3c64xx-adc");
226 s3c_fb_setname("s5p64x0-fb");
227 s3c64xx_spi_setname("s5p64x0-spi");
229 s5p64x0_default_sdhci0();
230 s5p64x0_default_sdhci1();
231 s5p6450_default_sdhci2();
233 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
237 * s5p64x0_init_clocks
239 * register and setup the CPU clocks
242 void __init s5p6440_init_clocks(int xtal)
244 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
246 s3c24xx_register_baseclocks(xtal);
247 s5p_register_clocks(xtal);
248 s5p6440_register_clocks();
249 s5p6440_setup_clocks();
252 void __init s5p6450_init_clocks(int xtal)
254 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
256 s3c24xx_register_baseclocks(xtal);
257 s5p_register_clocks(xtal);
258 s5p6450_register_clocks();
259 s5p6450_setup_clocks();
265 * register the CPU interrupts
268 void __init s5p6440_init_irq(void)
270 /* S5P6440 supports 2 VIC */
274 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
275 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
280 s5p_init_irq(vic, ARRAY_SIZE(vic));
283 void __init s5p6450_init_irq(void)
285 /* S5P6450 supports only 2 VIC */
289 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
290 * VIC1 is missing IRQ VIC1[12, 14, 23]
295 s5p_init_irq(vic, ARRAY_SIZE(vic));
298 struct bus_type s5p64x0_subsys = {
299 .name = "s5p64x0-core",
300 .dev_name = "s5p64x0-core",
303 static struct device s5p64x0_dev = {
304 .bus = &s5p64x0_subsys,
307 static int __init s5p64x0_core_init(void)
309 return subsys_system_register(&s5p64x0_subsys, NULL);
311 core_initcall(s5p64x0_core_init);
313 int __init s5p64x0_init(void)
315 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
317 /* set idle function */
318 arm_pm_idle = s5p64x0_idle;
320 return device_register(&s5p64x0_dev);
323 /* uart registration process */
324 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
328 for (uart = 0; uart < no; uart++) {
329 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
330 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
333 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
336 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
338 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
341 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
343 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
345 int offs = eint_offset(data->irq);
355 printk(KERN_WARNING "No edge setting!\n");
357 case IRQ_TYPE_EDGE_RISING:
358 newvalue = S3C2410_EXTINT_RISEEDGE;
360 case IRQ_TYPE_EDGE_FALLING:
361 newvalue = S3C2410_EXTINT_FALLEDGE;
363 case IRQ_TYPE_EDGE_BOTH:
364 newvalue = S3C2410_EXTINT_BOTHEDGE;
366 case IRQ_TYPE_LEVEL_LOW:
367 newvalue = S3C2410_EXTINT_LOWLEV;
369 case IRQ_TYPE_LEVEL_HIGH:
370 newvalue = S3C2410_EXTINT_HILEV;
373 printk(KERN_ERR "No such irq type %d", type);
377 shift = (offs / 2) * 4;
380 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
381 ctrl |= newvalue << shift;
382 __raw_writel(ctrl, S5P64X0_EINT0CON0);
384 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
385 if (soc_is_s5p6450())
386 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
388 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
394 * s5p64x0_irq_demux_eint
396 * This function demuxes the IRQ from the group0 external interrupts,
397 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
398 * the specific handlers s5p64x0_irq_demux_eintX_Y.
400 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
402 u32 status = __raw_readl(S5P64X0_EINT0PEND);
403 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
408 status &= (1 << (end - start + 1)) - 1;
410 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
412 generic_handle_irq(irq);
417 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
419 s5p64x0_irq_demux_eint(0, 3);
422 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
424 s5p64x0_irq_demux_eint(4, 11);
427 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
428 struct irq_desc *desc)
430 s5p64x0_irq_demux_eint(12, 15);
433 static int s5p64x0_alloc_gc(void)
435 struct irq_chip_generic *gc;
436 struct irq_chip_type *ct;
438 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
439 S5P_VA_GPIO, handle_level_irq);
441 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
442 "external interrupts failed\n", __func__);
447 ct->chip.irq_ack = irq_gc_ack_set_bit;
448 ct->chip.irq_mask = irq_gc_mask_set_bit;
449 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
450 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
451 ct->chip.irq_set_wake = s3c_irqext_wake;
452 ct->regs.ack = EINT0PEND_OFFSET;
453 ct->regs.mask = EINT0MASK_OFFSET;
454 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
455 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
459 static int __init s5p64x0_init_irq_eint(void)
461 int ret = s5p64x0_alloc_gc();
462 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
463 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
464 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
468 arch_initcall(s5p64x0_init_irq_eint);
470 void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
472 if (mode != REBOOT_SOFT)