arch/arm/mach-s5p64x0/common.c

   1 /*
   2  * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for S5P64X0 machines
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/device.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/sched.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/gpio.h>
  26 #include <linux/irq.h>
  27
  28 #include <asm/irq.h>
  29 #include <asm/proc-fns.h>
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/map.h>
  35 #include <mach/hardware.h>
  36 #include <mach/regs-clock.h>
  37 #include <mach/regs-gpio.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/clock.h>
  41 #include <plat/devs.h>
  42 #include <plat/pm.h>
  43 #include <plat/adc-core.h>
  44 #include <plat/fb-core.h>
  45 #include <plat/gpio-cfg.h>
  46 #include <plat/regs-irqtype.h>
  47 #include <plat/regs-serial.h>
  48 #include <plat/watchdog-reset.h>
  49
  50 #include "common.h"
  51
  52 static const char name_s5p6440[] = "S5P6440";
  53 static const char name_s5p6450[] = "S5P6450";
  54
  55 static struct cpu_table cpu_ids[] __initdata = {
  56         {
  57                 .idcode         = S5P6440_CPU_ID,
  58                 .idmask         = S5P64XX_CPU_MASK,
  59                 .map_io         = s5p6440_map_io,
  60                 .init_clocks    = s5p6440_init_clocks,
  61                 .init_uarts     = s5p6440_init_uarts,
  62                 .init           = s5p64x0_init,
  63                 .name           = name_s5p6440,
  64         }, {
  65                 .idcode         = S5P6450_CPU_ID,
  66                 .idmask         = S5P64XX_CPU_MASK,
  67                 .map_io         = s5p6450_map_io,
  68                 .init_clocks    = s5p6450_init_clocks,
  69                 .init_uarts     = s5p6450_init_uarts,
  70                 .init           = s5p64x0_init,
  71                 .name           = name_s5p6450,
  72         },
  73 };
  74
  75 /* Initial IO mappings */
  76
  77 static struct map_desc s5p64x0_iodesc[] __initdata = {
  78         {
  79                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  80                 .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
  81                 .length         = SZ_4K,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = (unsigned long)S3C_VA_SYS,
  85                 .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
  86                 .length         = SZ_64K,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = (unsigned long)S3C_VA_TIMER,
  90                 .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
  91                 .length         = SZ_16K,
  92                 .type           = MT_DEVICE,
  93         }, {
  94                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  95                 .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE,
  98         }, {
  99                 .virtual        = (unsigned long)S5P_VA_SROMC,
 100                 .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE,
 103         }, {
 104                 .virtual        = (unsigned long)S5P_VA_GPIO,
 105                 .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE,
 108         }, {
 109                 .virtual        = (unsigned long)VA_VIC0,
 110                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
 111                 .length         = SZ_16K,
 112                 .type           = MT_DEVICE,
 113         }, {
 114                 .virtual        = (unsigned long)VA_VIC1,
 115                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
 116                 .length         = SZ_16K,
 117                 .type           = MT_DEVICE,
 118         },
 119 };
 120
 121 static struct map_desc s5p6440_iodesc[] __initdata = {
 122         {
 123                 .virtual        = (unsigned long)S3C_VA_UART,
 124                 .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
 125                 .length         = SZ_4K,
 126                 .type           = MT_DEVICE,
 127         },
 128 };
 129
 130 static struct map_desc s5p6450_iodesc[] __initdata = {
 131         {
 132                 .virtual        = (unsigned long)S3C_VA_UART,
 133                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
 134                 .length         = SZ_512K,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
 138                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
 139                 .length         = SZ_4K,
 140                 .type           = MT_DEVICE,
 141         },
 142 };
 143
 144 static void s5p64x0_idle(void)
 145 {
 146         unsigned long val;
 147
 148         if (!need_resched()) {
 149                 val = __raw_readl(S5P64X0_PWR_CFG);
 150                 val &= ~(0x3 << 5);
 151                 val |= (0x1 << 5);
 152                 __raw_writel(val, S5P64X0_PWR_CFG);
 153
 154                 cpu_do_idle();
 155         }
 156         local_irq_enable();
 157 }
 158
 159 /*
 160  * s5p64x0_map_io
 161  *
 162  * register the standard CPU IO areas
 163  */
 164
 165 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
 166 {
 167         /* initialize the io descriptors we need for initialization */
 168         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
 169         if (mach_desc)
 170                 iotable_init(mach_desc, size);
 171
 172         /* detect cpu id and rev. */
 173         s5p_init_cpu(S5P64X0_SYS_ID);
 174
 175         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 176 }
 177
 178 void __init s5p6440_map_io(void)
 179 {
 180         /* initialize any device information early */
 181         s3c_adc_setname("s3c64xx-adc");
 182         s3c_fb_setname("s5p64x0-fb");
 183
 184         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
 185         init_consistent_dma_size(SZ_8M);
 186 }
 187
 188 void __init s5p6450_map_io(void)
 189 {
 190         /* initialize any device information early */
 191         s3c_adc_setname("s3c64xx-adc");
 192         s3c_fb_setname("s5p64x0-fb");
 193
 194         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 195         init_consistent_dma_size(SZ_8M);
 196 }
 197
 198 /*
 199  * s5p64x0_init_clocks
 200  *
 201  * register and setup the CPU clocks
 202  */
 203
 204 void __init s5p6440_init_clocks(int xtal)
 205 {
 206         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 207
 208         s3c24xx_register_baseclocks(xtal);
 209         s5p_register_clocks(xtal);
 210         s5p6440_register_clocks();
 211         s5p6440_setup_clocks();
 212 }
 213
 214 void __init s5p6450_init_clocks(int xtal)
 215 {
 216         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 217
 218         s3c24xx_register_baseclocks(xtal);
 219         s5p_register_clocks(xtal);
 220         s5p6450_register_clocks();
 221         s5p6450_setup_clocks();
 222 }
 223
 224 /*
 225  * s5p64x0_init_irq
 226  *
 227  * register the CPU interrupts
 228  */
 229
 230 void __init s5p6440_init_irq(void)
 231 {
 232         /* S5P6440 supports 2 VIC */
 233         u32 vic[2];
 234
 235         /*
 236          * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
 237          * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
 238          */
 239         vic[0] = 0xff800ae7;
 240         vic[1] = 0xffbf23e5;
 241
 242         s5p_init_irq(vic, ARRAY_SIZE(vic));
 243 }
 244
 245 void __init s5p6450_init_irq(void)
 246 {
 247         /* S5P6450 supports only 2 VIC */
 248         u32 vic[2];
 249
 250         /*
 251          * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
 252          * VIC1 is missing IRQ VIC1[12, 14, 23]
 253          */
 254         vic[0] = 0xff9f1fff;
 255         vic[1] = 0xff7fafff;
 256
 257         s5p_init_irq(vic, ARRAY_SIZE(vic));
 258 }
 259
 260 struct bus_type s5p64x0_subsys = {
 261         .name           = "s5p64x0-core",
 262         .dev_name       = "s5p64x0-core",
 263 };
 264
 265 static struct device s5p64x0_dev = {
 266         .bus    = &s5p64x0_subsys,
 267 };
 268
 269 static int __init s5p64x0_core_init(void)
 270 {
 271         return subsys_system_register(&s5p64x0_subsys, NULL);
 272 }
 273 core_initcall(s5p64x0_core_init);
 274
 275 int __init s5p64x0_init(void)
 276 {
 277         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 278
 279         /* set idle function */
 280         pm_idle = s5p64x0_idle;
 281
 282         return device_register(&s5p64x0_dev);
 283 }
 284
 285 /* uart registration process */
 286 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 287 {
 288         int uart;
 289
 290         for (uart = 0; uart < no; uart++) {
 291                 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
 292                 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
 293         }
 294
 295         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 296 }
 297
 298 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 299 {
 300         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 301 }
 302
 303 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 304
 305 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
 306 {
 307         int offs = eint_offset(data->irq);
 308         int shift;
 309         u32 ctrl, mask;
 310         u32 newvalue = 0;
 311
 312         if (offs > 15)
 313                 return -EINVAL;
 314
 315         switch (type) {
 316         case IRQ_TYPE_NONE:
 317                 printk(KERN_WARNING "No edge setting!\n");
 318                 break;
 319         case IRQ_TYPE_EDGE_RISING:
 320                 newvalue = S3C2410_EXTINT_RISEEDGE;
 321                 break;
 322         case IRQ_TYPE_EDGE_FALLING:
 323                 newvalue = S3C2410_EXTINT_FALLEDGE;
 324                 break;
 325         case IRQ_TYPE_EDGE_BOTH:
 326                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 327                 break;
 328         case IRQ_TYPE_LEVEL_LOW:
 329                 newvalue = S3C2410_EXTINT_LOWLEV;
 330                 break;
 331         case IRQ_TYPE_LEVEL_HIGH:
 332                 newvalue = S3C2410_EXTINT_HILEV;
 333                 break;
 334         default:
 335                 printk(KERN_ERR "No such irq type %d", type);
 336                 return -EINVAL;
 337         }
 338
 339         shift = (offs / 2) * 4;
 340         mask = 0x7 << shift;
 341
 342         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
 343         ctrl |= newvalue << shift;
 344         __raw_writel(ctrl, S5P64X0_EINT0CON0);
 345
 346         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
 347         if (soc_is_s5p6450())
 348                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
 349         else
 350                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
 351
 352         return 0;
 353 }
 354
 355 /*
 356  * s5p64x0_irq_demux_eint
 357  *
 358  * This function demuxes the IRQ from the group0 external interrupts,
 359  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
 360  * the specific handlers s5p64x0_irq_demux_eintX_Y.
 361  */
 362 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
 363 {
 364         u32 status = __raw_readl(S5P64X0_EINT0PEND);
 365         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
 366         unsigned int irq;
 367
 368         status &= ~mask;
 369         status >>= start;
 370         status &= (1 << (end - start + 1)) - 1;
 371
 372         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 373                 if (status & 1)
 374                         generic_handle_irq(irq);
 375                 status >>= 1;
 376         }
 377 }
 378
 379 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 380 {
 381         s5p64x0_irq_demux_eint(0, 3);
 382 }
 383
 384 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 385 {
 386         s5p64x0_irq_demux_eint(4, 11);
 387 }
 388
 389 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 390                                         struct irq_desc *desc)
 391 {
 392         s5p64x0_irq_demux_eint(12, 15);
 393 }
 394
 395 static int s5p64x0_alloc_gc(void)
 396 {
 397         struct irq_chip_generic *gc;
 398         struct irq_chip_type *ct;
 399
 400         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 401                                     S5P_VA_GPIO, handle_level_irq);
 402         if (!gc) {
 403                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 404                         "external interrupts failed\n", __func__);
 405                 return -EINVAL;
 406         }
 407
 408         ct = gc->chip_types;
 409         ct->chip.irq_ack = irq_gc_ack_set_bit;
 410         ct->chip.irq_mask = irq_gc_mask_set_bit;
 411         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 412         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 413         ct->chip.irq_set_wake = s3c_irqext_wake;
 414         ct->regs.ack = EINT0PEND_OFFSET;
 415         ct->regs.mask = EINT0MASK_OFFSET;
 416         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 417                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 418         return 0;
 419 }
 420
 421 static int __init s5p64x0_init_irq_eint(void)
 422 {
 423         int ret = s5p64x0_alloc_gc();
 424         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 425         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 426         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 427
 428         return ret;
 429 }
 430 arch_initcall(s5p64x0_init_irq_eint);
 431
 432 void s5p64x0_restart(char mode, const char *cmd)
 433 {
 434         if (mode != 's')
 435                 arch_wdt_reset();
 436
 437         soft_restart(0);
 438 }