2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for S5P64X0 machines
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
20 #include <linux/device.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/gpio.h>
26 #include <linux/irq.h>
29 #include <asm/proc-fns.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
35 #include <mach/hardware.h>
36 #include <mach/regs-clock.h>
37 #include <mach/regs-gpio.h>
40 #include <plat/clock.h>
41 #include <plat/devs.h>
43 #include <plat/adc-core.h>
44 #include <plat/fb-core.h>
45 #include <plat/gpio-cfg.h>
46 #include <plat/regs-irqtype.h>
47 #include <plat/regs-serial.h>
48 #include <plat/watchdog-reset.h>
52 static const char name_s5p6440[] = "S5P6440";
53 static const char name_s5p6450[] = "S5P6450";
55 static struct cpu_table cpu_ids[] __initdata = {
57 .idcode = S5P6440_CPU_ID,
58 .idmask = S5P64XX_CPU_MASK,
59 .map_io = s5p6440_map_io,
60 .init_clocks = s5p6440_init_clocks,
61 .init_uarts = s5p6440_init_uarts,
65 .idcode = S5P6450_CPU_ID,
66 .idmask = S5P64XX_CPU_MASK,
67 .map_io = s5p6450_map_io,
68 .init_clocks = s5p6450_init_clocks,
69 .init_uarts = s5p6450_init_uarts,
75 /* Initial IO mappings */
77 static struct map_desc s5p64x0_iodesc[] __initdata = {
79 .virtual = (unsigned long)S5P_VA_CHIPID,
80 .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
84 .virtual = (unsigned long)S3C_VA_SYS,
85 .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
89 .virtual = (unsigned long)S3C_VA_TIMER,
90 .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
94 .virtual = (unsigned long)S3C_VA_WATCHDOG,
95 .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
99 .virtual = (unsigned long)S5P_VA_SROMC,
100 .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
104 .virtual = (unsigned long)S5P_VA_GPIO,
105 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
109 .virtual = (unsigned long)VA_VIC0,
110 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
114 .virtual = (unsigned long)VA_VIC1,
115 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
121 static struct map_desc s5p6440_iodesc[] __initdata = {
123 .virtual = (unsigned long)S3C_VA_UART,
124 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
130 static struct map_desc s5p6450_iodesc[] __initdata = {
132 .virtual = (unsigned long)S3C_VA_UART,
133 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
137 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
138 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
144 static void s5p64x0_idle(void)
148 if (!need_resched()) {
149 val = __raw_readl(S5P64X0_PWR_CFG);
152 __raw_writel(val, S5P64X0_PWR_CFG);
162 * register the standard CPU IO areas
165 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
167 /* initialize the io descriptors we need for initialization */
168 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
170 iotable_init(mach_desc, size);
172 /* detect cpu id and rev. */
173 s5p_init_cpu(S5P64X0_SYS_ID);
175 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
178 void __init s5p6440_map_io(void)
180 /* initialize any device information early */
181 s3c_adc_setname("s3c64xx-adc");
182 s3c_fb_setname("s5p64x0-fb");
184 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
185 init_consistent_dma_size(SZ_8M);
188 void __init s5p6450_map_io(void)
190 /* initialize any device information early */
191 s3c_adc_setname("s3c64xx-adc");
192 s3c_fb_setname("s5p64x0-fb");
194 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
195 init_consistent_dma_size(SZ_8M);
199 * s5p64x0_init_clocks
201 * register and setup the CPU clocks
204 void __init s5p6440_init_clocks(int xtal)
206 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
208 s3c24xx_register_baseclocks(xtal);
209 s5p_register_clocks(xtal);
210 s5p6440_register_clocks();
211 s5p6440_setup_clocks();
214 void __init s5p6450_init_clocks(int xtal)
216 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
218 s3c24xx_register_baseclocks(xtal);
219 s5p_register_clocks(xtal);
220 s5p6450_register_clocks();
221 s5p6450_setup_clocks();
227 * register the CPU interrupts
230 void __init s5p6440_init_irq(void)
232 /* S5P6440 supports 2 VIC */
236 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
237 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
242 s5p_init_irq(vic, ARRAY_SIZE(vic));
245 void __init s5p6450_init_irq(void)
247 /* S5P6450 supports only 2 VIC */
251 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
252 * VIC1 is missing IRQ VIC1[12, 14, 23]
257 s5p_init_irq(vic, ARRAY_SIZE(vic));
260 struct bus_type s5p64x0_subsys = {
261 .name = "s5p64x0-core",
262 .dev_name = "s5p64x0-core",
265 static struct device s5p64x0_dev = {
266 .bus = &s5p64x0_subsys,
269 static int __init s5p64x0_core_init(void)
271 return subsys_system_register(&s5p64x0_subsys, NULL);
273 core_initcall(s5p64x0_core_init);
275 int __init s5p64x0_init(void)
277 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
279 /* set idle function */
280 pm_idle = s5p64x0_idle;
282 return device_register(&s5p64x0_dev);
285 /* uart registration process */
286 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
290 for (uart = 0; uart < no; uart++) {
291 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
292 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
295 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
298 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
300 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
303 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
305 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
307 int offs = eint_offset(data->irq);
317 printk(KERN_WARNING "No edge setting!\n");
319 case IRQ_TYPE_EDGE_RISING:
320 newvalue = S3C2410_EXTINT_RISEEDGE;
322 case IRQ_TYPE_EDGE_FALLING:
323 newvalue = S3C2410_EXTINT_FALLEDGE;
325 case IRQ_TYPE_EDGE_BOTH:
326 newvalue = S3C2410_EXTINT_BOTHEDGE;
328 case IRQ_TYPE_LEVEL_LOW:
329 newvalue = S3C2410_EXTINT_LOWLEV;
331 case IRQ_TYPE_LEVEL_HIGH:
332 newvalue = S3C2410_EXTINT_HILEV;
335 printk(KERN_ERR "No such irq type %d", type);
339 shift = (offs / 2) * 4;
342 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
343 ctrl |= newvalue << shift;
344 __raw_writel(ctrl, S5P64X0_EINT0CON0);
346 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
347 if (soc_is_s5p6450())
348 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
350 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
356 * s5p64x0_irq_demux_eint
358 * This function demuxes the IRQ from the group0 external interrupts,
359 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
360 * the specific handlers s5p64x0_irq_demux_eintX_Y.
362 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
364 u32 status = __raw_readl(S5P64X0_EINT0PEND);
365 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
370 status &= (1 << (end - start + 1)) - 1;
372 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
374 generic_handle_irq(irq);
379 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
381 s5p64x0_irq_demux_eint(0, 3);
384 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
386 s5p64x0_irq_demux_eint(4, 11);
389 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
390 struct irq_desc *desc)
392 s5p64x0_irq_demux_eint(12, 15);
395 static int s5p64x0_alloc_gc(void)
397 struct irq_chip_generic *gc;
398 struct irq_chip_type *ct;
400 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
401 S5P_VA_GPIO, handle_level_irq);
403 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
404 "external interrupts failed\n", __func__);
409 ct->chip.irq_ack = irq_gc_ack_set_bit;
410 ct->chip.irq_mask = irq_gc_mask_set_bit;
411 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
412 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
413 ct->chip.irq_set_wake = s3c_irqext_wake;
414 ct->regs.ack = EINT0PEND_OFFSET;
415 ct->regs.mask = EINT0MASK_OFFSET;
416 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
417 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
421 static int __init s5p64x0_init_irq_eint(void)
423 int ret = s5p64x0_alloc_gc();
424 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
425 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
426 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
430 arch_initcall(s5p64x0_init_irq_eint);
432 void s5p64x0_restart(char mode, const char *cmd)