arch/arm/mach-s3c64xx/clock.c

   1 /* linux/arch/arm/plat-s3c64xx/clock.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX Base clock support
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25
  26 #include <mach/regs-sys.h>
  27 #include <mach/regs-clock.h>
  28
  29 #include <plat/cpu.h>
  30 #include <plat/devs.h>
  31 #include <plat/cpu-freq.h>
  32 #include <plat/clock.h>
  33 #include <plat/clock-clksrc.h>
  34 #include <plat/pll.h>
  35
  36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  37  * ext_xtal_mux for want of an actual name from the manual.
  38 */
  39
  40 static struct clk clk_ext_xtal_mux = {
  41         .name           = "ext_xtal",
  42 };
  43
  44 #define clk_fin_apll clk_ext_xtal_mux
  45 #define clk_fin_mpll clk_ext_xtal_mux
  46 #define clk_fin_epll clk_ext_xtal_mux
  47
  48 #define clk_fout_mpll   clk_mpll
  49 #define clk_fout_epll   clk_epll
  50
  51 struct clk clk_h2 = {
  52         .name           = "hclk2",
  53         .rate           = 0,
  54 };
  55
  56 struct clk clk_27m = {
  57         .name           = "clk_27m",
  58         .rate           = 27000000,
  59 };
  60
  61 static int clk_48m_ctrl(struct clk *clk, int enable)
  62 {
  63         unsigned long flags;
  64         u32 val;
  65
  66         /* can't rely on clock lock, this register has other usages */
  67         local_irq_save(flags);
  68
  69         val = __raw_readl(S3C64XX_OTHERS);
  70         if (enable)
  71                 val |= S3C64XX_OTHERS_USBMASK;
  72         else
  73                 val &= ~S3C64XX_OTHERS_USBMASK;
  74
  75         __raw_writel(val, S3C64XX_OTHERS);
  76         local_irq_restore(flags);
  77
  78         return 0;
  79 }
  80
  81 struct clk clk_48m = {
  82         .name           = "clk_48m",
  83         .rate           = 48000000,
  84         .enable         = clk_48m_ctrl,
  85 };
  86
  87 struct clk clk_xusbxti = {
  88         .name           = "xusbxti",
  89         .rate           = 48000000,
  90 };
  91
  92 static int inline s3c64xx_gate(void __iomem *reg,
  93                                 struct clk *clk,
  94                                 int enable)
  95 {
  96         unsigned int ctrlbit = clk->ctrlbit;
  97         u32 con;
  98
  99         con = __raw_readl(reg);
 100
 101         if (enable)
 102                 con |= ctrlbit;
 103         else
 104                 con &= ~ctrlbit;
 105
 106         __raw_writel(con, reg);
 107         return 0;
 108 }
 109
 110 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
 111 {
 112         return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
 113 }
 114
 115 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
 116 {
 117         return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
 118 }
 119
 120 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
 121 {
 122         return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
 123 }
 124
 125 static struct clk init_clocks_off[] = {
 126         {
 127                 .name           = "nand",
 128                 .parent         = &clk_h,
 129         }, {
 130                 .name           = "rtc",
 131                 .parent         = &clk_p,
 132                 .enable         = s3c64xx_pclk_ctrl,
 133                 .ctrlbit        = S3C_CLKCON_PCLK_RTC,
 134         }, {
 135                 .name           = "adc",
 136                 .parent         = &clk_p,
 137                 .enable         = s3c64xx_pclk_ctrl,
 138                 .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
 139         }, {
 140                 .name           = "i2c",
 141                 .devname        = "s3c2440-i2c.0",
 142                 .parent         = &clk_p,
 143                 .enable         = s3c64xx_pclk_ctrl,
 144                 .ctrlbit        = S3C_CLKCON_PCLK_IIC,
 145         }, {
 146                 .name           = "i2c",
 147                 .devname        = "s3c2440-i2c.1",
 148                 .parent         = &clk_p,
 149                 .enable         = s3c64xx_pclk_ctrl,
 150                 .ctrlbit        = S3C6410_CLKCON_PCLK_I2C1,
 151         }, {
 152                 .name           = "keypad",
 153                 .parent         = &clk_p,
 154                 .enable         = s3c64xx_pclk_ctrl,
 155                 .ctrlbit        = S3C_CLKCON_PCLK_KEYPAD,
 156         }, {
 157                 .name           = "spi",
 158                 .devname        = "s3c6410-spi.0",
 159                 .parent         = &clk_p,
 160                 .enable         = s3c64xx_pclk_ctrl,
 161                 .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
 162         }, {
 163                 .name           = "spi",
 164                 .devname        = "s3c6410-spi.1",
 165                 .parent         = &clk_p,
 166                 .enable         = s3c64xx_pclk_ctrl,
 167                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
 168         }, {
 169                 .name           = "48m",
 170                 .devname        = "s3c-sdhci.0",
 171                 .parent         = &clk_48m,
 172                 .enable         = s3c64xx_sclk_ctrl,
 173                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
 174         }, {
 175                 .name           = "48m",
 176                 .devname        = "s3c-sdhci.1",
 177                 .parent         = &clk_48m,
 178                 .enable         = s3c64xx_sclk_ctrl,
 179                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
 180         }, {
 181                 .name           = "48m",
 182                 .devname        = "s3c-sdhci.2",
 183                 .parent         = &clk_48m,
 184                 .enable         = s3c64xx_sclk_ctrl,
 185                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
 186         }, {
 187                 .name           = "ac97",
 188                 .parent         = &clk_p,
 189                 .ctrlbit        = S3C_CLKCON_PCLK_AC97,
 190         }, {
 191                 .name           = "cfcon",
 192                 .parent         = &clk_h,
 193                 .enable         = s3c64xx_hclk_ctrl,
 194                 .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
 195         }, {
 196                 .name           = "dma0",
 197                 .parent         = &clk_h,
 198                 .enable         = s3c64xx_hclk_ctrl,
 199                 .ctrlbit        = S3C_CLKCON_HCLK_DMA0,
 200         }, {
 201                 .name           = "dma1",
 202                 .parent         = &clk_h,
 203                 .enable         = s3c64xx_hclk_ctrl,
 204                 .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
 205         }, {
 206                 .name           = "3dse",
 207                 .parent         = &clk_h,
 208                 .enable         = s3c64xx_hclk_ctrl,
 209                 .ctrlbit        = S3C_CLKCON_HCLK_3DSE,
 210         }, {
 211                 .name           = "hclk_secur",
 212                 .parent         = &clk_h,
 213                 .enable         = s3c64xx_hclk_ctrl,
 214                 .ctrlbit        = S3C_CLKCON_HCLK_SECUR,
 215         }, {
 216                 .name           = "sdma1",
 217                 .parent         = &clk_h,
 218                 .enable         = s3c64xx_hclk_ctrl,
 219                 .ctrlbit        = S3C_CLKCON_HCLK_SDMA1,
 220         }, {
 221                 .name           = "sdma0",
 222                 .parent         = &clk_h,
 223                 .enable         = s3c64xx_hclk_ctrl,
 224                 .ctrlbit        = S3C_CLKCON_HCLK_SDMA0,
 225         }, {
 226                 .name           = "hclk_jpeg",
 227                 .parent         = &clk_h,
 228                 .enable         = s3c64xx_hclk_ctrl,
 229                 .ctrlbit        = S3C_CLKCON_HCLK_JPEG,
 230         }, {
 231                 .name           = "camif",
 232                 .parent         = &clk_h,
 233                 .enable         = s3c64xx_hclk_ctrl,
 234                 .ctrlbit        = S3C_CLKCON_HCLK_CAMIF,
 235         }, {
 236                 .name           = "hclk_scaler",
 237                 .parent         = &clk_h,
 238                 .enable         = s3c64xx_hclk_ctrl,
 239                 .ctrlbit        = S3C_CLKCON_HCLK_SCALER,
 240         }, {
 241                 .name           = "2d",
 242                 .parent         = &clk_h,
 243                 .enable         = s3c64xx_hclk_ctrl,
 244                 .ctrlbit        = S3C_CLKCON_HCLK_2D,
 245         }, {
 246                 .name           = "tv",
 247                 .parent         = &clk_h,
 248                 .enable         = s3c64xx_hclk_ctrl,
 249                 .ctrlbit        = S3C_CLKCON_HCLK_TV,
 250         }, {
 251                 .name           = "post0",
 252                 .parent         = &clk_h,
 253                 .enable         = s3c64xx_hclk_ctrl,
 254                 .ctrlbit        = S3C_CLKCON_HCLK_POST0,
 255         }, {
 256                 .name           = "rot",
 257                 .parent         = &clk_h,
 258                 .enable         = s3c64xx_hclk_ctrl,
 259                 .ctrlbit        = S3C_CLKCON_HCLK_ROT,
 260         }, {
 261                 .name           = "hclk_mfc",
 262                 .parent         = &clk_h,
 263                 .enable         = s3c64xx_hclk_ctrl,
 264                 .ctrlbit        = S3C_CLKCON_HCLK_MFC,
 265         }, {
 266                 .name           = "pclk_mfc",
 267                 .parent         = &clk_p,
 268                 .enable         = s3c64xx_pclk_ctrl,
 269                 .ctrlbit        = S3C_CLKCON_PCLK_MFC,
 270         }, {
 271                 .name           = "dac27",
 272                 .enable         = s3c64xx_sclk_ctrl,
 273                 .ctrlbit        = S3C_CLKCON_SCLK_DAC27,
 274         }, {
 275                 .name           = "tv27",
 276                 .enable         = s3c64xx_sclk_ctrl,
 277                 .ctrlbit        = S3C_CLKCON_SCLK_TV27,
 278         }, {
 279                 .name           = "scaler27",
 280                 .enable         = s3c64xx_sclk_ctrl,
 281                 .ctrlbit        = S3C_CLKCON_SCLK_SCALER27,
 282         }, {
 283                 .name           = "sclk_scaler",
 284                 .enable         = s3c64xx_sclk_ctrl,
 285                 .ctrlbit        = S3C_CLKCON_SCLK_SCALER,
 286         }, {
 287                 .name           = "post0_27",
 288                 .enable         = s3c64xx_sclk_ctrl,
 289                 .ctrlbit        = S3C_CLKCON_SCLK_POST0_27,
 290         }, {
 291                 .name           = "secur",
 292                 .enable         = s3c64xx_sclk_ctrl,
 293                 .ctrlbit        = S3C_CLKCON_SCLK_SECUR,
 294         }, {
 295                 .name           = "sclk_mfc",
 296                 .enable         = s3c64xx_sclk_ctrl,
 297                 .ctrlbit        = S3C_CLKCON_SCLK_MFC,
 298         }, {
 299                 .name           = "sclk_jpeg",
 300                 .enable         = s3c64xx_sclk_ctrl,
 301                 .ctrlbit        = S3C_CLKCON_SCLK_JPEG,
 302         },
 303 };
 304
 305 static struct clk clk_48m_spi0 = {
 306         .name           = "spi_48m",
 307         .devname        = "s3c6410-spi.0",
 308         .parent         = &clk_48m,
 309         .enable         = s3c64xx_sclk_ctrl,
 310         .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
 311 };
 312
 313 static struct clk clk_48m_spi1 = {
 314         .name           = "spi_48m",
 315         .devname        = "s3c6410-spi.1",
 316         .parent         = &clk_48m,
 317         .enable         = s3c64xx_sclk_ctrl,
 318         .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
 319 };
 320
 321 static struct clk clk_i2s0 = {
 322         .name           = "iis",
 323         .devname        = "samsung-i2s.0",
 324         .parent         = &clk_p,
 325         .enable         = s3c64xx_pclk_ctrl,
 326         .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
 327 };
 328
 329 static struct clk clk_i2s1 = {
 330         .name           = "iis",
 331         .devname        = "samsung-i2s.1",
 332         .parent         = &clk_p,
 333         .enable         = s3c64xx_pclk_ctrl,
 334         .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
 335 };
 336
 337 #ifdef CONFIG_CPU_S3C6410
 338 static struct clk clk_i2s2 = {
 339         .name           = "iis",
 340         .devname        = "samsung-i2s.2",
 341         .parent         = &clk_p,
 342         .enable         = s3c64xx_pclk_ctrl,
 343         .ctrlbit        = S3C6410_CLKCON_PCLK_IIS2,
 344 };
 345 #endif
 346
 347 static struct clk init_clocks[] = {
 348         {
 349                 .name           = "lcd",
 350                 .parent         = &clk_h,
 351                 .enable         = s3c64xx_hclk_ctrl,
 352                 .ctrlbit        = S3C_CLKCON_HCLK_LCD,
 353         }, {
 354                 .name           = "gpio",
 355                 .parent         = &clk_p,
 356                 .enable         = s3c64xx_pclk_ctrl,
 357                 .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
 358         }, {
 359                 .name           = "usb-host",
 360                 .parent         = &clk_h,
 361                 .enable         = s3c64xx_hclk_ctrl,
 362                 .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
 363         }, {
 364                 .name           = "otg",
 365                 .parent         = &clk_h,
 366                 .enable         = s3c64xx_hclk_ctrl,
 367                 .ctrlbit        = S3C_CLKCON_HCLK_USB,
 368         }, {
 369                 .name           = "timers",
 370                 .parent         = &clk_p,
 371                 .enable         = s3c64xx_pclk_ctrl,
 372                 .ctrlbit        = S3C_CLKCON_PCLK_PWM,
 373         }, {
 374                 .name           = "uart",
 375                 .devname        = "s3c6400-uart.0",
 376                 .parent         = &clk_p,
 377                 .enable         = s3c64xx_pclk_ctrl,
 378                 .ctrlbit        = S3C_CLKCON_PCLK_UART0,
 379         }, {
 380                 .name           = "uart",
 381                 .devname        = "s3c6400-uart.1",
 382                 .parent         = &clk_p,
 383                 .enable         = s3c64xx_pclk_ctrl,
 384                 .ctrlbit        = S3C_CLKCON_PCLK_UART1,
 385         }, {
 386                 .name           = "uart",
 387                 .devname        = "s3c6400-uart.2",
 388                 .parent         = &clk_p,
 389                 .enable         = s3c64xx_pclk_ctrl,
 390                 .ctrlbit        = S3C_CLKCON_PCLK_UART2,
 391         }, {
 392                 .name           = "uart",
 393                 .devname        = "s3c6400-uart.3",
 394                 .parent         = &clk_p,
 395                 .enable         = s3c64xx_pclk_ctrl,
 396                 .ctrlbit        = S3C_CLKCON_PCLK_UART3,
 397         }, {
 398                 .name           = "watchdog",
 399                 .parent         = &clk_p,
 400                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
 401         },
 402 };
 403
 404 static struct clk clk_hsmmc0 = {
 405         .name           = "hsmmc",
 406         .devname        = "s3c-sdhci.0",
 407         .parent         = &clk_h,
 408         .enable         = s3c64xx_hclk_ctrl,
 409         .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
 410 };
 411
 412 static struct clk clk_hsmmc1 = {
 413         .name           = "hsmmc",
 414         .devname        = "s3c-sdhci.1",
 415         .parent         = &clk_h,
 416         .enable         = s3c64xx_hclk_ctrl,
 417         .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
 418 };
 419
 420 static struct clk clk_hsmmc2 = {
 421         .name           = "hsmmc",
 422         .devname        = "s3c-sdhci.2",
 423         .parent         = &clk_h,
 424         .enable         = s3c64xx_hclk_ctrl,
 425         .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
 426 };
 427
 428 static struct clk clk_fout_apll = {
 429         .name           = "fout_apll",
 430 };
 431
 432 static struct clk *clk_src_apll_list[] = {
 433         [0] = &clk_fin_apll,
 434         [1] = &clk_fout_apll,
 435 };
 436
 437 static struct clksrc_sources clk_src_apll = {
 438         .sources        = clk_src_apll_list,
 439         .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
 440 };
 441
 442 static struct clksrc_clk clk_mout_apll = {
 443         .clk    = {
 444                 .name           = "mout_apll",
 445         },
 446         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1  },
 447         .sources        = &clk_src_apll,
 448 };
 449
 450 static struct clk *clk_src_epll_list[] = {
 451         [0] = &clk_fin_epll,
 452         [1] = &clk_fout_epll,
 453 };
 454
 455 static struct clksrc_sources clk_src_epll = {
 456         .sources        = clk_src_epll_list,
 457         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
 458 };
 459
 460 static struct clksrc_clk clk_mout_epll = {
 461         .clk    = {
 462                 .name           = "mout_epll",
 463         },
 464         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1  },
 465         .sources        = &clk_src_epll,
 466 };
 467
 468 static struct clk *clk_src_mpll_list[] = {
 469         [0] = &clk_fin_mpll,
 470         [1] = &clk_fout_mpll,
 471 };
 472
 473 static struct clksrc_sources clk_src_mpll = {
 474         .sources        = clk_src_mpll_list,
 475         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
 476 };
 477
 478 static struct clksrc_clk clk_mout_mpll = {
 479         .clk = {
 480                 .name           = "mout_mpll",
 481         },
 482         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1  },
 483         .sources        = &clk_src_mpll,
 484 };
 485
 486 static unsigned int armclk_mask;
 487
 488 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
 489 {
 490         unsigned long rate = clk_get_rate(clk->parent);
 491         u32 clkdiv;
 492
 493         /* divisor mask starts at bit0, so no need to shift */
 494         clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
 495
 496         return rate / (clkdiv + 1);
 497 }
 498
 499 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
 500                                                 unsigned long rate)
 501 {
 502         unsigned long parent = clk_get_rate(clk->parent);
 503         u32 div;
 504
 505         if (parent < rate)
 506                 return parent;
 507
 508         div = (parent / rate) - 1;
 509         if (div > armclk_mask)
 510                 div = armclk_mask;
 511
 512         return parent / (div + 1);
 513 }
 514
 515 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
 516 {
 517         unsigned long parent = clk_get_rate(clk->parent);
 518         u32 div;
 519         u32 val;
 520
 521         if (rate < parent / (armclk_mask + 1))
 522                 return -EINVAL;
 523
 524         rate = clk_round_rate(clk, rate);
 525         div = clk_get_rate(clk->parent) / rate;
 526
 527         val = __raw_readl(S3C_CLK_DIV0);
 528         val &= ~armclk_mask;
 529         val |= (div - 1);
 530         __raw_writel(val, S3C_CLK_DIV0);
 531
 532         return 0;
 533
 534 }
 535
 536 static struct clk clk_arm = {
 537         .name           = "armclk",
 538         .parent         = &clk_mout_apll.clk,
 539         .ops            = &(struct clk_ops) {
 540                 .get_rate       = s3c64xx_clk_arm_get_rate,
 541                 .set_rate       = s3c64xx_clk_arm_set_rate,
 542                 .round_rate     = s3c64xx_clk_arm_round_rate,
 543         },
 544 };
 545
 546 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
 547 {
 548         unsigned long rate = clk_get_rate(clk->parent);
 549
 550         printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
 551
 552         if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
 553                 rate /= 2;
 554
 555         return rate;
 556 }
 557
 558 static struct clk_ops clk_dout_ops = {
 559         .get_rate       = s3c64xx_clk_doutmpll_get_rate,
 560 };
 561
 562 static struct clk clk_dout_mpll = {
 563         .name           = "dout_mpll",
 564         .parent         = &clk_mout_mpll.clk,
 565         .ops            = &clk_dout_ops,
 566 };
 567
 568 static struct clk *clkset_spi_mmc_list[] = {
 569         &clk_mout_epll.clk,
 570         &clk_dout_mpll,
 571         &clk_fin_epll,
 572         &clk_27m,
 573 };
 574
 575 static struct clksrc_sources clkset_spi_mmc = {
 576         .sources        = clkset_spi_mmc_list,
 577         .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
 578 };
 579
 580 static struct clk *clkset_irda_list[] = {
 581         &clk_mout_epll.clk,
 582         &clk_dout_mpll,
 583         NULL,
 584         &clk_27m,
 585 };
 586
 587 static struct clksrc_sources clkset_irda = {
 588         .sources        = clkset_irda_list,
 589         .nr_sources     = ARRAY_SIZE(clkset_irda_list),
 590 };
 591
 592 static struct clk *clkset_uart_list[] = {
 593         &clk_mout_epll.clk,
 594         &clk_dout_mpll,
 595         NULL,
 596         NULL
 597 };
 598
 599 static struct clksrc_sources clkset_uart = {
 600         .sources        = clkset_uart_list,
 601         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 602 };
 603
 604 static struct clk *clkset_uhost_list[] = {
 605         &clk_48m,
 606         &clk_mout_epll.clk,
 607         &clk_dout_mpll,
 608         &clk_fin_epll,
 609 };
 610
 611 static struct clksrc_sources clkset_uhost = {
 612         .sources        = clkset_uhost_list,
 613         .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
 614 };
 615
 616 /* The peripheral clocks are all controlled via clocksource followed
 617  * by an optional divider and gate stage. We currently roll this into
 618  * one clock which hides the intermediate clock from the mux.
 619  *
 620  * Note, the JPEG clock can only be an even divider...
 621  *
 622  * The scaler and LCD clocks depend on the S3C64XX version, and also
 623  * have a common parent divisor so are not included here.
 624  */
 625
 626 /* clocks that feed other parts of the clock source tree */
 627
 628 static struct clk clk_iis_cd0 = {
 629         .name           = "iis_cdclk0",
 630 };
 631
 632 static struct clk clk_iis_cd1 = {
 633         .name           = "iis_cdclk1",
 634 };
 635
 636 static struct clk clk_iisv4_cd = {
 637         .name           = "iis_cdclk_v4",
 638 };
 639
 640 static struct clk clk_pcm_cd = {
 641         .name           = "pcm_cdclk",
 642 };
 643
 644 static struct clk *clkset_audio0_list[] = {
 645         [0] = &clk_mout_epll.clk,
 646         [1] = &clk_dout_mpll,
 647         [2] = &clk_fin_epll,
 648         [3] = &clk_iis_cd0,
 649         [4] = &clk_pcm_cd,
 650 };
 651
 652 static struct clksrc_sources clkset_audio0 = {
 653         .sources        = clkset_audio0_list,
 654         .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
 655 };
 656
 657 static struct clk *clkset_audio1_list[] = {
 658         [0] = &clk_mout_epll.clk,
 659         [1] = &clk_dout_mpll,
 660         [2] = &clk_fin_epll,
 661         [3] = &clk_iis_cd1,
 662         [4] = &clk_pcm_cd,
 663 };
 664
 665 static struct clksrc_sources clkset_audio1 = {
 666         .sources        = clkset_audio1_list,
 667         .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
 668 };
 669
 670 #ifdef CONFIG_CPU_S3C6410
 671 static struct clk *clkset_audio2_list[] = {
 672         [0] = &clk_mout_epll.clk,
 673         [1] = &clk_dout_mpll,
 674         [2] = &clk_fin_epll,
 675         [3] = &clk_iisv4_cd,
 676         [4] = &clk_pcm_cd,
 677 };
 678
 679 static struct clksrc_sources clkset_audio2 = {
 680         .sources        = clkset_audio2_list,
 681         .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
 682 };
 683 #endif
 684
 685 static struct clksrc_clk clksrcs[] = {
 686         {
 687                 .clk    = {
 688                         .name           = "usb-bus-host",
 689                         .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
 690                         .enable         = s3c64xx_sclk_ctrl,
 691                 },
 692                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2  },
 693                 .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },
 694                 .sources        = &clkset_uhost,
 695         }, {
 696                 .clk    = {
 697                         .name           = "irda-bus",
 698                         .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
 699                         .enable         = s3c64xx_sclk_ctrl,
 700                 },
 701                 .reg_src        = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2  },
 702                 .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4  },
 703                 .sources        = &clkset_irda,
 704         }, {
 705                 .clk    = {
 706                         .name           = "camera",
 707                         .ctrlbit        = S3C_CLKCON_SCLK_CAM,
 708                         .enable         = s3c64xx_sclk_ctrl,
 709                         .parent         = &clk_h2,
 710                 },
 711                 .reg_div        = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
 712         },
 713 };
 714
 715 /* Where does UCLK0 come from? */
 716 static struct clksrc_clk clk_sclk_uclk = {
 717         .clk    = {
 718                 .name           = "uclk1",
 719                 .ctrlbit        = S3C_CLKCON_SCLK_UART,
 720                 .enable         = s3c64xx_sclk_ctrl,
 721         },
 722         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
 723         .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
 724         .sources        = &clkset_uart,
 725 };
 726
 727 static struct clksrc_clk clk_sclk_mmc0 = {
 728         .clk    = {
 729                 .name           = "mmc_bus",
 730                 .devname        = "s3c-sdhci.0",
 731                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
 732                 .enable         = s3c64xx_sclk_ctrl,
 733         },
 734         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
 735         .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
 736         .sources        = &clkset_spi_mmc,
 737 };
 738
 739 static struct clksrc_clk clk_sclk_mmc1 = {
 740         .clk    = {
 741                 .name           = "mmc_bus",
 742                 .devname        = "s3c-sdhci.1",
 743                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
 744                 .enable         = s3c64xx_sclk_ctrl,
 745         },
 746         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
 747         .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
 748         .sources        = &clkset_spi_mmc,
 749 };
 750
 751 static struct clksrc_clk clk_sclk_mmc2 = {
 752         .clk    = {
 753                 .name           = "mmc_bus",
 754                 .devname        = "s3c-sdhci.2",
 755                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
 756                 .enable         = s3c64xx_sclk_ctrl,
 757         },
 758         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
 759         .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
 760         .sources        = &clkset_spi_mmc,
 761 };
 762
 763 static struct clksrc_clk clk_sclk_spi0 = {
 764         .clk    = {
 765                 .name           = "spi-bus",
 766                 .devname        = "s3c6410-spi.0",
 767                 .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
 768                 .enable         = s3c64xx_sclk_ctrl,
 769         },
 770         .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
 771         .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
 772         .sources = &clkset_spi_mmc,
 773 };
 774
 775 static struct clksrc_clk clk_sclk_spi1 = {
 776         .clk    = {
 777                 .name           = "spi-bus",
 778                 .devname        = "s3c6410-spi.1",
 779                 .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
 780                 .enable         = s3c64xx_sclk_ctrl,
 781         },
 782         .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
 783         .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
 784         .sources = &clkset_spi_mmc,
 785 };
 786
 787 static struct clksrc_clk clk_audio_bus0 = {
 788         .clk    = {
 789                 .name           = "audio-bus",
 790                 .devname        = "samsung-i2s.0",
 791                 .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
 792                 .enable         = s3c64xx_sclk_ctrl,
 793         },
 794         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3  },
 795         .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4  },
 796         .sources        = &clkset_audio0,
 797 };
 798
 799 static struct clksrc_clk clk_audio_bus1 = {
 800         .clk    = {
 801                 .name           = "audio-bus",
 802                 .devname        = "samsung-i2s.1",
 803                 .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
 804                 .enable         = s3c64xx_sclk_ctrl,
 805         },
 806         .reg_src        = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3  },
 807         .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4  },
 808         .sources        = &clkset_audio1,
 809 };
 810
 811 #ifdef CONFIG_CPU_S3C6410
 812 static struct clksrc_clk clk_audio_bus2 = {
 813         .clk    = {
 814                 .name           = "audio-bus",
 815                 .devname        = "samsung-i2s.2",
 816                 .ctrlbit        = S3C6410_CLKCON_SCLK_AUDIO2,
 817                 .enable         = s3c64xx_sclk_ctrl,
 818         },
 819         .reg_src        = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3  },
 820         .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4  },
 821         .sources        = &clkset_audio2,
 822 };
 823 #endif
 824 /* Clock initialisation code */
 825
 826 static struct clksrc_clk *init_parents[] = {
 827         &clk_mout_apll,
 828         &clk_mout_epll,
 829         &clk_mout_mpll,
 830 };
 831
 832 static struct clksrc_clk *clksrc_cdev[] = {
 833         &clk_sclk_uclk,
 834         &clk_sclk_mmc0,
 835         &clk_sclk_mmc1,
 836         &clk_sclk_mmc2,
 837         &clk_sclk_spi0,
 838         &clk_sclk_spi1,
 839         &clk_audio_bus0,
 840         &clk_audio_bus1,
 841 };
 842
 843 static struct clk *clk_cdev[] = {
 844         &clk_hsmmc0,
 845         &clk_hsmmc1,
 846         &clk_hsmmc2,
 847         &clk_48m_spi0,
 848         &clk_48m_spi1,
 849         &clk_i2s0,
 850         &clk_i2s1,
 851 };
 852
 853 static struct clk_lookup s3c64xx_clk_lookup[] = {
 854         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
 855         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 856         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
 857         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
 858         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
 859         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
 860         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 861         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 862         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
 863         CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
 864         CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
 865         CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 866         CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
 867         CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
 868         CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk),
 869         CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
 870         CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk),
 871 #ifdef CONFIG_CPU_S3C6410
 872         CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
 873         CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk),
 874 #endif
 875 };
 876
 877 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 878
 879 void __init_or_cpufreq s3c64xx_setup_clocks(void)
 880 {
 881         struct clk *xtal_clk;
 882         unsigned long xtal;
 883         unsigned long fclk;
 884         unsigned long hclk;
 885         unsigned long hclk2;
 886         unsigned long pclk;
 887         unsigned long epll;
 888         unsigned long apll;
 889         unsigned long mpll;
 890         unsigned int ptr;
 891         u32 clkdiv0;
 892
 893         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 894
 895         clkdiv0 = __raw_readl(S3C_CLK_DIV0);
 896         printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
 897
 898         xtal_clk = clk_get(NULL, "xtal");
 899         BUG_ON(IS_ERR(xtal_clk));
 900
 901         xtal = clk_get_rate(xtal_clk);
 902         clk_put(xtal_clk);
 903
 904         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 905
 906         /* For now assume the mux always selects the crystal */
 907         clk_ext_xtal_mux.parent = xtal_clk;
 908
 909         epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
 910                                 __raw_readl(S3C_EPLL_CON1));
 911         mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
 912         apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
 913
 914         fclk = mpll;
 915
 916         printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
 917                apll, mpll, epll);
 918
 919         if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
 920                 /* Synchronous mode */
 921                 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
 922         else
 923                 /* Asynchronous mode */
 924                 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
 925
 926         hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
 927         pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
 928
 929         printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
 930                hclk2, hclk, pclk);
 931
 932         clk_fout_mpll.rate = mpll;
 933         clk_fout_epll.rate = epll;
 934         clk_fout_apll.rate = apll;
 935
 936         clk_h2.rate = hclk2;
 937         clk_h.rate = hclk;
 938         clk_p.rate = pclk;
 939         clk_f.rate = fclk;
 940
 941         for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
 942                 s3c_set_clksrc(init_parents[ptr], true);
 943
 944         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 945                 s3c_set_clksrc(&clksrcs[ptr], true);
 946 }
 947
 948 static struct clk *clks1[] __initdata = {
 949         &clk_ext_xtal_mux,
 950         &clk_iis_cd0,
 951         &clk_iis_cd1,
 952         &clk_iisv4_cd,
 953         &clk_pcm_cd,
 954         &clk_mout_epll.clk,
 955         &clk_mout_mpll.clk,
 956         &clk_dout_mpll,
 957         &clk_arm,
 958 };
 959
 960 static struct clk *clks[] __initdata = {
 961         &clk_ext,
 962         &clk_epll,
 963         &clk_27m,
 964         &clk_48m,
 965         &clk_h2,
 966         &clk_xusbxti,
 967 };
 968
 969 /**
 970  * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
 971  * @xtal: The rate for the clock crystal feeding the PLLs.
 972  * @armclk_divlimit: Divisor mask for ARMCLK.
 973  *
 974  * Register the clocks for the S3C6400 and S3C6410 SoC range, such
 975  * as ARMCLK as well as the necessary parent clocks.
 976  *
 977  * This call does not setup the clocks, which is left to the
 978  * s3c64xx_setup_clocks() call which may be needed by the cpufreq
 979  * or resume code to re-set the clocks if the bootloader has changed
 980  * them.
 981  */
 982 void __init s3c64xx_register_clocks(unsigned long xtal,
 983                                     unsigned armclk_divlimit)
 984 {
 985         unsigned int cnt;
 986
 987         armclk_mask = armclk_divlimit;
 988
 989         s3c24xx_register_baseclocks(xtal);
 990         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 991
 992         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 993
 994         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 995         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 996
 997         s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
 998         for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
 999                 s3c_disable_clocks(clk_cdev[cnt], 1);
1000
1001         s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
1002         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1003         for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
1004                 s3c_register_clksrc(clksrc_cdev[cnt], 1);
1005         clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
1006
1007         s3c_pwmclk_init();
1008 }