1 /* arch/arm/mach-s3c2410/include/mach/dma.h
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * Samsung S3C24XX DMA support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_DMA_H
14 #define __ASM_ARCH_DMA_H __FILE__
16 #include <linux/device.h>
18 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
20 /* We use `virtual` dma channels to hide the fact we have only a limited
21 * number of DMA channels, and not of all of them (dependent on the device)
22 * can be attached to any DMA source. We therefore let the DMA core handle
23 * the allocation of hardware channels to clients.
27 DMACH_DT_PROP = -1, /* not yet supported, do not use */
46 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
49 DMACH_UART3, /* s3c2443 has extra uart */
51 DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */
52 DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */
53 DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */
54 DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */
55 DMACH_MAX, /* the end entry */
58 static inline bool samsung_dma_has_circular(void)
63 static inline bool samsung_dma_is_dmadev(void)
70 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
72 /* we have 4 dma channels */
73 #if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
74 #define S3C_DMA_CHANNELS (4)
76 #define S3C_DMA_CHANNELS (6)
81 enum s3c2410_dma_state {
87 /* enum s3c2410_dma_loadst
89 * This represents the state of the DMA engine, wrt to the loaded / running
90 * transfers. Since we don't have any way of knowing exactly the state of
91 * the DMA transfers, we need to know the state to make decisions on wether
96 * There are no buffers loaded (the channel should be inactive)
100 * There is one buffer loaded, however it has not been confirmed to be
101 * loaded by the DMA engine. This may be because the channel is not
102 * yet running, or the DMA driver decided that it was too costly to
103 * sit and wait for it to happen.
105 * S3C2410_DMA_1RUNNING
107 * The buffer has been confirmed running, and not finisged
109 * S3C2410_DMA_1LOADED_1RUNNING
111 * There is a buffer waiting to be loaded by the DMA engine, and one
115 enum s3c2410_dma_loadst {
116 S3C2410_DMALOAD_NONE,
117 S3C2410_DMALOAD_1LOADED,
118 S3C2410_DMALOAD_1RUNNING,
119 S3C2410_DMALOAD_1LOADED_1RUNNING,
125 #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
126 * waiting for reloads */
127 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
129 #define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
133 struct s3c2410_dma_buf;
137 * internally used buffer structure to describe a queued or running
141 struct s3c2410_dma_buf {
142 struct s3c2410_dma_buf *next;
143 int magic; /* magic */
144 int size; /* buffer size in bytes */
145 dma_addr_t data; /* start of DMA data */
146 dma_addr_t ptr; /* where the DMA got to [1] */
147 void *id; /* client's id */
150 /* [1] is this updated for both recv/send modes? */
152 struct s3c2410_dma_stats {
154 unsigned long timeout_longest;
155 unsigned long timeout_shortest;
156 unsigned long timeout_avg;
157 unsigned long timeout_failed;
160 struct s3c2410_dma_map;
162 /* struct s3c2410_dma_chan
164 * full state information for each DMA channel
167 struct s3c2410_dma_chan {
168 /* channel state flags and information */
169 unsigned char number; /* number of this dma channel */
170 unsigned char in_use; /* channel allocated */
171 unsigned char irq_claimed; /* irq claimed for channel */
172 unsigned char irq_enabled; /* irq enabled for channel */
173 unsigned char xfer_unit; /* size of an transfer */
177 enum s3c2410_dma_state state;
178 enum s3c2410_dma_loadst load_state;
179 struct s3c2410_dma_client *client;
181 /* channel configuration */
182 enum dma_data_direction source;
184 unsigned long dev_addr;
185 unsigned long load_timeout;
186 unsigned int flags; /* channel flags */
188 struct s3c24xx_dma_map *map; /* channel hw maps */
190 /* channel's hardware position and configuration */
191 void __iomem *regs; /* channels registers */
192 void __iomem *addr_reg; /* data address register */
193 unsigned int irq; /* channel irq */
194 unsigned long dcon; /* default value of DCON */
197 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
198 s3c2410_dma_opfn_t op_fn; /* channel op callback */
200 /* stats gathering */
201 struct s3c2410_dma_stats *stats;
202 struct s3c2410_dma_stats stats_store;
204 /* buffer list and information */
205 struct s3c2410_dma_buf *curr; /* current dma buffer */
206 struct s3c2410_dma_buf *next; /* next buffer to load */
207 struct s3c2410_dma_buf *end; /* end of queue */
213 typedef unsigned long dma_device_t;
215 #endif /* __ASM_ARCH_DMA_H */