1 /* linux/arch/arm/mach-s3c2410/cpu-freq.c
3 * Copyright (c) 2006-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C2410 CPU Frequency scaling
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/cpufreq.h>
19 #include <linux/device.h>
20 #include <linux/clk.h>
21 #include <linux/err.h>
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
27 #include <mach/regs-clock.h>
30 #include <plat/clock.h>
31 #include <plat/cpu-freq-core.h>
33 /* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
35 static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
39 if (cfg->divs.h_divisor == 2)
40 clkdiv |= S3C2410_CLKDIVN_HDIVN;
42 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
43 clkdiv |= S3C2410_CLKDIVN_PDIVN;
45 __raw_writel(clkdiv, S3C2410_CLKDIVN);
48 static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
50 unsigned long hclk, fclk, pclk;
51 unsigned int hdiv, pdiv;
52 unsigned long hclk_max;
54 fclk = cfg->freq.fclk;
55 hclk_max = cfg->max.hclk;
57 cfg->freq.armclk = fclk;
59 s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
60 __func__, fclk, hclk_max);
62 hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
65 if (hclk > cfg->max.hclk) {
66 s3c_freq_dbg("%s: hclk too big\n", __func__);
70 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
73 if (pclk > cfg->max.pclk) {
74 s3c_freq_dbg("%s: pclk too big\n", __func__);
80 /* record the result */
81 cfg->divs.p_divisor = pdiv;
82 cfg->divs.h_divisor = hdiv;
87 static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
94 /* transition latency is about 5ms worst-case, so
95 * set 10ms to be sure */
105 .calc_iotiming = s3c2410_iotiming_calc,
106 .set_iotiming = s3c2410_iotiming_set,
107 .get_iotiming = s3c2410_iotiming_get,
108 .resume_clocks = s3c2410_setup_clocks,
110 .set_fvco = s3c2410_set_fvco,
111 .set_refresh = s3c2410_cpufreq_setrefresh,
112 .set_divs = s3c2410_cpufreq_setdivs,
113 .calc_divs = s3c2410_cpufreq_calcdivs,
115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
118 static int s3c2410_cpufreq_add(struct device *dev)
120 return s3c_cpufreq_register(&s3c2410_cpufreq_info);
123 static struct subsys_interface s3c2410_cpufreq_interface = {
124 .name = "s3c2410_cpufreq",
125 .subsys = &s3c2410_subsys,
126 .add_dev = s3c2410_cpufreq_add,
129 static int __init s3c2410_cpufreq_init(void)
131 return subsys_interface_register(&s3c2410_cpufreq_interface);
134 arch_initcall(s3c2410_cpufreq_init);
136 static int s3c2410a_cpufreq_add(struct device *dev)
138 /* alter the maximum freq settings for S3C2410A. If a board knows
139 * it only has a maximum of 200, then it should register its own
142 s3c2410_cpufreq_info.max.fclk = 266000000;
143 s3c2410_cpufreq_info.max.hclk = 133000000;
144 s3c2410_cpufreq_info.max.pclk = 66500000;
145 s3c2410_cpufreq_info.name = "s3c2410a";
147 return s3c2410_cpufreq_add(dev);
150 static struct subsys_interface s3c2410a_cpufreq_interface = {
151 .name = "s3c2410a_cpufreq",
152 .subsys = &s3c2410a_subsys,
153 .add_dev = s3c2410a_cpufreq_add,
156 static int __init s3c2410a_cpufreq_init(void)
158 return subsys_interface_register(&s3c2410a_cpufreq_interface);
161 arch_initcall(s3c2410a_cpufreq_init);