arch/arm/mach-rockchip/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <debug_uart.h>
   8 #include <dm.h>
   9 #include <hang.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <ram.h>
  14 #include <spl.h>
  15 #include <asm/arch-rockchip/bootrom.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <linux/bitops.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 int board_return_to_bootrom(struct spl_image_info *spl_image,
  23                             struct spl_boot_device *bootdev)
  24 {
  25         back_to_bootrom(BROM_BOOT_NEXTSTAGE);
  26
  27         return 0;
  28 }
  29
  30 __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  31 };
  32
  33 const char *board_spl_was_booted_from(void)
  34 {
  35         u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
  36         const char *bootdevice_ofpath = NULL;
  37
  38         if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
  39                 bootdevice_ofpath = boot_devices[bootdevice_brom_id];
  40
  41         if (bootdevice_ofpath)
  42                 debug("%s: brom_bootdevice_id %x maps to '%s'\n",
  43                       __func__, bootdevice_brom_id, bootdevice_ofpath);
  44         else
  45                 debug("%s: failed to resolve brom_bootdevice_id %x\n",
  46                       __func__, bootdevice_brom_id);
  47
  48         return bootdevice_ofpath;
  49 }
  50
  51 u32 spl_boot_device(void)
  52 {
  53         u32 boot_device = BOOT_DEVICE_MMC1;
  54
  55 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
  56                 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
  57                 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
  58                 defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \
  59                 defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \
  60                 defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
  61         return BOOT_DEVICE_SPI;
  62 #endif
  63         if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
  64                 return BOOT_DEVICE_BOOTROM;
  65
  66         return boot_device;
  67 }
  68
  69 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
  70 {
  71         return MMCSD_MODE_RAW;
  72 }
  73
  74 #if !defined(CONFIG_ROCKCHIP_RK3188)
  75 #define TIMER_LOAD_COUNT_L      0x00
  76 #define TIMER_LOAD_COUNT_H      0x04
  77 #define TIMER_CONTROL_REG       0x10
  78 #define TIMER_EN        0x1
  79 #define TIMER_FMODE     BIT(0)
  80 #define TIMER_RMODE     BIT(1)
  81
  82 __weak void rockchip_stimer_init(void)
  83 {
  84         /* If Timer already enabled, don't re-init it */
  85         u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  86
  87         if (reg & TIMER_EN)
  88                 return;
  89 #ifndef CONFIG_ARM64
  90         asm volatile("mcr p15, 0, %0, c14, c0, 0"
  91                      : : "r"(COUNTER_FREQUENCY));
  92 #endif
  93         writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
  94         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
  95         writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
  96         writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
  97                TIMER_CONTROL_REG);
  98 }
  99 #endif
 100
 101 __weak int board_early_init_f(void)
 102 {
 103         return 0;
 104 }
 105
 106 __weak int arch_cpu_init(void)
 107 {
 108         return 0;
 109 }
 110
 111 void board_init_f(ulong dummy)
 112 {
 113         int ret;
 114
 115 #ifdef CONFIG_DEBUG_UART
 116         /*
 117          * Debug UART can be used from here if required:
 118          *
 119          * debug_uart_init();
 120          * printch('a');
 121          * printhex8(0x1234);
 122          * printascii("string");
 123          */
 124         debug_uart_init();
 125         debug("\nspl:debug uart enabled in %s\n", __func__);
 126 #endif
 127
 128         board_early_init_f();
 129
 130         ret = spl_early_init();
 131         if (ret) {
 132                 printf("spl_early_init() failed: %d\n", ret);
 133                 hang();
 134         }
 135         arch_cpu_init();
 136 #if !defined(CONFIG_ROCKCHIP_RK3188)
 137         rockchip_stimer_init();
 138 #endif
 139 #ifdef CONFIG_SYS_ARCH_TIMER
 140         /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
 141         timer_init();
 142 #endif
 143 #if !defined(CONFIG_TPL) || defined(CONFIG_SPL_RAM)
 144         debug("\nspl:init dram\n");
 145         ret = dram_init();
 146         if (ret) {
 147                 printf("DRAM init failed: %d\n", ret);
 148                 return;
 149         }
 150         gd->ram_top = gd->ram_base + get_effective_memsize();
 151         gd->ram_top = board_get_usable_ram_top(gd->ram_size);
 152 #endif
 153         preloader_console_init();
 154 }