arch/arm/mach-rockchip/sdram_common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <ram.h>
   9 #include <asm/io.h>
  10 #include <asm/arch-rockchip/sdram_common.h>
  11 #include <dm/uclass-internal.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 #define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)
  16
  17 struct tos_parameter_t {
  18         u32 version;
  19         u32 checksum;
  20         struct {
  21                 char name[8];
  22                 s64 phy_addr;
  23                 u32 size;
  24                 u32 flags;
  25         } tee_mem;
  26         struct {
  27                 char name[8];
  28                 s64 phy_addr;
  29                 u32 size;
  30                 u32 flags;
  31         } drm_mem;
  32         s64 reserve[8];
  33 };
  34
  35 int dram_init_banksize(void)
  36 {
  37         size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
  38                          gd->ram_top);
  39
  40 #ifdef CONFIG_ARM64
  41         /* Reserve 0x200000 for ATF bl31 */
  42         gd->bd->bi_dram[0].start = 0x200000;
  43         gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  44 #else
  45 #ifdef CONFIG_SPL_OPTEE
  46         struct tos_parameter_t *tos_parameter;
  47
  48         tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
  49                         TRUST_PARAMETER_OFFSET);
  50
  51         if (tos_parameter->tee_mem.flags == 1) {
  52                 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  53                 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
  54                                         - CONFIG_SYS_SDRAM_BASE;
  55                 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
  56                                         tos_parameter->tee_mem.size;
  57                 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  58                                         + top - gd->bd->bi_dram[1].start;
  59         } else {
  60                 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  61                 gd->bd->bi_dram[0].size = 0x8400000;
  62                 /* Reserve 32M for OPTEE with TA */
  63                 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
  64                                         + gd->bd->bi_dram[0].size + 0x2000000;
  65                 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  66                                         + top - gd->bd->bi_dram[1].start;
  67         }
  68 #else
  69         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  70         gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  71 #endif
  72 #endif
  73
  74         return 0;
  75 }
  76
  77 size_t rockchip_sdram_size(phys_addr_t reg)
  78 {
  79         u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
  80         size_t chipsize_mb = 0;
  81         size_t size_mb = 0;
  82         u32 ch;
  83
  84         u32 sys_reg = readl(reg);
  85         u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
  86                        & SYS_REG_NUM_CH_MASK);
  87
  88         debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
  89         for (ch = 0; ch < ch_num; ch++) {
  90                 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
  91                         SYS_REG_RANK_MASK);
  92                 col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
  93                 bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
  94                 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
  95                                 SYS_REG_CS0_ROW_MASK);
  96                 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
  97                                 SYS_REG_CS1_ROW_MASK);
  98                 bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
  99                         SYS_REG_BW_MASK));
 100                 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 101                         SYS_REG_ROW_3_4_MASK;
 102
 103                 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
 104
 105                 if (rank > 1)
 106                         chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
 107                 if (row_3_4)
 108                         chipsize_mb = chipsize_mb * 3 / 4;
 109                 size_mb += chipsize_mb;
 110                 debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
 111                       rank, col, bk, cs0_row, bw, row_3_4);
 112         }
 113
 114         /*
 115          * This is workaround for issue we can't get correct size for 4GB ram
 116          * in 32bit system and available before we really need ram space
 117          * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
 118          * The size of 4GB is '0x1 00000000', and this value will be truncated
 119          * to 0 in 32bit system, and system can not get correct ram size.
 120          * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
 121          * and we are now setting SDRAM_MAX_SIZE as max available space for
 122          * ram in 4GB, so we can use this directly to workaround the issue.
 123          * TODO:
 124          *   1. update correct value for SDRAM_MAX_SIZE as what dram
 125          *   controller sees.
 126          *   2. update board_get_usable_ram_top() and dram_init_banksize()
 127          *   to reserve memory for peripheral space after previous update.
 128          */
 129         if (size_mb > (SDRAM_MAX_SIZE >> 20))
 130                 size_mb = (SDRAM_MAX_SIZE >> 20);
 131
 132         return (size_t)size_mb << 20;
 133 }
 134
 135 int dram_init(void)
 136 {
 137         struct ram_info ram;
 138         struct udevice *dev;
 139         int ret;
 140
 141         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 142         if (ret) {
 143                 debug("DRAM init failed: %d\n", ret);
 144                 return ret;
 145         }
 146         ret = ram_get_info(dev, &ram);
 147         if (ret) {
 148                 debug("Cannot get DRAM size: %d\n", ret);
 149                 return ret;
 150         }
 151         gd->ram_size = ram.size;
 152         debug("SDRAM base=%lx, size=%lx\n",
 153               (unsigned long)ram.base, (unsigned long)ram.size);
 154
 155         return 0;
 156 }
 157
 158 ulong board_get_usable_ram_top(ulong total_size)
 159 {
 160         unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
 161
 162         return (gd->ram_top > top) ? top : gd->ram_top;
 163 }