arch/arm/mach-rockchip/sdram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <ram.h>
  11 #include <asm/global_data.h>
  12 #include <asm/io.h>
  13 #include <asm/arch-rockchip/sdram.h>
  14 #include <dm/uclass-internal.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)
  19
  20 struct tos_parameter_t {
  21         u32 version;
  22         u32 checksum;
  23         struct {
  24                 char name[8];
  25                 s64 phy_addr;
  26                 u32 size;
  27                 u32 flags;
  28         } tee_mem;
  29         struct {
  30                 char name[8];
  31                 s64 phy_addr;
  32                 u32 size;
  33                 u32 flags;
  34         } drm_mem;
  35         s64 reserve[8];
  36 };
  37
  38 int dram_init_banksize(void)
  39 {
  40         size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
  41         size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top));
  42
  43 #ifdef CONFIG_ARM64
  44         /* Reserve 0x200000 for ATF bl31 */
  45         gd->bd->bi_dram[0].start = 0x200000;
  46         gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  47
  48         /* Add usable memory beyond the blob of space for peripheral near 4GB */
  49         if (ram_top > SZ_4G && top < SZ_4G) {
  50                 gd->bd->bi_dram[1].start = SZ_4G;
  51                 gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
  52         }
  53 #else
  54 #ifdef CONFIG_SPL_OPTEE_IMAGE
  55         struct tos_parameter_t *tos_parameter;
  56
  57         tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE +
  58                         TRUST_PARAMETER_OFFSET);
  59
  60         if (tos_parameter->tee_mem.flags == 1) {
  61                 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
  62                 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
  63                                         - CFG_SYS_SDRAM_BASE;
  64                 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
  65                                         tos_parameter->tee_mem.size;
  66                 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
  67         } else {
  68                 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
  69                 gd->bd->bi_dram[0].size = 0x8400000;
  70                 /* Reserve 32M for OPTEE with TA */
  71                 gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
  72                                         + gd->bd->bi_dram[0].size + 0x2000000;
  73                 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
  74         }
  75 #else
  76         gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
  77         gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  78 #endif
  79 #endif
  80
  81         return 0;
  82 }
  83
  84 size_t rockchip_sdram_size(phys_addr_t reg)
  85 {
  86         u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
  87         size_t chipsize_mb = 0;
  88         size_t size_mb = 0;
  89         u32 ch;
  90         u32 cs1_col = 0;
  91         u32 bg = 0;
  92         u32 dbw, dram_type;
  93         u32 sys_reg2 = readl(reg);
  94         u32 sys_reg3 = readl(reg + 4);
  95         u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
  96                        & SYS_REG_NUM_CH_MASK);
  97         u32 version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) &
  98                       SYS_REG_VERSION_MASK;
  99
 100         dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
 101         if (version >= 3)
 102                 dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
 103                               SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
 104         debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
 105         debug("%s %x %x\n", __func__, (u32)reg + 4, sys_reg3);
 106         for (ch = 0; ch < ch_num; ch++) {
 107                 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
 108                         SYS_REG_RANK_MASK);
 109                 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
 110                           SYS_REG_COL_MASK);
 111                 cs1_col = cs0_col;
 112                 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
 113                 if (version >= 2) {
 114                         cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
 115                                   SYS_REG_CS1_COL_MASK);
 116                         if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
 117                             SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
 118                             SYS_REG_CS0_ROW_SHIFT(ch) &
 119                             SYS_REG_CS0_ROW_MASK) == 7)
 120                                 cs0_row = 12;
 121                         else
 122                                 cs0_row = 13 + (sys_reg2 >>
 123                                           SYS_REG_CS0_ROW_SHIFT(ch) &
 124                                           SYS_REG_CS0_ROW_MASK) +
 125                                           ((sys_reg3 >>
 126                                           SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
 127                                           SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
 128                         if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
 129                             SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
 130                             SYS_REG_CS1_ROW_SHIFT(ch) &
 131                             SYS_REG_CS1_ROW_MASK) == 7)
 132                                 cs1_row = 12;
 133                         else
 134                                 cs1_row = 13 + (sys_reg2 >>
 135                                           SYS_REG_CS1_ROW_SHIFT(ch) &
 136                                           SYS_REG_CS1_ROW_MASK) +
 137                                           ((sys_reg3 >>
 138                                           SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
 139                                           SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
 140                 } else {
 141                         cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
 142                                 SYS_REG_CS0_ROW_MASK);
 143                         cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
 144                                 SYS_REG_CS1_ROW_MASK);
 145                 }
 146                 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
 147                         SYS_REG_BW_MASK));
 148                 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
 149                         SYS_REG_ROW_3_4_MASK;
 150                 if (dram_type == DDR4) {
 151                         dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
 152                                 SYS_REG_DBW_MASK;
 153                         bg = (dbw == 2) ? 2 : 1;
 154                 }
 155                 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
 156
 157                 if (rank > 1)
 158                         chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
 159                                        (cs0_col - cs1_col));
 160                 if (row_3_4)
 161                         chipsize_mb = chipsize_mb * 3 / 4;
 162                 size_mb += chipsize_mb;
 163                 if (rank > 1)
 164                         debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
 165                                cs1_row %d bw %d row_3_4 %d\n",
 166                                rank, cs0_col, cs1_col, bk, cs0_row,
 167                                cs1_row, bw, row_3_4);
 168                 else
 169                         debug("rank %d cs0_col %d bk %d cs0_row %d\
 170                                bw %d row_3_4 %d\n",
 171                                rank, cs0_col, bk, cs0_row,
 172                                bw, row_3_4);
 173         }
 174
 175         /*
 176          * This is workaround for issue we can't get correct size for 4GB ram
 177          * in 32bit system and available before we really need ram space
 178          * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
 179          * The size of 4GB is '0x1 00000000', and this value will be truncated
 180          * to 0 in 32bit system, and system can not get correct ram size.
 181          * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
 182          * and we are now setting SDRAM_MAX_SIZE as max available space for
 183          * ram in 4GB, so we can use this directly to workaround the issue.
 184          * TODO:
 185          *   1. update correct value for SDRAM_MAX_SIZE as what dram
 186          *   controller sees.
 187          *   2. update board_get_usable_ram_top() and dram_init_banksize()
 188          *   to reserve memory for peripheral space after previous update.
 189          */
 190         if (!IS_ENABLED(CONFIG_ARM64) && size_mb > (SDRAM_MAX_SIZE >> 20))
 191                 size_mb = (SDRAM_MAX_SIZE >> 20);
 192
 193         return (size_t)size_mb << 20;
 194 }
 195
 196 int dram_init(void)
 197 {
 198         struct ram_info ram;
 199         struct udevice *dev;
 200         int ret;
 201
 202         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 203         if (ret) {
 204                 debug("DRAM init failed: %d\n", ret);
 205                 return ret;
 206         }
 207         ret = ram_get_info(dev, &ram);
 208         if (ret) {
 209                 debug("Cannot get DRAM size: %d\n", ret);
 210                 return ret;
 211         }
 212         gd->ram_size = ram.size;
 213         debug("SDRAM base=%lx, size=%lx\n",
 214               (unsigned long)ram.base, (unsigned long)ram.size);
 215
 216         return 0;
 217 }
 218
 219 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 220 {
 221         unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
 222
 223         return (gd->ram_top > top) ? top : gd->ram_top;
 224 }