arch/arm/mach-rockchip/sdram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <ram.h>
  11 #include <asm/io.h>
  12 #include <asm/arch-rockchip/sdram.h>
  13 #include <dm/uclass-internal.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #define TRUST_PARAMETER_OFFSET    (34 * 1024 * 1024)
  18
  19 struct tos_parameter_t {
  20         u32 version;
  21         u32 checksum;
  22         struct {
  23                 char name[8];
  24                 s64 phy_addr;
  25                 u32 size;
  26                 u32 flags;
  27         } tee_mem;
  28         struct {
  29                 char name[8];
  30                 s64 phy_addr;
  31                 u32 size;
  32                 u32 flags;
  33         } drm_mem;
  34         s64 reserve[8];
  35 };
  36
  37 int dram_init_banksize(void)
  38 {
  39         size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
  40                          (unsigned long)(gd->ram_top));
  41
  42 #ifdef CONFIG_ARM64
  43         /* Reserve 0x200000 for ATF bl31 */
  44         gd->bd->bi_dram[0].start = 0x200000;
  45         gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  46 #else
  47 #ifdef CONFIG_SPL_OPTEE
  48         struct tos_parameter_t *tos_parameter;
  49
  50         tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
  51                         TRUST_PARAMETER_OFFSET);
  52
  53         if (tos_parameter->tee_mem.flags == 1) {
  54                 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  55                 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
  56                                         - CONFIG_SYS_SDRAM_BASE;
  57                 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
  58                                         tos_parameter->tee_mem.size;
  59                 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
  60         } else {
  61                 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  62                 gd->bd->bi_dram[0].size = 0x8400000;
  63                 /* Reserve 32M for OPTEE with TA */
  64                 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
  65                                         + gd->bd->bi_dram[0].size + 0x2000000;
  66                 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
  67         }
  68 #else
  69         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  70         gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
  71 #endif
  72 #endif
  73
  74         return 0;
  75 }
  76
  77 size_t rockchip_sdram_size(phys_addr_t reg)
  78 {
  79         u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
  80         size_t chipsize_mb = 0;
  81         size_t size_mb = 0;
  82         u32 ch;
  83         u32 cs1_col = 0;
  84         u32 bg = 0;
  85         u32 dbw, dram_type;
  86         u32 sys_reg2 = readl(reg);
  87         u32 sys_reg3 = readl(reg + 4);
  88         u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
  89                        & SYS_REG_NUM_CH_MASK);
  90
  91         dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
  92         debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
  93         for (ch = 0; ch < ch_num; ch++) {
  94                 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
  95                         SYS_REG_RANK_MASK);
  96                 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
  97                           SYS_REG_COL_MASK);
  98                 cs1_col = cs0_col;
  99                 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
 100                 if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
 101                      SYS_REG_VERSION_MASK) == 0x2) {
 102                         cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
 103                                   SYS_REG_CS1_COL_MASK);
 104                         if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
 105                             SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
 106                             SYS_REG_CS0_ROW_SHIFT(ch) &
 107                             SYS_REG_CS0_ROW_MASK) == 7)
 108                                 cs0_row = 12;
 109                         else
 110                                 cs0_row = 13 + (sys_reg2 >>
 111                                           SYS_REG_CS0_ROW_SHIFT(ch) &
 112                                           SYS_REG_CS0_ROW_MASK) +
 113                                           ((sys_reg3 >>
 114                                           SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
 115                                           SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
 116                         if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
 117                             SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
 118                             SYS_REG_CS1_ROW_SHIFT(ch) &
 119                             SYS_REG_CS1_ROW_MASK) == 7)
 120                                 cs1_row = 12;
 121                         else
 122                                 cs1_row = 13 + (sys_reg2 >>
 123                                           SYS_REG_CS1_ROW_SHIFT(ch) &
 124                                           SYS_REG_CS1_ROW_MASK) +
 125                                           ((sys_reg3 >>
 126                                           SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
 127                                           SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
 128                 } else {
 129                         cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
 130                                 SYS_REG_CS0_ROW_MASK);
 131                         cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
 132                                 SYS_REG_CS1_ROW_MASK);
 133                 }
 134                 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
 135                         SYS_REG_BW_MASK));
 136                 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
 137                         SYS_REG_ROW_3_4_MASK;
 138                 if (dram_type == DDR4) {
 139                         dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
 140                                 SYS_REG_DBW_MASK;
 141                         bg = (dbw == 2) ? 2 : 1;
 142                 }
 143                 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
 144
 145                 if (rank > 1)
 146                         chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
 147                                        (cs0_col - cs1_col));
 148                 if (row_3_4)
 149                         chipsize_mb = chipsize_mb * 3 / 4;
 150                 size_mb += chipsize_mb;
 151                 if (rank > 1)
 152                         debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
 153                                cs1_row %d bw %d row_3_4 %d\n",
 154                                rank, cs0_col, cs1_col, bk, cs0_row,
 155                                cs1_row, bw, row_3_4);
 156                 else
 157                         debug("rank %d cs0_col %d bk %d cs0_row %d\
 158                                bw %d row_3_4 %d\n",
 159                                rank, cs0_col, bk, cs0_row,
 160                                bw, row_3_4);
 161         }
 162
 163         /*
 164          * This is workaround for issue we can't get correct size for 4GB ram
 165          * in 32bit system and available before we really need ram space
 166          * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
 167          * The size of 4GB is '0x1 00000000', and this value will be truncated
 168          * to 0 in 32bit system, and system can not get correct ram size.
 169          * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
 170          * and we are now setting SDRAM_MAX_SIZE as max available space for
 171          * ram in 4GB, so we can use this directly to workaround the issue.
 172          * TODO:
 173          *   1. update correct value for SDRAM_MAX_SIZE as what dram
 174          *   controller sees.
 175          *   2. update board_get_usable_ram_top() and dram_init_banksize()
 176          *   to reserve memory for peripheral space after previous update.
 177          */
 178         if (size_mb > (SDRAM_MAX_SIZE >> 20))
 179                 size_mb = (SDRAM_MAX_SIZE >> 20);
 180
 181         return (size_t)size_mb << 20;
 182 }
 183
 184 int dram_init(void)
 185 {
 186         struct ram_info ram;
 187         struct udevice *dev;
 188         int ret;
 189
 190         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 191         if (ret) {
 192                 debug("DRAM init failed: %d\n", ret);
 193                 return ret;
 194         }
 195         ret = ram_get_info(dev, &ram);
 196         if (ret) {
 197                 debug("Cannot get DRAM size: %d\n", ret);
 198                 return ret;
 199         }
 200         gd->ram_size = ram.size;
 201         debug("SDRAM base=%lx, size=%lx\n",
 202               (unsigned long)ram.base, (unsigned long)ram.size);
 203
 204         return 0;
 205 }
 206
 207 ulong board_get_usable_ram_top(ulong total_size)
 208 {
 209         unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
 210
 211         return (gd->ram_top > top) ? top : gd->ram_top;
 212 }