rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
[platform/kernel/u-boot.git] / arch / arm / mach-rockchip / rk3399-board-spl.c
1 /*
2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3  * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/arch/bootrom.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/grf_rk3399.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/periph.h>
14 #include <asm/io.h>
15 #include <debug_uart.h>
16 #include <dm.h>
17 #include <dm/pinctrl.h>
18 #include <ram.h>
19 #include <spl.h>
20 #include <syscon.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 void board_return_to_bootrom(void)
25 {
26         back_to_bootrom();
27 }
28
29 u32 spl_boot_device(void)
30 {
31         u32 boot_device = BOOT_DEVICE_MMC1;
32
33         if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
34                 return BOOT_DEVICE_BOOTROM;
35
36         return boot_device;
37 }
38
39 u32 spl_boot_mode(const u32 boot_device)
40 {
41         return MMCSD_MODE_RAW;
42 }
43
44 #define TIMER_CHN10_BASE        0xff8680a0
45 #define TIMER_END_COUNT_L       0x00
46 #define TIMER_END_COUNT_H       0x04
47 #define TIMER_INIT_COUNT_L      0x10
48 #define TIMER_INIT_COUNT_H      0x14
49 #define TIMER_CONTROL_REG       0x1c
50
51 #define TIMER_EN        0x1
52 #define TIMER_FMODE     (0 << 1)
53 #define TIMER_RMODE     (1 << 1)
54
55 void secure_timer_init(void)
56 {
57         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
58         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
59         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
60         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
61         writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
62 }
63
64 void board_debug_uart_init(void)
65 {
66 #define GRF_BASE        0xff770000
67         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
68
69 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
70         /* Enable early UART0 on the RK3399 */
71         rk_clrsetreg(&grf->gpio2c_iomux,
72                      GRF_GPIO2C0_SEL_MASK,
73                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
74         rk_clrsetreg(&grf->gpio2c_iomux,
75                      GRF_GPIO2C1_SEL_MASK,
76                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
77 #else
78         /* Enable early UART2 channel C on the RK3399 */
79         rk_clrsetreg(&grf->gpio4c_iomux,
80                      GRF_GPIO4C3_SEL_MASK,
81                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
82         rk_clrsetreg(&grf->gpio4c_iomux,
83                      GRF_GPIO4C4_SEL_MASK,
84                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
85         /* Set channel C as UART2 input */
86         rk_clrsetreg(&grf->soc_con7,
87                      GRF_UART_DBG_SEL_MASK,
88                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
89 #endif
90 }
91
92 void board_init_f(ulong dummy)
93 {
94         struct udevice *pinctrl;
95         struct udevice *dev;
96         struct rk3399_pmusgrf_regs *sgrf;
97         struct rk3399_grf_regs *grf;
98         int ret;
99
100 #define EARLY_UART
101 #ifdef EARLY_UART
102         /*
103          * Debug UART can be used from here if required:
104          *
105          * debug_uart_init();
106          * printch('a');
107          * printhex8(0x1234);
108          * printascii("string");
109          */
110         debug_uart_init();
111         printascii("U-Boot SPL board init");
112 #endif
113
114         ret = spl_early_init();
115         if (ret) {
116                 debug("spl_early_init() failed: %d\n", ret);
117                 hang();
118         }
119
120         /*
121          * Disable DDR and SRAM security regions.
122          *
123          * As we are entered from the BootROM, the region from
124          * 0x0 through 0xfffff (i.e. the first MB of memory) will
125          * be protected. This will cause issues with the DW_MMC
126          * driver, which tries to DMA from/to the stack (likely)
127          * located in this range.
128          */
129         sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
130         rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
131         rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
132
133         /*  eMMC clock generator: disable the clock multipilier */
134         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
135         rk_clrreg(&grf->emmccore_con[11], 0x0ff);
136
137         secure_timer_init();
138
139         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
140         if (ret) {
141                 debug("Pinctrl init failed: %d\n", ret);
142                 return;
143         }
144
145         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
146         if (ret) {
147                 debug("DRAM init failed: %d\n", ret);
148                 return;
149         }
150 }
151
152 void spl_board_init(void)
153 {
154         struct udevice *pinctrl;
155         int ret;
156
157         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
158         if (ret) {
159                 debug("%s: Cannot find pinctrl device\n", __func__);
160                 goto err;
161         }
162
163         /* Enable debug UART */
164         ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
165         if (ret) {
166                 debug("%s: Failed to set up console UART\n", __func__);
167                 goto err;
168         }
169
170         preloader_console_init();
171         return;
172 err:
173         printf("spl_board_init: Error %d\n", ret);
174
175         /* No way to report error here */
176         hang();
177 }
178
179 #ifdef CONFIG_SPL_LOAD_FIT
180 int board_fit_config_name_match(const char *name)
181 {
182         /* Just empty function now - can't decide what to choose */
183         debug("%s: %s\n", __func__, name);
184
185         return 0;
186 }
187 #endif