2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/bootrom.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/grf_rk3399.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/periph.h>
15 #include <debug_uart.h>
17 #include <dm/pinctrl.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 void board_return_to_bootrom(void)
29 u32 spl_boot_device(void)
31 u32 boot_device = BOOT_DEVICE_MMC1;
33 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
34 return BOOT_DEVICE_BOOTROM;
39 u32 spl_boot_mode(const u32 boot_device)
41 return MMCSD_MODE_RAW;
44 #define TIMER_CHN10_BASE 0xff8680a0
45 #define TIMER_END_COUNT_L 0x00
46 #define TIMER_END_COUNT_H 0x04
47 #define TIMER_INIT_COUNT_L 0x10
48 #define TIMER_INIT_COUNT_H 0x14
49 #define TIMER_CONTROL_REG 0x1c
52 #define TIMER_FMODE (0 << 1)
53 #define TIMER_RMODE (1 << 1)
55 void secure_timer_init(void)
57 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
58 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
59 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
60 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
61 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
64 void board_debug_uart_init(void)
66 #define GRF_BASE 0xff770000
67 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
69 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
70 /* Enable early UART0 on the RK3399 */
71 rk_clrsetreg(&grf->gpio2c_iomux,
73 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
74 rk_clrsetreg(&grf->gpio2c_iomux,
76 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
78 /* Enable early UART2 channel C on the RK3399 */
79 rk_clrsetreg(&grf->gpio4c_iomux,
81 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
82 rk_clrsetreg(&grf->gpio4c_iomux,
84 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
85 /* Set channel C as UART2 input */
86 rk_clrsetreg(&grf->soc_con7,
87 GRF_UART_DBG_SEL_MASK,
88 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
92 void board_init_f(ulong dummy)
94 struct udevice *pinctrl;
96 struct rk3399_pmusgrf_regs *sgrf;
97 struct rk3399_grf_regs *grf;
103 * Debug UART can be used from here if required:
108 * printascii("string");
111 printascii("U-Boot SPL board init");
114 ret = spl_early_init();
116 debug("spl_early_init() failed: %d\n", ret);
121 * Disable DDR and SRAM security regions.
123 * As we are entered from the BootROM, the region from
124 * 0x0 through 0xfffff (i.e. the first MB of memory) will
125 * be protected. This will cause issues with the DW_MMC
126 * driver, which tries to DMA from/to the stack (likely)
127 * located in this range.
129 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
130 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
131 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
133 /* eMMC clock generator: disable the clock multipilier */
134 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
135 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
139 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
141 debug("Pinctrl init failed: %d\n", ret);
145 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
147 debug("DRAM init failed: %d\n", ret);
152 void spl_board_init(void)
154 struct udevice *pinctrl;
157 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
159 debug("%s: Cannot find pinctrl device\n", __func__);
163 /* Enable debug UART */
164 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
166 debug("%s: Failed to set up console UART\n", __func__);
170 preloader_console_init();
173 printf("spl_board_init: Error %d\n", ret);
175 /* No way to report error here */
179 #ifdef CONFIG_SPL_LOAD_FIT
180 int board_fit_config_name_match(const char *name)
182 /* Just empty function now - can't decide what to choose */
183 debug("%s: %s\n", __func__, name);