arch/arm/mach-rockchip/rk3399-board-spl.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <debug_uart.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <ram.h>
  12 #include <spl.h>
  13 #include <asm/gpio.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/periph.h>
  18 #include <asm/arch/sdram.h>
  19 #include <asm/arch/timer.h>
  20 #include <dm/pinctrl.h>
  21 #include <power/regulator.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 u32 spl_boot_device(void)
  26 {
  27         return BOOT_DEVICE_MMC1;
  28 }
  29
  30 u32 spl_boot_mode(const u32 boot_device)
  31 {
  32         return MMCSD_MODE_RAW;
  33 }
  34
  35 #define TIMER_CHN10_BASE        0xff8680a0
  36 #define TIMER_END_COUNT_L       0x00
  37 #define TIMER_END_COUNT_H       0x04
  38 #define TIMER_INIT_COUNT_L      0x10
  39 #define TIMER_INIT_COUNT_H      0x14
  40 #define TIMER_CONTROL_REG       0x1c
  41
  42 #define TIMER_EN        0x1
  43 #define TIMER_FMODE     (0 << 1)
  44 #define TIMER_RMODE     (1 << 1)
  45
  46 void secure_timer_init(void)
  47 {
  48         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
  49         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
  50         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
  51         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
  52         writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
  53 }
  54
  55 void board_debug_uart_init(void)
  56 {
  57 #include <asm/arch/grf_rk3399.h>
  58 #define GRF_BASE        0xff770000
  59         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  60
  61 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  62         /* Enable early UART0 on the RK3399 */
  63         rk_clrsetreg(&grf->gpio2c_iomux,
  64                      GRF_GPIO2C0_SEL_MASK,
  65                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  66         rk_clrsetreg(&grf->gpio2c_iomux,
  67                      GRF_GPIO2C1_SEL_MASK,
  68                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  69 #else
  70         /* Enable early UART2 channel C on the RK3399 */
  71         rk_clrsetreg(&grf->gpio4c_iomux,
  72                      GRF_GPIO4C3_SEL_MASK,
  73                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
  74         rk_clrsetreg(&grf->gpio4c_iomux,
  75                      GRF_GPIO4C4_SEL_MASK,
  76                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
  77         /* Set channel C as UART2 input */
  78         rk_clrsetreg(&grf->soc_con7,
  79                      GRF_UART_DBG_SEL_MASK,
  80                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
  81 #endif
  82 }
  83
  84 #define GRF_EMMCCORE_CON11 0xff77f02c
  85 #define SGRF_DDR_RGN_CON16 0xff330040
  86 #define SGRF_SLV_SECURE_CON4 0xff33e3d0
  87 void board_init_f(ulong dummy)
  88 {
  89         struct udevice *pinctrl;
  90         struct udevice *dev;
  91         int ret;
  92
  93 #define EARLY_UART
  94 #ifdef EARLY_UART
  95         /*
  96          * Debug UART can be used from here if required:
  97          *
  98          * debug_uart_init();
  99          * printch('a');
 100          * printhex8(0x1234);
 101          * printascii("string");
 102          */
 103         debug_uart_init();
 104         printascii("U-Boot SPL board init");
 105 #endif
 106
 107         /*  Emmc clock generator: disable the clock multipilier */
 108         rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
 109
 110         ret = spl_early_init();
 111         if (ret) {
 112                 debug("spl_early_init() failed: %d\n", ret);
 113                 hang();
 114         }
 115
 116         /*
 117          * Disable DDR and SRAM security regions.
 118          *
 119          * As we are entered from the BootROM, the region from
 120          * 0x0 through 0xfffff (i.e. the first MB of memory) will
 121          * be protected. This will cause issues with the DW_MMC
 122          * driver, which tries to DMA from/to the stack (likely)
 123          * located in this range.
 124          */
 125         rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
 126         rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000);
 127
 128         secure_timer_init();
 129
 130         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
 131         if (ret) {
 132                 debug("Pinctrl init failed: %d\n", ret);
 133                 return;
 134         }
 135
 136         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 137         if (ret) {
 138                 debug("DRAM init failed: %d\n", ret);
 139                 return;
 140         }
 141 }
 142
 143 void spl_board_init(void)
 144 {
 145         struct udevice *pinctrl;
 146         int ret;
 147
 148         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
 149         if (ret) {
 150                 debug("%s: Cannot find pinctrl device\n", __func__);
 151                 goto err;
 152         }
 153
 154         /* Enable debug UART */
 155         ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
 156         if (ret) {
 157                 debug("%s: Failed to set up console UART\n", __func__);
 158                 goto err;
 159         }
 160
 161         preloader_console_init();
 162 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 163         back_to_bootrom();
 164 #endif
 165
 166         return;
 167 err:
 168         printf("spl_board_init: Error %d\n", ret);
 169
 170         /* No way to report error here */
 171         hang();
 172 }
 173
 174 #ifdef CONFIG_SPL_LOAD_FIT
 175 int board_fit_config_name_match(const char *name)
 176 {
 177         /* Just empty function now - can't decide what to choose */
 178         debug("%s: %s\n", __func__, name);
 179
 180         return 0;
 181 }
 182 #endif