2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <debug_uart.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/periph.h>
17 #include <asm/arch/sdram.h>
18 #include <asm/arch/timer.h>
19 #include <dm/pinctrl.h>
20 #include <power/regulator.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 u32 spl_boot_device(void)
26 return BOOT_DEVICE_MMC1;
29 u32 spl_boot_mode(const u32 boot_device)
31 return MMCSD_MODE_RAW;
34 #define TIMER_CHN10_BASE 0xff8680a0
35 #define TIMER_END_COUNT_L 0x00
36 #define TIMER_END_COUNT_H 0x04
37 #define TIMER_INIT_COUNT_L 0x10
38 #define TIMER_INIT_COUNT_H 0x14
39 #define TIMER_CONTROL_REG 0x1c
42 #define TIMER_FMODE (0 << 1)
43 #define TIMER_RMODE (1 << 1)
45 void secure_timer_init(void)
47 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
48 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
49 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
50 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
51 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
54 void board_debug_uart_init(void)
56 #include <asm/arch/grf_rk3399.h>
57 #define GRF_BASE 0xff770000
58 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
60 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
61 /* Enable early UART0 on the RK3399 */
62 rk_clrsetreg(&grf->gpio2c_iomux,
64 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
65 rk_clrsetreg(&grf->gpio2c_iomux,
67 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
69 /* Enable early UART2 channel C on the RK3399 */
70 rk_clrsetreg(&grf->gpio4c_iomux,
72 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
73 rk_clrsetreg(&grf->gpio4c_iomux,
75 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
76 /* Set channel C as UART2 input */
77 rk_clrsetreg(&grf->soc_con7,
78 GRF_UART_DBG_SEL_MASK,
79 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
83 #define GRF_EMMCCORE_CON11 0xff77f02c
84 #define SGRF_DDR_RGN_CON16 0xff330040
85 #define SGRF_SLV_SECURE_CON4 0xff33e3d0
86 void board_init_f(ulong dummy)
88 struct udevice *pinctrl;
95 * Debug UART can be used from here if required:
100 * printascii("string");
103 printascii("U-Boot SPL board init");
106 /* Emmc clock generator: disable the clock multipilier */
107 rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
109 ret = spl_early_init();
111 debug("spl_early_init() failed: %d\n", ret);
116 * Disable DDR and SRAM security regions.
118 * As we are entered from the BootROM, the region from
119 * 0x0 through 0xfffff (i.e. the first MB of memory) will
120 * be protected. This will cause issues with the DW_MMC
121 * driver, which tries to DMA from/to the stack (likely)
122 * located in this range.
124 rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
125 rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000);
129 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
131 debug("Pinctrl init failed: %d\n", ret);
135 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
137 debug("DRAM init failed: %d\n", ret);
142 void spl_board_init(void)
144 struct udevice *pinctrl;
147 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
149 debug("%s: Cannot find pinctrl device\n", __func__);
153 /* Enable debug UART */
154 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
156 debug("%s: Failed to set up console UART\n", __func__);
160 preloader_console_init();
161 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
167 printf("spl_board_init: Error %d\n", ret);
169 /* No way to report error here */
173 #ifdef CONFIG_SPL_LOAD_FIT
174 int board_fit_config_name_match(const char *name)
176 /* Just empty function now - can't decide what to choose */
177 debug("%s: %s\n", __func__, name);