arch/arm/mach-rockchip/rk3399-board-spl.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/grf_rk3399.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/periph.h>
  12 #include <asm/io.h>
  13 #include <debug_uart.h>
  14 #include <dm.h>
  15 #include <dm/pinctrl.h>
  16 #include <ram.h>
  17 #include <spl.h>
  18 #include <syscon.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 u32 spl_boot_device(void)
  23 {
  24         return BOOT_DEVICE_MMC1;
  25 }
  26
  27 u32 spl_boot_mode(const u32 boot_device)
  28 {
  29         return MMCSD_MODE_RAW;
  30 }
  31
  32 #define TIMER_CHN10_BASE        0xff8680a0
  33 #define TIMER_END_COUNT_L       0x00
  34 #define TIMER_END_COUNT_H       0x04
  35 #define TIMER_INIT_COUNT_L      0x10
  36 #define TIMER_INIT_COUNT_H      0x14
  37 #define TIMER_CONTROL_REG       0x1c
  38
  39 #define TIMER_EN        0x1
  40 #define TIMER_FMODE     (0 << 1)
  41 #define TIMER_RMODE     (1 << 1)
  42
  43 void secure_timer_init(void)
  44 {
  45         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
  46         writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
  47         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
  48         writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
  49         writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
  50 }
  51
  52 void board_debug_uart_init(void)
  53 {
  54 #define GRF_BASE        0xff770000
  55         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  56
  57 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  58         /* Enable early UART0 on the RK3399 */
  59         rk_clrsetreg(&grf->gpio2c_iomux,
  60                      GRF_GPIO2C0_SEL_MASK,
  61                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  62         rk_clrsetreg(&grf->gpio2c_iomux,
  63                      GRF_GPIO2C1_SEL_MASK,
  64                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  65 #else
  66         /* Enable early UART2 channel C on the RK3399 */
  67         rk_clrsetreg(&grf->gpio4c_iomux,
  68                      GRF_GPIO4C3_SEL_MASK,
  69                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
  70         rk_clrsetreg(&grf->gpio4c_iomux,
  71                      GRF_GPIO4C4_SEL_MASK,
  72                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
  73         /* Set channel C as UART2 input */
  74         rk_clrsetreg(&grf->soc_con7,
  75                      GRF_UART_DBG_SEL_MASK,
  76                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
  77 #endif
  78 }
  79
  80 void board_init_f(ulong dummy)
  81 {
  82         struct udevice *pinctrl;
  83         struct udevice *dev;
  84         struct rk3399_pmusgrf_regs *sgrf;
  85         struct rk3399_grf_regs *grf;
  86         int ret;
  87
  88 #define EARLY_UART
  89 #ifdef EARLY_UART
  90         /*
  91          * Debug UART can be used from here if required:
  92          *
  93          * debug_uart_init();
  94          * printch('a');
  95          * printhex8(0x1234);
  96          * printascii("string");
  97          */
  98         debug_uart_init();
  99         printascii("U-Boot SPL board init");
 100 #endif
 101
 102         ret = spl_early_init();
 103         if (ret) {
 104                 debug("spl_early_init() failed: %d\n", ret);
 105                 hang();
 106         }
 107
 108         /*
 109          * Disable DDR and SRAM security regions.
 110          *
 111          * As we are entered from the BootROM, the region from
 112          * 0x0 through 0xfffff (i.e. the first MB of memory) will
 113          * be protected. This will cause issues with the DW_MMC
 114          * driver, which tries to DMA from/to the stack (likely)
 115          * located in this range.
 116          */
 117         sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
 118         rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
 119         rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
 120
 121         /*  eMMC clock generator: disable the clock multipilier */
 122         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 123         rk_clrreg(&grf->emmccore_con[11], 0x0ff);
 124
 125         secure_timer_init();
 126
 127         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
 128         if (ret) {
 129                 debug("Pinctrl init failed: %d\n", ret);
 130                 return;
 131         }
 132
 133         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 134         if (ret) {
 135                 debug("DRAM init failed: %d\n", ret);
 136                 return;
 137         }
 138 }
 139
 140 void spl_board_init(void)
 141 {
 142         struct udevice *pinctrl;
 143         int ret;
 144
 145         ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
 146         if (ret) {
 147                 debug("%s: Cannot find pinctrl device\n", __func__);
 148                 goto err;
 149         }
 150
 151         /* Enable debug UART */
 152         ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
 153         if (ret) {
 154                 debug("%s: Failed to set up console UART\n", __func__);
 155                 goto err;
 156         }
 157
 158         preloader_console_init();
 159 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 160         back_to_bootrom();
 161 #endif
 162
 163         return;
 164 err:
 165         printf("spl_board_init: Error %d\n", ret);
 166
 167         /* No way to report error here */
 168         hang();
 169 }
 170
 171 #ifdef CONFIG_SPL_LOAD_FIT
 172 int board_fit_config_name_match(const char *name)
 173 {
 174         /* Just empty function now - can't decide what to choose */
 175         debug("%s: %s\n", __func__, name);
 176
 177         return 0;
 178 }
 179 #endif