2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
9 #include <asm/arch/grf_rk3399.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/periph.h>
13 #include <debug_uart.h>
15 #include <dm/pinctrl.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 u32 spl_boot_device(void)
24 return BOOT_DEVICE_MMC1;
27 u32 spl_boot_mode(const u32 boot_device)
29 return MMCSD_MODE_RAW;
32 #define TIMER_CHN10_BASE 0xff8680a0
33 #define TIMER_END_COUNT_L 0x00
34 #define TIMER_END_COUNT_H 0x04
35 #define TIMER_INIT_COUNT_L 0x10
36 #define TIMER_INIT_COUNT_H 0x14
37 #define TIMER_CONTROL_REG 0x1c
40 #define TIMER_FMODE (0 << 1)
41 #define TIMER_RMODE (1 << 1)
43 void secure_timer_init(void)
45 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
46 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
47 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
48 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
49 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
52 void board_debug_uart_init(void)
54 #define GRF_BASE 0xff770000
55 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
57 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
58 /* Enable early UART0 on the RK3399 */
59 rk_clrsetreg(&grf->gpio2c_iomux,
61 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
62 rk_clrsetreg(&grf->gpio2c_iomux,
64 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
66 /* Enable early UART2 channel C on the RK3399 */
67 rk_clrsetreg(&grf->gpio4c_iomux,
69 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
70 rk_clrsetreg(&grf->gpio4c_iomux,
72 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
73 /* Set channel C as UART2 input */
74 rk_clrsetreg(&grf->soc_con7,
75 GRF_UART_DBG_SEL_MASK,
76 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
80 void board_init_f(ulong dummy)
82 struct udevice *pinctrl;
84 struct rk3399_pmusgrf_regs *sgrf;
85 struct rk3399_grf_regs *grf;
91 * Debug UART can be used from here if required:
96 * printascii("string");
99 printascii("U-Boot SPL board init");
102 ret = spl_early_init();
104 debug("spl_early_init() failed: %d\n", ret);
109 * Disable DDR and SRAM security regions.
111 * As we are entered from the BootROM, the region from
112 * 0x0 through 0xfffff (i.e. the first MB of memory) will
113 * be protected. This will cause issues with the DW_MMC
114 * driver, which tries to DMA from/to the stack (likely)
115 * located in this range.
117 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
118 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
119 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
121 /* eMMC clock generator: disable the clock multipilier */
122 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
123 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
127 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
129 debug("Pinctrl init failed: %d\n", ret);
133 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
135 debug("DRAM init failed: %d\n", ret);
140 void spl_board_init(void)
142 struct udevice *pinctrl;
145 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
147 debug("%s: Cannot find pinctrl device\n", __func__);
151 /* Enable debug UART */
152 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
154 debug("%s: Failed to set up console UART\n", __func__);
158 preloader_console_init();
159 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
165 printf("spl_board_init: Error %d\n", ret);
167 /* No way to report error here */
171 #ifdef CONFIG_SPL_LOAD_FIT
172 int board_fit_config_name_match(const char *name)
174 /* Just empty function now - can't decide what to choose */
175 debug("%s: %s\n", __func__, name);