arch/arm/mach-rockchip/rk3399/sdram_rk3399.c

   1 /*
   2  * (C) Copyright 2016-2017 Rockchip Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  *
   6  * Adapted from coreboot.
   7  */
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <dt-structs.h>
  13 #include <ram.h>
  14 #include <regmap.h>
  15 #include <syscon.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sdram_rk3399.h>
  19 #include <asm/arch/cru_rk3399.h>
  20 #include <asm/arch/grf_rk3399.h>
  21 #include <asm/arch/hardware.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26 struct chan_info {
  27         struct rk3399_ddr_pctl_regs *pctl;
  28         struct rk3399_ddr_pi_regs *pi;
  29         struct rk3399_ddr_publ_regs *publ;
  30         struct rk3399_msch_regs *msch;
  31 };
  32
  33 struct dram_info {
  34 #ifdef CONFIG_SPL_BUILD
  35         struct chan_info chan[2];
  36         struct clk ddr_clk;
  37         struct rk3399_cru *cru;
  38         struct rk3399_pmucru *pmucru;
  39         struct rk3399_pmusgrf_regs *pmusgrf;
  40         struct rk3399_ddr_cic_regs *cic;
  41 #endif
  42         struct ram_info info;
  43         struct rk3399_pmugrf_regs *pmugrf;
  44 };
  45
  46 /*
  47  * sys_reg bitfield struct
  48  * [31]         row_3_4_ch1
  49  * [30]         row_3_4_ch0
  50  * [29:28]      chinfo
  51  * [27]         rank_ch1
  52  * [26:25]      col_ch1
  53  * [24]         bk_ch1
  54  * [23:22]      cs0_row_ch1
  55  * [21:20]      cs1_row_ch1
  56  * [19:18]      bw_ch1
  57  * [17:16]      dbw_ch1;
  58  * [15:13]      ddrtype
  59  * [12]         channelnum
  60  * [11]         rank_ch0
  61  * [10:9]       col_ch0
  62  * [8]          bk_ch0
  63  * [7:6]        cs0_row_ch0
  64  * [5:4]        cs1_row_ch0
  65  * [3:2]        bw_ch0
  66  * [1:0]        dbw_ch0
  67 */
  68 #define SYS_REG_DDRTYPE_SHIFT           13
  69 #define SYS_REG_DDRTYPE_MASK            7
  70 #define SYS_REG_NUM_CH_SHIFT            12
  71 #define SYS_REG_NUM_CH_MASK             1
  72 #define SYS_REG_ROW_3_4_SHIFT(ch)       (30 + (ch))
  73 #define SYS_REG_ROW_3_4_MASK            1
  74 #define SYS_REG_CHINFO_SHIFT(ch)        (28 + (ch))
  75 #define SYS_REG_RANK_SHIFT(ch)          (11 + (ch) * 16)
  76 #define SYS_REG_RANK_MASK               1
  77 #define SYS_REG_COL_SHIFT(ch)           (9 + (ch) * 16)
  78 #define SYS_REG_COL_MASK                3
  79 #define SYS_REG_BK_SHIFT(ch)            (8 + (ch) * 16)
  80 #define SYS_REG_BK_MASK                 1
  81 #define SYS_REG_CS0_ROW_SHIFT(ch)       (6 + (ch) * 16)
  82 #define SYS_REG_CS0_ROW_MASK            3
  83 #define SYS_REG_CS1_ROW_SHIFT(ch)       (4 + (ch) * 16)
  84 #define SYS_REG_CS1_ROW_MASK            3
  85 #define SYS_REG_BW_SHIFT(ch)            (2 + (ch) * 16)
  86 #define SYS_REG_BW_MASK                 3
  87 #define SYS_REG_DBW_SHIFT(ch)           ((ch) * 16)
  88 #define SYS_REG_DBW_MASK                3
  89
  90 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  91 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  92 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  93
  94 #define PHY_DRV_ODT_Hi_Z        0x0
  95 #define PHY_DRV_ODT_240         0x1
  96 #define PHY_DRV_ODT_120         0x8
  97 #define PHY_DRV_ODT_80          0x9
  98 #define PHY_DRV_ODT_60          0xc
  99 #define PHY_DRV_ODT_48          0xd
 100 #define PHY_DRV_ODT_40          0xe
 101 #define PHY_DRV_ODT_34_3        0xf
 102
 103 #ifdef CONFIG_SPL_BUILD
 104
 105 struct rockchip_dmc_plat {
 106 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 107         struct dtd_rockchip_rk3399_dmc dtplat;
 108 #else
 109         struct rk3399_sdram_params sdram_params;
 110 #endif
 111         struct regmap *map;
 112 };
 113
 114 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 115 {
 116         int i;
 117
 118         for (i = 0; i < n / sizeof(u32); i++) {
 119                 writel(*src, dest);
 120                 src++;
 121                 dest++;
 122         }
 123 }
 124
 125 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
 126                                u32 freq)
 127 {
 128         u32 *denali_phy = ddr_publ_regs->denali_phy;
 129
 130         /* From IP spec, only freq small than 125 can enter dll bypass mode */
 131         if (freq <= 125) {
 132                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 133                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 134                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 135                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 136                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 137
 138                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 139                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 140                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 141                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 142         } else {
 143                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 144                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 145                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 146                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 147                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 148
 149                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 150                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 151                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 152                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 153         }
 154 }
 155
 156 static void set_memory_map(const struct chan_info *chan, u32 channel,
 157                            const struct rk3399_sdram_params *sdram_params)
 158 {
 159         const struct rk3399_sdram_channel *sdram_ch =
 160                 &sdram_params->ch[channel];
 161         u32 *denali_ctl = chan->pctl->denali_ctl;
 162         u32 *denali_pi = chan->pi->denali_pi;
 163         u32 cs_map;
 164         u32 reduc;
 165         u32 row;
 166
 167         /* Get row number from ddrconfig setting */
 168         if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
 169                 row = 16;
 170         else if (sdram_ch->ddrconfig == 3)
 171                 row = 14;
 172         else
 173                 row = 15;
 174
 175         cs_map = (sdram_ch->rank > 1) ? 3 : 1;
 176         reduc = (sdram_ch->bw == 2) ? 0 : 1;
 177
 178         /* Set the dram configuration to ctrl */
 179         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
 180         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 181                         ((3 - sdram_ch->bk) << 16) |
 182                         ((16 - row) << 24));
 183
 184         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 185                         cs_map | (reduc << 16));
 186
 187         /* PI_199 PI_COL_DIFF:RW:0:4 */
 188         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
 189
 190         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 191         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 192                         ((3 - sdram_ch->bk) << 16) |
 193                         ((16 - row) << 24));
 194         /* PI_41 PI_CS_MAP:RW:24:4 */
 195         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 196         if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))
 197                 writel(0x2EC7FFFF, &denali_pi[34]);
 198 }
 199
 200 static void set_ds_odt(const struct chan_info *chan,
 201                        const struct rk3399_sdram_params *sdram_params)
 202 {
 203         u32 *denali_phy = chan->publ->denali_phy;
 204
 205         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 206         u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
 207         u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
 208         u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
 209         u32 reg_value;
 210
 211         if (sdram_params->base.dramtype == LPDDR4) {
 212                 tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
 213                 tsel_wr_select_p = PHY_DRV_ODT_40;
 214                 ca_tsel_wr_select_p = PHY_DRV_ODT_40;
 215                 tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
 216
 217                 tsel_rd_select_n = PHY_DRV_ODT_240;
 218                 tsel_wr_select_n = PHY_DRV_ODT_40;
 219                 ca_tsel_wr_select_n = PHY_DRV_ODT_40;
 220                 tsel_idle_select_n = PHY_DRV_ODT_240;
 221         } else if (sdram_params->base.dramtype == LPDDR3) {
 222                 tsel_rd_select_p = PHY_DRV_ODT_240;
 223                 tsel_wr_select_p = PHY_DRV_ODT_34_3;
 224                 ca_tsel_wr_select_p = PHY_DRV_ODT_48;
 225                 tsel_idle_select_p = PHY_DRV_ODT_240;
 226
 227                 tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
 228                 tsel_wr_select_n = PHY_DRV_ODT_34_3;
 229                 ca_tsel_wr_select_n = PHY_DRV_ODT_48;
 230                 tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
 231         } else {
 232                 tsel_rd_select_p = PHY_DRV_ODT_240;
 233                 tsel_wr_select_p = PHY_DRV_ODT_34_3;
 234                 ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
 235                 tsel_idle_select_p = PHY_DRV_ODT_240;
 236
 237                 tsel_rd_select_n = PHY_DRV_ODT_240;
 238                 tsel_wr_select_n = PHY_DRV_ODT_34_3;
 239                 ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
 240                 tsel_idle_select_n = PHY_DRV_ODT_240;
 241         }
 242
 243         if (sdram_params->base.odt == 1)
 244                 tsel_rd_en = 1;
 245         else
 246                 tsel_rd_en = 0;
 247
 248         tsel_wr_en = 0;
 249         tsel_idle_en = 0;
 250
 251         /*
 252          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 253          * sets termination values for read/idle cycles and drive strength
 254          * for write cycles for DQ/DM
 255          */
 256         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 257                     (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
 258                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 259         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 260         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 261         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 262         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 263
 264         /*
 265          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 266          * sets termination values for read/idle cycles and drive strength
 267          * for write cycles for DQS
 268          */
 269         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 270         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 271         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 272         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 273
 274         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 275         reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
 276         clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 277         clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 278         clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 279
 280         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 281         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 282
 283         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 284         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 285
 286         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 287         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 288
 289         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 290         clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
 291
 292         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 293         clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
 294
 295         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 296         clrsetbits_le32(&denali_phy[924], 0xff,
 297                         tsel_wr_select_n | (tsel_wr_select_p << 4));
 298         clrsetbits_le32(&denali_phy[925], 0xff,
 299                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 300
 301         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 302         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 303                 << 16;
 304         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 305         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 306         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 307         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 308
 309         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 310         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 311                 << 24;
 312         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 313         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 314         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 315         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 316
 317         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 318         reg_value = tsel_wr_en << 8;
 319         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 320         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 321         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 322
 323         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 324         reg_value = tsel_wr_en << 17;
 325         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 326         /*
 327          * pad_rst/cke/cs/clk_term tsel 1bits
 328          * DENALI_PHY_938/936/940/934 offset_17
 329          */
 330         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 331         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 332         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 333         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 334
 335         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 336         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 337 }
 338
 339 static int phy_io_config(const struct chan_info *chan,
 340                           const struct rk3399_sdram_params *sdram_params)
 341 {
 342         u32 *denali_phy = chan->publ->denali_phy;
 343         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 344         u32 mode_sel;
 345         u32 reg_value;
 346         u32 drv_value, odt_value;
 347         u32 speed;
 348
 349         /* vref setting */
 350         if (sdram_params->base.dramtype == LPDDR4) {
 351                 /* LPDDR4 */
 352                 vref_mode_dq = 0x6;
 353                 vref_value_dq = 0x1f;
 354                 vref_mode_ac = 0x6;
 355                 vref_value_ac = 0x1f;
 356         } else if (sdram_params->base.dramtype == LPDDR3) {
 357                 if (sdram_params->base.odt == 1) {
 358                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 359                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 360                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 361                         if (drv_value == PHY_DRV_ODT_48) {
 362                                 switch (odt_value) {
 363                                 case PHY_DRV_ODT_240:
 364                                         vref_value_dq = 0x16;
 365                                         break;
 366                                 case PHY_DRV_ODT_120:
 367                                         vref_value_dq = 0x26;
 368                                         break;
 369                                 case PHY_DRV_ODT_60:
 370                                         vref_value_dq = 0x36;
 371                                         break;
 372                                 default:
 373                                         debug("Invalid ODT value.\n");
 374                                         return -EINVAL;
 375                                 }
 376                         } else if (drv_value == PHY_DRV_ODT_40) {
 377                                 switch (odt_value) {
 378                                 case PHY_DRV_ODT_240:
 379                                         vref_value_dq = 0x19;
 380                                         break;
 381                                 case PHY_DRV_ODT_120:
 382                                         vref_value_dq = 0x23;
 383                                         break;
 384                                 case PHY_DRV_ODT_60:
 385                                         vref_value_dq = 0x31;
 386                                         break;
 387                                 default:
 388                                         debug("Invalid ODT value.\n");
 389                                         return -EINVAL;
 390                                 }
 391                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 392                                 switch (odt_value) {
 393                                 case PHY_DRV_ODT_240:
 394                                         vref_value_dq = 0x17;
 395                                         break;
 396                                 case PHY_DRV_ODT_120:
 397                                         vref_value_dq = 0x20;
 398                                         break;
 399                                 case PHY_DRV_ODT_60:
 400                                         vref_value_dq = 0x2e;
 401                                         break;
 402                                 default:
 403                                         debug("Invalid ODT value.\n");
 404                                         return -EINVAL;
 405                                 }
 406                         } else {
 407                                 debug("Invalid DRV value.\n");
 408                                 return -EINVAL;
 409                         }
 410                 } else {
 411                         vref_mode_dq = 0x2;  /* LPDDR3 */
 412                         vref_value_dq = 0x1f;
 413                 }
 414                 vref_mode_ac = 0x2;
 415                 vref_value_ac = 0x1f;
 416         } else if (sdram_params->base.dramtype == DDR3) {
 417                 /* DDR3L */
 418                 vref_mode_dq = 0x1;
 419                 vref_value_dq = 0x1f;
 420                 vref_mode_ac = 0x1;
 421                 vref_value_ac = 0x1f;
 422         } else {
 423                 debug("Unknown DRAM type.\n");
 424                 return -EINVAL;
 425         }
 426
 427         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 428
 429         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 430         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 431         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 432         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 433         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 434         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 435         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 436         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 437
 438         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 439
 440         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 441         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 442
 443         if (sdram_params->base.dramtype == LPDDR4)
 444                 mode_sel = 0x6;
 445         else if (sdram_params->base.dramtype == LPDDR3)
 446                 mode_sel = 0x0;
 447         else if (sdram_params->base.dramtype == DDR3)
 448                 mode_sel = 0x1;
 449         else
 450                 return -EINVAL;
 451
 452         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 453         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 454         /* PHY_926 PHY_PAD_DATA_DRIVE */
 455         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 456         /* PHY_927 PHY_PAD_DQS_DRIVE */
 457         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 458         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 459         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 460         /* PHY_929 PHY_PAD_CLK_DRIVE */
 461         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 462         /* PHY_935 PHY_PAD_CKE_DRIVE */
 463         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 464         /* PHY_937 PHY_PAD_RST_DRIVE */
 465         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 466         /* PHY_939 PHY_PAD_CS_DRIVE */
 467         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 468
 469
 470         /* speed setting */
 471         if (sdram_params->base.ddr_freq < 400)
 472                 speed = 0x0;
 473         else if (sdram_params->base.ddr_freq < 800)
 474                 speed = 0x1;
 475         else if (sdram_params->base.ddr_freq < 1200)
 476                 speed = 0x2;
 477         else
 478                 speed = 0x3;
 479
 480         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 481         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 482         /* PHY_926 PHY_PAD_DATA_DRIVE */
 483         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 484         /* PHY_927 PHY_PAD_DQS_DRIVE */
 485         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 486         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 487         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 488         /* PHY_929 PHY_PAD_CLK_DRIVE */
 489         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 490         /* PHY_935 PHY_PAD_CKE_DRIVE */
 491         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 492         /* PHY_937 PHY_PAD_RST_DRIVE */
 493         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 494         /* PHY_939 PHY_PAD_CS_DRIVE */
 495         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 496
 497         return 0;
 498 }
 499
 500 static int pctl_cfg(const struct chan_info *chan, u32 channel,
 501                     const struct rk3399_sdram_params *sdram_params)
 502 {
 503         u32 *denali_ctl = chan->pctl->denali_ctl;
 504         u32 *denali_pi = chan->pi->denali_pi;
 505         u32 *denali_phy = chan->publ->denali_phy;
 506         const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
 507         const u32 *params_phy = sdram_params->phy_regs.denali_phy;
 508         u32 tmp, tmp1, tmp2;
 509         u32 pwrup_srefresh_exit;
 510         int ret;
 511         const ulong timeout_ms = 200;
 512
 513         /*
 514          * work around controller bug:
 515          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 516          */
 517         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 518                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 519         writel(params_ctl[0], &denali_ctl[0]);
 520         copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
 521                     sizeof(struct rk3399_ddr_pi_regs));
 522         /* rank count need to set for init */
 523         set_memory_map(chan, channel, sdram_params);
 524
 525         writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]);
 526         writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
 527         writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
 528
 529         pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
 530         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 531
 532         /* PHY_DLL_RST_EN */
 533         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 534
 535         setbits_le32(&denali_pi[0], START);
 536         setbits_le32(&denali_ctl[0], START);
 537
 538         /* Wating for phy DLL lock */
 539         while (1) {
 540                 tmp = readl(&denali_phy[920]);
 541                 tmp1 = readl(&denali_phy[921]);
 542                 tmp2 = readl(&denali_phy[922]);
 543                 if ((((tmp >> 16) & 0x1) == 0x1) &&
 544                     (((tmp1 >> 16) & 0x1) == 0x1) &&
 545                     (((tmp1 >> 0) & 0x1) == 0x1) &&
 546                     (((tmp2 >> 0) & 0x1) == 0x1))
 547                         break;
 548         }
 549
 550         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 551         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 552         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 553         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 554         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 555         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 556         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 557         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 558         set_ds_odt(chan, sdram_params);
 559
 560         /*
 561          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 562          * dqs_tsel_wr_end[7:4] add Half cycle
 563          */
 564         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 565         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 566         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 567         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 568         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 569         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 570         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 571         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 572
 573         /*
 574          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 575          * dq_tsel_wr_end[7:4] add Half cycle
 576          */
 577         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 578         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 579         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 580         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 581         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 582         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 583         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 584         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 585
 586         ret = phy_io_config(chan, sdram_params);
 587         if (ret)
 588                 return ret;
 589
 590         /* PHY_DLL_RST_EN */
 591         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 592
 593         /* Wating for PHY and DRAM init complete */
 594         tmp = get_timer(0);
 595         do {
 596                 if (get_timer(tmp) > timeout_ms) {
 597                         error("DRAM (%s): phy failed to lock within  %ld ms\n",
 598                               __func__, timeout_ms);
 599                         return -ETIME;
 600                 }
 601         } while (!(readl(&denali_ctl[203]) & (1 << 3)));
 602         debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
 603
 604         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 605                         pwrup_srefresh_exit);
 606         return 0;
 607 }
 608
 609 static void select_per_cs_training_index(const struct chan_info *chan,
 610                                          u32 rank)
 611 {
 612         u32 *denali_phy = chan->publ->denali_phy;
 613
 614         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 615         if ((readl(&denali_phy[84])>>16) & 1) {
 616                 /*
 617                  * PHY_8/136/264/392
 618                  * phy_per_cs_training_index_X 1bit offset_24
 619                  */
 620                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 621                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 622                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 623                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 624         }
 625 }
 626
 627 static void override_write_leveling_value(const struct chan_info *chan)
 628 {
 629         u32 *denali_ctl = chan->pctl->denali_ctl;
 630         u32 *denali_phy = chan->publ->denali_phy;
 631         u32 byte;
 632
 633         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 634         setbits_le32(&denali_phy[896], 1);
 635
 636         /*
 637          * PHY_8/136/264/392
 638          * phy_per_cs_training_multicast_en_X 1bit offset_16
 639          */
 640         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 641         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 642         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 643         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 644
 645         for (byte = 0; byte < 4; byte++)
 646                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 647                                 0x200 << 16);
 648
 649         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 650         clrbits_le32(&denali_phy[896], 1);
 651
 652         /* CTL_200 ctrlupd_req 1bit offset_8 */
 653         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 654 }
 655
 656 static int data_training_ca(const struct chan_info *chan, u32 channel,
 657                             const struct rk3399_sdram_params *sdram_params)
 658 {
 659         u32 *denali_pi = chan->pi->denali_pi;
 660         u32 *denali_phy = chan->publ->denali_phy;
 661         u32 i, tmp;
 662         u32 obs_0, obs_1, obs_2, obs_err = 0;
 663         u32 rank = sdram_params->ch[channel].rank;
 664
 665         for (i = 0; i < rank; i++) {
 666                 select_per_cs_training_index(chan, i);
 667                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 668                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 669                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 670                 clrsetbits_le32(&denali_pi[92],
 671                                 (0x1 << 16) | (0x3 << 24),
 672                                 (0x1 << 16) | (i << 24));
 673
 674                 /* Waiting for training complete */
 675                 while (1) {
 676                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 677                         tmp = readl(&denali_pi[174]) >> 8;
 678                         /*
 679                          * check status obs
 680                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 681                          */
 682                         obs_0 = readl(&denali_phy[532]);
 683                         obs_1 = readl(&denali_phy[660]);
 684                         obs_2 = readl(&denali_phy[788]);
 685                         if (((obs_0 >> 30) & 0x3) ||
 686                             ((obs_1 >> 30) & 0x3) ||
 687                             ((obs_2 >> 30) & 0x3))
 688                                 obs_err = 1;
 689                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 690                             (((tmp >> 13) & 0x1) == 0x1) &&
 691                             (((tmp >> 5) & 0x1) == 0x0) &&
 692                             (obs_err == 0))
 693                                 break;
 694                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 695                                  (obs_err == 1))
 696                                 return -EIO;
 697                 }
 698                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 699                 writel(0x00003f7c, (&denali_pi[175]));
 700         }
 701         clrbits_le32(&denali_pi[100], 0x3 << 8);
 702
 703         return 0;
 704 }
 705
 706 static int data_training_wl(const struct chan_info *chan, u32 channel,
 707                             const struct rk3399_sdram_params *sdram_params)
 708 {
 709         u32 *denali_pi = chan->pi->denali_pi;
 710         u32 *denali_phy = chan->publ->denali_phy;
 711         u32 i, tmp;
 712         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 713         u32 rank = sdram_params->ch[channel].rank;
 714
 715         for (i = 0; i < rank; i++) {
 716                 select_per_cs_training_index(chan, i);
 717                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
 718                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 719                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
 720                 clrsetbits_le32(&denali_pi[59],
 721                                 (0x1 << 8) | (0x3 << 16),
 722                                 (0x1 << 8) | (i << 16));
 723
 724                 /* Waiting for training complete */
 725                 while (1) {
 726                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 727                         tmp = readl(&denali_pi[174]) >> 8;
 728
 729                         /*
 730                          * check status obs, if error maybe can not
 731                          * get leveling done PHY_40/168/296/424
 732                          * phy_wrlvl_status_obs_X:0:13
 733                          */
 734                         obs_0 = readl(&denali_phy[40]);
 735                         obs_1 = readl(&denali_phy[168]);
 736                         obs_2 = readl(&denali_phy[296]);
 737                         obs_3 = readl(&denali_phy[424]);
 738                         if (((obs_0 >> 12) & 0x1) ||
 739                             ((obs_1 >> 12) & 0x1) ||
 740                             ((obs_2 >> 12) & 0x1) ||
 741                             ((obs_3 >> 12) & 0x1))
 742                                 obs_err = 1;
 743                         if ((((tmp >> 10) & 0x1) == 0x1) &&
 744                             (((tmp >> 13) & 0x1) == 0x1) &&
 745                             (((tmp >> 4) & 0x1) == 0x0) &&
 746                             (obs_err == 0))
 747                                 break;
 748                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
 749                                  (obs_err == 1))
 750                                 return -EIO;
 751                 }
 752                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 753                 writel(0x00003f7c, (&denali_pi[175]));
 754         }
 755
 756         override_write_leveling_value(chan);
 757         clrbits_le32(&denali_pi[60], 0x3 << 8);
 758
 759         return 0;
 760 }
 761
 762 static int data_training_rg(const struct chan_info *chan, u32 channel,
 763                             const struct rk3399_sdram_params *sdram_params)
 764 {
 765         u32 *denali_pi = chan->pi->denali_pi;
 766         u32 *denali_phy = chan->publ->denali_phy;
 767         u32 i, tmp;
 768         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 769         u32 rank = sdram_params->ch[channel].rank;
 770
 771         for (i = 0; i < rank; i++) {
 772                 select_per_cs_training_index(chan, i);
 773                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
 774                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
 775                 /*
 776                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
 777                  * PI_RDLVL_CS:RW:24:2
 778                  */
 779                 clrsetbits_le32(&denali_pi[74],
 780                                 (0x1 << 16) | (0x3 << 24),
 781                                 (0x1 << 16) | (i << 24));
 782
 783                 /* Waiting for training complete */
 784                 while (1) {
 785                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 786                         tmp = readl(&denali_pi[174]) >> 8;
 787
 788                         /*
 789                          * check status obs
 790                          * PHY_43/171/299/427
 791                          *     PHY_GTLVL_STATUS_OBS_x:16:8
 792                          */
 793                         obs_0 = readl(&denali_phy[43]);
 794                         obs_1 = readl(&denali_phy[171]);
 795                         obs_2 = readl(&denali_phy[299]);
 796                         obs_3 = readl(&denali_phy[427]);
 797                         if (((obs_0 >> (16 + 6)) & 0x3) ||
 798                             ((obs_1 >> (16 + 6)) & 0x3) ||
 799                             ((obs_2 >> (16 + 6)) & 0x3) ||
 800                             ((obs_3 >> (16 + 6)) & 0x3))
 801                                 obs_err = 1;
 802                         if ((((tmp >> 9) & 0x1) == 0x1) &&
 803                             (((tmp >> 13) & 0x1) == 0x1) &&
 804                             (((tmp >> 3) & 0x1) == 0x0) &&
 805                             (obs_err == 0))
 806                                 break;
 807                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
 808                                  (obs_err == 1))
 809                                 return -EIO;
 810                 }
 811                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 812                 writel(0x00003f7c, (&denali_pi[175]));
 813         }
 814         clrbits_le32(&denali_pi[80], 0x3 << 24);
 815
 816         return 0;
 817 }
 818
 819 static int data_training_rl(const struct chan_info *chan, u32 channel,
 820                             const struct rk3399_sdram_params *sdram_params)
 821 {
 822         u32 *denali_pi = chan->pi->denali_pi;
 823         u32 i, tmp;
 824         u32 rank = sdram_params->ch[channel].rank;
 825
 826         for (i = 0; i < rank; i++) {
 827                 select_per_cs_training_index(chan, i);
 828                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
 829                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
 830                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
 831                 clrsetbits_le32(&denali_pi[74],
 832                                 (0x1 << 8) | (0x3 << 24),
 833                                 (0x1 << 8) | (i << 24));
 834
 835                 /* Waiting for training complete */
 836                 while (1) {
 837                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 838                         tmp = readl(&denali_pi[174]) >> 8;
 839
 840                         /*
 841                          * make sure status obs not report error bit
 842                          * PHY_46/174/302/430
 843                          *     phy_rdlvl_status_obs_X:16:8
 844                          */
 845                         if ((((tmp >> 8) & 0x1) == 0x1) &&
 846                             (((tmp >> 13) & 0x1) == 0x1) &&
 847                             (((tmp >> 2) & 0x1) == 0x0))
 848                                 break;
 849                         else if (((tmp >> 2) & 0x1) == 0x1)
 850                                 return -EIO;
 851                 }
 852                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 853                 writel(0x00003f7c, (&denali_pi[175]));
 854         }
 855         clrbits_le32(&denali_pi[80], 0x3 << 16);
 856
 857         return 0;
 858 }
 859
 860 static int data_training_wdql(const struct chan_info *chan, u32 channel,
 861                               const struct rk3399_sdram_params *sdram_params)
 862 {
 863         u32 *denali_pi = chan->pi->denali_pi;
 864         u32 i, tmp;
 865         u32 rank = sdram_params->ch[channel].rank;
 866
 867         for (i = 0; i < rank; i++) {
 868                 select_per_cs_training_index(chan, i);
 869                 /*
 870                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
 871                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
 872                  */
 873                 clrbits_le32(&denali_pi[181], 0x1 << 8);
 874                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
 875                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
 876                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
 877                 clrsetbits_le32(&denali_pi[121],
 878                                 (0x1 << 8) | (0x3 << 16),
 879                                 (0x1 << 8) | (i << 16));
 880
 881                 /* Waiting for training complete */
 882                 while (1) {
 883                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 884                         tmp = readl(&denali_pi[174]) >> 8;
 885                         if ((((tmp >> 12) & 0x1) == 0x1) &&
 886                             (((tmp >> 13) & 0x1) == 0x1) &&
 887                             (((tmp >> 6) & 0x1) == 0x0))
 888                                 break;
 889                         else if (((tmp >> 6) & 0x1) == 0x1)
 890                                 return -EIO;
 891                 }
 892                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 893                 writel(0x00003f7c, (&denali_pi[175]));
 894         }
 895         clrbits_le32(&denali_pi[124], 0x3 << 16);
 896
 897         return 0;
 898 }
 899
 900 static int data_training(const struct chan_info *chan, u32 channel,
 901                          const struct rk3399_sdram_params *sdram_params,
 902                          u32 training_flag)
 903 {
 904         u32 *denali_phy = chan->publ->denali_phy;
 905
 906         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 907         setbits_le32(&denali_phy[927], (1 << 22));
 908
 909         if (training_flag == PI_FULL_TRAINING) {
 910                 if (sdram_params->base.dramtype == LPDDR4) {
 911                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 912                                         PI_READ_GATE_TRAINING |
 913                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
 914                 } else if (sdram_params->base.dramtype == LPDDR3) {
 915                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 916                                         PI_READ_GATE_TRAINING;
 917                 } else if (sdram_params->base.dramtype == DDR3) {
 918                         training_flag = PI_WRITE_LEVELING |
 919                                         PI_READ_GATE_TRAINING |
 920                                         PI_READ_LEVELING;
 921                 }
 922         }
 923
 924         /* ca training(LPDDR4,LPDDR3 support) */
 925         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
 926                 data_training_ca(chan, channel, sdram_params);
 927
 928         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
 929         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
 930                 data_training_wl(chan, channel, sdram_params);
 931
 932         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
 933         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
 934                 data_training_rg(chan, channel, sdram_params);
 935
 936         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
 937         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
 938                 data_training_rl(chan, channel, sdram_params);
 939
 940         /* wdq leveling(LPDDR4 support) */
 941         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
 942                 data_training_wdql(chan, channel, sdram_params);
 943
 944         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 945         clrbits_le32(&denali_phy[927], (1 << 22));
 946
 947         return 0;
 948 }
 949
 950 static void set_ddrconfig(const struct chan_info *chan,
 951                           const struct rk3399_sdram_params *sdram_params,
 952                           unsigned char channel, u32 ddrconfig)
 953 {
 954         /* only need to set ddrconfig */
 955         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
 956         unsigned int cs0_cap = 0;
 957         unsigned int cs1_cap = 0;
 958
 959         cs0_cap = (1 << (sdram_params->ch[channel].cs0_row
 960                         + sdram_params->ch[channel].col
 961                         + sdram_params->ch[channel].bk
 962                         + sdram_params->ch[channel].bw - 20));
 963         if (sdram_params->ch[channel].rank > 1)
 964                 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row
 965                                 - sdram_params->ch[channel].cs1_row);
 966         if (sdram_params->ch[channel].row_3_4) {
 967                 cs0_cap = cs0_cap * 3 / 4;
 968                 cs1_cap = cs1_cap * 3 / 4;
 969         }
 970
 971         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
 972         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
 973                &ddr_msch_regs->ddrsize);
 974 }
 975
 976 static void dram_all_config(struct dram_info *dram,
 977                             const struct rk3399_sdram_params *sdram_params)
 978 {
 979         u32 sys_reg = 0;
 980         unsigned int channel, idx;
 981
 982         sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
 983         sys_reg |= (sdram_params->base.num_channels - 1)
 984                     << SYS_REG_NUM_CH_SHIFT;
 985         for (channel = 0, idx = 0;
 986              (idx < sdram_params->base.num_channels) && (channel < 2);
 987              channel++) {
 988                 const struct rk3399_sdram_channel *info =
 989                         &sdram_params->ch[channel];
 990                 struct rk3399_msch_regs *ddr_msch_regs;
 991                 const struct rk3399_msch_timings *noc_timing;
 992
 993                 if (sdram_params->ch[channel].col == 0)
 994                         continue;
 995                 idx++;
 996                 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);
 997                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
 998                 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
 999                 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
1000                 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
1001                 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel);
1002                 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel);
1003                 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
1004                 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
1005
1006                 ddr_msch_regs = dram->chan[channel].msch;
1007                 noc_timing = &sdram_params->ch[channel].noc_timings;
1008                 writel(noc_timing->ddrtiminga0,
1009                        &ddr_msch_regs->ddrtiminga0);
1010                 writel(noc_timing->ddrtimingb0,
1011                        &ddr_msch_regs->ddrtimingb0);
1012                 writel(noc_timing->ddrtimingc0,
1013                        &ddr_msch_regs->ddrtimingc0);
1014                 writel(noc_timing->devtodev0,
1015                        &ddr_msch_regs->devtodev0);
1016                 writel(noc_timing->ddrmode,
1017                        &ddr_msch_regs->ddrmode);
1018
1019                 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1020                 if (sdram_params->ch[channel].rank == 1)
1021                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1022                                      1 << 17);
1023         }
1024
1025         writel(sys_reg, &dram->pmugrf->os_reg2);
1026         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1027                      sdram_params->base.stride << 10);
1028
1029         /* reboot hold register set */
1030         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1031                 PRESET_GPIO1_HOLD(1),
1032                 &dram->pmucru->pmucru_rstnhold_con[1]);
1033         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1034 }
1035
1036 static int switch_to_phy_index1(struct dram_info *dram,
1037                                  const struct rk3399_sdram_params *sdram_params)
1038 {
1039         u32 channel;
1040         u32 *denali_phy;
1041         u32 ch_count = sdram_params->base.num_channels;
1042         int ret;
1043         int i = 0;
1044
1045         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1046                              1 << 4 | 1 << 2 | 1),
1047                         &dram->cic->cic_ctrl0);
1048         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1049                 mdelay(10);
1050                 i++;
1051                 if (i > 10) {
1052                         debug("index1 frequency change overtime\n");
1053                         return -ETIME;
1054                 }
1055         }
1056
1057         i = 0;
1058         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1059         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1060                 mdelay(10);
1061                 if (i > 10) {
1062                         debug("index1 frequency done overtime\n");
1063                         return -ETIME;
1064                 }
1065         }
1066
1067         for (channel = 0; channel < ch_count; channel++) {
1068                 denali_phy = dram->chan[channel].publ->denali_phy;
1069                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1070                 ret = data_training(&dram->chan[channel], channel,
1071                                   sdram_params, PI_FULL_TRAINING);
1072                 if (ret) {
1073                         debug("index1 training failed\n");
1074                         return ret;
1075                 }
1076         }
1077
1078         return 0;
1079 }
1080
1081 static int sdram_init(struct dram_info *dram,
1082                       const struct rk3399_sdram_params *sdram_params)
1083 {
1084         unsigned char dramtype = sdram_params->base.dramtype;
1085         unsigned int ddr_freq = sdram_params->base.ddr_freq;
1086         int channel;
1087
1088         debug("Starting SDRAM initialization...\n");
1089
1090         if ((dramtype == DDR3 && ddr_freq > 933) ||
1091             (dramtype == LPDDR3 && ddr_freq > 933) ||
1092             (dramtype == LPDDR4 && ddr_freq > 800)) {
1093                 debug("SDRAM frequency is to high!");
1094                 return -E2BIG;
1095         }
1096
1097         for (channel = 0; channel < 2; channel++) {
1098                 const struct chan_info *chan = &dram->chan[channel];
1099                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1100
1101                 phy_dll_bypass_set(publ, ddr_freq);
1102
1103                 if (channel >= sdram_params->base.num_channels)
1104                         continue;
1105
1106                 if (pctl_cfg(chan, channel, sdram_params) != 0) {
1107                         printf("pctl_cfg fail, reset\n");
1108                         return -EIO;
1109                 }
1110
1111                 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1112                 if (dramtype == LPDDR3)
1113                         udelay(10);
1114
1115                 if (data_training(chan, channel,
1116                                   sdram_params, PI_FULL_TRAINING)) {
1117                         printf("SDRAM initialization failed, reset\n");
1118                         return -EIO;
1119                 }
1120
1121                 set_ddrconfig(chan, sdram_params, channel,
1122                               sdram_params->ch[channel].ddrconfig);
1123         }
1124         dram_all_config(dram, sdram_params);
1125         switch_to_phy_index1(dram, sdram_params);
1126
1127         debug("Finish SDRAM initialization...\n");
1128         return 0;
1129 }
1130
1131 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1132 {
1133 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1134         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1135         const void *blob = gd->fdt_blob;
1136         int node = dev_of_offset(dev);
1137         int ret;
1138
1139         ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
1140                         (u32 *)&plat->sdram_params,
1141                         sizeof(plat->sdram_params) / sizeof(u32));
1142         if (ret) {
1143                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1144                        __func__, ret);
1145                 return ret;
1146         }
1147         ret = regmap_init_mem(dev, &plat->map);
1148         if (ret)
1149                 printf("%s: regmap failed %d\n", __func__, ret);
1150
1151 #endif
1152         return 0;
1153 }
1154
1155 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1156 static int conv_of_platdata(struct udevice *dev)
1157 {
1158         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1159         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1160         int ret;
1161
1162         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1163                         ARRAY_SIZE(dtplat->reg) / 4,
1164                         &plat->map);
1165         if (ret)
1166                 return ret;
1167
1168         return 0;
1169 }
1170 #endif
1171
1172 static int rk3399_dmc_init(struct udevice *dev)
1173 {
1174         struct dram_info *priv = dev_get_priv(dev);
1175         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1176         int ret;
1177 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1178         struct rk3399_sdram_params *params = &plat->sdram_params;
1179 #else
1180         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1181         struct rk3399_sdram_params *params =
1182                                         (void *)dtplat->rockchip_sdram_params;
1183
1184         ret = conv_of_platdata(dev);
1185         if (ret)
1186                 return ret;
1187 #endif
1188
1189         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1190         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1191         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1192         priv->pmucru = rockchip_get_pmucru();
1193         priv->cru = rockchip_get_cru();
1194         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1195         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1196         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1197         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1198         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1199         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1200         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1201         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1202
1203         debug("con reg %p %p %p %p %p %p %p %p\n",
1204               priv->chan[0].pctl, priv->chan[0].pi,
1205               priv->chan[0].publ, priv->chan[0].msch,
1206               priv->chan[1].pctl, priv->chan[1].pi,
1207               priv->chan[1].publ, priv->chan[1].msch);
1208         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1209               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1210 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1211         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1212 #else
1213         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1214 #endif
1215         if (ret) {
1216                 printf("%s clk get failed %d\n", __func__, ret);
1217                 return ret;
1218         }
1219         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1220         if (ret < 0) {
1221                 printf("%s clk set failed %d\n", __func__, ret);
1222                 return ret;
1223         }
1224         ret = sdram_init(priv, params);
1225         if (ret < 0) {
1226                 printf("%s DRAM init failed%d\n", __func__, ret);
1227                 return ret;
1228         }
1229
1230         return 0;
1231 }
1232 #endif
1233
1234 size_t sdram_size_mb(struct dram_info *dram)
1235 {
1236         u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
1237         size_t chipsize_mb = 0;
1238         size_t size_mb = 0;
1239         u32 ch;
1240
1241         u32 sys_reg = readl(&dram->pmugrf->os_reg2);
1242         u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
1243                        & SYS_REG_NUM_CH_MASK);
1244
1245         for (ch = 0; ch < ch_num; ch++) {
1246                 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
1247                         SYS_REG_RANK_MASK);
1248                 col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
1249                 bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
1250                 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
1251                                 SYS_REG_CS0_ROW_MASK);
1252                 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
1253                                 SYS_REG_CS1_ROW_MASK);
1254                 bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
1255                         SYS_REG_BW_MASK));
1256                 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
1257                         SYS_REG_ROW_3_4_MASK;
1258
1259                 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
1260
1261                 if (rank > 1)
1262                         chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
1263                 if (row_3_4)
1264                         chipsize_mb = chipsize_mb * 3 / 4;
1265                 size_mb += chipsize_mb;
1266         }
1267
1268         /*
1269          * we use the 0x00000000~0xf7ffffff space
1270          * since 0xf8000000~0xffffffff is soc register space
1271          * so we reserve it
1272          */
1273         size_mb = min_t(size_t, size_mb, 0xf8000000/(1<<20));
1274
1275         return size_mb;
1276 }
1277
1278 static int rk3399_dmc_probe(struct udevice *dev)
1279 {
1280 #ifdef CONFIG_SPL_BUILD
1281         if (rk3399_dmc_init(dev))
1282                 return 0;
1283 #else
1284         struct dram_info *priv = dev_get_priv(dev);
1285
1286         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1287         debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
1288         priv->info.base = 0;
1289         priv->info.size = sdram_size_mb(priv) << 20;
1290 #endif
1291         return 0;
1292 }
1293
1294 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1295 {
1296         struct dram_info *priv = dev_get_priv(dev);
1297
1298         *info = priv->info;
1299
1300         return 0;
1301 }
1302
1303 static struct ram_ops rk3399_dmc_ops = {
1304         .get_info = rk3399_dmc_get_info,
1305 };
1306
1307
1308 static const struct udevice_id rk3399_dmc_ids[] = {
1309         { .compatible = "rockchip,rk3399-dmc" },
1310         { }
1311 };
1312
1313 U_BOOT_DRIVER(dmc_rk3399) = {
1314         .name = "rockchip_rk3399_dmc",
1315         .id = UCLASS_RAM,
1316         .of_match = rk3399_dmc_ids,
1317         .ops = &rk3399_dmc_ops,
1318 #ifdef CONFIG_SPL_BUILD
1319         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1320 #endif
1321         .probe = rk3399_dmc_probe,
1322         .priv_auto_alloc_size = sizeof(struct dram_info),
1323 #ifdef CONFIG_SPL_BUILD
1324         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1325 #endif
1326 };