arch/arm/mach-rockchip/rk3399/rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <spl_gpio.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/io.h>
  10 #include <asm/arch-rockchip/grf_rk3399.h>
  11 #include <asm/arch-rockchip/hardware.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 #define GRF_EMMCCORE_CON11 0xff77f02c
  16 #define GRF_BASE        0xff770000
  17
  18 static struct mm_region rk3399_mem_map[] = {
  19         {
  20                 .virt = 0x0UL,
  21                 .phys = 0x0UL,
  22                 .size = 0xf8000000UL,
  23                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  24                          PTE_BLOCK_INNER_SHARE
  25         }, {
  26                 .virt = 0xf8000000UL,
  27                 .phys = 0xf8000000UL,
  28                 .size = 0x08000000UL,
  29                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  30                          PTE_BLOCK_NON_SHARE |
  31                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  32         }, {
  33                 /* List terminator */
  34                 0,
  35         }
  36 };
  37
  38 struct mm_region *mem_map = rk3399_mem_map;
  39
  40 int dram_init_banksize(void)
  41 {
  42         size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
  43
  44         /* Reserve 0x200000 for ATF bl31 */
  45         gd->bd->bi_dram[0].start = 0x200000;
  46         gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
  47
  48         return 0;
  49 }
  50
  51 int arch_cpu_init(void)
  52 {
  53         /* We do some SoC one time setting here. */
  54         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  55
  56         /* Emmc clock generator: disable the clock multipilier */
  57         rk_clrreg(&grf->emmccore_con[11], 0x0ff);
  58
  59         return 0;
  60 }
  61
  62 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  63 void board_debug_uart_init(void)
  64 {
  65 #define GRF_BASE        0xff770000
  66 #define GPIO0_BASE      0xff720000
  67 #define PMUGRF_BASE     0xff320000
  68         struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
  69 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  70         struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
  71         struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
  72 #endif
  73
  74 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  75         /* Enable early UART0 on the RK3399 */
  76         rk_clrsetreg(&grf->gpio2c_iomux,
  77                      GRF_GPIO2C0_SEL_MASK,
  78                      GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
  79         rk_clrsetreg(&grf->gpio2c_iomux,
  80                      GRF_GPIO2C1_SEL_MASK,
  81                      GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
  82 #else
  83 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
  84         rk_setreg(&grf->io_vsel, 1 << 0);
  85
  86         /*
  87          * Let's enable these power rails here, we are already running the SPI
  88          * Flash based code.
  89          */
  90         spl_gpio_output(gpio, GPIO(BANK_B, 2), 1);  /* PP1500_EN */
  91         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
  92
  93         spl_gpio_output(gpio, GPIO(BANK_B, 4), 1);  /* PP3000_EN */
  94         spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
  95 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
  96
  97         /* Enable early UART2 channel C on the RK3399 */
  98         rk_clrsetreg(&grf->gpio4c_iomux,
  99                      GRF_GPIO4C3_SEL_MASK,
 100                      GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 101         rk_clrsetreg(&grf->gpio4c_iomux,
 102                      GRF_GPIO4C4_SEL_MASK,
 103                      GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 104         /* Set channel C as UART2 input */
 105         rk_clrsetreg(&grf->soc_con7,
 106                      GRF_UART_DBG_SEL_MASK,
 107                      GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
 108 #endif
 109 }
 110 #endif