arch/arm/mach-rockchip/rk3328/rk3328.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <asm/arch-rockchip/bootrom.h>
   9 #include <asm/arch-rockchip/hardware.h>
  10 #include <asm/arch-rockchip/grf_rk3328.h>
  11 #include <asm/arch-rockchip/uart.h>
  12 #include <asm/armv8/mmu.h>
  13 #include <asm/global_data.h>
  14 #include <asm/io.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #define CRU_BASE                0xFF440000
  19 #define GRF_BASE                0xFF100000
  20 #define UART2_BASE              0xFF130000
  21 #define FW_DDR_CON_REG          0xFF7C0040
  22
  23 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  24         [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
  25         [BROM_BOOTSOURCE_SD] = "/mmc@ff500000",
  26 };
  27
  28 static struct mm_region rk3328_mem_map[] = {
  29         {
  30                 .virt = 0x0UL,
  31                 .phys = 0x0UL,
  32                 .size = 0xff000000UL,
  33                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  34                          PTE_BLOCK_INNER_SHARE
  35         }, {
  36                 .virt = 0xff000000UL,
  37                 .phys = 0xff000000UL,
  38                 .size = 0x1000000UL,
  39                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  40                          PTE_BLOCK_NON_SHARE |
  41                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  42         }, {
  43                 /* List terminator */
  44                 0,
  45         }
  46 };
  47
  48 struct mm_region *mem_map = rk3328_mem_map;
  49
  50 int arch_cpu_init(void)
  51 {
  52 #ifdef CONFIG_SPL_BUILD
  53         /* We do some SoC one time setting here. */
  54
  55         /* Disable the ddr secure region setting to make it non-secure */
  56         rk_setreg(FW_DDR_CON_REG, 0x200);
  57 #endif
  58         return 0;
  59 }
  60
  61 void board_debug_uart_init(void)
  62 {
  63         struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
  64         struct rk_uart * const uart = (void *)UART2_BASE;
  65         enum{
  66                 GPIO2A0_SEL_SHIFT       = 0,
  67                 GPIO2A0_SEL_MASK        = 3 << GPIO2A0_SEL_SHIFT,
  68                 GPIO2A0_UART2_TX_M1     = 1,
  69
  70                 GPIO2A1_SEL_SHIFT       = 2,
  71                 GPIO2A1_SEL_MASK        = 3 << GPIO2A1_SEL_SHIFT,
  72                 GPIO2A1_UART2_RX_M1     = 1,
  73         };
  74         enum {
  75                 IOMUX_SEL_UART2_SHIFT   = 0,
  76                 IOMUX_SEL_UART2_MASK    = 3 << IOMUX_SEL_UART2_SHIFT,
  77                 IOMUX_SEL_UART2_M0      = 0,
  78                 IOMUX_SEL_UART2_M1,
  79         };
  80
  81         /* uart_sel_clk default select 24MHz */
  82         writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
  83
  84         /* init uart baud rate 1500000 */
  85         writel(0x83, &uart->lcr);
  86         writel(0x1, &uart->rbr);
  87         writel(0x3, &uart->lcr);
  88
  89         /* Enable early UART2 */
  90         rk_clrsetreg(&grf->com_iomux,
  91                      IOMUX_SEL_UART2_MASK,
  92                      IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
  93         rk_clrsetreg(&grf->gpio2a_iomux,
  94                      GPIO2A0_SEL_MASK,
  95                      GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
  96         rk_clrsetreg(&grf->gpio2a_iomux,
  97                      GPIO2A1_SEL_MASK,
  98                      GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
  99
 100         /* enable FIFO */
 101         writel(0x1, &uart->sfe);
 102 }