1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Google, Inc
7 #include <debug_uart.h>
17 #include <asm/arch-rockchip/bootrom.h>
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/hardware.h>
20 #include <asm/arch-rockchip/periph.h>
21 #include <asm/arch-rockchip/pmu_rk3288.h>
22 #include <asm/arch-rockchip/sdram.h>
23 #include <asm/arch-rockchip/sdram_common.h>
24 #include <asm/arch-rockchip/sys_proto.h>
28 #include <power/regulator.h>
29 #include <power/rk8xx_pmic.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 u32 spl_boot_device(void)
35 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
36 const void *blob = gd->fdt_blob;
42 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
43 debug("Boot device %s\n", bootdev);
47 node = fdt_path_offset(blob, bootdev);
49 debug("node=%d\n", node);
52 ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev);
54 debug("device at node %s/%d not found: %d\n", bootdev, node,
58 debug("Found device %s\n", dev->name);
59 switch (device_get_uclass_id(dev)) {
60 case UCLASS_SPI_FLASH:
61 return BOOT_DEVICE_SPI;
63 return BOOT_DEVICE_MMC1;
65 debug("Booting from device uclass '%s' not supported\n",
66 dev_get_uclass_name(dev));
70 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
71 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
72 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
73 defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
74 return BOOT_DEVICE_SPI;
76 return BOOT_DEVICE_MMC1;
79 #if !defined(CONFIG_SPL_OF_PLATDATA)
80 static int phycore_init(void)
85 ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
89 #if defined(CONFIG_SPL_POWER_SUPPORT)
90 /* Increase USB input current to 2A */
91 ret = rk818_spl_configure_usb_input_current(pmic, 2000);
95 /* Close charger when USB lower then 3.26V */
96 ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
105 __weak int arch_cpu_init(void)
110 #define TIMER_LOAD_COUNT_L 0x00
111 #define TIMER_LOAD_COUNT_H 0x04
112 #define TIMER_CONTROL_REG 0x10
114 #define TIMER_FMODE BIT(0)
115 #define TIMER_RMODE BIT(1)
117 void rockchip_stimer_init(void)
119 /* If Timer already enabled, don't re-init it */
120 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
125 asm volatile("mcr p15, 0, %0, c14, c0, 0"
126 : : "r"(COUNTER_FREQUENCY));
128 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
129 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
130 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
131 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
135 void board_init_f(ulong dummy)
140 #ifdef CONFIG_DEBUG_UART
142 * Debug UART can be used from here if required:
147 * printascii("string");
150 debug("\nspl:debug uart enabled in %s\n", __func__);
152 ret = spl_early_init();
154 debug("spl_early_init() failed: %d\n", ret);
158 /* Init secure timer */
159 rockchip_stimer_init();
160 /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
165 ret = rockchip_get_clk(&dev);
167 debug("CLK init failed: %d\n", ret);
171 #if !defined(CONFIG_SPL_OF_PLATDATA)
172 if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
173 ret = phycore_init();
175 debug("Failed to set up phycore power settings: %d\n",
182 #if !defined(CONFIG_SUPPORT_TPL)
183 debug("\nspl:init dram\n");
184 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
186 debug("DRAM init failed: %d\n", ret);
191 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
192 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
196 static int setup_led(void)
198 #ifdef CONFIG_SPL_LED
203 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
206 ret = led_get_by_label(led_name, &dev);
208 debug("%s: get=%d\n", __func__, ret);
211 ret = led_set_on(dev, 1);
219 void spl_board_init(void)
225 debug("LED ret=%d\n", ret);
229 preloader_console_init();
230 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
231 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
236 #ifdef CONFIG_SPL_OS_BOOT
238 #define PMU_BASE 0xff730000
239 int dram_init_banksize(void)
241 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
242 size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
244 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
245 gd->bd->bi_dram[0].size = size;