1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
14 #include <asm/cache.h>
15 #include <asm/global_data.h>
17 #include <asm/arch-rockchip/boot_mode.h>
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/periph.h>
20 #include <asm/arch-rockchip/misc.h>
21 #include <power/regulator.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 __weak int rk_board_late_init(void)
30 int board_late_init(void)
34 return rk_board_late_init();
41 #ifdef CONFIG_DM_REGULATOR
42 ret = regulators_enable_boot_on(false);
44 debug("%s: Cannot enable boot on regulator\n", __func__);
50 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
51 void enable_caches(void)
53 /* Enable D-cache. I-cache is already enabled in start.S */
58 #if defined(CONFIG_USB_GADGET)
61 #if defined(CONFIG_USB_GADGET_DWC2_OTG)
62 #include <usb/dwc2_udc.h>
64 static struct dwc2_plat_otg_data otg_data = {
70 int board_usb_init(int index, enum usb_init_type init)
76 /* find the usb_otg node */
77 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
78 while (ofnode_valid(node)) {
79 mode = ofnode_read_string(node, "dr_mode");
80 if (mode && strcmp(mode, "otg") == 0) {
85 node = ofnode_by_compatible(node, "snps,dwc2");
88 debug("Not found usb_otg device\n");
91 otg_data.regs_otg = ofnode_get_addr(node);
93 #ifdef CONFIG_ROCKCHIP_RK3288
98 ret = ofnode_read_u32(node, "phys", &phandle);
102 node = ofnode_get_by_phandle(phandle);
103 if (!ofnode_valid(node)) {
104 debug("Not found usb phy device\n");
108 phy_node = ofnode_get_parent(node);
109 if (!ofnode_valid(node)) {
110 debug("Not found usb phy device\n");
114 otg_data.phy_of_node = phy_node;
115 ret = ofnode_read_u32(node, "reg", &offset);
118 otg_data.regs_phy = offset +
119 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
121 return dwc2_udc_probe(&otg_data);
124 int board_usb_cleanup(int index, enum usb_init_type init)
128 #endif /* CONFIG_USB_GADGET_DWC2_OTG */
130 #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
131 #include <dwc3-uboot.h>
133 static struct dwc3_device dwc3_device_data = {
134 .maximum_speed = USB_SPEED_HIGH,
136 .dr_mode = USB_DR_MODE_PERIPHERAL,
138 .dis_u2_susphy_quirk = 1,
139 .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
142 int usb_gadget_handle_interrupts(void)
144 dwc3_uboot_handle_interrupt(0);
148 int board_usb_init(int index, enum usb_init_type init)
150 return dwc3_uboot_init(&dwc3_device_data);
152 #endif /* CONFIG_USB_DWC3_GADGET */
154 #endif /* CONFIG_USB_GADGET */
156 #if CONFIG_IS_ENABLED(FASTBOOT)
157 int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
159 if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
162 printf("Setting reboot to fastboot flag ...\n");
163 /* Set boot mode to fastboot */
164 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
170 #ifdef CONFIG_MISC_INIT_R
171 __weak int misc_init_r(void)
173 const u32 cpuid_offset = 0x7;
174 const u32 cpuid_length = 0x10;
175 u8 cpuid[cpuid_length];
178 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
182 ret = rockchip_cpuid_set(cpuid, cpuid_length);
186 ret = rockchip_setup_macaddr();