1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
12 #include <asm/arch-rockchip/boot_mode.h>
13 #include <asm/arch-rockchip/clock.h>
14 #include <asm/arch-rockchip/periph.h>
15 #include <asm/arch-rockchip/misc.h>
16 #include <power/regulator.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 __weak int rk_board_late_init(void)
25 int board_late_init(void)
29 return rk_board_late_init();
36 #ifdef CONFIG_DM_REGULATOR
37 ret = regulators_enable_boot_on(false);
39 debug("%s: Cannot enable boot on regulator\n", __func__);
45 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
46 void enable_caches(void)
48 /* Enable D-cache. I-cache is already enabled in start.S */
53 #if defined(CONFIG_USB_GADGET)
56 #if defined(CONFIG_USB_GADGET_DWC2_OTG)
57 #include <usb/dwc2_udc.h>
59 static struct dwc2_plat_otg_data otg_data = {
65 int board_usb_init(int index, enum usb_init_type init)
71 /* find the usb_otg node */
72 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
73 while (ofnode_valid(node)) {
74 mode = ofnode_read_string(node, "dr_mode");
75 if (mode && strcmp(mode, "otg") == 0) {
80 node = ofnode_by_compatible(node, "snps,dwc2");
83 debug("Not found usb_otg device\n");
86 otg_data.regs_otg = ofnode_get_addr(node);
88 #ifdef CONFIG_ROCKCHIP_RK3288
93 ret = ofnode_read_u32(node, "phys", &phandle);
97 node = ofnode_get_by_phandle(phandle);
98 if (!ofnode_valid(node)) {
99 debug("Not found usb phy device\n");
103 phy_node = ofnode_get_parent(node);
104 if (!ofnode_valid(node)) {
105 debug("Not found usb phy device\n");
109 otg_data.phy_of_node = phy_node;
110 ret = ofnode_read_u32(node, "reg", &offset);
113 otg_data.regs_phy = offset +
114 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
116 return dwc2_udc_probe(&otg_data);
119 int board_usb_cleanup(int index, enum usb_init_type init)
123 #endif /* CONFIG_USB_GADGET_DWC2_OTG */
125 #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
126 #include <dwc3-uboot.h>
128 static struct dwc3_device dwc3_device_data = {
129 .maximum_speed = USB_SPEED_HIGH,
131 .dr_mode = USB_DR_MODE_PERIPHERAL,
133 .dis_u2_susphy_quirk = 1,
134 .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
137 int usb_gadget_handle_interrupts(void)
139 dwc3_uboot_handle_interrupt(0);
143 int board_usb_init(int index, enum usb_init_type init)
145 return dwc3_uboot_init(&dwc3_device_data);
147 #endif /* CONFIG_USB_DWC3_GADGET */
149 #endif /* CONFIG_USB_GADGET */
151 #if CONFIG_IS_ENABLED(FASTBOOT)
152 int fastboot_set_reboot_flag(void)
154 printf("Setting reboot to fastboot flag ...\n");
155 /* Set boot mode to fastboot */
156 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
162 #ifdef CONFIG_MISC_INIT_R
163 __weak int misc_init_r(void)
165 const u32 cpuid_offset = 0x7;
166 const u32 cpuid_length = 0x10;
167 u8 cpuid[cpuid_length];
170 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
174 ret = rockchip_cpuid_set(cpuid, cpuid_length);
178 ret = rockchip_setup_macaddr();