arch/arm/mach-pxa/zeus.c

   1 /*
   2  *  Support for the Arcom ZEUS.
   3  *
   4  *  Copyright (C) 2006 Arcom Control Systems Ltd.
   5  *
   6  *  Loosely based on Arcom's 2.6.16.28.
   7  *  Maintained by Marc Zyngier <maz@misterjones.org>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/cpufreq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/leds.h>
  17 #include <linux/irq.h>
  18 #include <linux/pm.h>
  19 #include <linux/gpio.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/dm9000.h>
  22 #include <linux/mmc/host.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/spi/pxa2xx_spi.h>
  25 #include <linux/mtd/mtd.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/mtd/physmap.h>
  28 #include <linux/i2c.h>
  29 #include <linux/platform_data/i2c-pxa.h>
  30 #include <linux/platform_data/pca953x.h>
  31 #include <linux/apm-emulation.h>
  32 #include <linux/can/platform/mcp251x.h>
  33 #include <linux/regulator/fixed.h>
  34 #include <linux/regulator/machine.h>
  35
  36 #include <asm/mach-types.h>
  37 #include <asm/suspend.h>
  38 #include <asm/system_info.h>
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/map.h>
  41
  42 #include "pxa27x.h"
  43 #include "devices.h"
  44 #include <mach/regs-uart.h>
  45 #include <linux/platform_data/usb-ohci-pxa27x.h>
  46 #include <linux/platform_data/mmc-pxamci.h>
  47 #include "pxa27x-udc.h"
  48 #include "udc.h"
  49 #include <linux/platform_data/video-pxafb.h>
  50 #include "pm.h"
  51 #include <mach/audio.h>
  52 #include <linux/platform_data/pcmcia-pxa2xx_viper.h>
  53 #include "zeus.h"
  54 #include <mach/smemc.h>
  55
  56 #include "generic.h"
  57
  58 /*
  59  * Interrupt handling
  60  */
  61
  62 static unsigned long zeus_irq_enabled_mask;
  63 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
  64 static const int zeus_isa_irq_map[] = {
  65         0,              /* ISA irq #0, invalid */
  66         0,              /* ISA irq #1, invalid */
  67         0,              /* ISA irq #2, invalid */
  68         1 << 0,         /* ISA irq #3 */
  69         1 << 1,         /* ISA irq #4 */
  70         1 << 2,         /* ISA irq #5 */
  71         1 << 3,         /* ISA irq #6 */
  72         1 << 4,         /* ISA irq #7 */
  73         0,              /* ISA irq #8, invalid */
  74         0,              /* ISA irq #9, invalid */
  75         1 << 5,         /* ISA irq #10 */
  76         1 << 6,         /* ISA irq #11 */
  77         1 << 7,         /* ISA irq #12 */
  78 };
  79
  80 static inline int zeus_irq_to_bitmask(unsigned int irq)
  81 {
  82         return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
  83 }
  84
  85 static inline int zeus_bit_to_irq(int bit)
  86 {
  87         return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
  88 }
  89
  90 static void zeus_ack_irq(struct irq_data *d)
  91 {
  92         __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
  93 }
  94
  95 static void zeus_mask_irq(struct irq_data *d)
  96 {
  97         zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
  98 }
  99
 100 static void zeus_unmask_irq(struct irq_data *d)
 101 {
 102         zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
 103 }
 104
 105 static inline unsigned long zeus_irq_pending(void)
 106 {
 107         return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
 108 }
 109
 110 static void zeus_irq_handler(struct irq_desc *desc)
 111 {
 112         unsigned int irq;
 113         unsigned long pending;
 114
 115         pending = zeus_irq_pending();
 116         do {
 117                 /* we're in a chained irq handler,
 118                  * so ack the interrupt by hand */
 119                 desc->irq_data.chip->irq_ack(&desc->irq_data);
 120
 121                 if (likely(pending)) {
 122                         irq = zeus_bit_to_irq(__ffs(pending));
 123                         generic_handle_irq(irq);
 124                 }
 125                 pending = zeus_irq_pending();
 126         } while (pending);
 127 }
 128
 129 static struct irq_chip zeus_irq_chip = {
 130         .name           = "ISA",
 131         .irq_ack        = zeus_ack_irq,
 132         .irq_mask       = zeus_mask_irq,
 133         .irq_unmask     = zeus_unmask_irq,
 134 };
 135
 136 static void __init zeus_init_irq(void)
 137 {
 138         int level;
 139         int isa_irq;
 140
 141         pxa27x_init_irq();
 142
 143         /* Peripheral IRQs. It would be nice to move those inside driver
 144            configuration, but it is not supported at the moment. */
 145         irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
 146         irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
 147         irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
 148         irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
 149                          IRQ_TYPE_EDGE_FALLING);
 150         irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
 151
 152         /* Setup ISA IRQs */
 153         for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
 154                 isa_irq = zeus_bit_to_irq(level);
 155                 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
 156                                          handle_edge_irq);
 157                 irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
 158         }
 159
 160         irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
 161         irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
 162 }
 163
 164
 165 /*
 166  * Platform devices
 167  */
 168
 169 /* Flash */
 170 static struct resource zeus_mtd_resources[] = {
 171         [0] = { /* NOR Flash (up to 64MB) */
 172                 .start  = ZEUS_FLASH_PHYS,
 173                 .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
 174                 .flags  = IORESOURCE_MEM,
 175         },
 176         [1] = { /* SRAM */
 177                 .start  = ZEUS_SRAM_PHYS,
 178                 .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
 179                 .flags  = IORESOURCE_MEM,
 180         },
 181 };
 182
 183 static struct physmap_flash_data zeus_flash_data[] = {
 184         [0] = {
 185                 .width          = 2,
 186                 .parts          = NULL,
 187                 .nr_parts       = 0,
 188         },
 189 };
 190
 191 static struct platform_device zeus_mtd_devices[] = {
 192         [0] = {
 193                 .name           = "physmap-flash",
 194                 .id             = 0,
 195                 .dev            = {
 196                         .platform_data = &zeus_flash_data[0],
 197                 },
 198                 .resource       = &zeus_mtd_resources[0],
 199                 .num_resources  = 1,
 200         },
 201 };
 202
 203 /* Serial */
 204 static struct resource zeus_serial_resources[] = {
 205         {
 206                 .start  = 0x10000000,
 207                 .end    = 0x1000000f,
 208                 .flags  = IORESOURCE_MEM,
 209         },
 210         {
 211                 .start  = 0x10800000,
 212                 .end    = 0x1080000f,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         {
 216                 .start  = 0x11000000,
 217                 .end    = 0x1100000f,
 218                 .flags  = IORESOURCE_MEM,
 219         },
 220         {
 221                 .start  = 0x40100000,
 222                 .end    = 0x4010001f,
 223                 .flags  = IORESOURCE_MEM,
 224         },
 225         {
 226                 .start  = 0x40200000,
 227                 .end    = 0x4020001f,
 228                 .flags  = IORESOURCE_MEM,
 229         },
 230         {
 231                 .start  = 0x40700000,
 232                 .end    = 0x4070001f,
 233                 .flags  = IORESOURCE_MEM,
 234         },
 235 };
 236
 237 static struct plat_serial8250_port serial_platform_data[] = {
 238         /* External UARTs */
 239         /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
 240         { /* COM1 */
 241                 .mapbase        = 0x10000000,
 242                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
 243                 .irqflags       = IRQF_TRIGGER_RISING,
 244                 .uartclk        = 14745600,
 245                 .regshift       = 1,
 246                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 247                 .iotype         = UPIO_MEM,
 248         },
 249         { /* COM2 */
 250                 .mapbase        = 0x10800000,
 251                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
 252                 .irqflags       = IRQF_TRIGGER_RISING,
 253                 .uartclk        = 14745600,
 254                 .regshift       = 1,
 255                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 256                 .iotype         = UPIO_MEM,
 257         },
 258         { /* COM3 */
 259                 .mapbase        = 0x11000000,
 260                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
 261                 .irqflags       = IRQF_TRIGGER_RISING,
 262                 .uartclk        = 14745600,
 263                 .regshift       = 1,
 264                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 265                 .iotype         = UPIO_MEM,
 266         },
 267         { /* COM4 */
 268                 .mapbase        = 0x11800000,
 269                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
 270                 .irqflags       = IRQF_TRIGGER_RISING,
 271                 .uartclk        = 14745600,
 272                 .regshift       = 1,
 273                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 274                 .iotype         = UPIO_MEM,
 275         },
 276         /* Internal UARTs */
 277         { /* FFUART */
 278                 .membase        = (void *)&FFUART,
 279                 .mapbase        = __PREG(FFUART),
 280                 .irq            = IRQ_FFUART,
 281                 .uartclk        = 921600 * 16,
 282                 .regshift       = 2,
 283                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 284                 .iotype         = UPIO_MEM,
 285         },
 286         { /* BTUART */
 287                 .membase        = (void *)&BTUART,
 288                 .mapbase        = __PREG(BTUART),
 289                 .irq            = IRQ_BTUART,
 290                 .uartclk        = 921600 * 16,
 291                 .regshift       = 2,
 292                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 293                 .iotype         = UPIO_MEM,
 294         },
 295         { /* STUART */
 296                 .membase        = (void *)&STUART,
 297                 .mapbase        = __PREG(STUART),
 298                 .irq            = IRQ_STUART,
 299                 .uartclk        = 921600 * 16,
 300                 .regshift       = 2,
 301                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 302                 .iotype         = UPIO_MEM,
 303         },
 304         { },
 305 };
 306
 307 static struct platform_device zeus_serial_device = {
 308         .name = "serial8250",
 309         .id   = PLAT8250_DEV_PLATFORM,
 310         .dev  = {
 311                 .platform_data = serial_platform_data,
 312         },
 313         .num_resources  = ARRAY_SIZE(zeus_serial_resources),
 314         .resource       = zeus_serial_resources,
 315 };
 316
 317 /* Ethernet */
 318 static struct resource zeus_dm9k0_resource[] = {
 319         [0] = {
 320                 .start = ZEUS_ETH0_PHYS,
 321                 .end   = ZEUS_ETH0_PHYS + 1,
 322                 .flags = IORESOURCE_MEM
 323         },
 324         [1] = {
 325                 .start = ZEUS_ETH0_PHYS + 2,
 326                 .end   = ZEUS_ETH0_PHYS + 3,
 327                 .flags = IORESOURCE_MEM
 328         },
 329         [2] = {
 330                 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
 331                 .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
 332                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 333         },
 334 };
 335
 336 static struct resource zeus_dm9k1_resource[] = {
 337         [0] = {
 338                 .start = ZEUS_ETH1_PHYS,
 339                 .end   = ZEUS_ETH1_PHYS + 1,
 340                 .flags = IORESOURCE_MEM
 341         },
 342         [1] = {
 343                 .start = ZEUS_ETH1_PHYS + 2,
 344                 .end   = ZEUS_ETH1_PHYS + 3,
 345                 .flags = IORESOURCE_MEM,
 346         },
 347         [2] = {
 348                 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
 349                 .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
 350                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 351         },
 352 };
 353
 354 static struct dm9000_plat_data zeus_dm9k_platdata = {
 355         .flags          = DM9000_PLATF_16BITONLY,
 356 };
 357
 358 static struct platform_device zeus_dm9k0_device = {
 359         .name           = "dm9000",
 360         .id             = 0,
 361         .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
 362         .resource       = zeus_dm9k0_resource,
 363         .dev            = {
 364                 .platform_data = &zeus_dm9k_platdata,
 365         }
 366 };
 367
 368 static struct platform_device zeus_dm9k1_device = {
 369         .name           = "dm9000",
 370         .id             = 1,
 371         .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
 372         .resource       = zeus_dm9k1_resource,
 373         .dev            = {
 374                 .platform_data = &zeus_dm9k_platdata,
 375         }
 376 };
 377
 378 /* External SRAM */
 379 static struct resource zeus_sram_resource = {
 380         .start          = ZEUS_SRAM_PHYS,
 381         .end            = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
 382         .flags          = IORESOURCE_MEM,
 383 };
 384
 385 static struct platform_device zeus_sram_device = {
 386         .name           = "pxa2xx-8bit-sram",
 387         .id             = 0,
 388         .num_resources  = 1,
 389         .resource       = &zeus_sram_resource,
 390 };
 391
 392 /* SPI interface on SSP3 */
 393 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
 394         .num_chipselect = 1,
 395         .enable_dma     = 1,
 396 };
 397
 398 /* CAN bus on SPI */
 399 static struct regulator_consumer_supply can_regulator_consumer =
 400         REGULATOR_SUPPLY("vdd", "spi3.0");
 401
 402 static struct regulator_init_data can_regulator_init_data = {
 403         .constraints    = {
 404                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 405         },
 406         .consumer_supplies      = &can_regulator_consumer,
 407         .num_consumer_supplies  = 1,
 408 };
 409
 410 static struct fixed_voltage_config can_regulator_pdata = {
 411         .supply_name    = "CAN_SHDN",
 412         .microvolts     = 3300000,
 413         .gpio           = ZEUS_CAN_SHDN_GPIO,
 414         .init_data      = &can_regulator_init_data,
 415 };
 416
 417 static struct platform_device can_regulator_device = {
 418         .name   = "reg-fixed-voltage",
 419         .id     = 0,
 420         .dev    = {
 421                 .platform_data  = &can_regulator_pdata,
 422         },
 423 };
 424
 425 static struct mcp251x_platform_data zeus_mcp2515_pdata = {
 426         .oscillator_frequency   = 16*1000*1000,
 427 };
 428
 429 static struct spi_board_info zeus_spi_board_info[] = {
 430         [0] = {
 431                 .modalias       = "mcp2515",
 432                 .platform_data  = &zeus_mcp2515_pdata,
 433                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
 434                 .max_speed_hz   = 1*1000*1000,
 435                 .bus_num        = 3,
 436                 .mode           = SPI_MODE_0,
 437                 .chip_select    = 0,
 438         },
 439 };
 440
 441 /* Leds */
 442 static struct gpio_led zeus_leds[] = {
 443         [0] = {
 444                 .name            = "zeus:yellow:1",
 445                 .default_trigger = "heartbeat",
 446                 .gpio            = ZEUS_EXT0_GPIO(3),
 447                 .active_low      = 1,
 448         },
 449         [1] = {
 450                 .name            = "zeus:yellow:2",
 451                 .default_trigger = "default-on",
 452                 .gpio            = ZEUS_EXT0_GPIO(4),
 453                 .active_low      = 1,
 454         },
 455         [2] = {
 456                 .name            = "zeus:yellow:3",
 457                 .default_trigger = "default-on",
 458                 .gpio            = ZEUS_EXT0_GPIO(5),
 459                 .active_low      = 1,
 460         },
 461 };
 462
 463 static struct gpio_led_platform_data zeus_leds_info = {
 464         .leds           = zeus_leds,
 465         .num_leds       = ARRAY_SIZE(zeus_leds),
 466 };
 467
 468 static struct platform_device zeus_leds_device = {
 469         .name           = "leds-gpio",
 470         .id             = -1,
 471         .dev            = {
 472                 .platform_data  = &zeus_leds_info,
 473         },
 474 };
 475
 476 static void zeus_cf_reset(int state)
 477 {
 478         u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
 479
 480         if (state)
 481                 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
 482         else
 483                 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
 484
 485         __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
 486 }
 487
 488 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
 489         .cd_gpio        = ZEUS_CF_CD_GPIO,
 490         .rdy_gpio       = ZEUS_CF_RDY_GPIO,
 491         .pwr_gpio       = ZEUS_CF_PWEN_GPIO,
 492         .reset          = zeus_cf_reset,
 493 };
 494
 495 static struct platform_device zeus_pcmcia_device = {
 496         .name           = "zeus-pcmcia",
 497         .id             = -1,
 498         .dev            = {
 499                 .platform_data  = &zeus_pcmcia_info,
 500         },
 501 };
 502
 503 static struct resource zeus_max6369_resource = {
 504         .start          = ZEUS_CPLD_EXTWDOG_PHYS,
 505         .end            = ZEUS_CPLD_EXTWDOG_PHYS,
 506         .flags          = IORESOURCE_MEM,
 507 };
 508
 509 struct platform_device zeus_max6369_device = {
 510         .name           = "max6369_wdt",
 511         .id             = -1,
 512         .resource       = &zeus_max6369_resource,
 513         .num_resources  = 1,
 514 };
 515
 516 /* AC'97 */
 517 static pxa2xx_audio_ops_t zeus_ac97_info = {
 518         .reset_gpio = 95,
 519 };
 520
 521
 522 /*
 523  * USB host
 524  */
 525
 526 static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
 527         REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
 528 };
 529
 530 static struct regulator_init_data zeus_ohci_regulator_data = {
 531         .constraints = {
 532                 .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 533         },
 534         .num_consumer_supplies  = ARRAY_SIZE(zeus_ohci_regulator_supplies),
 535         .consumer_supplies      = zeus_ohci_regulator_supplies,
 536 };
 537
 538 static struct fixed_voltage_config zeus_ohci_regulator_config = {
 539         .supply_name            = "vbus2",
 540         .microvolts             = 5000000, /* 5.0V */
 541         .gpio                   = ZEUS_USB2_PWREN_GPIO,
 542         .enable_high            = 1,
 543         .startup_delay          = 0,
 544         .init_data              = &zeus_ohci_regulator_data,
 545 };
 546
 547 static struct platform_device zeus_ohci_regulator_device = {
 548         .name           = "reg-fixed-voltage",
 549         .id             = 1,
 550         .dev = {
 551                 .platform_data = &zeus_ohci_regulator_config,
 552         },
 553 };
 554
 555 static struct pxaohci_platform_data zeus_ohci_platform_data = {
 556         .port_mode      = PMM_NPS_MODE,
 557         /* Clear Power Control Polarity Low and set Power Sense
 558          * Polarity Low. Supply power to USB ports. */
 559         .flags          = ENABLE_PORT_ALL | POWER_SENSE_LOW,
 560 };
 561
 562 static void zeus_register_ohci(void)
 563 {
 564         /* Port 2 is shared between host and client interface. */
 565         UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 566
 567         pxa_set_ohci_info(&zeus_ohci_platform_data);
 568 }
 569
 570 /*
 571  * Flat Panel
 572  */
 573
 574 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
 575 {
 576         gpio_set_value(ZEUS_LCD_EN_GPIO, on);
 577 }
 578
 579 static void zeus_backlight_power(int on)
 580 {
 581         gpio_set_value(ZEUS_BKLEN_GPIO, on);
 582 }
 583
 584 static int zeus_setup_fb_gpios(void)
 585 {
 586         int err;
 587
 588         if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
 589                 goto out_err;
 590
 591         if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
 592                 goto out_err_lcd;
 593
 594         if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
 595                 goto out_err_lcd;
 596
 597         if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
 598                 goto out_err_bkl;
 599
 600         return 0;
 601
 602 out_err_bkl:
 603         gpio_free(ZEUS_BKLEN_GPIO);
 604 out_err_lcd:
 605         gpio_free(ZEUS_LCD_EN_GPIO);
 606 out_err:
 607         return err;
 608 }
 609
 610 static struct pxafb_mode_info zeus_fb_mode_info[] = {
 611         {
 612                 .pixclock       = 39722,
 613
 614                 .xres           = 640,
 615                 .yres           = 480,
 616
 617                 .bpp            = 16,
 618
 619                 .hsync_len      = 63,
 620                 .left_margin    = 16,
 621                 .right_margin   = 81,
 622
 623                 .vsync_len      = 2,
 624                 .upper_margin   = 12,
 625                 .lower_margin   = 31,
 626
 627                 .sync           = 0,
 628         },
 629 };
 630
 631 static struct pxafb_mach_info zeus_fb_info = {
 632         .modes                  = zeus_fb_mode_info,
 633         .num_modes              = 1,
 634         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 635         .pxafb_lcd_power        = zeus_lcd_power,
 636         .pxafb_backlight_power  = zeus_backlight_power,
 637 };
 638
 639 /*
 640  * MMC/SD Device
 641  *
 642  * The card detect interrupt isn't debounced so we delay it by 250ms
 643  * to give the card a chance to fully insert/eject.
 644  */
 645
 646 static struct pxamci_platform_data zeus_mci_platform_data = {
 647         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
 648         .detect_delay_ms        = 250,
 649         .gpio_card_detect       = ZEUS_MMC_CD_GPIO,
 650         .gpio_card_ro           = ZEUS_MMC_WP_GPIO,
 651         .gpio_card_ro_invert    = 1,
 652         .gpio_power             = -1
 653 };
 654
 655 /*
 656  * USB Device Controller
 657  */
 658 static void zeus_udc_command(int cmd)
 659 {
 660         switch (cmd) {
 661         case PXA2XX_UDC_CMD_DISCONNECT:
 662                 pr_info("zeus: disconnecting USB client\n");
 663                 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 664                 break;
 665
 666         case PXA2XX_UDC_CMD_CONNECT:
 667                 pr_info("zeus: connecting USB client\n");
 668                 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
 669                 break;
 670         }
 671 }
 672
 673 static struct pxa2xx_udc_mach_info zeus_udc_info = {
 674         .udc_command = zeus_udc_command,
 675 };
 676
 677 static struct platform_device *zeus_devices[] __initdata = {
 678         &zeus_serial_device,
 679         &zeus_mtd_devices[0],
 680         &zeus_dm9k0_device,
 681         &zeus_dm9k1_device,
 682         &zeus_sram_device,
 683         &zeus_leds_device,
 684         &zeus_pcmcia_device,
 685         &zeus_max6369_device,
 686         &can_regulator_device,
 687         &zeus_ohci_regulator_device,
 688 };
 689
 690 #ifdef CONFIG_PM
 691 static void zeus_power_off(void)
 692 {
 693         local_irq_disable();
 694         cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
 695 }
 696 #else
 697 #define zeus_power_off   NULL
 698 #endif
 699
 700 #ifdef CONFIG_APM_EMULATION
 701 static void zeus_get_power_status(struct apm_power_info *info)
 702 {
 703         /* Power supply is always present */
 704         info->ac_line_status    = APM_AC_ONLINE;
 705         info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
 706         info->battery_flag      = APM_BATTERY_FLAG_NOT_PRESENT;
 707 }
 708
 709 static inline void zeus_setup_apm(void)
 710 {
 711         apm_get_power_status = zeus_get_power_status;
 712 }
 713 #else
 714 static inline void zeus_setup_apm(void)
 715 {
 716 }
 717 #endif
 718
 719 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
 720                              unsigned ngpio, void *context)
 721 {
 722         int i;
 723         u8 pcb_info = 0;
 724
 725         for (i = 0; i < 8; i++) {
 726                 int pcb_bit = gpio + i + 8;
 727
 728                 if (gpio_request(pcb_bit, "pcb info")) {
 729                         dev_err(&client->dev, "Can't request pcb info %d\n", i);
 730                         continue;
 731                 }
 732
 733                 if (gpio_direction_input(pcb_bit)) {
 734                         dev_err(&client->dev, "Can't read pcb info %d\n", i);
 735                         gpio_free(pcb_bit);
 736                         continue;
 737                 }
 738
 739                 pcb_info |= !!gpio_get_value(pcb_bit) << i;
 740
 741                 gpio_free(pcb_bit);
 742         }
 743
 744         dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
 745                  pcb_info >> 4, pcb_info & 0xf);
 746
 747         return 0;
 748 }
 749
 750 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
 751         [0] = { .gpio_base      = ZEUS_EXT0_GPIO_BASE, },
 752         [1] = {
 753                 .gpio_base      = ZEUS_EXT1_GPIO_BASE,
 754                 .setup          = zeus_get_pcb_info,
 755         },
 756         [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
 757 };
 758
 759 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
 760         {
 761                 I2C_BOARD_INFO("pca9535",       0x21),
 762                 .platform_data  = &zeus_pca953x_pdata[0],
 763         },
 764         {
 765                 I2C_BOARD_INFO("pca9535",       0x22),
 766                 .platform_data  = &zeus_pca953x_pdata[1],
 767         },
 768         {
 769                 I2C_BOARD_INFO("pca9535",       0x20),
 770                 .platform_data  = &zeus_pca953x_pdata[2],
 771                 .irq            = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
 772         },
 773         { I2C_BOARD_INFO("lm75a",       0x48) },
 774         { I2C_BOARD_INFO("24c01",       0x50) },
 775         { I2C_BOARD_INFO("isl1208",     0x6f) },
 776 };
 777
 778 static mfp_cfg_t zeus_pin_config[] __initdata = {
 779         /* AC97 */
 780         GPIO28_AC97_BITCLK,
 781         GPIO29_AC97_SDATA_IN_0,
 782         GPIO30_AC97_SDATA_OUT,
 783         GPIO31_AC97_SYNC,
 784
 785         GPIO15_nCS_1,
 786         GPIO78_nCS_2,
 787         GPIO80_nCS_4,
 788         GPIO33_nCS_5,
 789
 790         GPIO22_GPIO,
 791         GPIO32_MMC_CLK,
 792         GPIO92_MMC_DAT_0,
 793         GPIO109_MMC_DAT_1,
 794         GPIO110_MMC_DAT_2,
 795         GPIO111_MMC_DAT_3,
 796         GPIO112_MMC_CMD,
 797
 798         GPIO88_USBH1_PWR,
 799         GPIO89_USBH1_PEN,
 800         GPIO119_USBH2_PWR,
 801         GPIO120_USBH2_PEN,
 802
 803         GPIO86_LCD_LDD_16,
 804         GPIO87_LCD_LDD_17,
 805
 806         GPIO102_GPIO,
 807         GPIO104_CIF_DD_2,
 808         GPIO105_CIF_DD_1,
 809
 810         GPIO81_SSP3_TXD,
 811         GPIO82_SSP3_RXD,
 812         GPIO83_SSP3_SFRM,
 813         GPIO84_SSP3_SCLK,
 814
 815         GPIO48_nPOE,
 816         GPIO49_nPWE,
 817         GPIO50_nPIOR,
 818         GPIO51_nPIOW,
 819         GPIO85_nPCE_1,
 820         GPIO54_nPCE_2,
 821         GPIO79_PSKTSEL,
 822         GPIO55_nPREG,
 823         GPIO56_nPWAIT,
 824         GPIO57_nIOIS16,
 825         GPIO36_GPIO,            /* CF CD */
 826         GPIO97_GPIO,            /* CF PWREN */
 827         GPIO99_GPIO,            /* CF RDY */
 828 };
 829
 830 /*
 831  * DM9k MSCx settings:  SRAM, 16 bits
 832  *                      17 cycles delay first access
 833  *                       5 cycles delay next access
 834  *                      13 cycles recovery time
 835  *                      faster device
 836  */
 837 #define DM9K_MSC_VALUE          0xe4c9
 838
 839 static void __init zeus_init(void)
 840 {
 841         u16 dm9000_msc = DM9K_MSC_VALUE;
 842         u32 msc0, msc1;
 843
 844         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
 845         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
 846
 847         /* Fix timings for dm9000s (CS1/CS2)*/
 848         msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
 849         msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
 850         __raw_writel(msc0, MSC0);
 851         __raw_writel(msc1, MSC1);
 852
 853         pm_power_off = zeus_power_off;
 854         zeus_setup_apm();
 855
 856         pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
 857
 858         platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
 859
 860         zeus_register_ohci();
 861
 862         if (zeus_setup_fb_gpios())
 863                 pr_err("Failed to setup fb gpios\n");
 864         else
 865                 pxa_set_fb_info(NULL, &zeus_fb_info);
 866
 867         pxa_set_mci_info(&zeus_mci_platform_data);
 868         pxa_set_udc_info(&zeus_udc_info);
 869         pxa_set_ac97_info(&zeus_ac97_info);
 870         pxa_set_i2c_info(NULL);
 871         i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
 872         pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
 873         spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
 874
 875         regulator_has_full_constraints();
 876 }
 877
 878 static struct map_desc zeus_io_desc[] __initdata = {
 879         {
 880                 .virtual = (unsigned long)ZEUS_CPLD_VERSION,
 881                 .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
 882                 .length  = 0x1000,
 883                 .type    = MT_DEVICE,
 884         },
 885         {
 886                 .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
 887                 .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
 888                 .length  = 0x1000,
 889                 .type    = MT_DEVICE,
 890         },
 891         {
 892                 .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
 893                 .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
 894                 .length  = 0x1000,
 895                 .type    = MT_DEVICE,
 896         },
 897         {
 898                 .virtual = (unsigned long)ZEUS_PC104IO,
 899                 .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
 900                 .length  = 0x00800000,
 901                 .type    = MT_DEVICE,
 902         },
 903 };
 904
 905 static void __init zeus_map_io(void)
 906 {
 907         pxa27x_map_io();
 908
 909         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
 910
 911         /* Clear PSPR to ensure a full restart on wake-up. */
 912         PMCR = PSPR = 0;
 913
 914         /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
 915         writel(readl(OSCC) | OSCC_OON, OSCC);
 916
 917         /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
 918          * float chip selects and PCMCIA */
 919         PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
 920 }
 921
 922 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
 923         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
 924         .atag_offset    = 0x100,
 925         .map_io         = zeus_map_io,
 926         .nr_irqs        = ZEUS_NR_IRQS,
 927         .init_irq       = zeus_init_irq,
 928         .handle_irq     = pxa27x_handle_irq,
 929         .init_time      = pxa_timer_init,
 930         .init_machine   = zeus_init,
 931         .restart        = pxa_restart,
 932 MACHINE_END
 933