2 * arch/arm/mach-pxa/include/mach/hardware.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_HARDWARE_H
14 #define __ASM_ARCH_HARDWARE_H
17 * We requires absolute addresses.
22 * Workarounds for at least 2 errata so far require this.
23 * The mapping is set in mach-pxa/generic.c.
25 #define UNCACHED_PHYS_0 0xff000000
26 #define UNCACHED_ADDR UNCACHED_PHYS_0
29 * Intel PXA2xx internal register mapping:
31 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
32 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
33 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
34 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
35 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
36 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
37 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
39 * Note that not all PXA2xx chips implement all those addresses, and the
40 * kernel only maps the minimum needed range of this mapping.
42 #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
43 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
47 # define __REG(x) (*((volatile u32 *)io_p2v(x)))
49 /* With indexed regs we don't want to feed the index through io_p2v()
50 especially if it is a variable, otherwise horrible code will result. */
51 # define __REG2(x,y) \
52 (*(volatile u32 *)((u32)&__REG(x) + (y)))
54 # define __PREG(x) (io_v2p((u32)&(x)))
58 # define __REG(x) io_p2v(x)
59 # define __PREG(x) io_v2p(x)
66 * CPU Stepping CPU_ID JTAG_ID
68 * PXA210 B0 0x69052922 0x2926C013
69 * PXA210 B1 0x69052923 0x3926C013
70 * PXA210 B2 0x69052924 0x4926C013
71 * PXA210 C0 0x69052D25 0x5926C013
73 * PXA250 A0 0x69052100 0x09264013
74 * PXA250 A1 0x69052101 0x19264013
75 * PXA250 B0 0x69052902 0x29264013
76 * PXA250 B1 0x69052903 0x39264013
77 * PXA250 B2 0x69052904 0x49264013
78 * PXA250 C0 0x69052D05 0x59264013
80 * PXA255 A0 0x69052D06 0x69264013
82 * PXA26x A0 0x69052903 0x39264013
83 * PXA26x B0 0x69052D05 0x59264013
85 * PXA27x A0 0x69054110 0x09265013
86 * PXA27x A1 0x69054111 0x19265013
87 * PXA27x B0 0x69054112 0x29265013
88 * PXA27x B1 0x69054113 0x39265013
89 * PXA27x C0 0x69054114 0x49265013
90 * PXA27x C5 0x69054117 0x79265013
92 * PXA30x A0 0x69056880 0x0E648013
93 * PXA30x A1 0x69056881 0x1E648013
94 * PXA31x A0 0x69056890 0x0E649013
95 * PXA31x A1 0x69056891 0x1E649013
96 * PXA31x A2 0x69056892 0x2E649013
97 * PXA32x B1 0x69056825 0x5E642013
98 * PXA32x B2 0x69056826 0x6E642013
100 * PXA930 B0 0x69056835 0x5E643013
101 * PXA930 B1 0x69056837 0x7E643013
102 * PXA930 B2 0x69056838 0x8E643013
105 #define __cpu_is_pxa210(id) \
107 unsigned int _id = (id) & 0xf3f0; \
111 #define __cpu_is_pxa250(id) \
113 unsigned int _id = (id) & 0xf3ff; \
117 #define __cpu_is_pxa255(id) \
119 unsigned int _id = (id) & 0xffff; \
123 #define __cpu_is_pxa25x(id) \
125 unsigned int _id = (id) & 0xf300; \
129 #define __cpu_is_pxa210(id) (0)
130 #define __cpu_is_pxa250(id) (0)
131 #define __cpu_is_pxa255(id) (0)
132 #define __cpu_is_pxa25x(id) (0)
136 #define __cpu_is_pxa27x(id) \
138 unsigned int _id = (id) >> 4 & 0xfff; \
142 #define __cpu_is_pxa27x(id) (0)
145 #ifdef CONFIG_CPU_PXA300
146 #define __cpu_is_pxa300(id) \
148 unsigned int _id = (id) >> 4 & 0xfff; \
152 #define __cpu_is_pxa300(id) (0)
155 #ifdef CONFIG_CPU_PXA310
156 #define __cpu_is_pxa310(id) \
158 unsigned int _id = (id) >> 4 & 0xfff; \
162 #define __cpu_is_pxa310(id) (0)
165 #ifdef CONFIG_CPU_PXA320
166 #define __cpu_is_pxa320(id) \
168 unsigned int _id = (id) >> 4 & 0xfff; \
169 _id == 0x603 || _id == 0x682; \
172 #define __cpu_is_pxa320(id) (0)
175 #ifdef CONFIG_CPU_PXA930
176 #define __cpu_is_pxa930(id) \
178 unsigned int _id = (id) >> 4 & 0xfff; \
182 #define __cpu_is_pxa930(id) (0)
185 #define cpu_is_pxa210() \
187 __cpu_is_pxa210(read_cpuid_id()); \
190 #define cpu_is_pxa250() \
192 __cpu_is_pxa250(read_cpuid_id()); \
195 #define cpu_is_pxa255() \
197 __cpu_is_pxa255(read_cpuid_id()); \
200 #define cpu_is_pxa25x() \
202 __cpu_is_pxa25x(read_cpuid_id()); \
205 extern int cpu_is_pxa26x(void);
207 #define cpu_is_pxa27x() \
209 __cpu_is_pxa27x(read_cpuid_id()); \
212 #define cpu_is_pxa300() \
214 __cpu_is_pxa300(read_cpuid_id()); \
217 #define cpu_is_pxa310() \
219 __cpu_is_pxa310(read_cpuid_id()); \
222 #define cpu_is_pxa320() \
224 __cpu_is_pxa320(read_cpuid_id()); \
227 #define cpu_is_pxa930() \
229 unsigned int id = read_cpuid(CPUID_ID); \
230 __cpu_is_pxa930(id); \
234 * CPUID Core Generation Bit
235 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
236 * == 0x3 for pxa300/pxa310/pxa320
238 #define __cpu_is_pxa2xx(id) \
240 unsigned int _id = (id) >> 13 & 0x7; \
244 #define __cpu_is_pxa3xx(id) \
246 unsigned int _id = (id) >> 13 & 0x7; \
250 #define cpu_is_pxa2xx() \
252 __cpu_is_pxa2xx(read_cpuid_id()); \
255 #define cpu_is_pxa3xx() \
257 __cpu_is_pxa3xx(read_cpuid_id()); \
261 * Handy routine to set GPIO alternate functions
263 extern int pxa_gpio_mode( int gpio_mode );
266 * Return GPIO level, nonzero means high, zero is low
268 extern int pxa_gpio_get_value(unsigned gpio);
271 * Set output GPIO level
273 extern void pxa_gpio_set_value(unsigned gpio, int value);
276 * return current memory and LCD clock frequency in units of 10kHz
278 extern unsigned int get_memclk_frequency_10khz(void);
282 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
283 #define PCIBIOS_MIN_IO 0
284 #define PCIBIOS_MIN_MEM 0
285 #define pcibios_assign_all_busses() 1
288 #endif /* _ASM_ARCH_HARDWARE_H */