arch/arm/mach-prima2/irq.c

   1 /*
   2  * interrupt controller support for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <mach/hardware.h>
  13 #include <asm/mach/irq.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/syscore_ops.h>
  18
  19 #define SIRFSOC_INT_RISC_MASK0          0x0018
  20 #define SIRFSOC_INT_RISC_MASK1          0x001C
  21 #define SIRFSOC_INT_RISC_LEVEL0         0x0020
  22 #define SIRFSOC_INT_RISC_LEVEL1         0x0024
  23
  24 void __iomem *sirfsoc_intc_base;
  25
  26 static __init void
  27 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
  28 {
  29         struct irq_chip_generic *gc;
  30         struct irq_chip_type *ct;
  31
  32         gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
  33         ct = gc->chip_types;
  34
  35         ct->chip.irq_mask = irq_gc_mask_clr_bit;
  36         ct->chip.irq_unmask = irq_gc_mask_set_bit;
  37         ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
  38
  39         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
  40 }
  41
  42 static __init void sirfsoc_irq_init(void)
  43 {
  44         sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
  45         sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
  46                         SIRFSOC_INTENAL_IRQ_END + 1 - 32);
  47
  48         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
  49         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
  50
  51         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
  52         writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
  53 }
  54
  55 static struct of_device_id intc_ids[]  = {
  56         { .compatible = "sirf,prima2-intc" },
  57         {},
  58 };
  59
  60 void __init sirfsoc_of_irq_init(void)
  61 {
  62         struct device_node *np;
  63
  64         np = of_find_matching_node(NULL, intc_ids);
  65         if (!np)
  66                 panic("unable to find compatible intc node in dtb\n");
  67
  68         sirfsoc_intc_base = of_iomap(np, 0);
  69         if (!sirfsoc_intc_base)
  70                 panic("unable to map intc cpu registers\n");
  71
  72         irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
  73                 &irq_domain_simple_ops, NULL);
  74
  75         of_node_put(np);
  76
  77         sirfsoc_irq_init();
  78 }
  79
  80 struct sirfsoc_irq_status {
  81         u32 mask0;
  82         u32 mask1;
  83         u32 level0;
  84         u32 level1;
  85 };
  86
  87 static struct sirfsoc_irq_status sirfsoc_irq_st;
  88
  89 static int sirfsoc_irq_suspend(void)
  90 {
  91         sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
  92         sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
  93         sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
  94         sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
  95
  96         return 0;
  97 }
  98
  99 static void sirfsoc_irq_resume(void)
 100 {
 101         writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
 102         writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
 103         writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
 104         writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
 105 }
 106
 107 static struct syscore_ops sirfsoc_irq_syscore_ops = {
 108         .suspend        = sirfsoc_irq_suspend,
 109         .resume         = sirfsoc_irq_resume,
 110 };
 111
 112 static int __init sirfsoc_irq_pm_init(void)
 113 {
 114         register_syscore_ops(&sirfsoc_irq_syscore_ops);
 115         return 0;
 116 }
 117 device_initcall(sirfsoc_irq_pm_init);