arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44
  45 #include <asm/mach/time.h>
  46 #include <asm/smp_twd.h>
  47 #include <asm/sched_clock.h>
  48
  49 #include <asm/arch_timer.h>
  50 #include "omap_hwmod.h"
  51 #include "omap_device.h"
  52 #include <plat/counter-32k.h>
  53 #include <plat/dmtimer.h>
  54 #include "omap-pm.h"
  55
  56 #include "soc.h"
  57 #include "common.h"
  58 #include "powerdomain.h"
  59
  60 /* Parent clocks, eventually these will come from the clock framework */
  61
  62 #define OMAP2_MPU_SOURCE        "sys_ck"
  63 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  64 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  65 #define OMAP2_32K_SOURCE        "func_32k_ck"
  66 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  67 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  68
  69 #define REALTIME_COUNTER_BASE                           0x48243200
  70 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  71 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  72 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  73
  74 /* Clockevent code */
  75
  76 static struct omap_dm_timer clkev;
  77 static struct clock_event_device clockevent_gpt;
  78
  79 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  80 {
  81         struct clock_event_device *evt = &clockevent_gpt;
  82
  83         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  84
  85         evt->event_handler(evt);
  86         return IRQ_HANDLED;
  87 }
  88
  89 static struct irqaction omap2_gp_timer_irq = {
  90         .name           = "gp_timer",
  91         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  92         .handler        = omap2_gp_timer_interrupt,
  93 };
  94
  95 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  96                                          struct clock_event_device *evt)
  97 {
  98         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
  99                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 100
 101         return 0;
 102 }
 103
 104 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 105                                     struct clock_event_device *evt)
 106 {
 107         u32 period;
 108
 109         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 110
 111         switch (mode) {
 112         case CLOCK_EVT_MODE_PERIODIC:
 113                 period = clkev.rate / HZ;
 114                 period -= 1;
 115                 /* Looks like we need to first set the load value separately */
 116                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 117                                       0xffffffff - period, OMAP_TIMER_POSTED);
 118                 __omap_dm_timer_load_start(&clkev,
 119                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 120                                         0xffffffff - period, OMAP_TIMER_POSTED);
 121                 break;
 122         case CLOCK_EVT_MODE_ONESHOT:
 123                 break;
 124         case CLOCK_EVT_MODE_UNUSED:
 125         case CLOCK_EVT_MODE_SHUTDOWN:
 126         case CLOCK_EVT_MODE_RESUME:
 127                 break;
 128         }
 129 }
 130
 131 static struct clock_event_device clockevent_gpt = {
 132         .name           = "gp_timer",
 133         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 134         .shift          = 32,
 135         .rating         = 300,
 136         .set_next_event = omap2_gp_timer_set_next_event,
 137         .set_mode       = omap2_gp_timer_set_mode,
 138 };
 139
 140 static struct property device_disabled = {
 141         .name = "status",
 142         .length = sizeof("disabled"),
 143         .value = "disabled",
 144 };
 145
 146 static struct of_device_id omap_timer_match[] __initdata = {
 147         { .compatible = "ti,omap2-timer", },
 148         { }
 149 };
 150
 151 /**
 152  * omap_get_timer_dt - get a timer using device-tree
 153  * @match       - device-tree match structure for matching a device type
 154  * @property    - optional timer property to match
 155  *
 156  * Helper function to get a timer during early boot using device-tree for use
 157  * as kernel system timer. Optionally, the property argument can be used to
 158  * select a timer with a specific property. Once a timer is found then mark
 159  * the timer node in device-tree as disabled, to prevent the kernel from
 160  * registering this timer as a platform device and so no one else can use it.
 161  */
 162 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
 163                                                      const char *property)
 164 {
 165         struct device_node *np;
 166
 167         for_each_matching_node(np, match) {
 168                 if (!of_device_is_available(np))
 169                         continue;
 170
 171                 if (property && !of_get_property(np, property, NULL))
 172                         continue;
 173
 174                 of_add_property(np, &device_disabled);
 175                 return np;
 176         }
 177
 178         return NULL;
 179 }
 180
 181 /**
 182  * omap_dmtimer_init - initialisation function when device tree is used
 183  *
 184  * For secure OMAP3 devices, timers with device type "timer-secure" cannot
 185  * be used by the kernel as they are reserved. Therefore, to prevent the
 186  * kernel registering these devices remove them dynamically from the device
 187  * tree on boot.
 188  */
 189 static void __init omap_dmtimer_init(void)
 190 {
 191         struct device_node *np;
 192
 193         if (!cpu_is_omap34xx())
 194                 return;
 195
 196         /* If we are a secure device, remove any secure timer nodes */
 197         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 198                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 199                 if (np)
 200                         of_node_put(np);
 201         }
 202 }
 203
 204 /**
 205  * omap_dm_timer_get_errata - get errata flags for a timer
 206  *
 207  * Get the timer errata flags that are specific to the OMAP device being used.
 208  */
 209 static u32 __init omap_dm_timer_get_errata(void)
 210 {
 211         if (cpu_is_omap24xx())
 212                 return 0;
 213
 214         return OMAP_TIMER_ERRATA_I103_I767;
 215 }
 216
 217 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 218                                                 int gptimer_id,
 219                                                 const char *fck_source,
 220                                                 const char *property,
 221                                                 int posted)
 222 {
 223         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 224         const char *oh_name;
 225         struct device_node *np;
 226         struct omap_hwmod *oh;
 227         struct resource irq, mem;
 228         int r = 0;
 229
 230         if (of_have_populated_dt()) {
 231                 np = omap_get_timer_dt(omap_timer_match, NULL);
 232                 if (!np)
 233                         return -ENODEV;
 234
 235                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 236                 if (!oh_name)
 237                         return -ENODEV;
 238
 239                 timer->irq = irq_of_parse_and_map(np, 0);
 240                 if (!timer->irq)
 241                         return -ENXIO;
 242
 243                 timer->io_base = of_iomap(np, 0);
 244
 245                 of_node_put(np);
 246         } else {
 247                 if (omap_dm_timer_reserve_systimer(gptimer_id))
 248                         return -ENODEV;
 249
 250                 sprintf(name, "timer%d", gptimer_id);
 251                 oh_name = name;
 252         }
 253
 254         oh = omap_hwmod_lookup(oh_name);
 255         if (!oh)
 256                 return -ENODEV;
 257
 258         if (!of_have_populated_dt()) {
 259                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
 260                                                    &irq);
 261                 if (r)
 262                         return -ENXIO;
 263                 timer->irq = irq.start;
 264
 265                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
 266                                                    &mem);
 267                 if (r)
 268                         return -ENXIO;
 269
 270                 /* Static mapping, never released */
 271                 timer->io_base = ioremap(mem.start, mem.end - mem.start);
 272         }
 273
 274         if (!timer->io_base)
 275                 return -ENXIO;
 276
 277         /* After the dmtimer is using hwmod these clocks won't be needed */
 278         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 279         if (IS_ERR(timer->fclk))
 280                 return -ENODEV;
 281
 282         /* FIXME: Need to remove hard-coded test on timer ID */
 283         if (gptimer_id != 12) {
 284                 struct clk *src;
 285
 286                 src = clk_get(NULL, fck_source);
 287                 if (IS_ERR(src)) {
 288                         r = -EINVAL;
 289                 } else {
 290                         r = clk_set_parent(timer->fclk, src);
 291                         if (IS_ERR_VALUE(r))
 292                                 pr_warn("%s: %s cannot set source\n",
 293                                         __func__, oh->name);
 294                         clk_put(src);
 295                 }
 296         }
 297
 298         omap_hwmod_setup_one(oh_name);
 299         omap_hwmod_enable(oh);
 300         __omap_dm_timer_init_regs(timer);
 301
 302         if (posted)
 303                 __omap_dm_timer_enable_posted(timer);
 304
 305         /* Check that the intended posted configuration matches the actual */
 306         if (posted != timer->posted)
 307                 return -EINVAL;
 308
 309         timer->rate = clk_get_rate(timer->fclk);
 310         timer->reserved = 1;
 311
 312         return r;
 313 }
 314
 315 static void __init omap2_gp_clockevent_init(int gptimer_id,
 316                                                 const char *fck_source,
 317                                                 const char *property)
 318 {
 319         int res;
 320
 321         clkev.errata = omap_dm_timer_get_errata();
 322
 323         /*
 324          * For clock-event timers we never read the timer counter and
 325          * so we are not impacted by errata i103 and i767. Therefore,
 326          * we can safely ignore this errata for clock-event timers.
 327          */
 328         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 329
 330         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
 331                                      OMAP_TIMER_POSTED);
 332         BUG_ON(res);
 333
 334         omap2_gp_timer_irq.dev_id = &clkev;
 335         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 336
 337         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 338
 339         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 340                                      clockevent_gpt.shift);
 341         clockevent_gpt.max_delta_ns =
 342                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 343         clockevent_gpt.min_delta_ns =
 344                 clockevent_delta2ns(3, &clockevent_gpt);
 345                 /* Timer internal resynch latency. */
 346
 347         clockevent_gpt.cpumask = cpu_possible_mask;
 348         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 349         clockevents_register_device(&clockevent_gpt);
 350
 351         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 352                 gptimer_id, clkev.rate);
 353 }
 354
 355 /* Clocksource code */
 356 static struct omap_dm_timer clksrc;
 357 static bool use_gptimer_clksrc;
 358
 359 /*
 360  * clocksource
 361  */
 362 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 363 {
 364         return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
 365                                                      OMAP_TIMER_NONPOSTED);
 366 }
 367
 368 static struct clocksource clocksource_gpt = {
 369         .name           = "gp_timer",
 370         .rating         = 300,
 371         .read           = clocksource_read_cycles,
 372         .mask           = CLOCKSOURCE_MASK(32),
 373         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 374 };
 375
 376 static u32 notrace dmtimer_read_sched_clock(void)
 377 {
 378         if (clksrc.reserved)
 379                 return __omap_dm_timer_read_counter(&clksrc,
 380                                                     OMAP_TIMER_NONPOSTED);
 381
 382         return 0;
 383 }
 384
 385 static struct of_device_id omap_counter_match[] __initdata = {
 386         { .compatible = "ti,omap-counter32k", },
 387         { }
 388 };
 389
 390 /* Setup free-running counter for clocksource */
 391 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 392 {
 393         int ret;
 394         struct device_node *np = NULL;
 395         struct omap_hwmod *oh;
 396         void __iomem *vbase;
 397         const char *oh_name = "counter_32k";
 398
 399         /*
 400          * If device-tree is present, then search the DT blob
 401          * to see if the 32kHz counter is supported.
 402          */
 403         if (of_have_populated_dt()) {
 404                 np = omap_get_timer_dt(omap_counter_match, NULL);
 405                 if (!np)
 406                         return -ENODEV;
 407
 408                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 409                 if (!oh_name)
 410                         return -ENODEV;
 411         }
 412
 413         /*
 414          * First check hwmod data is available for sync32k counter
 415          */
 416         oh = omap_hwmod_lookup(oh_name);
 417         if (!oh || oh->slaves_cnt == 0)
 418                 return -ENODEV;
 419
 420         omap_hwmod_setup_one(oh_name);
 421
 422         if (np) {
 423                 vbase = of_iomap(np, 0);
 424                 of_node_put(np);
 425         } else {
 426                 vbase = omap_hwmod_get_mpu_rt_va(oh);
 427         }
 428
 429         if (!vbase) {
 430                 pr_warn("%s: failed to get counter_32k resource\n", __func__);
 431                 return -ENXIO;
 432         }
 433
 434         ret = omap_hwmod_enable(oh);
 435         if (ret) {
 436                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 437                                                         __func__, ret);
 438                 return ret;
 439         }
 440
 441         ret = omap_init_clocksource_32k(vbase);
 442         if (ret) {
 443                 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 444                                                         __func__, ret);
 445                 omap_hwmod_idle(oh);
 446         }
 447
 448         return ret;
 449 }
 450
 451 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 452                                                 const char *fck_source)
 453 {
 454         int res;
 455
 456         clksrc.errata = omap_dm_timer_get_errata();
 457
 458         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
 459                                      OMAP_TIMER_NONPOSTED);
 460         BUG_ON(res);
 461
 462         __omap_dm_timer_load_start(&clksrc,
 463                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 464                                    OMAP_TIMER_NONPOSTED);
 465         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 466
 467         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 468                 pr_err("Could not register clocksource %s\n",
 469                         clocksource_gpt.name);
 470         else
 471                 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 472                         gptimer_id, clksrc.rate);
 473 }
 474
 475 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 476 /*
 477  * The realtime counter also called master counter, is a free-running
 478  * counter, which is related to real time. It produces the count used
 479  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 480  * at a rate of 6.144 MHz. Because the device operates on different clocks
 481  * in different power modes, the master counter shifts operation between
 482  * clocks, adjusting the increment per clock in hardware accordingly to
 483  * maintain a constant count rate.
 484  */
 485 static void __init realtime_counter_init(void)
 486 {
 487         void __iomem *base;
 488         static struct clk *sys_clk;
 489         unsigned long rate;
 490         unsigned int reg, num, den;
 491
 492         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 493         if (!base) {
 494                 pr_err("%s: ioremap failed\n", __func__);
 495                 return;
 496         }
 497         sys_clk = clk_get(NULL, "sys_clkin_ck");
 498         if (IS_ERR(sys_clk)) {
 499                 pr_err("%s: failed to get system clock handle\n", __func__);
 500                 iounmap(base);
 501                 return;
 502         }
 503
 504         rate = clk_get_rate(sys_clk);
 505         /* Numerator/denumerator values refer TRM Realtime Counter section */
 506         switch (rate) {
 507         case 1200000:
 508                 num = 64;
 509                 den = 125;
 510                 break;
 511         case 1300000:
 512                 num = 768;
 513                 den = 1625;
 514                 break;
 515         case 19200000:
 516                 num = 8;
 517                 den = 25;
 518                 break;
 519         case 2600000:
 520                 num = 384;
 521                 den = 1625;
 522                 break;
 523         case 2700000:
 524                 num = 256;
 525                 den = 1125;
 526                 break;
 527         case 38400000:
 528         default:
 529                 /* Program it for 38.4 MHz */
 530                 num = 4;
 531                 den = 25;
 532                 break;
 533         }
 534
 535         /* Program numerator and denumerator registers */
 536         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 537                         NUMERATOR_DENUMERATOR_MASK;
 538         reg |= num;
 539         __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 540
 541         reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
 542                         NUMERATOR_DENUMERATOR_MASK;
 543         reg |= den;
 544         __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 545
 546         iounmap(base);
 547 }
 548 #else
 549 static inline void __init realtime_counter_init(void)
 550 {}
 551 #endif
 552
 553 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
 554                                clksrc_nr, clksrc_src)                   \
 555 static void __init omap##name##_gptimer_timer_init(void)                \
 556 {                                                                       \
 557         omap_dmtimer_init();                                            \
 558         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 559         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
 560 }
 561
 562 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
 563                                 clksrc_nr, clksrc_src)                  \
 564 static void __init omap##name##_sync32k_timer_init(void)                \
 565 {                                                                       \
 566         omap_dmtimer_init();                                            \
 567         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
 568         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
 569         if (use_gptimer_clksrc)                                         \
 570                 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
 571         else                                                            \
 572                 omap2_sync32k_clocksource_init();                       \
 573 }
 574
 575 #define OMAP_SYS_TIMER(name, clksrc)                                    \
 576 struct sys_timer omap##name##_timer = {                                 \
 577         .init   = omap##name##_##clksrc##_timer_init,                   \
 578 };
 579
 580 #ifdef CONFIG_ARCH_OMAP2
 581 OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
 582                         2, OMAP2_MPU_SOURCE);
 583 OMAP_SYS_TIMER(2, sync32k);
 584 #endif /* CONFIG_ARCH_OMAP2 */
 585
 586 #ifdef CONFIG_ARCH_OMAP3
 587 OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
 588                         2, OMAP3_MPU_SOURCE);
 589 OMAP_SYS_TIMER(3, sync32k);
 590 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
 591                         2, OMAP3_MPU_SOURCE);
 592 OMAP_SYS_TIMER(3_secure, sync32k);
 593 OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
 594                        2, OMAP3_MPU_SOURCE);
 595 OMAP_SYS_TIMER(3_gp, gptimer);
 596 #endif /* CONFIG_ARCH_OMAP3 */
 597
 598 #ifdef CONFIG_SOC_AM33XX
 599 OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
 600                        2, OMAP4_MPU_SOURCE);
 601 OMAP_SYS_TIMER(3_am33xx, gptimer);
 602 #endif /* CONFIG_SOC_AM33XX */
 603
 604 #ifdef CONFIG_ARCH_OMAP4
 605 OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
 606                         2, OMAP4_MPU_SOURCE);
 607 #ifdef CONFIG_LOCAL_TIMERS
 608 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 609 static void __init omap4_local_timer_init(void)
 610 {
 611         omap4_sync32k_timer_init();
 612         /* Local timers are not supprted on OMAP4430 ES1.0 */
 613         if (omap_rev() != OMAP4430_REV_ES1_0) {
 614                 int err;
 615
 616                 if (of_have_populated_dt()) {
 617                         twd_local_timer_of_register();
 618                         return;
 619                 }
 620
 621                 err = twd_local_timer_register(&twd_local_timer);
 622                 if (err)
 623                         pr_err("twd_local_timer_register failed %d\n", err);
 624         }
 625 }
 626 #else /* CONFIG_LOCAL_TIMERS */
 627 static void __init omap4_local_timer_init(void)
 628 {
 629         omap4_sync32k_timer_init();
 630 }
 631 #endif /* CONFIG_LOCAL_TIMERS */
 632 OMAP_SYS_TIMER(4, local);
 633 #endif /* CONFIG_ARCH_OMAP4 */
 634
 635 #ifdef CONFIG_SOC_OMAP5
 636 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
 637                         2, OMAP4_MPU_SOURCE);
 638 static void __init omap5_realtime_timer_init(void)
 639 {
 640         int err;
 641
 642         omap5_sync32k_timer_init();
 643         realtime_counter_init();
 644
 645         err = arch_timer_of_register();
 646         if (err)
 647                 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
 648 }
 649 OMAP_SYS_TIMER(5, realtime);
 650 #endif /* CONFIG_SOC_OMAP5 */
 651
 652 /**
 653  * omap_timer_init - build and register timer device with an
 654  * associated timer hwmod
 655  * @oh: timer hwmod pointer to be used to build timer device
 656  * @user:       parameter that can be passed from calling hwmod API
 657  *
 658  * Called by omap_hwmod_for_each_by_class to register each of the timer
 659  * devices present in the system. The number of timer devices is known
 660  * by parsing through the hwmod database for a given class name. At the
 661  * end of function call memory is allocated for timer device and it is
 662  * registered to the framework ready to be proved by the driver.
 663  */
 664 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 665 {
 666         int id;
 667         int ret = 0;
 668         char *name = "omap_timer";
 669         struct dmtimer_platform_data *pdata;
 670         struct platform_device *pdev;
 671         struct omap_timer_capability_dev_attr *timer_dev_attr;
 672
 673         pr_debug("%s: %s\n", __func__, oh->name);
 674
 675         /* on secure device, do not register secure timer */
 676         timer_dev_attr = oh->dev_attr;
 677         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 678                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 679                         return ret;
 680
 681         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 682         if (!pdata) {
 683                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 684                 return -ENOMEM;
 685         }
 686
 687         /*
 688          * Extract the IDs from name field in hwmod database
 689          * and use the same for constructing ids' for the
 690          * timer devices. In a way, we are avoiding usage of
 691          * static variable witin the function to do the same.
 692          * CAUTION: We have to be careful and make sure the
 693          * name in hwmod database does not change in which case
 694          * we might either make corresponding change here or
 695          * switch back static variable mechanism.
 696          */
 697         sscanf(oh->name, "timer%2d", &id);
 698
 699         if (timer_dev_attr)
 700                 pdata->timer_capability = timer_dev_attr->timer_capability;
 701
 702         pdata->timer_errata = omap_dm_timer_get_errata();
 703         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 704
 705         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 706                                  NULL, 0, 0);
 707
 708         if (IS_ERR(pdev)) {
 709                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 710                         __func__, name, oh->name);
 711                 ret = -EINVAL;
 712         }
 713
 714         kfree(pdata);
 715
 716         return ret;
 717 }
 718
 719 /**
 720  * omap2_dm_timer_init - top level regular device initialization
 721  *
 722  * Uses dedicated hwmod api to parse through hwmod database for
 723  * given class name and then build and register the timer device.
 724  */
 725 static int __init omap2_dm_timer_init(void)
 726 {
 727         int ret;
 728
 729         /* If dtb is there, the devices will be created dynamically */
 730         if (of_have_populated_dt())
 731                 return -ENODEV;
 732
 733         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 734         if (unlikely(ret)) {
 735                 pr_err("%s: device registration failed.\n", __func__);
 736                 return -EINVAL;
 737         }
 738
 739         return 0;
 740 }
 741 arch_initcall(omap2_dm_timer_init);
 742
 743 /**
 744  * omap2_override_clocksource - clocksource override with user configuration
 745  *
 746  * Allows user to override default clocksource, using kernel parameter
 747  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 748  *
 749  * Note that, here we are using same standard kernel parameter "clocksource=",
 750  * and not introducing any OMAP specific interface.
 751  */
 752 static int __init omap2_override_clocksource(char *str)
 753 {
 754         if (!str)
 755                 return 0;
 756         /*
 757          * For OMAP architecture, we only have two options
 758          *    - sync_32k (default)
 759          *    - gp_timer (sys_clk based)
 760          */
 761         if (!strcmp(str, "gp_timer"))
 762                 use_gptimer_clksrc = true;
 763
 764         return 0;
 765 }
 766 early_param("clocksource", omap2_override_clocksource);