arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28
  29 #include <plat/sram.h>
  30 #include <plat/clockdomain.h>
  31 #include <plat/powerdomain.h>
  32 #include <plat/control.h>
  33 #include <plat/serial.h>
  34 #include <plat/sdrc.h>
  35 #include <plat/prcm.h>
  36 #include <plat/gpmc.h>
  37
  38 #include <asm/tlbflush.h>
  39
  40 #include "cm.h"
  41 #include "cm-regbits-34xx.h"
  42 #include "prm-regbits-34xx.h"
  43
  44 #include "prm.h"
  45 #include "pm.h"
  46
  47 /* Scratchpad offsets */
  48 #define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
  49 #define OMAP343X_TABLE_VALUE_OFFSET        0x30
  50 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
  51
  52 struct power_state {
  53         struct powerdomain *pwrdm;
  54         u32 next_state;
  55 #ifdef CONFIG_SUSPEND
  56         u32 saved_state;
  57 #endif
  58         struct list_head node;
  59 };
  60
  61 static LIST_HEAD(pwrst_list);
  62
  63 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  64
  65 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  66 static struct powerdomain *core_pwrdm, *per_pwrdm;
  67
  68 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
  69
  70 static inline void omap3_per_save_context(void)
  71 {
  72         omap_gpio_save_context();
  73 }
  74
  75 static inline void omap3_per_restore_context(void)
  76 {
  77         omap_gpio_restore_context();
  78 }
  79
  80 static void omap3_core_save_context(void)
  81 {
  82         u32 control_padconf_off;
  83
  84         /* Save the padconf registers */
  85         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
  86         control_padconf_off |= START_PADCONF_SAVE;
  87         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
  88         /* wait for the save to complete */
  89         while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
  90                         & PADCONF_SAVE_DONE)
  91                 ;
  92         /* Save the Interrupt controller context */
  93         omap_intc_save_context();
  94         /* Save the GPMC context */
  95         omap3_gpmc_save_context();
  96         /* Save the system control module context, padconf already save above*/
  97         omap3_control_save_context();
  98 }
  99
 100 static void omap3_core_restore_context(void)
 101 {
 102         /* Restore the control module context, padconf restored by h/w */
 103         omap3_control_restore_context();
 104         /* Restore the GPMC context */
 105         omap3_gpmc_restore_context();
 106         /* Restore the interrupt controller context */
 107         omap_intc_restore_context();
 108 }
 109
 110 /*
 111  * PRCM Interrupt Handler Helper Function
 112  *
 113  * The purpose of this function is to clear any wake-up events latched
 114  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 115  * may occur whilst attempting to clear a PM_WKST_x register and thus
 116  * set another bit in this register. A while loop is used to ensure
 117  * that any peripheral wake-up events occurring while attempting to
 118  * clear the PM_WKST_x are detected and cleared.
 119  */
 120 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 121 {
 122         u32 wkst, fclk, iclk, clken;
 123         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 124         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 125         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 126         u16 grpsel_off = (regs == 3) ?
 127                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 128         int c = 0;
 129
 130         wkst = prm_read_mod_reg(module, wkst_off);
 131         wkst &= prm_read_mod_reg(module, grpsel_off);
 132         if (wkst) {
 133                 iclk = cm_read_mod_reg(module, iclk_off);
 134                 fclk = cm_read_mod_reg(module, fclk_off);
 135                 while (wkst) {
 136                         clken = wkst;
 137                         cm_set_mod_reg_bits(clken, module, iclk_off);
 138                         /*
 139                          * For USBHOST, we don't know whether HOST1 or
 140                          * HOST2 woke us up, so enable both f-clocks
 141                          */
 142                         if (module == OMAP3430ES2_USBHOST_MOD)
 143                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 144                         cm_set_mod_reg_bits(clken, module, fclk_off);
 145                         prm_write_mod_reg(wkst, module, wkst_off);
 146                         wkst = prm_read_mod_reg(module, wkst_off);
 147                         c++;
 148                 }
 149                 cm_write_mod_reg(iclk, module, iclk_off);
 150                 cm_write_mod_reg(fclk, module, fclk_off);
 151         }
 152
 153         return c;
 154 }
 155
 156 static int _prcm_int_handle_wakeup(void)
 157 {
 158         int c;
 159
 160         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 161         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 162         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 163         if (omap_rev() > OMAP3430_REV_ES1_0) {
 164                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 165                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 166         }
 167
 168         return c;
 169 }
 170
 171 /*
 172  * PRCM Interrupt Handler
 173  *
 174  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 175  * interrupts from the PRCM for the MPU. These bits must be cleared in
 176  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 177  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 178  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 179  * register indicates that a wake-up event is pending for the MPU and
 180  * this bit can only be cleared if the all the wake-up events latched
 181  * in the various PM_WKST_x registers have been cleared. The interrupt
 182  * handler is implemented using a do-while loop so that if a wake-up
 183  * event occurred during the processing of the prcm interrupt handler
 184  * (setting a bit in the corresponding PM_WKST_x register and thus
 185  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 186  * this would be handled.
 187  */
 188 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 189 {
 190         u32 irqstatus_mpu;
 191         int c = 0;
 192
 193         do {
 194                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 195                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 196
 197                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 198                         c = _prcm_int_handle_wakeup();
 199
 200                         /*
 201                          * Is the MPU PRCM interrupt handler racing with the
 202                          * IVA2 PRCM interrupt handler ?
 203                          */
 204                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 205                              "but no wakeup sources are marked\n");
 206                 } else {
 207                         /* XXX we need to expand our PRCM interrupt handler */
 208                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 209                              "no code to handle it (%08x)\n", irqstatus_mpu);
 210                 }
 211
 212                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 213                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 214
 215         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 216
 217         return IRQ_HANDLED;
 218 }
 219
 220 static void restore_control_register(u32 val)
 221 {
 222         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 223 }
 224
 225 /* Function to restore the table entry that was modified for enabling MMU */
 226 static void restore_table_entry(void)
 227 {
 228         u32 *scratchpad_address;
 229         u32 previous_value, control_reg_value;
 230         u32 *address;
 231
 232         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 233
 234         /* Get address of entry that was modified */
 235         address = (u32 *)__raw_readl(scratchpad_address +
 236                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 237         /* Get the previous value which needs to be restored */
 238         previous_value = __raw_readl(scratchpad_address +
 239                                      OMAP343X_TABLE_VALUE_OFFSET);
 240         address = __va(address);
 241         *address = previous_value;
 242         flush_tlb_all();
 243         control_reg_value = __raw_readl(scratchpad_address
 244                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 245         /* This will enable caches and prediction */
 246         restore_control_register(control_reg_value);
 247 }
 248
 249 static void omap_sram_idle(void)
 250 {
 251         /* Variable to tell what needs to be saved and restored
 252          * in omap_sram_idle*/
 253         /* save_state = 0 => Nothing to save and restored */
 254         /* save_state = 1 => Only L1 and logic lost */
 255         /* save_state = 2 => Only L2 lost */
 256         /* save_state = 3 => L1, L2 and logic lost */
 257         int save_state = 0;
 258         int mpu_next_state = PWRDM_POWER_ON;
 259         int per_next_state = PWRDM_POWER_ON;
 260         int core_next_state = PWRDM_POWER_ON;
 261         int core_prev_state, per_prev_state;
 262
 263         if (!_omap_sram_idle)
 264                 return;
 265
 266         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 267         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 268         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 269         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 270
 271         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 272         switch (mpu_next_state) {
 273         case PWRDM_POWER_ON:
 274         case PWRDM_POWER_RET:
 275                 /* No need to save context */
 276                 save_state = 0;
 277                 break;
 278         case PWRDM_POWER_OFF:
 279                 save_state = 3;
 280                 break;
 281         default:
 282                 /* Invalid state */
 283                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 284                 return;
 285         }
 286         pwrdm_pre_transition();
 287
 288         /* NEON control */
 289         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 290                 set_pwrdm_state(neon_pwrdm, mpu_next_state);
 291
 292         /* CORE & PER */
 293         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 294         if (core_next_state < PWRDM_POWER_ON) {
 295                 omap2_gpio_prepare_for_retention();
 296                 omap_uart_prepare_idle(0);
 297                 omap_uart_prepare_idle(1);
 298                 /* PER changes only with core */
 299                 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 300                 if (per_next_state < PWRDM_POWER_ON) {
 301                         omap_uart_prepare_idle(2);
 302                         if (per_next_state == PWRDM_POWER_OFF)
 303                                 omap3_per_save_context();
 304                 }
 305                 if (core_next_state == PWRDM_POWER_OFF) {
 306                         omap3_core_save_context();
 307                         omap3_prcm_save_context();
 308                 }
 309                 /* Enable IO-PAD wakeup */
 310                 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 311         }
 312
 313         /*
 314          * omap3_arm_context is the location where ARM registers
 315          * get saved. The restore path then reads from this
 316          * location and restores them back.
 317          */
 318         _omap_sram_idle(omap3_arm_context, save_state);
 319         cpu_init();
 320
 321         /* Restore table entry modified during MMU restoration */
 322         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 323                 restore_table_entry();
 324
 325         if (core_next_state < PWRDM_POWER_ON) {
 326                 if (per_next_state < PWRDM_POWER_ON)
 327                         omap_uart_resume_idle(2);
 328                 omap_uart_resume_idle(1);
 329                 omap_uart_resume_idle(0);
 330
 331                 /* Disable IO-PAD wakeup */
 332                 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 333                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 334                 if (core_prev_state == PWRDM_POWER_OFF) {
 335                         omap3_core_restore_context();
 336                         omap3_prcm_restore_context();
 337                         omap3_sram_restore_context();
 338                 }
 339                 if (per_next_state < PWRDM_POWER_ON) {
 340                         per_prev_state =
 341                                 pwrdm_read_prev_pwrst(per_pwrdm);
 342                         if (per_prev_state == PWRDM_POWER_OFF)
 343                                 omap3_per_restore_context();
 344                 }
 345                 omap2_gpio_resume_after_retention();
 346         }
 347
 348         pwrdm_post_transition();
 349
 350 }
 351
 352 /*
 353  * Check if functional clocks are enabled before entering
 354  * sleep. This function could be behind CONFIG_PM_DEBUG
 355  * when all drivers are configuring their sysconfig registers
 356  * properly and using their clocks properly.
 357  */
 358 static int omap3_fclks_active(void)
 359 {
 360         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 361                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 362
 363         fck_core1 = cm_read_mod_reg(CORE_MOD,
 364                                     CM_FCLKEN1);
 365         if (omap_rev() > OMAP3430_REV_ES1_0) {
 366                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 367                                             OMAP3430ES2_CM_FCLKEN3);
 368                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 369                                           CM_FCLKEN);
 370                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 371                                               CM_FCLKEN);
 372         } else
 373                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 374                                           OMAP3430ES2_CM_FCLKEN3);
 375         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 376                                   CM_FCLKEN);
 377         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 378                                   CM_FCLKEN);
 379         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 380                                   CM_FCLKEN);
 381
 382         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 383         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 384         fck_per &= ~OMAP3430_EN_UART3;
 385
 386         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 387             fck_cam | fck_per | fck_usbhost)
 388                 return 1;
 389         return 0;
 390 }
 391
 392 static int omap3_can_sleep(void)
 393 {
 394         if (!omap_uart_can_sleep())
 395                 return 0;
 396         if (omap3_fclks_active())
 397                 return 0;
 398         return 1;
 399 }
 400
 401 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 402  * RET are supported. Function is assuming that clkdm doesn't have
 403  * hw_sup mode enabled. */
 404 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 405 {
 406         u32 cur_state;
 407         int sleep_switch = 0;
 408         int ret = 0;
 409
 410         if (pwrdm == NULL || IS_ERR(pwrdm))
 411                 return -EINVAL;
 412
 413         while (!(pwrdm->pwrsts & (1 << state))) {
 414                 if (state == PWRDM_POWER_OFF)
 415                         return ret;
 416                 state--;
 417         }
 418
 419         cur_state = pwrdm_read_next_pwrst(pwrdm);
 420         if (cur_state == state)
 421                 return ret;
 422
 423         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 424                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 425                 sleep_switch = 1;
 426                 pwrdm_wait_transition(pwrdm);
 427         }
 428
 429         ret = pwrdm_set_next_pwrst(pwrdm, state);
 430         if (ret) {
 431                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 432                        pwrdm->name);
 433                 goto err;
 434         }
 435
 436         if (sleep_switch) {
 437                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 438                 pwrdm_wait_transition(pwrdm);
 439                 pwrdm_state_switch(pwrdm);
 440         }
 441
 442 err:
 443         return ret;
 444 }
 445
 446 static void omap3_pm_idle(void)
 447 {
 448         local_irq_disable();
 449         local_fiq_disable();
 450
 451         if (!omap3_can_sleep())
 452                 goto out;
 453
 454         if (omap_irq_pending())
 455                 goto out;
 456
 457         omap_sram_idle();
 458
 459 out:
 460         local_fiq_enable();
 461         local_irq_enable();
 462 }
 463
 464 #ifdef CONFIG_SUSPEND
 465 static suspend_state_t suspend_state;
 466
 467 static int omap3_pm_prepare(void)
 468 {
 469         disable_hlt();
 470         return 0;
 471 }
 472
 473 static int omap3_pm_suspend(void)
 474 {
 475         struct power_state *pwrst;
 476         int state, ret = 0;
 477
 478         /* Read current next_pwrsts */
 479         list_for_each_entry(pwrst, &pwrst_list, node)
 480                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 481         /* Set ones wanted by suspend */
 482         list_for_each_entry(pwrst, &pwrst_list, node) {
 483                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 484                         goto restore;
 485                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 486                         goto restore;
 487         }
 488
 489         omap_uart_prepare_suspend();
 490         omap_sram_idle();
 491
 492 restore:
 493         /* Restore next_pwrsts */
 494         list_for_each_entry(pwrst, &pwrst_list, node) {
 495                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 496                 if (state > pwrst->next_state) {
 497                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 498                                "target state %d\n",
 499                                pwrst->pwrdm->name, pwrst->next_state);
 500                         ret = -1;
 501                 }
 502                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 503         }
 504         if (ret)
 505                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 506         else
 507                 printk(KERN_INFO "Successfully put all powerdomains "
 508                        "to target state\n");
 509
 510         return ret;
 511 }
 512
 513 static int omap3_pm_enter(suspend_state_t unused)
 514 {
 515         int ret = 0;
 516
 517         switch (suspend_state) {
 518         case PM_SUSPEND_STANDBY:
 519         case PM_SUSPEND_MEM:
 520                 ret = omap3_pm_suspend();
 521                 break;
 522         default:
 523                 ret = -EINVAL;
 524         }
 525
 526         return ret;
 527 }
 528
 529 static void omap3_pm_finish(void)
 530 {
 531         enable_hlt();
 532 }
 533
 534 /* Hooks to enable / disable UART interrupts during suspend */
 535 static int omap3_pm_begin(suspend_state_t state)
 536 {
 537         suspend_state = state;
 538         omap_uart_enable_irqs(0);
 539         return 0;
 540 }
 541
 542 static void omap3_pm_end(void)
 543 {
 544         suspend_state = PM_SUSPEND_ON;
 545         omap_uart_enable_irqs(1);
 546         return;
 547 }
 548
 549 static struct platform_suspend_ops omap_pm_ops = {
 550         .begin          = omap3_pm_begin,
 551         .end            = omap3_pm_end,
 552         .prepare        = omap3_pm_prepare,
 553         .enter          = omap3_pm_enter,
 554         .finish         = omap3_pm_finish,
 555         .valid          = suspend_valid_only_mem,
 556 };
 557 #endif /* CONFIG_SUSPEND */
 558
 559
 560 /**
 561  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 562  *                   retention
 563  *
 564  * In cases where IVA2 is activated by bootcode, it may prevent
 565  * full-chip retention or off-mode because it is not idle.  This
 566  * function forces the IVA2 into idle state so it can go
 567  * into retention/off and thus allow full-chip retention/off.
 568  *
 569  **/
 570 static void __init omap3_iva_idle(void)
 571 {
 572         /* ensure IVA2 clock is disabled */
 573         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 574
 575         /* if no clock activity, nothing else to do */
 576         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 577               OMAP3430_CLKACTIVITY_IVA2_MASK))
 578                 return;
 579
 580         /* Reset IVA2 */
 581         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 582                           OMAP3430_RST2_IVA2 |
 583                           OMAP3430_RST3_IVA2,
 584                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 585
 586         /* Enable IVA2 clock */
 587         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 588                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 589
 590         /* Set IVA2 boot mode to 'idle' */
 591         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 592                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 593
 594         /* Un-reset IVA2 */
 595         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 596
 597         /* Disable IVA2 clock */
 598         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 599
 600         /* Reset IVA2 */
 601         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 602                           OMAP3430_RST2_IVA2 |
 603                           OMAP3430_RST3_IVA2,
 604                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 605 }
 606
 607 static void __init omap3_d2d_idle(void)
 608 {
 609         u16 mask, padconf;
 610
 611         /* In a stand alone OMAP3430 where there is not a stacked
 612          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 613          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 614          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 615         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 616         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 617         padconf |= mask;
 618         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 619
 620         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 621         padconf |= mask;
 622         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 623
 624         /* reset modem */
 625         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 626                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 627                           CORE_MOD, RM_RSTCTRL);
 628         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 629 }
 630
 631 static void __init prcm_setup_regs(void)
 632 {
 633         /* XXX Reset all wkdeps. This should be done when initializing
 634          * powerdomains */
 635         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 636         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 637         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 638         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 639         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 640         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 641         if (omap_rev() > OMAP3430_REV_ES1_0) {
 642                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 643                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 644         } else
 645                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 646
 647         /*
 648          * Enable interface clock autoidle for all modules.
 649          * Note that in the long run this should be done by clockfw
 650          */
 651         cm_write_mod_reg(
 652                 OMAP3430_AUTO_MODEM |
 653                 OMAP3430ES2_AUTO_MMC3 |
 654                 OMAP3430ES2_AUTO_ICR |
 655                 OMAP3430_AUTO_AES2 |
 656                 OMAP3430_AUTO_SHA12 |
 657                 OMAP3430_AUTO_DES2 |
 658                 OMAP3430_AUTO_MMC2 |
 659                 OMAP3430_AUTO_MMC1 |
 660                 OMAP3430_AUTO_MSPRO |
 661                 OMAP3430_AUTO_HDQ |
 662                 OMAP3430_AUTO_MCSPI4 |
 663                 OMAP3430_AUTO_MCSPI3 |
 664                 OMAP3430_AUTO_MCSPI2 |
 665                 OMAP3430_AUTO_MCSPI1 |
 666                 OMAP3430_AUTO_I2C3 |
 667                 OMAP3430_AUTO_I2C2 |
 668                 OMAP3430_AUTO_I2C1 |
 669                 OMAP3430_AUTO_UART2 |
 670                 OMAP3430_AUTO_UART1 |
 671                 OMAP3430_AUTO_GPT11 |
 672                 OMAP3430_AUTO_GPT10 |
 673                 OMAP3430_AUTO_MCBSP5 |
 674                 OMAP3430_AUTO_MCBSP1 |
 675                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 676                 OMAP3430_AUTO_MAILBOXES |
 677                 OMAP3430_AUTO_OMAPCTRL |
 678                 OMAP3430ES1_AUTO_FSHOSTUSB |
 679                 OMAP3430_AUTO_HSOTGUSB |
 680                 OMAP3430_AUTO_SAD2D |
 681                 OMAP3430_AUTO_SSI,
 682                 CORE_MOD, CM_AUTOIDLE1);
 683
 684         cm_write_mod_reg(
 685                 OMAP3430_AUTO_PKA |
 686                 OMAP3430_AUTO_AES1 |
 687                 OMAP3430_AUTO_RNG |
 688                 OMAP3430_AUTO_SHA11 |
 689                 OMAP3430_AUTO_DES1,
 690                 CORE_MOD, CM_AUTOIDLE2);
 691
 692         if (omap_rev() > OMAP3430_REV_ES1_0) {
 693                 cm_write_mod_reg(
 694                         OMAP3430_AUTO_MAD2D |
 695                         OMAP3430ES2_AUTO_USBTLL,
 696                         CORE_MOD, CM_AUTOIDLE3);
 697         }
 698
 699         cm_write_mod_reg(
 700                 OMAP3430_AUTO_WDT2 |
 701                 OMAP3430_AUTO_WDT1 |
 702                 OMAP3430_AUTO_GPIO1 |
 703                 OMAP3430_AUTO_32KSYNC |
 704                 OMAP3430_AUTO_GPT12 |
 705                 OMAP3430_AUTO_GPT1 ,
 706                 WKUP_MOD, CM_AUTOIDLE);
 707
 708         cm_write_mod_reg(
 709                 OMAP3430_AUTO_DSS,
 710                 OMAP3430_DSS_MOD,
 711                 CM_AUTOIDLE);
 712
 713         cm_write_mod_reg(
 714                 OMAP3430_AUTO_CAM,
 715                 OMAP3430_CAM_MOD,
 716                 CM_AUTOIDLE);
 717
 718         cm_write_mod_reg(
 719                 OMAP3430_AUTO_GPIO6 |
 720                 OMAP3430_AUTO_GPIO5 |
 721                 OMAP3430_AUTO_GPIO4 |
 722                 OMAP3430_AUTO_GPIO3 |
 723                 OMAP3430_AUTO_GPIO2 |
 724                 OMAP3430_AUTO_WDT3 |
 725                 OMAP3430_AUTO_UART3 |
 726                 OMAP3430_AUTO_GPT9 |
 727                 OMAP3430_AUTO_GPT8 |
 728                 OMAP3430_AUTO_GPT7 |
 729                 OMAP3430_AUTO_GPT6 |
 730                 OMAP3430_AUTO_GPT5 |
 731                 OMAP3430_AUTO_GPT4 |
 732                 OMAP3430_AUTO_GPT3 |
 733                 OMAP3430_AUTO_GPT2 |
 734                 OMAP3430_AUTO_MCBSP4 |
 735                 OMAP3430_AUTO_MCBSP3 |
 736                 OMAP3430_AUTO_MCBSP2,
 737                 OMAP3430_PER_MOD,
 738                 CM_AUTOIDLE);
 739
 740         if (omap_rev() > OMAP3430_REV_ES1_0) {
 741                 cm_write_mod_reg(
 742                         OMAP3430ES2_AUTO_USBHOST,
 743                         OMAP3430ES2_USBHOST_MOD,
 744                         CM_AUTOIDLE);
 745         }
 746
 747         /*
 748          * Set all plls to autoidle. This is needed until autoidle is
 749          * enabled by clockfw
 750          */
 751         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 752                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 753         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 754                          MPU_MOD,
 755                          CM_AUTOIDLE2);
 756         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 757                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 758                          PLL_MOD,
 759                          CM_AUTOIDLE);
 760         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 761                          PLL_MOD,
 762                          CM_AUTOIDLE2);
 763
 764         /*
 765          * Enable control of expternal oscillator through
 766          * sys_clkreq. In the long run clock framework should
 767          * take care of this.
 768          */
 769         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 770                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 771                              OMAP3430_GR_MOD,
 772                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 773
 774         /* setup wakup source */
 775         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 776                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 777                           WKUP_MOD, PM_WKEN);
 778         /* No need to write EN_IO, that is always enabled */
 779         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 780                           OMAP3430_EN_GPT12,
 781                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 782         /* For some reason IO doesn't generate wakeup event even if
 783          * it is selected to mpu wakeup goup */
 784         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 785                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 786
 787         /* Enable wakeups in PER */
 788         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 789                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 790                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
 791                           OMAP3430_PER_MOD, PM_WKEN);
 792         /* and allow them to wake up MPU */
 793         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 794                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 795                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
 796                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 797
 798         /* Don't attach IVA interrupts */
 799         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 800         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 801         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 802         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 803
 804         /* Clear any pending 'reset' flags */
 805         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 806         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 807         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 808         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 809         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 810         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 811         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 812
 813         /* Clear any pending PRCM interrupts */
 814         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 815
 816         /* Don't attach IVA interrupts */
 817         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 818         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 819         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 820         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 821
 822         /* Clear any pending 'reset' flags */
 823         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 824         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 825         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 826         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 827         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 828         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 829         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 830
 831         /* Clear any pending PRCM interrupts */
 832         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 833
 834         omap3_iva_idle();
 835         omap3_d2d_idle();
 836 }
 837
 838 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 839 {
 840         struct power_state *pwrst;
 841
 842         list_for_each_entry(pwrst, &pwrst_list, node) {
 843                 if (pwrst->pwrdm == pwrdm)
 844                         return pwrst->next_state;
 845         }
 846         return -EINVAL;
 847 }
 848
 849 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 850 {
 851         struct power_state *pwrst;
 852
 853         list_for_each_entry(pwrst, &pwrst_list, node) {
 854                 if (pwrst->pwrdm == pwrdm) {
 855                         pwrst->next_state = state;
 856                         return 0;
 857                 }
 858         }
 859         return -EINVAL;
 860 }
 861
 862 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 863 {
 864         struct power_state *pwrst;
 865
 866         if (!pwrdm->pwrsts)
 867                 return 0;
 868
 869         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 870         if (!pwrst)
 871                 return -ENOMEM;
 872         pwrst->pwrdm = pwrdm;
 873         pwrst->next_state = PWRDM_POWER_RET;
 874         list_add(&pwrst->node, &pwrst_list);
 875
 876         if (pwrdm_has_hdwr_sar(pwrdm))
 877                 pwrdm_enable_hdwr_sar(pwrdm);
 878
 879         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 880 }
 881
 882 /*
 883  * Enable hw supervised mode for all clockdomains if it's
 884  * supported. Initiate sleep transition for other clockdomains, if
 885  * they are not used
 886  */
 887 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 888 {
 889         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 890                 omap2_clkdm_allow_idle(clkdm);
 891         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 892                  atomic_read(&clkdm->usecount) == 0)
 893                 omap2_clkdm_sleep(clkdm);
 894         return 0;
 895 }
 896
 897 void omap_push_sram_idle(void)
 898 {
 899         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 900                                         omap34xx_cpu_suspend_sz);
 901 }
 902
 903 static int __init omap3_pm_init(void)
 904 {
 905         struct power_state *pwrst, *tmp;
 906         int ret;
 907
 908         if (!cpu_is_omap34xx())
 909                 return -ENODEV;
 910
 911         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 912
 913         /* XXX prcm_setup_regs needs to be before enabling hw
 914          * supervised mode for powerdomains */
 915         prcm_setup_regs();
 916         omap3_save_scratchpad_contents();
 917
 918         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 919                           (irq_handler_t)prcm_interrupt_handler,
 920                           IRQF_DISABLED, "prcm", NULL);
 921         if (ret) {
 922                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 923                        INT_34XX_PRCM_MPU_IRQ);
 924                 goto err1;
 925         }
 926
 927         ret = pwrdm_for_each(pwrdms_setup, NULL);
 928         if (ret) {
 929                 printk(KERN_ERR "Failed to setup powerdomains\n");
 930                 goto err2;
 931         }
 932
 933         (void) clkdm_for_each(clkdms_setup, NULL);
 934
 935         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 936         if (mpu_pwrdm == NULL) {
 937                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 938                 goto err2;
 939         }
 940
 941         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 942         per_pwrdm = pwrdm_lookup("per_pwrdm");
 943         core_pwrdm = pwrdm_lookup("core_pwrdm");
 944
 945         omap_push_sram_idle();
 946 #ifdef CONFIG_SUSPEND
 947         suspend_set_ops(&omap_pm_ops);
 948 #endif /* CONFIG_SUSPEND */
 949
 950         pm_idle = omap3_pm_idle;
 951
 952         pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
 953         /*
 954          * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
 955          * IO-pad wakeup.  Otherwise it will unnecessarily waste power
 956          * waking up PER with every CORE wakeup - see
 957          * http://marc.info/?l=linux-omap&m=121852150710062&w=2
 958         */
 959         pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
 960
 961 err1:
 962         return ret;
 963 err2:
 964         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 965         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 966                 list_del(&pwrst->node);
 967                 kfree(pwrst);
 968         }
 969         return ret;
 970 }
 971
 972 late_initcall(omap3_pm_init);