2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk-provider.h>
29 #include <linux/irq.h>
30 #include <linux/time.h>
31 #include <linux/gpio.h>
32 #include <linux/platform_data/gpio-omap.h>
34 #include <asm/fncpy.h>
36 #include <asm/mach/time.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach-types.h>
39 #include <asm/system_misc.h>
41 #include <linux/omap-dma.h>
47 #include "prm-regbits-24xx.h"
49 #include "cm-regbits-24xx.h"
54 #include "powerdomain.h"
55 #include "clockdomain.h"
57 static void (*omap2_sram_idle)(void);
58 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
59 void __iomem *sdrc_power);
61 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
62 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
64 static struct clk *osc_ck, *emul_ck;
66 static int omap2_fclks_active(void)
70 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
71 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
73 return (f1 | f2) ? 1 : 0;
76 static int omap2_enter_full_retention(void)
80 /* There is 1 reference hold for all children of the oscillator
81 * clock, the following will remove it. If no one else uses the
82 * oscillator itself it will be disabled if/when we enter retention
87 /* Clear old wake-up events */
88 /* REVISIT: These write to reserved bits? */
89 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
90 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
91 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
93 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
94 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
96 /* Workaround to kill USB */
97 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
98 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
100 omap2_gpio_prepare_for_idle(0);
102 /* One last check for pending IRQs to avoid extra latency due
103 * to sleeping unnecessarily. */
104 if (omap_irq_pending())
107 /* Jump to SRAM suspend code */
108 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
109 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
110 OMAP_SDRC_REGADDR(SDRC_POWER));
113 omap2_gpio_resume_after_idle();
117 /* clear CORE wake-up events */
118 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
119 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
121 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
122 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
124 /* MPU domain wake events */
125 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
127 omap2_prm_write_mod_reg(0x01, OCP_MOD,
128 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
130 omap2_prm_write_mod_reg(0x20, OCP_MOD,
131 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
133 /* Mask future PRCM-to-MPU interrupts */
134 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
136 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
137 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
142 static int sti_console_enabled;
144 static int omap2_allow_mpu_retention(void)
148 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
149 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
150 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
151 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
152 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
154 /* Check for UART3. */
155 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
156 if (l & OMAP24XX_EN_UART3_MASK)
158 if (sti_console_enabled)
164 static void omap2_enter_mpu_retention(void)
166 /* The peripherals seem not to be able to wake up the MPU when
167 * it is in retention mode. */
168 if (omap2_allow_mpu_retention()) {
169 /* REVISIT: These write to reserved bits? */
170 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
171 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
172 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
174 /* Try to enter MPU retention */
175 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
178 /* Block MPU retention */
179 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
184 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
187 static int omap2_can_sleep(void)
189 if (omap2_fclks_active())
191 if (__clk_is_enabled(osc_ck))
193 if (omap_dma_running())
199 static void omap2_pm_idle(void)
203 if (!omap2_can_sleep()) {
204 if (omap_irq_pending())
206 omap2_enter_mpu_retention();
210 if (omap_irq_pending())
213 omap2_enter_full_retention();
219 static void __init prcm_setup_regs(void)
221 int i, num_mem_banks;
222 struct powerdomain *pwrdm;
226 * XXX This should be handled by hwmod code or PRCM init code
228 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
229 OMAP2_PRCM_SYSCONFIG_OFFSET);
232 * Set CORE powerdomain memory banks to retain their contents
235 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
236 for (i = 0; i < num_mem_banks; i++)
237 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
239 pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
241 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
243 /* Force-power down DSP, GFX powerdomains */
245 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
246 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
248 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
249 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
251 /* Enable hardware-supervised idle for all clkdms */
252 clkdm_for_each(omap_pm_clkdms_setup, NULL);
253 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
255 #ifdef CONFIG_SUSPEND
256 omap_pm_suspend = omap2_enter_full_retention;
259 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
261 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
262 OMAP2_PRCM_CLKSSETUP_OFFSET);
264 /* Configure automatic voltage transition */
265 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
266 OMAP2_PRCM_VOLTSETUP_OFFSET);
267 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
268 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
269 OMAP24XX_MEMRETCTRL_MASK |
270 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
271 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
272 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
274 /* Enable wake-up events */
275 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
279 int __init omap2_pm_init(void)
283 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
284 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
285 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
287 /* Look up important powerdomains */
289 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
291 pr_err("PM: mpu_pwrdm not found\n");
293 core_pwrdm = pwrdm_lookup("core_pwrdm");
295 pr_err("PM: core_pwrdm not found\n");
297 /* Look up important clockdomains */
299 mpu_clkdm = clkdm_lookup("mpu_clkdm");
301 pr_err("PM: mpu_clkdm not found\n");
303 wkup_clkdm = clkdm_lookup("wkup_clkdm");
305 pr_err("PM: wkup_clkdm not found\n");
307 dsp_clkdm = clkdm_lookup("dsp_clkdm");
309 pr_err("PM: dsp_clkdm not found\n");
311 gfx_clkdm = clkdm_lookup("gfx_clkdm");
313 pr_err("PM: gfx_clkdm not found\n");
316 osc_ck = clk_get(NULL, "osc_ck");
317 if (IS_ERR(osc_ck)) {
318 printk(KERN_ERR "could not get osc_ck\n");
322 if (cpu_is_omap242x()) {
323 emul_ck = clk_get(NULL, "emul_ck");
324 if (IS_ERR(emul_ck)) {
325 printk(KERN_ERR "could not get emul_ck\n");
334 * We copy the assembler sleep/wakeup routines to SRAM.
335 * These routines need to be in SRAM as that's the only
336 * memory the MPU can see when it wakes up.
338 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
339 omap24xx_idle_loop_suspend_sz);
341 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
342 omap24xx_cpu_suspend_sz);
344 arm_pm_idle = omap2_pm_idle;