2 * This file configures the internal USB PHY in OMAP4430. Used
3 * with TWL6030 transceiver and MUSB on OMAP4430.
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * Author: Hema HK <hemahk@ti.com>
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/types.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/err.h>
29 #include <linux/usb.h>
34 void am35x_musb_reset(void)
38 /* Reset the musb interface */
39 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
41 regval |= AM35XX_USBOTGSS_SW_RST;
42 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
44 regval &= ~AM35XX_USBOTGSS_SW_RST;
45 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
47 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
50 void am35x_musb_phy_power(u8 on)
52 unsigned long timeout = jiffies + msecs_to_jiffies(100);
57 * Start the on-chip PHY and its PLL.
59 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
61 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
62 devconf2 |= CONF2_PHY_PLLON;
64 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
66 pr_info(KERN_INFO "Waiting for PHY clock good...\n");
67 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
71 if (time_after(jiffies, timeout)) {
72 pr_err(KERN_ERR "musb PHY clock good timed out\n");
78 * Power down the on-chip PHY.
80 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
82 devconf2 &= ~CONF2_PHY_PLLON;
83 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
84 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
88 void am35x_musb_clear_irq(void)
92 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
93 regval |= AM35XX_USBOTGSS_INT_CLR;
94 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
95 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
98 void am35x_set_mode(u8 musb_mode)
100 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
102 devconf2 &= ~CONF2_OTGMODE;
104 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
105 devconf2 |= CONF2_FORCE_HOST;
107 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
108 devconf2 |= CONF2_FORCE_DEVICE;
110 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
111 devconf2 |= CONF2_NO_OVERRIDE;
114 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
117 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
120 void ti81xx_musb_phy_power(u8 on)
122 void __iomem *scm_base = NULL;
125 scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
127 pr_err("system control module ioremap failed\n");
131 usbphycfg = __raw_readl(scm_base + USBCTRL0);
134 if (cpu_is_ti816x()) {
135 usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
136 usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
137 } else if (cpu_is_ti814x()) {
138 usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
139 | USBPHY_DPINPUT | USBPHY_DMINPUT);
140 usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
141 | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
145 usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
146 else if (cpu_is_ti814x())
147 usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
150 __raw_writel(usbphycfg, scm_base + USBCTRL0);