arch/arm/mach-omap2/omap_phy_internal.c

   1 /*
   2   * This file configures the internal USB PHY in OMAP4430. Used
   3   * with TWL6030 transceiver and MUSB on OMAP4430.
   4   *
   5   * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
   6   * This program is free software; you can redistribute it and/or modify
   7   * it under the terms of the GNU General Public License as published by
   8   * the Free Software Foundation; either version 2 of the License, or
   9   * (at your option) any later version.
  10   *
  11   * Author: Hema HK <hemahk@ti.com>
  12   *
  13   * This program is distributed in the hope that it will be useful,
  14   * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   * GNU General Public License for more details.
  17   *
  18   * You should have received a copy of the GNU General Public License
  19   * along with this program; if not, write to the Free Software
  20   * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21   *
  22   */
  23
  24 #include <linux/types.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/err.h>
  29 #include <linux/usb.h>
  30
  31 #include <plat/usb.h>
  32
  33 #include "soc.h"
  34 #include "control.h"
  35
  36 /* OMAP control module register for UTMI PHY */
  37 #define CONTROL_DEV_CONF                0x300
  38 #define PHY_PD                          0x1
  39
  40 #define USBOTGHS_CONTROL                0x33c
  41 #define AVALID                          BIT(0)
  42 #define BVALID                          BIT(1)
  43 #define VBUSVALID                       BIT(2)
  44 #define SESSEND                         BIT(3)
  45 #define IDDIG                           BIT(4)
  46
  47 static struct clk *phyclk, *clk48m, *clk32k;
  48 static void __iomem *ctrl_base;
  49 static int usbotghs_control;
  50
  51 int omap4430_phy_init(struct device *dev)
  52 {
  53         ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
  54         if (!ctrl_base) {
  55                 pr_err("control module ioremap failed\n");
  56                 return -ENOMEM;
  57         }
  58         /* Power down the phy */
  59         __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
  60
  61         if (!dev) {
  62                 iounmap(ctrl_base);
  63                 return 0;
  64         }
  65
  66         phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
  67         if (IS_ERR(phyclk)) {
  68                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
  69                 iounmap(ctrl_base);
  70                 return PTR_ERR(phyclk);
  71         }
  72
  73         clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
  74         if (IS_ERR(clk48m)) {
  75                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
  76                 clk_put(phyclk);
  77                 iounmap(ctrl_base);
  78                 return PTR_ERR(clk48m);
  79         }
  80
  81         clk32k = clk_get(dev, "usb_phy_cm_clk32k");
  82         if (IS_ERR(clk32k)) {
  83                 dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
  84                 clk_put(phyclk);
  85                 clk_put(clk48m);
  86                 iounmap(ctrl_base);
  87                 return PTR_ERR(clk32k);
  88         }
  89         return 0;
  90 }
  91
  92 int omap4430_phy_set_clk(struct device *dev, int on)
  93 {
  94         static int state;
  95
  96         if (on && !state) {
  97                 /* Enable the phy clocks */
  98                 clk_enable(phyclk);
  99                 clk_enable(clk48m);
 100                 clk_enable(clk32k);
 101                 state = 1;
 102         } else if (state) {
 103                 /* Disable the phy clocks */
 104                 clk_disable(phyclk);
 105                 clk_disable(clk48m);
 106                 clk_disable(clk32k);
 107                 state = 0;
 108         }
 109         return 0;
 110 }
 111
 112 int omap4430_phy_power(struct device *dev, int ID, int on)
 113 {
 114         if (on) {
 115                 if (ID)
 116                         /* enable VBUS valid, IDDIG groung */
 117                         __raw_writel(AVALID | VBUSVALID, ctrl_base +
 118                                                         USBOTGHS_CONTROL);
 119                 else
 120                         /*
 121                          * Enable VBUS Valid, AValid and IDDIG
 122                          * high impedance
 123                          */
 124                         __raw_writel(IDDIG | AVALID | VBUSVALID,
 125                                                 ctrl_base + USBOTGHS_CONTROL);
 126         } else {
 127                 /* Enable session END and IDIG to high impedance. */
 128                 __raw_writel(SESSEND | IDDIG, ctrl_base +
 129                                         USBOTGHS_CONTROL);
 130         }
 131         return 0;
 132 }
 133
 134 int omap4430_phy_suspend(struct device *dev, int suspend)
 135 {
 136         if (suspend) {
 137                 /* Disable the clocks */
 138                 omap4430_phy_set_clk(dev, 0);
 139                 /* Power down the phy */
 140                 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 141
 142                 /* save the context */
 143                 usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
 144         } else {
 145                 /* Enable the internel phy clcoks */
 146                 omap4430_phy_set_clk(dev, 1);
 147                 /* power on the phy */
 148                 if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
 149                         __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 150                         mdelay(200);
 151                 }
 152
 153                 /* restore the context */
 154                 __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
 155         }
 156
 157         return 0;
 158 }
 159
 160 int omap4430_phy_exit(struct device *dev)
 161 {
 162         if (ctrl_base)
 163                 iounmap(ctrl_base);
 164         if (phyclk)
 165                 clk_put(phyclk);
 166         if (clk48m)
 167                 clk_put(clk48m);
 168         if (clk32k)
 169                 clk_put(clk32k);
 170
 171         return 0;
 172 }
 173
 174 void am35x_musb_reset(void)
 175 {
 176         u32     regval;
 177
 178         /* Reset the musb interface */
 179         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 180
 181         regval |= AM35XX_USBOTGSS_SW_RST;
 182         omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
 183
 184         regval &= ~AM35XX_USBOTGSS_SW_RST;
 185         omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
 186
 187         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 188 }
 189
 190 void am35x_musb_phy_power(u8 on)
 191 {
 192         unsigned long timeout = jiffies + msecs_to_jiffies(100);
 193         u32 devconf2;
 194
 195         if (on) {
 196                 /*
 197                  * Start the on-chip PHY and its PLL.
 198                  */
 199                 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 200
 201                 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
 202                 devconf2 |= CONF2_PHY_PLLON;
 203
 204                 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 205
 206                 pr_info(KERN_INFO "Waiting for PHY clock good...\n");
 207                 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
 208                                 & CONF2_PHYCLKGD)) {
 209                         cpu_relax();
 210
 211                         if (time_after(jiffies, timeout)) {
 212                                 pr_err(KERN_ERR "musb PHY clock good timed out\n");
 213                                 break;
 214                         }
 215                 }
 216         } else {
 217                 /*
 218                  * Power down the on-chip PHY.
 219                  */
 220                 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 221
 222                 devconf2 &= ~CONF2_PHY_PLLON;
 223                 devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
 224                 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 225         }
 226 }
 227
 228 void am35x_musb_clear_irq(void)
 229 {
 230         u32 regval;
 231
 232         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 233         regval |= AM35XX_USBOTGSS_INT_CLR;
 234         omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
 235         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 236 }
 237
 238 void am35x_set_mode(u8 musb_mode)
 239 {
 240         u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 241
 242         devconf2 &= ~CONF2_OTGMODE;
 243         switch (musb_mode) {
 244         case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
 245                 devconf2 |= CONF2_FORCE_HOST;
 246                 break;
 247         case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
 248                 devconf2 |= CONF2_FORCE_DEVICE;
 249                 break;
 250         case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
 251                 devconf2 |= CONF2_NO_OVERRIDE;
 252                 break;
 253         default:
 254                 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
 255         }
 256
 257         omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 258 }
 259
 260 void ti81xx_musb_phy_power(u8 on)
 261 {
 262         void __iomem *scm_base = NULL;
 263         u32 usbphycfg;
 264
 265         scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
 266         if (!scm_base) {
 267                 pr_err("system control module ioremap failed\n");
 268                 return;
 269         }
 270
 271         usbphycfg = __raw_readl(scm_base + USBCTRL0);
 272
 273         if (on) {
 274                 if (cpu_is_ti816x()) {
 275                         usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
 276                         usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
 277                 } else if (cpu_is_ti814x()) {
 278                         usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
 279                                 | USBPHY_DPINPUT | USBPHY_DMINPUT);
 280                         usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
 281                                 | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
 282                 }
 283         } else {
 284                 if (cpu_is_ti816x())
 285                         usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
 286                 else if (cpu_is_ti814x())
 287                         usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
 288
 289         }
 290         __raw_writel(usbphycfg, scm_base + USBCTRL0);
 291
 292         iounmap(scm_base);
 293 }