arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/asoc-ti-mcbsp.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "omap_hwmod_common_data.h"
  32 #include "cm1_54xx.h"
  33 #include "cm2_54xx.h"
  34 #include "prm54xx.h"
  35 #include "prm-regbits-54xx.h"
  36 #include "i2c.h"
  37 #include "mmc.h"
  38 #include "wd_timer.h"
  39
  40 /* Base offset for all OMAP5 interrupts external to MPUSS */
  41 #define OMAP54XX_IRQ_GIC_START  32
  42
  43 /* Base offset for all OMAP5 dma requests */
  44 #define OMAP54XX_DMA_REQ_START  1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod omap54xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &omap54xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  75  */
  76 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &omap54xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &omap54xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &omap54xx_l3_hwmod_class,
 111         .clkdm_name     = "l3main2_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 116                 },
 117         },
 118 };
 119
 120 /* l3_main_3 */
 121 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 122         .name           = "l3_main_3",
 123         .class          = &omap54xx_l3_hwmod_class,
 124         .clkdm_name     = "l3instr_clkdm",
 125         .prcm = {
 126                 .omap4 = {
 127                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 128                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 129                         .modulemode   = MODULEMODE_HWCTRL,
 130                 },
 131         },
 132 };
 133
 134 /*
 135  * 'l4' class
 136  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 137  */
 138 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 139         .name   = "l4",
 140 };
 141
 142 /* l4_abe */
 143 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 144         .name           = "l4_abe",
 145         .class          = &omap54xx_l4_hwmod_class,
 146         .clkdm_name     = "abe_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_cfg */
 156 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 157         .name           = "l4_cfg",
 158         .class          = &omap54xx_l4_hwmod_class,
 159         .clkdm_name     = "l4cfg_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 163                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per */
 169 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 170         .name           = "l4_per",
 171         .class          = &omap54xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 176                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &omap54xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'mpu_bus' class
 196  * instance(s): mpu_private
 197  */
 198 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 199         .name   = "mpu_bus",
 200 };
 201
 202 /* mpu_private */
 203 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 204         .name           = "mpu_private",
 205         .class          = &omap54xx_mpu_bus_hwmod_class,
 206         .clkdm_name     = "mpu_clkdm",
 207         .prcm = {
 208                 .omap4 = {
 209                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 210                 },
 211         },
 212 };
 213
 214 /*
 215  * 'counter' class
 216  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 217  */
 218
 219 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 220         .rev_offs       = 0x0000,
 221         .sysc_offs      = 0x0010,
 222         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 223         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 224         .sysc_fields    = &omap_hwmod_sysc_type1,
 225 };
 226
 227 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 228         .name   = "counter",
 229         .sysc   = &omap54xx_counter_sysc,
 230 };
 231
 232 /* counter_32k */
 233 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 234         .name           = "counter_32k",
 235         .class          = &omap54xx_counter_hwmod_class,
 236         .clkdm_name     = "wkupaon_clkdm",
 237         .flags          = HWMOD_SWSUP_SIDLE,
 238         .main_clk       = "wkupaon_iclk_mux",
 239         .prcm = {
 240                 .omap4 = {
 241                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 242                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 243                 },
 244         },
 245 };
 246
 247 /*
 248  * 'dma' class
 249  * dma controller for data exchange between memory to memory (i.e. internal or
 250  * external memory) and gp peripherals to memory or memory to gp peripherals
 251  */
 252
 253 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 254         .rev_offs       = 0x0000,
 255         .sysc_offs      = 0x002c,
 256         .syss_offs      = 0x0028,
 257         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 258                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 259                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 260                            SYSS_HAS_RESET_STATUS),
 261         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 262                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 263         .sysc_fields    = &omap_hwmod_sysc_type1,
 264 };
 265
 266 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 267         .name   = "dma",
 268         .sysc   = &omap54xx_dma_sysc,
 269 };
 270
 271 /* dma dev_attr */
 272 static struct omap_dma_dev_attr dma_dev_attr = {
 273         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 274                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 275         .lch_count      = 32,
 276 };
 277
 278 /* dma_system */
 279 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
 280         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
 281         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
 282         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
 283         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
 284         { .irq = -1 }
 285 };
 286
 287 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 288         .name           = "dma_system",
 289         .class          = &omap54xx_dma_hwmod_class,
 290         .clkdm_name     = "dma_clkdm",
 291         .mpu_irqs       = omap54xx_dma_system_irqs,
 292         .main_clk       = "l3_iclk_div",
 293         .prcm = {
 294                 .omap4 = {
 295                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 296                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 297                 },
 298         },
 299         .dev_attr       = &dma_dev_attr,
 300 };
 301
 302 /*
 303  * 'dmic' class
 304  * digital microphone controller
 305  */
 306
 307 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 308         .rev_offs       = 0x0000,
 309         .sysc_offs      = 0x0010,
 310         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 311                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 313                            SIDLE_SMART_WKUP),
 314         .sysc_fields    = &omap_hwmod_sysc_type2,
 315 };
 316
 317 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 318         .name   = "dmic",
 319         .sysc   = &omap54xx_dmic_sysc,
 320 };
 321
 322 /* dmic */
 323 static struct omap_hwmod omap54xx_dmic_hwmod = {
 324         .name           = "dmic",
 325         .class          = &omap54xx_dmic_hwmod_class,
 326         .clkdm_name     = "abe_clkdm",
 327         .main_clk       = "dmic_gfclk",
 328         .prcm = {
 329                 .omap4 = {
 330                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 331                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 332                         .modulemode   = MODULEMODE_SWCTRL,
 333                 },
 334         },
 335 };
 336
 337 /*
 338  * 'emif' class
 339  * external memory interface no1 (wrapper)
 340  */
 341
 342 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 343         .rev_offs       = 0x0000,
 344 };
 345
 346 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 347         .name   = "emif",
 348         .sysc   = &omap54xx_emif_sysc,
 349 };
 350
 351 /* emif1 */
 352 static struct omap_hwmod omap54xx_emif1_hwmod = {
 353         .name           = "emif1",
 354         .class          = &omap54xx_emif_hwmod_class,
 355         .clkdm_name     = "emif_clkdm",
 356         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 357         .main_clk       = "dpll_core_h11x2_ck",
 358         .prcm = {
 359                 .omap4 = {
 360                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 361                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 362                         .modulemode   = MODULEMODE_HWCTRL,
 363                 },
 364         },
 365 };
 366
 367 /* emif2 */
 368 static struct omap_hwmod omap54xx_emif2_hwmod = {
 369         .name           = "emif2",
 370         .class          = &omap54xx_emif_hwmod_class,
 371         .clkdm_name     = "emif_clkdm",
 372         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 373         .main_clk       = "dpll_core_h11x2_ck",
 374         .prcm = {
 375                 .omap4 = {
 376                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 377                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 378                         .modulemode   = MODULEMODE_HWCTRL,
 379                 },
 380         },
 381 };
 382
 383 /*
 384  * 'gpio' class
 385  * general purpose io module
 386  */
 387
 388 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 389         .rev_offs       = 0x0000,
 390         .sysc_offs      = 0x0010,
 391         .syss_offs      = 0x0114,
 392         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 393                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 394                            SYSS_HAS_RESET_STATUS),
 395         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 396                            SIDLE_SMART_WKUP),
 397         .sysc_fields    = &omap_hwmod_sysc_type1,
 398 };
 399
 400 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 401         .name   = "gpio",
 402         .sysc   = &omap54xx_gpio_sysc,
 403         .rev    = 2,
 404 };
 405
 406 /* gpio dev_attr */
 407 static struct omap_gpio_dev_attr gpio_dev_attr = {
 408         .bank_width     = 32,
 409         .dbck_flag      = true,
 410 };
 411
 412 /* gpio1 */
 413 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 414         { .role = "dbclk", .clk = "gpio1_dbclk" },
 415 };
 416
 417 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 418         .name           = "gpio1",
 419         .class          = &omap54xx_gpio_hwmod_class,
 420         .clkdm_name     = "wkupaon_clkdm",
 421         .main_clk       = "wkupaon_iclk_mux",
 422         .prcm = {
 423                 .omap4 = {
 424                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 425                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 426                         .modulemode   = MODULEMODE_HWCTRL,
 427                 },
 428         },
 429         .opt_clks       = gpio1_opt_clks,
 430         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 431         .dev_attr       = &gpio_dev_attr,
 432 };
 433
 434 /* gpio2 */
 435 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 436         { .role = "dbclk", .clk = "gpio2_dbclk" },
 437 };
 438
 439 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 440         .name           = "gpio2",
 441         .class          = &omap54xx_gpio_hwmod_class,
 442         .clkdm_name     = "l4per_clkdm",
 443         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 444         .main_clk       = "l4_root_clk_div",
 445         .prcm = {
 446                 .omap4 = {
 447                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 448                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 449                         .modulemode   = MODULEMODE_HWCTRL,
 450                 },
 451         },
 452         .opt_clks       = gpio2_opt_clks,
 453         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 454         .dev_attr       = &gpio_dev_attr,
 455 };
 456
 457 /* gpio3 */
 458 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 459         { .role = "dbclk", .clk = "gpio3_dbclk" },
 460 };
 461
 462 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 463         .name           = "gpio3",
 464         .class          = &omap54xx_gpio_hwmod_class,
 465         .clkdm_name     = "l4per_clkdm",
 466         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 467         .main_clk       = "l4_root_clk_div",
 468         .prcm = {
 469                 .omap4 = {
 470                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 471                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 472                         .modulemode   = MODULEMODE_HWCTRL,
 473                 },
 474         },
 475         .opt_clks       = gpio3_opt_clks,
 476         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 477         .dev_attr       = &gpio_dev_attr,
 478 };
 479
 480 /* gpio4 */
 481 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 482         { .role = "dbclk", .clk = "gpio4_dbclk" },
 483 };
 484
 485 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 486         .name           = "gpio4",
 487         .class          = &omap54xx_gpio_hwmod_class,
 488         .clkdm_name     = "l4per_clkdm",
 489         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 490         .main_clk       = "l4_root_clk_div",
 491         .prcm = {
 492                 .omap4 = {
 493                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 494                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 495                         .modulemode   = MODULEMODE_HWCTRL,
 496                 },
 497         },
 498         .opt_clks       = gpio4_opt_clks,
 499         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 500         .dev_attr       = &gpio_dev_attr,
 501 };
 502
 503 /* gpio5 */
 504 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 505         { .role = "dbclk", .clk = "gpio5_dbclk" },
 506 };
 507
 508 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 509         .name           = "gpio5",
 510         .class          = &omap54xx_gpio_hwmod_class,
 511         .clkdm_name     = "l4per_clkdm",
 512         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 513         .main_clk       = "l4_root_clk_div",
 514         .prcm = {
 515                 .omap4 = {
 516                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 517                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 518                         .modulemode   = MODULEMODE_HWCTRL,
 519                 },
 520         },
 521         .opt_clks       = gpio5_opt_clks,
 522         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 523         .dev_attr       = &gpio_dev_attr,
 524 };
 525
 526 /* gpio6 */
 527 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 528         { .role = "dbclk", .clk = "gpio6_dbclk" },
 529 };
 530
 531 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 532         .name           = "gpio6",
 533         .class          = &omap54xx_gpio_hwmod_class,
 534         .clkdm_name     = "l4per_clkdm",
 535         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 536         .main_clk       = "l4_root_clk_div",
 537         .prcm = {
 538                 .omap4 = {
 539                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 540                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 541                         .modulemode   = MODULEMODE_HWCTRL,
 542                 },
 543         },
 544         .opt_clks       = gpio6_opt_clks,
 545         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 546         .dev_attr       = &gpio_dev_attr,
 547 };
 548
 549 /* gpio7 */
 550 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 551         { .role = "dbclk", .clk = "gpio7_dbclk" },
 552 };
 553
 554 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 555         .name           = "gpio7",
 556         .class          = &omap54xx_gpio_hwmod_class,
 557         .clkdm_name     = "l4per_clkdm",
 558         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 559         .main_clk       = "l4_root_clk_div",
 560         .prcm = {
 561                 .omap4 = {
 562                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 563                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 564                         .modulemode   = MODULEMODE_HWCTRL,
 565                 },
 566         },
 567         .opt_clks       = gpio7_opt_clks,
 568         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 569         .dev_attr       = &gpio_dev_attr,
 570 };
 571
 572 /* gpio8 */
 573 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 574         { .role = "dbclk", .clk = "gpio8_dbclk" },
 575 };
 576
 577 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 578         .name           = "gpio8",
 579         .class          = &omap54xx_gpio_hwmod_class,
 580         .clkdm_name     = "l4per_clkdm",
 581         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 582         .main_clk       = "l4_root_clk_div",
 583         .prcm = {
 584                 .omap4 = {
 585                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 586                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 587                         .modulemode   = MODULEMODE_HWCTRL,
 588                 },
 589         },
 590         .opt_clks       = gpio8_opt_clks,
 591         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 592         .dev_attr       = &gpio_dev_attr,
 593 };
 594
 595 /*
 596  * 'i2c' class
 597  * multimaster high-speed i2c controller
 598  */
 599
 600 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 601         .sysc_offs      = 0x0010,
 602         .syss_offs      = 0x0090,
 603         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 604                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 605                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 606         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 607                            SIDLE_SMART_WKUP),
 608         .clockact       = CLOCKACT_TEST_ICLK,
 609         .sysc_fields    = &omap_hwmod_sysc_type1,
 610 };
 611
 612 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 613         .name   = "i2c",
 614         .sysc   = &omap54xx_i2c_sysc,
 615         .reset  = &omap_i2c_reset,
 616         .rev    = OMAP_I2C_IP_VERSION_2,
 617 };
 618
 619 /* i2c dev_attr */
 620 static struct omap_i2c_dev_attr i2c_dev_attr = {
 621         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 622 };
 623
 624 /* i2c1 */
 625 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 626         .name           = "i2c1",
 627         .class          = &omap54xx_i2c_hwmod_class,
 628         .clkdm_name     = "l4per_clkdm",
 629         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 630         .main_clk       = "func_96m_fclk",
 631         .prcm = {
 632                 .omap4 = {
 633                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 634                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 635                         .modulemode   = MODULEMODE_SWCTRL,
 636                 },
 637         },
 638         .dev_attr       = &i2c_dev_attr,
 639 };
 640
 641 /* i2c2 */
 642 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 643         .name           = "i2c2",
 644         .class          = &omap54xx_i2c_hwmod_class,
 645         .clkdm_name     = "l4per_clkdm",
 646         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 647         .main_clk       = "func_96m_fclk",
 648         .prcm = {
 649                 .omap4 = {
 650                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 651                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 652                         .modulemode   = MODULEMODE_SWCTRL,
 653                 },
 654         },
 655         .dev_attr       = &i2c_dev_attr,
 656 };
 657
 658 /* i2c3 */
 659 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 660         .name           = "i2c3",
 661         .class          = &omap54xx_i2c_hwmod_class,
 662         .clkdm_name     = "l4per_clkdm",
 663         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 664         .main_clk       = "func_96m_fclk",
 665         .prcm = {
 666                 .omap4 = {
 667                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 668                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 669                         .modulemode   = MODULEMODE_SWCTRL,
 670                 },
 671         },
 672         .dev_attr       = &i2c_dev_attr,
 673 };
 674
 675 /* i2c4 */
 676 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 677         .name           = "i2c4",
 678         .class          = &omap54xx_i2c_hwmod_class,
 679         .clkdm_name     = "l4per_clkdm",
 680         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 681         .main_clk       = "func_96m_fclk",
 682         .prcm = {
 683                 .omap4 = {
 684                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 685                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 686                         .modulemode   = MODULEMODE_SWCTRL,
 687                 },
 688         },
 689         .dev_attr       = &i2c_dev_attr,
 690 };
 691
 692 /* i2c5 */
 693 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 694         .name           = "i2c5",
 695         .class          = &omap54xx_i2c_hwmod_class,
 696         .clkdm_name     = "l4per_clkdm",
 697         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 698         .main_clk       = "func_96m_fclk",
 699         .prcm = {
 700                 .omap4 = {
 701                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 702                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 703                         .modulemode   = MODULEMODE_SWCTRL,
 704                 },
 705         },
 706         .dev_attr       = &i2c_dev_attr,
 707 };
 708
 709 /*
 710  * 'kbd' class
 711  * keyboard controller
 712  */
 713
 714 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 715         .rev_offs       = 0x0000,
 716         .sysc_offs      = 0x0010,
 717         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 718                            SYSC_HAS_SOFTRESET),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 724         .name   = "kbd",
 725         .sysc   = &omap54xx_kbd_sysc,
 726 };
 727
 728 /* kbd */
 729 static struct omap_hwmod omap54xx_kbd_hwmod = {
 730         .name           = "kbd",
 731         .class          = &omap54xx_kbd_hwmod_class,
 732         .clkdm_name     = "wkupaon_clkdm",
 733         .main_clk       = "sys_32k_ck",
 734         .prcm = {
 735                 .omap4 = {
 736                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 737                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 738                         .modulemode   = MODULEMODE_SWCTRL,
 739                 },
 740         },
 741 };
 742
 743 /*
 744  * 'mailbox' class
 745  * mailbox module allowing communication between the on-chip processors using a
 746  * queued mailbox-interrupt mechanism.
 747  */
 748
 749 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
 750         .rev_offs       = 0x0000,
 751         .sysc_offs      = 0x0010,
 752         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 753                            SYSC_HAS_SOFTRESET),
 754         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 755         .sysc_fields    = &omap_hwmod_sysc_type2,
 756 };
 757
 758 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
 759         .name   = "mailbox",
 760         .sysc   = &omap54xx_mailbox_sysc,
 761 };
 762
 763 /* mailbox */
 764 static struct omap_hwmod omap54xx_mailbox_hwmod = {
 765         .name           = "mailbox",
 766         .class          = &omap54xx_mailbox_hwmod_class,
 767         .clkdm_name     = "l4cfg_clkdm",
 768         .prcm = {
 769                 .omap4 = {
 770                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
 771                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
 772                 },
 773         },
 774 };
 775
 776 /*
 777  * 'mcbsp' class
 778  * multi channel buffered serial port controller
 779  */
 780
 781 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
 782         .sysc_offs      = 0x008c,
 783         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
 784                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 785         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 786         .sysc_fields    = &omap_hwmod_sysc_type1,
 787 };
 788
 789 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
 790         .name   = "mcbsp",
 791         .sysc   = &omap54xx_mcbsp_sysc,
 792         .rev    = MCBSP_CONFIG_TYPE4,
 793 };
 794
 795 /* mcbsp1 */
 796 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
 797         { .role = "pad_fck", .clk = "pad_clks_ck" },
 798         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
 799 };
 800
 801 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
 802         .name           = "mcbsp1",
 803         .class          = &omap54xx_mcbsp_hwmod_class,
 804         .clkdm_name     = "abe_clkdm",
 805         .main_clk       = "mcbsp1_gfclk",
 806         .prcm = {
 807                 .omap4 = {
 808                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
 809                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
 810                         .modulemode   = MODULEMODE_SWCTRL,
 811                 },
 812         },
 813         .opt_clks       = mcbsp1_opt_clks,
 814         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
 815 };
 816
 817 /* mcbsp2 */
 818 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
 819         { .role = "pad_fck", .clk = "pad_clks_ck" },
 820         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
 821 };
 822
 823 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
 824         .name           = "mcbsp2",
 825         .class          = &omap54xx_mcbsp_hwmod_class,
 826         .clkdm_name     = "abe_clkdm",
 827         .main_clk       = "mcbsp2_gfclk",
 828         .prcm = {
 829                 .omap4 = {
 830                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
 831                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
 832                         .modulemode   = MODULEMODE_SWCTRL,
 833                 },
 834         },
 835         .opt_clks       = mcbsp2_opt_clks,
 836         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
 837 };
 838
 839 /* mcbsp3 */
 840 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
 841         { .role = "pad_fck", .clk = "pad_clks_ck" },
 842         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
 843 };
 844
 845 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
 846         .name           = "mcbsp3",
 847         .class          = &omap54xx_mcbsp_hwmod_class,
 848         .clkdm_name     = "abe_clkdm",
 849         .main_clk       = "mcbsp3_gfclk",
 850         .prcm = {
 851                 .omap4 = {
 852                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
 853                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
 854                         .modulemode   = MODULEMODE_SWCTRL,
 855                 },
 856         },
 857         .opt_clks       = mcbsp3_opt_clks,
 858         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
 859 };
 860
 861 /*
 862  * 'mcpdm' class
 863  * multi channel pdm controller (proprietary interface with phoenix power
 864  * ic)
 865  */
 866
 867 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
 868         .rev_offs       = 0x0000,
 869         .sysc_offs      = 0x0010,
 870         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 871                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 872         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 873                            SIDLE_SMART_WKUP),
 874         .sysc_fields    = &omap_hwmod_sysc_type2,
 875 };
 876
 877 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
 878         .name   = "mcpdm",
 879         .sysc   = &omap54xx_mcpdm_sysc,
 880 };
 881
 882 /* mcpdm */
 883 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
 884         .name           = "mcpdm",
 885         .class          = &omap54xx_mcpdm_hwmod_class,
 886         .clkdm_name     = "abe_clkdm",
 887         /*
 888          * It's suspected that the McPDM requires an off-chip main
 889          * functional clock, controlled via I2C.  This IP block is
 890          * currently reset very early during boot, before I2C is
 891          * available, so it doesn't seem that we have any choice in
 892          * the kernel other than to avoid resetting it.  XXX This is
 893          * really a hardware issue workaround: every IP block should
 894          * be able to source its main functional clock from either
 895          * on-chip or off-chip sources.  McPDM seems to be the only
 896          * current exception.
 897          */
 898
 899         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
 900         .main_clk       = "pad_clks_ck",
 901         .prcm = {
 902                 .omap4 = {
 903                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
 904                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
 905                         .modulemode   = MODULEMODE_SWCTRL,
 906                 },
 907         },
 908 };
 909
 910 /*
 911  * 'mcspi' class
 912  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 913  * bus
 914  */
 915
 916 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
 917         .rev_offs       = 0x0000,
 918         .sysc_offs      = 0x0010,
 919         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 920                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 921         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 922                            SIDLE_SMART_WKUP),
 923         .sysc_fields    = &omap_hwmod_sysc_type2,
 924 };
 925
 926 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
 927         .name   = "mcspi",
 928         .sysc   = &omap54xx_mcspi_sysc,
 929         .rev    = OMAP4_MCSPI_REV,
 930 };
 931
 932 /* mcspi1 */
 933 /* mcspi1 dev_attr */
 934 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
 935         .num_chipselect = 4,
 936 };
 937
 938 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
 939         .name           = "mcspi1",
 940         .class          = &omap54xx_mcspi_hwmod_class,
 941         .clkdm_name     = "l4per_clkdm",
 942         .main_clk       = "func_48m_fclk",
 943         .prcm = {
 944                 .omap4 = {
 945                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
 946                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
 947                         .modulemode   = MODULEMODE_SWCTRL,
 948                 },
 949         },
 950         .dev_attr       = &mcspi1_dev_attr,
 951 };
 952
 953 /* mcspi2 */
 954 /* mcspi2 dev_attr */
 955 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
 956         .num_chipselect = 2,
 957 };
 958
 959 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
 960         .name           = "mcspi2",
 961         .class          = &omap54xx_mcspi_hwmod_class,
 962         .clkdm_name     = "l4per_clkdm",
 963         .main_clk       = "func_48m_fclk",
 964         .prcm = {
 965                 .omap4 = {
 966                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
 967                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
 968                         .modulemode   = MODULEMODE_SWCTRL,
 969                 },
 970         },
 971         .dev_attr       = &mcspi2_dev_attr,
 972 };
 973
 974 /* mcspi3 */
 975 /* mcspi3 dev_attr */
 976 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
 977         .num_chipselect = 2,
 978 };
 979
 980 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
 981         .name           = "mcspi3",
 982         .class          = &omap54xx_mcspi_hwmod_class,
 983         .clkdm_name     = "l4per_clkdm",
 984         .main_clk       = "func_48m_fclk",
 985         .prcm = {
 986                 .omap4 = {
 987                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
 988                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
 989                         .modulemode   = MODULEMODE_SWCTRL,
 990                 },
 991         },
 992         .dev_attr       = &mcspi3_dev_attr,
 993 };
 994
 995 /* mcspi4 */
 996 /* mcspi4 dev_attr */
 997 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
 998         .num_chipselect = 1,
 999 };
1000
1001 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1002         .name           = "mcspi4",
1003         .class          = &omap54xx_mcspi_hwmod_class,
1004         .clkdm_name     = "l4per_clkdm",
1005         .main_clk       = "func_48m_fclk",
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1010                         .modulemode   = MODULEMODE_SWCTRL,
1011                 },
1012         },
1013         .dev_attr       = &mcspi4_dev_attr,
1014 };
1015
1016 /*
1017  * 'mmc' class
1018  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1019  */
1020
1021 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1022         .rev_offs       = 0x0000,
1023         .sysc_offs      = 0x0010,
1024         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1025                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1026                            SYSC_HAS_SOFTRESET),
1027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1028                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1029                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1030         .sysc_fields    = &omap_hwmod_sysc_type2,
1031 };
1032
1033 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1034         .name   = "mmc",
1035         .sysc   = &omap54xx_mmc_sysc,
1036 };
1037
1038 /* mmc1 */
1039 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1040         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1041 };
1042
1043 /* mmc1 dev_attr */
1044 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1045         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1046 };
1047
1048 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1049         .name           = "mmc1",
1050         .class          = &omap54xx_mmc_hwmod_class,
1051         .clkdm_name     = "l3init_clkdm",
1052         .main_clk       = "mmc1_fclk",
1053         .prcm = {
1054                 .omap4 = {
1055                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1056                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1057                         .modulemode   = MODULEMODE_SWCTRL,
1058                 },
1059         },
1060         .opt_clks       = mmc1_opt_clks,
1061         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1062         .dev_attr       = &mmc1_dev_attr,
1063 };
1064
1065 /* mmc2 */
1066 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1067         .name           = "mmc2",
1068         .class          = &omap54xx_mmc_hwmod_class,
1069         .clkdm_name     = "l3init_clkdm",
1070         .main_clk       = "mmc2_fclk",
1071         .prcm = {
1072                 .omap4 = {
1073                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1074                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1075                         .modulemode   = MODULEMODE_SWCTRL,
1076                 },
1077         },
1078 };
1079
1080 /* mmc3 */
1081 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1082         .name           = "mmc3",
1083         .class          = &omap54xx_mmc_hwmod_class,
1084         .clkdm_name     = "l4per_clkdm",
1085         .main_clk       = "func_48m_fclk",
1086         .prcm = {
1087                 .omap4 = {
1088                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1089                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1090                         .modulemode   = MODULEMODE_SWCTRL,
1091                 },
1092         },
1093 };
1094
1095 /* mmc4 */
1096 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1097         .name           = "mmc4",
1098         .class          = &omap54xx_mmc_hwmod_class,
1099         .clkdm_name     = "l4per_clkdm",
1100         .main_clk       = "func_48m_fclk",
1101         .prcm = {
1102                 .omap4 = {
1103                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1104                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1105                         .modulemode   = MODULEMODE_SWCTRL,
1106                 },
1107         },
1108 };
1109
1110 /* mmc5 */
1111 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1112         .name           = "mmc5",
1113         .class          = &omap54xx_mmc_hwmod_class,
1114         .clkdm_name     = "l4per_clkdm",
1115         .main_clk       = "func_96m_fclk",
1116         .prcm = {
1117                 .omap4 = {
1118                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1119                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1120                         .modulemode   = MODULEMODE_SWCTRL,
1121                 },
1122         },
1123 };
1124
1125 /*
1126  * 'mpu' class
1127  * mpu sub-system
1128  */
1129
1130 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1131         .name   = "mpu",
1132 };
1133
1134 /* mpu */
1135 static struct omap_hwmod omap54xx_mpu_hwmod = {
1136         .name           = "mpu",
1137         .class          = &omap54xx_mpu_hwmod_class,
1138         .clkdm_name     = "mpu_clkdm",
1139         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1140         .main_clk       = "dpll_mpu_m2_ck",
1141         .prcm = {
1142                 .omap4 = {
1143                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1144                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1145                 },
1146         },
1147 };
1148
1149 /*
1150  * 'timer' class
1151  * general purpose timer module with accurate 1ms tick
1152  * This class contains several variants: ['timer_1ms', 'timer']
1153  */
1154
1155 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1156         .rev_offs       = 0x0000,
1157         .sysc_offs      = 0x0010,
1158         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1159                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1160         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1161                            SIDLE_SMART_WKUP),
1162         .sysc_fields    = &omap_hwmod_sysc_type2,
1163         .clockact       = CLOCKACT_TEST_ICLK,
1164 };
1165
1166 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1167         .name   = "timer",
1168         .sysc   = &omap54xx_timer_1ms_sysc,
1169 };
1170
1171 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1172         .rev_offs       = 0x0000,
1173         .sysc_offs      = 0x0010,
1174         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1175                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1176         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1177                            SIDLE_SMART_WKUP),
1178         .sysc_fields    = &omap_hwmod_sysc_type2,
1179 };
1180
1181 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1182         .name   = "timer",
1183         .sysc   = &omap54xx_timer_sysc,
1184 };
1185
1186 /* timer1 */
1187 static struct omap_hwmod omap54xx_timer1_hwmod = {
1188         .name           = "timer1",
1189         .class          = &omap54xx_timer_1ms_hwmod_class,
1190         .clkdm_name     = "wkupaon_clkdm",
1191         .main_clk       = "timer1_gfclk_mux",
1192         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1193         .prcm = {
1194                 .omap4 = {
1195                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1196                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1197                         .modulemode   = MODULEMODE_SWCTRL,
1198                 },
1199         },
1200 };
1201
1202 /* timer2 */
1203 static struct omap_hwmod omap54xx_timer2_hwmod = {
1204         .name           = "timer2",
1205         .class          = &omap54xx_timer_1ms_hwmod_class,
1206         .clkdm_name     = "l4per_clkdm",
1207         .main_clk       = "timer2_gfclk_mux",
1208         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1209         .prcm = {
1210                 .omap4 = {
1211                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1212                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1213                         .modulemode   = MODULEMODE_SWCTRL,
1214                 },
1215         },
1216 };
1217
1218 /* timer3 */
1219 static struct omap_hwmod omap54xx_timer3_hwmod = {
1220         .name           = "timer3",
1221         .class          = &omap54xx_timer_hwmod_class,
1222         .clkdm_name     = "l4per_clkdm",
1223         .main_clk       = "timer3_gfclk_mux",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_SWCTRL,
1229                 },
1230         },
1231 };
1232
1233 /* timer4 */
1234 static struct omap_hwmod omap54xx_timer4_hwmod = {
1235         .name           = "timer4",
1236         .class          = &omap54xx_timer_hwmod_class,
1237         .clkdm_name     = "l4per_clkdm",
1238         .main_clk       = "timer4_gfclk_mux",
1239         .prcm = {
1240                 .omap4 = {
1241                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1242                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1243                         .modulemode   = MODULEMODE_SWCTRL,
1244                 },
1245         },
1246 };
1247
1248 /* timer5 */
1249 static struct omap_hwmod omap54xx_timer5_hwmod = {
1250         .name           = "timer5",
1251         .class          = &omap54xx_timer_hwmod_class,
1252         .clkdm_name     = "abe_clkdm",
1253         .main_clk       = "timer5_gfclk_mux",
1254         .prcm = {
1255                 .omap4 = {
1256                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1257                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1258                         .modulemode   = MODULEMODE_SWCTRL,
1259                 },
1260         },
1261 };
1262
1263 /* timer6 */
1264 static struct omap_hwmod omap54xx_timer6_hwmod = {
1265         .name           = "timer6",
1266         .class          = &omap54xx_timer_hwmod_class,
1267         .clkdm_name     = "abe_clkdm",
1268         .main_clk       = "timer6_gfclk_mux",
1269         .prcm = {
1270                 .omap4 = {
1271                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1272                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1273                         .modulemode   = MODULEMODE_SWCTRL,
1274                 },
1275         },
1276 };
1277
1278 /* timer7 */
1279 static struct omap_hwmod omap54xx_timer7_hwmod = {
1280         .name           = "timer7",
1281         .class          = &omap54xx_timer_hwmod_class,
1282         .clkdm_name     = "abe_clkdm",
1283         .main_clk       = "timer7_gfclk_mux",
1284         .prcm = {
1285                 .omap4 = {
1286                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1287                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1288                         .modulemode   = MODULEMODE_SWCTRL,
1289                 },
1290         },
1291 };
1292
1293 /* timer8 */
1294 static struct omap_hwmod omap54xx_timer8_hwmod = {
1295         .name           = "timer8",
1296         .class          = &omap54xx_timer_hwmod_class,
1297         .clkdm_name     = "abe_clkdm",
1298         .main_clk       = "timer8_gfclk_mux",
1299         .prcm = {
1300                 .omap4 = {
1301                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1302                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1303                         .modulemode   = MODULEMODE_SWCTRL,
1304                 },
1305         },
1306 };
1307
1308 /* timer9 */
1309 static struct omap_hwmod omap54xx_timer9_hwmod = {
1310         .name           = "timer9",
1311         .class          = &omap54xx_timer_hwmod_class,
1312         .clkdm_name     = "l4per_clkdm",
1313         .main_clk       = "timer9_gfclk_mux",
1314         .prcm = {
1315                 .omap4 = {
1316                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1317                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1318                         .modulemode   = MODULEMODE_SWCTRL,
1319                 },
1320         },
1321 };
1322
1323 /* timer10 */
1324 static struct omap_hwmod omap54xx_timer10_hwmod = {
1325         .name           = "timer10",
1326         .class          = &omap54xx_timer_1ms_hwmod_class,
1327         .clkdm_name     = "l4per_clkdm",
1328         .main_clk       = "timer10_gfclk_mux",
1329         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1330         .prcm = {
1331                 .omap4 = {
1332                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1333                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1334                         .modulemode   = MODULEMODE_SWCTRL,
1335                 },
1336         },
1337 };
1338
1339 /* timer11 */
1340 static struct omap_hwmod omap54xx_timer11_hwmod = {
1341         .name           = "timer11",
1342         .class          = &omap54xx_timer_hwmod_class,
1343         .clkdm_name     = "l4per_clkdm",
1344         .main_clk       = "timer11_gfclk_mux",
1345         .prcm = {
1346                 .omap4 = {
1347                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1348                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1349                         .modulemode   = MODULEMODE_SWCTRL,
1350                 },
1351         },
1352 };
1353
1354 /*
1355  * 'uart' class
1356  * universal asynchronous receiver/transmitter (uart)
1357  */
1358
1359 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1360         .rev_offs       = 0x0050,
1361         .sysc_offs      = 0x0054,
1362         .syss_offs      = 0x0058,
1363         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1364                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1365                            SYSS_HAS_RESET_STATUS),
1366         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1367                            SIDLE_SMART_WKUP),
1368         .sysc_fields    = &omap_hwmod_sysc_type1,
1369 };
1370
1371 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1372         .name   = "uart",
1373         .sysc   = &omap54xx_uart_sysc,
1374 };
1375
1376 /* uart1 */
1377 static struct omap_hwmod omap54xx_uart1_hwmod = {
1378         .name           = "uart1",
1379         .class          = &omap54xx_uart_hwmod_class,
1380         .clkdm_name     = "l4per_clkdm",
1381         .main_clk       = "func_48m_fclk",
1382         .prcm = {
1383                 .omap4 = {
1384                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1385                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1386                         .modulemode   = MODULEMODE_SWCTRL,
1387                 },
1388         },
1389 };
1390
1391 /* uart2 */
1392 static struct omap_hwmod omap54xx_uart2_hwmod = {
1393         .name           = "uart2",
1394         .class          = &omap54xx_uart_hwmod_class,
1395         .clkdm_name     = "l4per_clkdm",
1396         .main_clk       = "func_48m_fclk",
1397         .prcm = {
1398                 .omap4 = {
1399                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1400                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1401                         .modulemode   = MODULEMODE_SWCTRL,
1402                 },
1403         },
1404 };
1405
1406 /* uart3 */
1407 static struct omap_hwmod omap54xx_uart3_hwmod = {
1408         .name           = "uart3",
1409         .class          = &omap54xx_uart_hwmod_class,
1410         .clkdm_name     = "l4per_clkdm",
1411         .flags          = DEBUG_OMAP4UART3_FLAGS,
1412         .main_clk       = "func_48m_fclk",
1413         .prcm = {
1414                 .omap4 = {
1415                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1416                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1417                         .modulemode   = MODULEMODE_SWCTRL,
1418                 },
1419         },
1420 };
1421
1422 /* uart4 */
1423 static struct omap_hwmod omap54xx_uart4_hwmod = {
1424         .name           = "uart4",
1425         .class          = &omap54xx_uart_hwmod_class,
1426         .clkdm_name     = "l4per_clkdm",
1427         .flags          = DEBUG_OMAP4UART4_FLAGS,
1428         .main_clk       = "func_48m_fclk",
1429         .prcm = {
1430                 .omap4 = {
1431                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1432                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1433                         .modulemode   = MODULEMODE_SWCTRL,
1434                 },
1435         },
1436 };
1437
1438 /* uart5 */
1439 static struct omap_hwmod omap54xx_uart5_hwmod = {
1440         .name           = "uart5",
1441         .class          = &omap54xx_uart_hwmod_class,
1442         .clkdm_name     = "l4per_clkdm",
1443         .main_clk       = "func_48m_fclk",
1444         .prcm = {
1445                 .omap4 = {
1446                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1447                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1448                         .modulemode   = MODULEMODE_SWCTRL,
1449                 },
1450         },
1451 };
1452
1453 /* uart6 */
1454 static struct omap_hwmod omap54xx_uart6_hwmod = {
1455         .name           = "uart6",
1456         .class          = &omap54xx_uart_hwmod_class,
1457         .clkdm_name     = "l4per_clkdm",
1458         .main_clk       = "func_48m_fclk",
1459         .prcm = {
1460                 .omap4 = {
1461                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1462                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1463                         .modulemode   = MODULEMODE_SWCTRL,
1464                 },
1465         },
1466 };
1467
1468 /*
1469  * 'usb_otg_ss' class
1470  * 2.0 super speed (usb_otg_ss) controller
1471  */
1472
1473 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1474         .rev_offs       = 0x0000,
1475         .sysc_offs      = 0x0010,
1476         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1477                            SYSC_HAS_SIDLEMODE),
1478         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1479                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1480                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1481         .sysc_fields    = &omap_hwmod_sysc_type2,
1482 };
1483
1484 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1485         .name   = "usb_otg_ss",
1486         .sysc   = &omap54xx_usb_otg_ss_sysc,
1487 };
1488
1489 /* usb_otg_ss */
1490 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1491         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1492 };
1493
1494 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1495         .name           = "usb_otg_ss",
1496         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1497         .clkdm_name     = "l3init_clkdm",
1498         .flags          = HWMOD_SWSUP_SIDLE,
1499         .main_clk       = "dpll_core_h13x2_ck",
1500         .prcm = {
1501                 .omap4 = {
1502                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1503                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1504                         .modulemode   = MODULEMODE_HWCTRL,
1505                 },
1506         },
1507         .opt_clks       = usb_otg_ss_opt_clks,
1508         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1509 };
1510
1511 /*
1512  * 'wd_timer' class
1513  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1514  * overflow condition
1515  */
1516
1517 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1518         .rev_offs       = 0x0000,
1519         .sysc_offs      = 0x0010,
1520         .syss_offs      = 0x0014,
1521         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1522                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1523         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1524                            SIDLE_SMART_WKUP),
1525         .sysc_fields    = &omap_hwmod_sysc_type1,
1526 };
1527
1528 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1529         .name           = "wd_timer",
1530         .sysc           = &omap54xx_wd_timer_sysc,
1531         .pre_shutdown   = &omap2_wd_timer_disable,
1532 };
1533
1534 /* wd_timer2 */
1535 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1536         .name           = "wd_timer2",
1537         .class          = &omap54xx_wd_timer_hwmod_class,
1538         .clkdm_name     = "wkupaon_clkdm",
1539         .main_clk       = "sys_32k_ck",
1540         .prcm = {
1541                 .omap4 = {
1542                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1543                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1544                         .modulemode   = MODULEMODE_SWCTRL,
1545                 },
1546         },
1547 };
1548
1549
1550 /*
1551  * Interfaces
1552  */
1553
1554 /* l3_main_1 -> dmm */
1555 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1556         .master         = &omap54xx_l3_main_1_hwmod,
1557         .slave          = &omap54xx_dmm_hwmod,
1558         .clk            = "l3_iclk_div",
1559         .user           = OCP_USER_SDMA,
1560 };
1561
1562 /* l3_main_3 -> l3_instr */
1563 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1564         .master         = &omap54xx_l3_main_3_hwmod,
1565         .slave          = &omap54xx_l3_instr_hwmod,
1566         .clk            = "l3_iclk_div",
1567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1568 };
1569
1570 /* l3_main_2 -> l3_main_1 */
1571 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1572         .master         = &omap54xx_l3_main_2_hwmod,
1573         .slave          = &omap54xx_l3_main_1_hwmod,
1574         .clk            = "l3_iclk_div",
1575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1576 };
1577
1578 /* l4_cfg -> l3_main_1 */
1579 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1580         .master         = &omap54xx_l4_cfg_hwmod,
1581         .slave          = &omap54xx_l3_main_1_hwmod,
1582         .clk            = "l3_iclk_div",
1583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1584 };
1585
1586 /* mpu -> l3_main_1 */
1587 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1588         .master         = &omap54xx_mpu_hwmod,
1589         .slave          = &omap54xx_l3_main_1_hwmod,
1590         .clk            = "l3_iclk_div",
1591         .user           = OCP_USER_MPU,
1592 };
1593
1594 /* l3_main_1 -> l3_main_2 */
1595 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1596         .master         = &omap54xx_l3_main_1_hwmod,
1597         .slave          = &omap54xx_l3_main_2_hwmod,
1598         .clk            = "l3_iclk_div",
1599         .user           = OCP_USER_MPU,
1600 };
1601
1602 /* l4_cfg -> l3_main_2 */
1603 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1604         .master         = &omap54xx_l4_cfg_hwmod,
1605         .slave          = &omap54xx_l3_main_2_hwmod,
1606         .clk            = "l3_iclk_div",
1607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1608 };
1609
1610 /* l3_main_1 -> l3_main_3 */
1611 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1612         .master         = &omap54xx_l3_main_1_hwmod,
1613         .slave          = &omap54xx_l3_main_3_hwmod,
1614         .clk            = "l3_iclk_div",
1615         .user           = OCP_USER_MPU,
1616 };
1617
1618 /* l3_main_2 -> l3_main_3 */
1619 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1620         .master         = &omap54xx_l3_main_2_hwmod,
1621         .slave          = &omap54xx_l3_main_3_hwmod,
1622         .clk            = "l3_iclk_div",
1623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1624 };
1625
1626 /* l4_cfg -> l3_main_3 */
1627 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1628         .master         = &omap54xx_l4_cfg_hwmod,
1629         .slave          = &omap54xx_l3_main_3_hwmod,
1630         .clk            = "l3_iclk_div",
1631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1632 };
1633
1634 /* l3_main_1 -> l4_abe */
1635 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1636         .master         = &omap54xx_l3_main_1_hwmod,
1637         .slave          = &omap54xx_l4_abe_hwmod,
1638         .clk            = "abe_iclk",
1639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1640 };
1641
1642 /* mpu -> l4_abe */
1643 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1644         .master         = &omap54xx_mpu_hwmod,
1645         .slave          = &omap54xx_l4_abe_hwmod,
1646         .clk            = "abe_iclk",
1647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1648 };
1649
1650 /* l3_main_1 -> l4_cfg */
1651 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1652         .master         = &omap54xx_l3_main_1_hwmod,
1653         .slave          = &omap54xx_l4_cfg_hwmod,
1654         .clk            = "l4_root_clk_div",
1655         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1656 };
1657
1658 /* l3_main_2 -> l4_per */
1659 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1660         .master         = &omap54xx_l3_main_2_hwmod,
1661         .slave          = &omap54xx_l4_per_hwmod,
1662         .clk            = "l4_root_clk_div",
1663         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1664 };
1665
1666 /* l3_main_1 -> l4_wkup */
1667 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1668         .master         = &omap54xx_l3_main_1_hwmod,
1669         .slave          = &omap54xx_l4_wkup_hwmod,
1670         .clk            = "wkupaon_iclk_mux",
1671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1672 };
1673
1674 /* mpu -> mpu_private */
1675 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1676         .master         = &omap54xx_mpu_hwmod,
1677         .slave          = &omap54xx_mpu_private_hwmod,
1678         .clk            = "l3_iclk_div",
1679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1680 };
1681
1682 /* l4_wkup -> counter_32k */
1683 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1684         .master         = &omap54xx_l4_wkup_hwmod,
1685         .slave          = &omap54xx_counter_32k_hwmod,
1686         .clk            = "wkupaon_iclk_mux",
1687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1688 };
1689
1690 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1691         {
1692                 .pa_start       = 0x4a056000,
1693                 .pa_end         = 0x4a056fff,
1694                 .flags          = ADDR_TYPE_RT
1695         },
1696         { }
1697 };
1698
1699 /* l4_cfg -> dma_system */
1700 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1701         .master         = &omap54xx_l4_cfg_hwmod,
1702         .slave          = &omap54xx_dma_system_hwmod,
1703         .clk            = "l4_root_clk_div",
1704         .addr           = omap54xx_dma_system_addrs,
1705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1706 };
1707
1708 /* l4_abe -> dmic */
1709 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1710         .master         = &omap54xx_l4_abe_hwmod,
1711         .slave          = &omap54xx_dmic_hwmod,
1712         .clk            = "abe_iclk",
1713         .user           = OCP_USER_MPU,
1714 };
1715
1716 /* mpu -> emif1 */
1717 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1718         .master         = &omap54xx_mpu_hwmod,
1719         .slave          = &omap54xx_emif1_hwmod,
1720         .clk            = "dpll_core_h11x2_ck",
1721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1722 };
1723
1724 /* mpu -> emif2 */
1725 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1726         .master         = &omap54xx_mpu_hwmod,
1727         .slave          = &omap54xx_emif2_hwmod,
1728         .clk            = "dpll_core_h11x2_ck",
1729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1730 };
1731
1732 /* l4_wkup -> gpio1 */
1733 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1734         .master         = &omap54xx_l4_wkup_hwmod,
1735         .slave          = &omap54xx_gpio1_hwmod,
1736         .clk            = "wkupaon_iclk_mux",
1737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1738 };
1739
1740 /* l4_per -> gpio2 */
1741 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1742         .master         = &omap54xx_l4_per_hwmod,
1743         .slave          = &omap54xx_gpio2_hwmod,
1744         .clk            = "l4_root_clk_div",
1745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1746 };
1747
1748 /* l4_per -> gpio3 */
1749 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1750         .master         = &omap54xx_l4_per_hwmod,
1751         .slave          = &omap54xx_gpio3_hwmod,
1752         .clk            = "l4_root_clk_div",
1753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1754 };
1755
1756 /* l4_per -> gpio4 */
1757 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1758         .master         = &omap54xx_l4_per_hwmod,
1759         .slave          = &omap54xx_gpio4_hwmod,
1760         .clk            = "l4_root_clk_div",
1761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1762 };
1763
1764 /* l4_per -> gpio5 */
1765 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1766         .master         = &omap54xx_l4_per_hwmod,
1767         .slave          = &omap54xx_gpio5_hwmod,
1768         .clk            = "l4_root_clk_div",
1769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1770 };
1771
1772 /* l4_per -> gpio6 */
1773 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1774         .master         = &omap54xx_l4_per_hwmod,
1775         .slave          = &omap54xx_gpio6_hwmod,
1776         .clk            = "l4_root_clk_div",
1777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1778 };
1779
1780 /* l4_per -> gpio7 */
1781 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1782         .master         = &omap54xx_l4_per_hwmod,
1783         .slave          = &omap54xx_gpio7_hwmod,
1784         .clk            = "l4_root_clk_div",
1785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1786 };
1787
1788 /* l4_per -> gpio8 */
1789 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1790         .master         = &omap54xx_l4_per_hwmod,
1791         .slave          = &omap54xx_gpio8_hwmod,
1792         .clk            = "l4_root_clk_div",
1793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1794 };
1795
1796 /* l4_per -> i2c1 */
1797 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1798         .master         = &omap54xx_l4_per_hwmod,
1799         .slave          = &omap54xx_i2c1_hwmod,
1800         .clk            = "l4_root_clk_div",
1801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1802 };
1803
1804 /* l4_per -> i2c2 */
1805 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1806         .master         = &omap54xx_l4_per_hwmod,
1807         .slave          = &omap54xx_i2c2_hwmod,
1808         .clk            = "l4_root_clk_div",
1809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1810 };
1811
1812 /* l4_per -> i2c3 */
1813 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1814         .master         = &omap54xx_l4_per_hwmod,
1815         .slave          = &omap54xx_i2c3_hwmod,
1816         .clk            = "l4_root_clk_div",
1817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1818 };
1819
1820 /* l4_per -> i2c4 */
1821 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1822         .master         = &omap54xx_l4_per_hwmod,
1823         .slave          = &omap54xx_i2c4_hwmod,
1824         .clk            = "l4_root_clk_div",
1825         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1826 };
1827
1828 /* l4_per -> i2c5 */
1829 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1830         .master         = &omap54xx_l4_per_hwmod,
1831         .slave          = &omap54xx_i2c5_hwmod,
1832         .clk            = "l4_root_clk_div",
1833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1834 };
1835
1836 /* l4_wkup -> kbd */
1837 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1838         .master         = &omap54xx_l4_wkup_hwmod,
1839         .slave          = &omap54xx_kbd_hwmod,
1840         .clk            = "wkupaon_iclk_mux",
1841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1842 };
1843
1844 /* l4_cfg -> mailbox */
1845 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
1846         .master         = &omap54xx_l4_cfg_hwmod,
1847         .slave          = &omap54xx_mailbox_hwmod,
1848         .clk            = "l4_root_clk_div",
1849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1850 };
1851
1852 /* l4_abe -> mcbsp1 */
1853 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1854         .master         = &omap54xx_l4_abe_hwmod,
1855         .slave          = &omap54xx_mcbsp1_hwmod,
1856         .clk            = "abe_iclk",
1857         .user           = OCP_USER_MPU,
1858 };
1859
1860 /* l4_abe -> mcbsp2 */
1861 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1862         .master         = &omap54xx_l4_abe_hwmod,
1863         .slave          = &omap54xx_mcbsp2_hwmod,
1864         .clk            = "abe_iclk",
1865         .user           = OCP_USER_MPU,
1866 };
1867
1868 /* l4_abe -> mcbsp3 */
1869 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1870         .master         = &omap54xx_l4_abe_hwmod,
1871         .slave          = &omap54xx_mcbsp3_hwmod,
1872         .clk            = "abe_iclk",
1873         .user           = OCP_USER_MPU,
1874 };
1875
1876 /* l4_abe -> mcpdm */
1877 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1878         .master         = &omap54xx_l4_abe_hwmod,
1879         .slave          = &omap54xx_mcpdm_hwmod,
1880         .clk            = "abe_iclk",
1881         .user           = OCP_USER_MPU,
1882 };
1883
1884 /* l4_per -> mcspi1 */
1885 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1886         .master         = &omap54xx_l4_per_hwmod,
1887         .slave          = &omap54xx_mcspi1_hwmod,
1888         .clk            = "l4_root_clk_div",
1889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1890 };
1891
1892 /* l4_per -> mcspi2 */
1893 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1894         .master         = &omap54xx_l4_per_hwmod,
1895         .slave          = &omap54xx_mcspi2_hwmod,
1896         .clk            = "l4_root_clk_div",
1897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1898 };
1899
1900 /* l4_per -> mcspi3 */
1901 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1902         .master         = &omap54xx_l4_per_hwmod,
1903         .slave          = &omap54xx_mcspi3_hwmod,
1904         .clk            = "l4_root_clk_div",
1905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1906 };
1907
1908 /* l4_per -> mcspi4 */
1909 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1910         .master         = &omap54xx_l4_per_hwmod,
1911         .slave          = &omap54xx_mcspi4_hwmod,
1912         .clk            = "l4_root_clk_div",
1913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1914 };
1915
1916 /* l4_per -> mmc1 */
1917 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
1918         .master         = &omap54xx_l4_per_hwmod,
1919         .slave          = &omap54xx_mmc1_hwmod,
1920         .clk            = "l3_iclk_div",
1921         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1922 };
1923
1924 /* l4_per -> mmc2 */
1925 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
1926         .master         = &omap54xx_l4_per_hwmod,
1927         .slave          = &omap54xx_mmc2_hwmod,
1928         .clk            = "l3_iclk_div",
1929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1930 };
1931
1932 /* l4_per -> mmc3 */
1933 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
1934         .master         = &omap54xx_l4_per_hwmod,
1935         .slave          = &omap54xx_mmc3_hwmod,
1936         .clk            = "l4_root_clk_div",
1937         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1938 };
1939
1940 /* l4_per -> mmc4 */
1941 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
1942         .master         = &omap54xx_l4_per_hwmod,
1943         .slave          = &omap54xx_mmc4_hwmod,
1944         .clk            = "l4_root_clk_div",
1945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1946 };
1947
1948 /* l4_per -> mmc5 */
1949 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
1950         .master         = &omap54xx_l4_per_hwmod,
1951         .slave          = &omap54xx_mmc5_hwmod,
1952         .clk            = "l4_root_clk_div",
1953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1954 };
1955
1956 /* l4_cfg -> mpu */
1957 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1958         .master         = &omap54xx_l4_cfg_hwmod,
1959         .slave          = &omap54xx_mpu_hwmod,
1960         .clk            = "l4_root_clk_div",
1961         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1962 };
1963
1964 /* l4_wkup -> timer1 */
1965 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1966         .master         = &omap54xx_l4_wkup_hwmod,
1967         .slave          = &omap54xx_timer1_hwmod,
1968         .clk            = "wkupaon_iclk_mux",
1969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1970 };
1971
1972 /* l4_per -> timer2 */
1973 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1974         .master         = &omap54xx_l4_per_hwmod,
1975         .slave          = &omap54xx_timer2_hwmod,
1976         .clk            = "l4_root_clk_div",
1977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1978 };
1979
1980 /* l4_per -> timer3 */
1981 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1982         .master         = &omap54xx_l4_per_hwmod,
1983         .slave          = &omap54xx_timer3_hwmod,
1984         .clk            = "l4_root_clk_div",
1985         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1986 };
1987
1988 /* l4_per -> timer4 */
1989 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1990         .master         = &omap54xx_l4_per_hwmod,
1991         .slave          = &omap54xx_timer4_hwmod,
1992         .clk            = "l4_root_clk_div",
1993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1994 };
1995
1996 /* l4_abe -> timer5 */
1997 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1998         .master         = &omap54xx_l4_abe_hwmod,
1999         .slave          = &omap54xx_timer5_hwmod,
2000         .clk            = "abe_iclk",
2001         .user           = OCP_USER_MPU,
2002 };
2003
2004 /* l4_abe -> timer6 */
2005 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2006         .master         = &omap54xx_l4_abe_hwmod,
2007         .slave          = &omap54xx_timer6_hwmod,
2008         .clk            = "abe_iclk",
2009         .user           = OCP_USER_MPU,
2010 };
2011
2012 /* l4_abe -> timer7 */
2013 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2014         .master         = &omap54xx_l4_abe_hwmod,
2015         .slave          = &omap54xx_timer7_hwmod,
2016         .clk            = "abe_iclk",
2017         .user           = OCP_USER_MPU,
2018 };
2019
2020 /* l4_abe -> timer8 */
2021 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2022         .master         = &omap54xx_l4_abe_hwmod,
2023         .slave          = &omap54xx_timer8_hwmod,
2024         .clk            = "abe_iclk",
2025         .user           = OCP_USER_MPU,
2026 };
2027
2028 /* l4_per -> timer9 */
2029 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2030         .master         = &omap54xx_l4_per_hwmod,
2031         .slave          = &omap54xx_timer9_hwmod,
2032         .clk            = "l4_root_clk_div",
2033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2034 };
2035
2036 /* l4_per -> timer10 */
2037 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2038         .master         = &omap54xx_l4_per_hwmod,
2039         .slave          = &omap54xx_timer10_hwmod,
2040         .clk            = "l4_root_clk_div",
2041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2042 };
2043
2044 /* l4_per -> timer11 */
2045 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2046         .master         = &omap54xx_l4_per_hwmod,
2047         .slave          = &omap54xx_timer11_hwmod,
2048         .clk            = "l4_root_clk_div",
2049         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2050 };
2051
2052 /* l4_per -> uart1 */
2053 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2054         .master         = &omap54xx_l4_per_hwmod,
2055         .slave          = &omap54xx_uart1_hwmod,
2056         .clk            = "l4_root_clk_div",
2057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2058 };
2059
2060 /* l4_per -> uart2 */
2061 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2062         .master         = &omap54xx_l4_per_hwmod,
2063         .slave          = &omap54xx_uart2_hwmod,
2064         .clk            = "l4_root_clk_div",
2065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2066 };
2067
2068 /* l4_per -> uart3 */
2069 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2070         .master         = &omap54xx_l4_per_hwmod,
2071         .slave          = &omap54xx_uart3_hwmod,
2072         .clk            = "l4_root_clk_div",
2073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2074 };
2075
2076 /* l4_per -> uart4 */
2077 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2078         .master         = &omap54xx_l4_per_hwmod,
2079         .slave          = &omap54xx_uart4_hwmod,
2080         .clk            = "l4_root_clk_div",
2081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2082 };
2083
2084 /* l4_per -> uart5 */
2085 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2086         .master         = &omap54xx_l4_per_hwmod,
2087         .slave          = &omap54xx_uart5_hwmod,
2088         .clk            = "l4_root_clk_div",
2089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2090 };
2091
2092 /* l4_per -> uart6 */
2093 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2094         .master         = &omap54xx_l4_per_hwmod,
2095         .slave          = &omap54xx_uart6_hwmod,
2096         .clk            = "l4_root_clk_div",
2097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2098 };
2099
2100 /* l4_cfg -> usb_otg_ss */
2101 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2102         .master         = &omap54xx_l4_cfg_hwmod,
2103         .slave          = &omap54xx_usb_otg_ss_hwmod,
2104         .clk            = "dpll_core_h13x2_ck",
2105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2106 };
2107
2108 /* l4_wkup -> wd_timer2 */
2109 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2110         .master         = &omap54xx_l4_wkup_hwmod,
2111         .slave          = &omap54xx_wd_timer2_hwmod,
2112         .clk            = "wkupaon_iclk_mux",
2113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2114 };
2115
2116 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2117         &omap54xx_l3_main_1__dmm,
2118         &omap54xx_l3_main_3__l3_instr,
2119         &omap54xx_l3_main_2__l3_main_1,
2120         &omap54xx_l4_cfg__l3_main_1,
2121         &omap54xx_mpu__l3_main_1,
2122         &omap54xx_l3_main_1__l3_main_2,
2123         &omap54xx_l4_cfg__l3_main_2,
2124         &omap54xx_l3_main_1__l3_main_3,
2125         &omap54xx_l3_main_2__l3_main_3,
2126         &omap54xx_l4_cfg__l3_main_3,
2127         &omap54xx_l3_main_1__l4_abe,
2128         &omap54xx_mpu__l4_abe,
2129         &omap54xx_l3_main_1__l4_cfg,
2130         &omap54xx_l3_main_2__l4_per,
2131         &omap54xx_l3_main_1__l4_wkup,
2132         &omap54xx_mpu__mpu_private,
2133         &omap54xx_l4_wkup__counter_32k,
2134         &omap54xx_l4_cfg__dma_system,
2135         &omap54xx_l4_abe__dmic,
2136         &omap54xx_mpu__emif1,
2137         &omap54xx_mpu__emif2,
2138         &omap54xx_l4_wkup__gpio1,
2139         &omap54xx_l4_per__gpio2,
2140         &omap54xx_l4_per__gpio3,
2141         &omap54xx_l4_per__gpio4,
2142         &omap54xx_l4_per__gpio5,
2143         &omap54xx_l4_per__gpio6,
2144         &omap54xx_l4_per__gpio7,
2145         &omap54xx_l4_per__gpio8,
2146         &omap54xx_l4_per__i2c1,
2147         &omap54xx_l4_per__i2c2,
2148         &omap54xx_l4_per__i2c3,
2149         &omap54xx_l4_per__i2c4,
2150         &omap54xx_l4_per__i2c5,
2151         &omap54xx_l4_wkup__kbd,
2152         &omap54xx_l4_cfg__mailbox,
2153         &omap54xx_l4_abe__mcbsp1,
2154         &omap54xx_l4_abe__mcbsp2,
2155         &omap54xx_l4_abe__mcbsp3,
2156         &omap54xx_l4_abe__mcpdm,
2157         &omap54xx_l4_per__mcspi1,
2158         &omap54xx_l4_per__mcspi2,
2159         &omap54xx_l4_per__mcspi3,
2160         &omap54xx_l4_per__mcspi4,
2161         &omap54xx_l4_per__mmc1,
2162         &omap54xx_l4_per__mmc2,
2163         &omap54xx_l4_per__mmc3,
2164         &omap54xx_l4_per__mmc4,
2165         &omap54xx_l4_per__mmc5,
2166         &omap54xx_l4_cfg__mpu,
2167         &omap54xx_l4_wkup__timer1,
2168         &omap54xx_l4_per__timer2,
2169         &omap54xx_l4_per__timer3,
2170         &omap54xx_l4_per__timer4,
2171         &omap54xx_l4_abe__timer5,
2172         &omap54xx_l4_abe__timer6,
2173         &omap54xx_l4_abe__timer7,
2174         &omap54xx_l4_abe__timer8,
2175         &omap54xx_l4_per__timer9,
2176         &omap54xx_l4_per__timer10,
2177         &omap54xx_l4_per__timer11,
2178         &omap54xx_l4_per__uart1,
2179         &omap54xx_l4_per__uart2,
2180         &omap54xx_l4_per__uart3,
2181         &omap54xx_l4_per__uart4,
2182         &omap54xx_l4_per__uart5,
2183         &omap54xx_l4_per__uart6,
2184         &omap54xx_l4_cfg__usb_otg_ss,
2185         &omap54xx_l4_wkup__wd_timer2,
2186         NULL,
2187 };
2188
2189 int __init omap54xx_hwmod_init(void)
2190 {
2191         omap_hwmod_init();
2192         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2193 }