arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <plat/omap_hwmod.h>
  27 #include <plat-omap/dma-omap.h>
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30 #include <plat/dmtimer.h>
  31 #include <plat/iommu.h>
  32
  33 #include "../plat-omap/common.h"
  34
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "i2c.h"
  41 #include "mmc.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'c2c_target_fw' class
  56  * instance(s): c2c_target_fw
  57  */
  58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  59         .name   = "c2c_target_fw",
  60 };
  61
  62 /* c2c_target_fw */
  63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  64         .name           = "c2c_target_fw",
  65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  66         .clkdm_name     = "d2d_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 static struct omap_hwmod omap44xx_dmm_hwmod = {
  90         .name           = "dmm",
  91         .class          = &omap44xx_dmm_hwmod_class,
  92         .clkdm_name     = "l3_emif_clkdm",
  93         .mpu_irqs       = omap44xx_dmm_irqs,
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /*
 103  * 'emif_fw' class
 104  * instance(s): emif_fw
 105  */
 106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 107         .name   = "emif_fw",
 108 };
 109
 110 /* emif_fw */
 111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 112         .name           = "emif_fw",
 113         .class          = &omap44xx_emif_fw_hwmod_class,
 114         .clkdm_name     = "l3_emif_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /*
 124  * 'l3' class
 125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 126  */
 127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 128         .name   = "l3",
 129 };
 130
 131 /* l3_instr */
 132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 133         .name           = "l3_instr",
 134         .class          = &omap44xx_l3_hwmod_class,
 135         .clkdm_name     = "l3_instr_clkdm",
 136         .prcm = {
 137                 .omap4 = {
 138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 140                         .modulemode   = MODULEMODE_HWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /* l3_main_1 */
 146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 149         { .irq = -1 }
 150 };
 151
 152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 153         .name           = "l3_main_1",
 154         .class          = &omap44xx_l3_hwmod_class,
 155         .clkdm_name     = "l3_1_clkdm",
 156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 157         .prcm = {
 158                 .omap4 = {
 159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 161                 },
 162         },
 163 };
 164
 165 /* l3_main_2 */
 166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 167         .name           = "l3_main_2",
 168         .class          = &omap44xx_l3_hwmod_class,
 169         .clkdm_name     = "l3_2_clkdm",
 170         .prcm = {
 171                 .omap4 = {
 172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 174                 },
 175         },
 176 };
 177
 178 /* l3_main_3 */
 179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 180         .name           = "l3_main_3",
 181         .class          = &omap44xx_l3_hwmod_class,
 182         .clkdm_name     = "l3_instr_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 187                         .modulemode   = MODULEMODE_HWCTRL,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * 'l4' class
 194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 195  */
 196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 197         .name   = "l4",
 198 };
 199
 200 /* l4_abe */
 201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 202         .name           = "l4_abe",
 203         .class          = &omap44xx_l4_hwmod_class,
 204         .clkdm_name     = "abe_clkdm",
 205         .prcm = {
 206                 .omap4 = {
 207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 211                 },
 212         },
 213 };
 214
 215 /* l4_cfg */
 216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 217         .name           = "l4_cfg",
 218         .class          = &omap44xx_l4_hwmod_class,
 219         .clkdm_name     = "l4_cfg_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 224                 },
 225         },
 226 };
 227
 228 /* l4_per */
 229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 230         .name           = "l4_per",
 231         .class          = &omap44xx_l4_hwmod_class,
 232         .clkdm_name     = "l4_per_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 237                 },
 238         },
 239 };
 240
 241 /* l4_wkup */
 242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 243         .name           = "l4_wkup",
 244         .class          = &omap44xx_l4_hwmod_class,
 245         .clkdm_name     = "l4_wkup_clkdm",
 246         .prcm = {
 247                 .omap4 = {
 248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 250                 },
 251         },
 252 };
 253
 254 /*
 255  * 'mpu_bus' class
 256  * instance(s): mpu_private
 257  */
 258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 259         .name   = "mpu_bus",
 260 };
 261
 262 /* mpu_private */
 263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 264         .name           = "mpu_private",
 265         .class          = &omap44xx_mpu_bus_hwmod_class,
 266         .clkdm_name     = "mpuss_clkdm",
 267         .prcm = {
 268                 .omap4 = {
 269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 270                 },
 271         },
 272 };
 273
 274 /*
 275  * 'ocp_wp_noc' class
 276  * instance(s): ocp_wp_noc
 277  */
 278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 279         .name   = "ocp_wp_noc",
 280 };
 281
 282 /* ocp_wp_noc */
 283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 284         .name           = "ocp_wp_noc",
 285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 286         .clkdm_name     = "l3_instr_clkdm",
 287         .prcm = {
 288                 .omap4 = {
 289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 291                         .modulemode   = MODULEMODE_HWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /*
 297  * Modules omap_hwmod structures
 298  *
 299  * The following IPs are excluded for the moment because:
 300  * - They do not need an explicit SW control using omap_hwmod API.
 301  * - They still need to be validated with the driver
 302  *   properly adapted to omap_hwmod / omap_device
 303  *
 304  * usim
 305  */
 306
 307 /*
 308  * 'aess' class
 309  * audio engine sub system
 310  */
 311
 312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 313         .rev_offs       = 0x0000,
 314         .sysc_offs      = 0x0010,
 315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 318                            MSTANDBY_SMART_WKUP),
 319         .sysc_fields    = &omap_hwmod_sysc_type2,
 320 };
 321
 322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 323         .name   = "aess",
 324         .sysc   = &omap44xx_aess_sysc,
 325 };
 326
 327 /* aess */
 328 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 329         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 330         { .irq = -1 }
 331 };
 332
 333 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 334         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 342         { .dma_req = -1 }
 343 };
 344
 345 static struct omap_hwmod omap44xx_aess_hwmod = {
 346         .name           = "aess",
 347         .class          = &omap44xx_aess_hwmod_class,
 348         .clkdm_name     = "abe_clkdm",
 349         .mpu_irqs       = omap44xx_aess_irqs,
 350         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 351         .main_clk       = "aess_fck",
 352         .prcm = {
 353                 .omap4 = {
 354                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 355                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 356                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 357                         .modulemode   = MODULEMODE_SWCTRL,
 358                 },
 359         },
 360 };
 361
 362 /*
 363  * 'c2c' class
 364  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 365  * soc
 366  */
 367
 368 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 369         .name   = "c2c",
 370 };
 371
 372 /* c2c */
 373 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 374         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 375         { .irq = -1 }
 376 };
 377
 378 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 379         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 380         { .dma_req = -1 }
 381 };
 382
 383 static struct omap_hwmod omap44xx_c2c_hwmod = {
 384         .name           = "c2c",
 385         .class          = &omap44xx_c2c_hwmod_class,
 386         .clkdm_name     = "d2d_clkdm",
 387         .mpu_irqs       = omap44xx_c2c_irqs,
 388         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 389         .prcm = {
 390                 .omap4 = {
 391                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 392                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 393                 },
 394         },
 395 };
 396
 397 /*
 398  * 'counter' class
 399  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 400  */
 401
 402 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 403         .rev_offs       = 0x0000,
 404         .sysc_offs      = 0x0004,
 405         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 407         .sysc_fields    = &omap_hwmod_sysc_type1,
 408 };
 409
 410 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 411         .name   = "counter",
 412         .sysc   = &omap44xx_counter_sysc,
 413 };
 414
 415 /* counter_32k */
 416 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 417         .name           = "counter_32k",
 418         .class          = &omap44xx_counter_hwmod_class,
 419         .clkdm_name     = "l4_wkup_clkdm",
 420         .flags          = HWMOD_SWSUP_SIDLE,
 421         .main_clk       = "sys_32k_ck",
 422         .prcm = {
 423                 .omap4 = {
 424                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 425                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 426                 },
 427         },
 428 };
 429
 430 /*
 431  * 'ctrl_module' class
 432  * attila core control module + core pad control module + wkup pad control
 433  * module + attila wkup control module
 434  */
 435
 436 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 437         .rev_offs       = 0x0000,
 438         .sysc_offs      = 0x0010,
 439         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 441                            SIDLE_SMART_WKUP),
 442         .sysc_fields    = &omap_hwmod_sysc_type2,
 443 };
 444
 445 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 446         .name   = "ctrl_module",
 447         .sysc   = &omap44xx_ctrl_module_sysc,
 448 };
 449
 450 /* ctrl_module_core */
 451 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 452         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 453         { .irq = -1 }
 454 };
 455
 456 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 457         .name           = "ctrl_module_core",
 458         .class          = &omap44xx_ctrl_module_hwmod_class,
 459         .clkdm_name     = "l4_cfg_clkdm",
 460         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 461         .prcm = {
 462                 .omap4 = {
 463                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 464                 },
 465         },
 466 };
 467
 468 /* ctrl_module_pad_core */
 469 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 470         .name           = "ctrl_module_pad_core",
 471         .class          = &omap44xx_ctrl_module_hwmod_class,
 472         .clkdm_name     = "l4_cfg_clkdm",
 473         .prcm = {
 474                 .omap4 = {
 475                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 476                 },
 477         },
 478 };
 479
 480 /* ctrl_module_wkup */
 481 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 482         .name           = "ctrl_module_wkup",
 483         .class          = &omap44xx_ctrl_module_hwmod_class,
 484         .clkdm_name     = "l4_wkup_clkdm",
 485         .prcm = {
 486                 .omap4 = {
 487                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 488                 },
 489         },
 490 };
 491
 492 /* ctrl_module_pad_wkup */
 493 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 494         .name           = "ctrl_module_pad_wkup",
 495         .class          = &omap44xx_ctrl_module_hwmod_class,
 496         .clkdm_name     = "l4_wkup_clkdm",
 497         .prcm = {
 498                 .omap4 = {
 499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 500                 },
 501         },
 502 };
 503
 504 /*
 505  * 'debugss' class
 506  * debug and emulation sub system
 507  */
 508
 509 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 510         .name   = "debugss",
 511 };
 512
 513 /* debugss */
 514 static struct omap_hwmod omap44xx_debugss_hwmod = {
 515         .name           = "debugss",
 516         .class          = &omap44xx_debugss_hwmod_class,
 517         .clkdm_name     = "emu_sys_clkdm",
 518         .main_clk       = "trace_clk_div_ck",
 519         .prcm = {
 520                 .omap4 = {
 521                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 522                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 523                 },
 524         },
 525 };
 526
 527 /*
 528  * 'dma' class
 529  * dma controller for data exchange between memory to memory (i.e. internal or
 530  * external memory) and gp peripherals to memory or memory to gp peripherals
 531  */
 532
 533 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 534         .rev_offs       = 0x0000,
 535         .sysc_offs      = 0x002c,
 536         .syss_offs      = 0x0028,
 537         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 538                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 539                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 540                            SYSS_HAS_RESET_STATUS),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 542                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 543         .sysc_fields    = &omap_hwmod_sysc_type1,
 544 };
 545
 546 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 547         .name   = "dma",
 548         .sysc   = &omap44xx_dma_sysc,
 549 };
 550
 551 /* dma dev_attr */
 552 static struct omap_dma_dev_attr dma_dev_attr = {
 553         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 554                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 555         .lch_count      = 32,
 556 };
 557
 558 /* dma_system */
 559 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 560         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 564         { .irq = -1 }
 565 };
 566
 567 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 568         .name           = "dma_system",
 569         .class          = &omap44xx_dma_hwmod_class,
 570         .clkdm_name     = "l3_dma_clkdm",
 571         .mpu_irqs       = omap44xx_dma_system_irqs,
 572         .main_clk       = "l3_div_ck",
 573         .prcm = {
 574                 .omap4 = {
 575                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 576                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 577                 },
 578         },
 579         .dev_attr       = &dma_dev_attr,
 580 };
 581
 582 /*
 583  * 'dmic' class
 584  * digital microphone controller
 585  */
 586
 587 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 588         .rev_offs       = 0x0000,
 589         .sysc_offs      = 0x0010,
 590         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 591                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 593                            SIDLE_SMART_WKUP),
 594         .sysc_fields    = &omap_hwmod_sysc_type2,
 595 };
 596
 597 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 598         .name   = "dmic",
 599         .sysc   = &omap44xx_dmic_sysc,
 600 };
 601
 602 /* dmic */
 603 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 604         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 605         { .irq = -1 }
 606 };
 607
 608 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 609         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 610         { .dma_req = -1 }
 611 };
 612
 613 static struct omap_hwmod omap44xx_dmic_hwmod = {
 614         .name           = "dmic",
 615         .class          = &omap44xx_dmic_hwmod_class,
 616         .clkdm_name     = "abe_clkdm",
 617         .mpu_irqs       = omap44xx_dmic_irqs,
 618         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 619         .main_clk       = "dmic_fck",
 620         .prcm = {
 621                 .omap4 = {
 622                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 623                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 624                         .modulemode   = MODULEMODE_SWCTRL,
 625                 },
 626         },
 627 };
 628
 629 /*
 630  * 'dsp' class
 631  * dsp sub-system
 632  */
 633
 634 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 635         .name   = "dsp",
 636 };
 637
 638 /* dsp */
 639 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 640         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 641         { .irq = -1 }
 642 };
 643
 644 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 645         { .name = "dsp", .rst_shift = 0 },
 646 };
 647
 648 static struct omap_hwmod omap44xx_dsp_hwmod = {
 649         .name           = "dsp",
 650         .class          = &omap44xx_dsp_hwmod_class,
 651         .clkdm_name     = "tesla_clkdm",
 652         .mpu_irqs       = omap44xx_dsp_irqs,
 653         .rst_lines      = omap44xx_dsp_resets,
 654         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 655         .main_clk       = "dsp_fck",
 656         .prcm = {
 657                 .omap4 = {
 658                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 659                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 660                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 661                         .modulemode   = MODULEMODE_HWCTRL,
 662                 },
 663         },
 664 };
 665
 666 /*
 667  * 'dss' class
 668  * display sub-system
 669  */
 670
 671 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 672         .rev_offs       = 0x0000,
 673         .syss_offs      = 0x0014,
 674         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 675 };
 676
 677 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 678         .name   = "dss",
 679         .sysc   = &omap44xx_dss_sysc,
 680         .reset  = omap_dss_reset,
 681 };
 682
 683 /* dss */
 684 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 685         { .role = "sys_clk", .clk = "dss_sys_clk" },
 686         { .role = "tv_clk", .clk = "dss_tv_clk" },
 687         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 688 };
 689
 690 static struct omap_hwmod omap44xx_dss_hwmod = {
 691         .name           = "dss_core",
 692         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 693         .class          = &omap44xx_dss_hwmod_class,
 694         .clkdm_name     = "l3_dss_clkdm",
 695         .main_clk       = "dss_dss_clk",
 696         .prcm = {
 697                 .omap4 = {
 698                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 699                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 700                 },
 701         },
 702         .opt_clks       = dss_opt_clks,
 703         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 704 };
 705
 706 /*
 707  * 'dispc' class
 708  * display controller
 709  */
 710
 711 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 712         .rev_offs       = 0x0000,
 713         .sysc_offs      = 0x0010,
 714         .syss_offs      = 0x0014,
 715         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 716                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 717                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 718                            SYSS_HAS_RESET_STATUS),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 720                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 721         .sysc_fields    = &omap_hwmod_sysc_type1,
 722 };
 723
 724 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 725         .name   = "dispc",
 726         .sysc   = &omap44xx_dispc_sysc,
 727 };
 728
 729 /* dss_dispc */
 730 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 731         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 732         { .irq = -1 }
 733 };
 734
 735 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 736         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 737         { .dma_req = -1 }
 738 };
 739
 740 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 741         .manager_count          = 3,
 742         .has_framedonetv_irq    = 1
 743 };
 744
 745 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 746         .name           = "dss_dispc",
 747         .class          = &omap44xx_dispc_hwmod_class,
 748         .clkdm_name     = "l3_dss_clkdm",
 749         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 750         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 751         .main_clk       = "dss_dss_clk",
 752         .prcm = {
 753                 .omap4 = {
 754                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 755                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 756                 },
 757         },
 758         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 759 };
 760
 761 /*
 762  * 'dsi' class
 763  * display serial interface controller
 764  */
 765
 766 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 767         .rev_offs       = 0x0000,
 768         .sysc_offs      = 0x0010,
 769         .syss_offs      = 0x0014,
 770         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 771                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 772                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 774         .sysc_fields    = &omap_hwmod_sysc_type1,
 775 };
 776
 777 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 778         .name   = "dsi",
 779         .sysc   = &omap44xx_dsi_sysc,
 780 };
 781
 782 /* dss_dsi1 */
 783 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 784         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 785         { .irq = -1 }
 786 };
 787
 788 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 789         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 790         { .dma_req = -1 }
 791 };
 792
 793 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 794         { .role = "sys_clk", .clk = "dss_sys_clk" },
 795 };
 796
 797 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 798         .name           = "dss_dsi1",
 799         .class          = &omap44xx_dsi_hwmod_class,
 800         .clkdm_name     = "l3_dss_clkdm",
 801         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 802         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 803         .main_clk       = "dss_dss_clk",
 804         .prcm = {
 805                 .omap4 = {
 806                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 807                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 808                 },
 809         },
 810         .opt_clks       = dss_dsi1_opt_clks,
 811         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 812 };
 813
 814 /* dss_dsi2 */
 815 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 816         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 817         { .irq = -1 }
 818 };
 819
 820 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 821         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 822         { .dma_req = -1 }
 823 };
 824
 825 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 826         { .role = "sys_clk", .clk = "dss_sys_clk" },
 827 };
 828
 829 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 830         .name           = "dss_dsi2",
 831         .class          = &omap44xx_dsi_hwmod_class,
 832         .clkdm_name     = "l3_dss_clkdm",
 833         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 834         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 835         .main_clk       = "dss_dss_clk",
 836         .prcm = {
 837                 .omap4 = {
 838                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 839                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 840                 },
 841         },
 842         .opt_clks       = dss_dsi2_opt_clks,
 843         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 844 };
 845
 846 /*
 847  * 'hdmi' class
 848  * hdmi controller
 849  */
 850
 851 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 852         .rev_offs       = 0x0000,
 853         .sysc_offs      = 0x0010,
 854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 855                            SYSC_HAS_SOFTRESET),
 856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 857                            SIDLE_SMART_WKUP),
 858         .sysc_fields    = &omap_hwmod_sysc_type2,
 859 };
 860
 861 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 862         .name   = "hdmi",
 863         .sysc   = &omap44xx_hdmi_sysc,
 864 };
 865
 866 /* dss_hdmi */
 867 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 868         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 869         { .irq = -1 }
 870 };
 871
 872 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 873         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 874         { .dma_req = -1 }
 875 };
 876
 877 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 878         { .role = "sys_clk", .clk = "dss_sys_clk" },
 879 };
 880
 881 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 882         .name           = "dss_hdmi",
 883         .class          = &omap44xx_hdmi_hwmod_class,
 884         .clkdm_name     = "l3_dss_clkdm",
 885         /*
 886          * HDMI audio requires to use no-idle mode. Hence,
 887          * set idle mode by software.
 888          */
 889         .flags          = HWMOD_SWSUP_SIDLE,
 890         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 891         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 892         .main_clk       = "dss_48mhz_clk",
 893         .prcm = {
 894                 .omap4 = {
 895                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 896                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 897                 },
 898         },
 899         .opt_clks       = dss_hdmi_opt_clks,
 900         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 901 };
 902
 903 /*
 904  * 'rfbi' class
 905  * remote frame buffer interface
 906  */
 907
 908 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 909         .rev_offs       = 0x0000,
 910         .sysc_offs      = 0x0010,
 911         .syss_offs      = 0x0014,
 912         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 913                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 914         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 915         .sysc_fields    = &omap_hwmod_sysc_type1,
 916 };
 917
 918 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 919         .name   = "rfbi",
 920         .sysc   = &omap44xx_rfbi_sysc,
 921 };
 922
 923 /* dss_rfbi */
 924 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 925         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 926         { .dma_req = -1 }
 927 };
 928
 929 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 930         { .role = "ick", .clk = "dss_fck" },
 931 };
 932
 933 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 934         .name           = "dss_rfbi",
 935         .class          = &omap44xx_rfbi_hwmod_class,
 936         .clkdm_name     = "l3_dss_clkdm",
 937         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 938         .main_clk       = "dss_dss_clk",
 939         .prcm = {
 940                 .omap4 = {
 941                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 942                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 943                 },
 944         },
 945         .opt_clks       = dss_rfbi_opt_clks,
 946         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 947 };
 948
 949 /*
 950  * 'venc' class
 951  * video encoder
 952  */
 953
 954 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 955         .name   = "venc",
 956 };
 957
 958 /* dss_venc */
 959 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 960         .name           = "dss_venc",
 961         .class          = &omap44xx_venc_hwmod_class,
 962         .clkdm_name     = "l3_dss_clkdm",
 963         .main_clk       = "dss_tv_clk",
 964         .prcm = {
 965                 .omap4 = {
 966                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 967                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 968                 },
 969         },
 970 };
 971
 972 /*
 973  * 'elm' class
 974  * bch error location module
 975  */
 976
 977 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 978         .rev_offs       = 0x0000,
 979         .sysc_offs      = 0x0010,
 980         .syss_offs      = 0x0014,
 981         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 982                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 983                            SYSS_HAS_RESET_STATUS),
 984         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 985         .sysc_fields    = &omap_hwmod_sysc_type1,
 986 };
 987
 988 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 989         .name   = "elm",
 990         .sysc   = &omap44xx_elm_sysc,
 991 };
 992
 993 /* elm */
 994 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 995         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 996         { .irq = -1 }
 997 };
 998
 999 static struct omap_hwmod omap44xx_elm_hwmod = {
1000         .name           = "elm",
1001         .class          = &omap44xx_elm_hwmod_class,
1002         .clkdm_name     = "l4_per_clkdm",
1003         .mpu_irqs       = omap44xx_elm_irqs,
1004         .prcm = {
1005                 .omap4 = {
1006                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1007                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1008                 },
1009         },
1010 };
1011
1012 /*
1013  * 'emif' class
1014  * external memory interface no1
1015  */
1016
1017 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1018         .rev_offs       = 0x0000,
1019 };
1020
1021 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1022         .name   = "emif",
1023         .sysc   = &omap44xx_emif_sysc,
1024 };
1025
1026 /* emif1 */
1027 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1028         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1029         { .irq = -1 }
1030 };
1031
1032 static struct omap_hwmod omap44xx_emif1_hwmod = {
1033         .name           = "emif1",
1034         .class          = &omap44xx_emif_hwmod_class,
1035         .clkdm_name     = "l3_emif_clkdm",
1036         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1037         .mpu_irqs       = omap44xx_emif1_irqs,
1038         .main_clk       = "ddrphy_ck",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_HWCTRL,
1044                 },
1045         },
1046 };
1047
1048 /* emif2 */
1049 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1050         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1051         { .irq = -1 }
1052 };
1053
1054 static struct omap_hwmod omap44xx_emif2_hwmod = {
1055         .name           = "emif2",
1056         .class          = &omap44xx_emif_hwmod_class,
1057         .clkdm_name     = "l3_emif_clkdm",
1058         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1059         .mpu_irqs       = omap44xx_emif2_irqs,
1060         .main_clk       = "ddrphy_ck",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_HWCTRL,
1066                 },
1067         },
1068 };
1069
1070 /*
1071  * 'fdif' class
1072  * face detection hw accelerator module
1073  */
1074
1075 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1076         .rev_offs       = 0x0000,
1077         .sysc_offs      = 0x0010,
1078         /*
1079          * FDIF needs 100 OCP clk cycles delay after a softreset before
1080          * accessing sysconfig again.
1081          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1082          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1083          *
1084          * TODO: Indicate errata when available.
1085          */
1086         .srst_udelay    = 2,
1087         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1088                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1089         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091         .sysc_fields    = &omap_hwmod_sysc_type2,
1092 };
1093
1094 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1095         .name   = "fdif",
1096         .sysc   = &omap44xx_fdif_sysc,
1097 };
1098
1099 /* fdif */
1100 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1101         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1102         { .irq = -1 }
1103 };
1104
1105 static struct omap_hwmod omap44xx_fdif_hwmod = {
1106         .name           = "fdif",
1107         .class          = &omap44xx_fdif_hwmod_class,
1108         .clkdm_name     = "iss_clkdm",
1109         .mpu_irqs       = omap44xx_fdif_irqs,
1110         .main_clk       = "fdif_fck",
1111         .prcm = {
1112                 .omap4 = {
1113                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1114                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1115                         .modulemode   = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118 };
1119
1120 /*
1121  * 'gpio' class
1122  * general purpose io module
1123  */
1124
1125 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1126         .rev_offs       = 0x0000,
1127         .sysc_offs      = 0x0010,
1128         .syss_offs      = 0x0114,
1129         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1130                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1131                            SYSS_HAS_RESET_STATUS),
1132         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1133                            SIDLE_SMART_WKUP),
1134         .sysc_fields    = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1138         .name   = "gpio",
1139         .sysc   = &omap44xx_gpio_sysc,
1140         .rev    = 2,
1141 };
1142
1143 /* gpio dev_attr */
1144 static struct omap_gpio_dev_attr gpio_dev_attr = {
1145         .bank_width     = 32,
1146         .dbck_flag      = true,
1147 };
1148
1149 /* gpio1 */
1150 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1151         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1152         { .irq = -1 }
1153 };
1154
1155 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1156         { .role = "dbclk", .clk = "gpio1_dbclk" },
1157 };
1158
1159 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1160         .name           = "gpio1",
1161         .class          = &omap44xx_gpio_hwmod_class,
1162         .clkdm_name     = "l4_wkup_clkdm",
1163         .mpu_irqs       = omap44xx_gpio1_irqs,
1164         .main_clk       = "gpio1_ick",
1165         .prcm = {
1166                 .omap4 = {
1167                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .opt_clks       = gpio1_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1174         .dev_attr       = &gpio_dev_attr,
1175 };
1176
1177 /* gpio2 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1179         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1180         { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio2_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1188         .name           = "gpio2",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .mpu_irqs       = omap44xx_gpio2_irqs,
1193         .main_clk       = "gpio2_ick",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio2_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio3 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1208         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1209         { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio3_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1217         .name           = "gpio3",
1218         .class          = &omap44xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4_per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .mpu_irqs       = omap44xx_gpio3_irqs,
1222         .main_clk       = "gpio3_ick",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1226                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1227                         .modulemode   = MODULEMODE_HWCTRL,
1228                 },
1229         },
1230         .opt_clks       = gpio3_opt_clks,
1231         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1232         .dev_attr       = &gpio_dev_attr,
1233 };
1234
1235 /* gpio4 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1237         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1238         { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1242         { .role = "dbclk", .clk = "gpio4_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1246         .name           = "gpio4",
1247         .class          = &omap44xx_gpio_hwmod_class,
1248         .clkdm_name     = "l4_per_clkdm",
1249         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250         .mpu_irqs       = omap44xx_gpio4_irqs,
1251         .main_clk       = "gpio4_ick",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1256                         .modulemode   = MODULEMODE_HWCTRL,
1257                 },
1258         },
1259         .opt_clks       = gpio4_opt_clks,
1260         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1261         .dev_attr       = &gpio_dev_attr,
1262 };
1263
1264 /* gpio5 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1266         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1267         { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1271         { .role = "dbclk", .clk = "gpio5_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1275         .name           = "gpio5",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .clkdm_name     = "l4_per_clkdm",
1278         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279         .mpu_irqs       = omap44xx_gpio5_irqs,
1280         .main_clk       = "gpio5_ick",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_HWCTRL,
1286                 },
1287         },
1288         .opt_clks       = gpio5_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1290         .dev_attr       = &gpio_dev_attr,
1291 };
1292
1293 /* gpio6 */
1294 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1295         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1296         { .irq = -1 }
1297 };
1298
1299 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1300         { .role = "dbclk", .clk = "gpio6_dbclk" },
1301 };
1302
1303 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1304         .name           = "gpio6",
1305         .class          = &omap44xx_gpio_hwmod_class,
1306         .clkdm_name     = "l4_per_clkdm",
1307         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1308         .mpu_irqs       = omap44xx_gpio6_irqs,
1309         .main_clk       = "gpio6_ick",
1310         .prcm = {
1311                 .omap4 = {
1312                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1313                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1314                         .modulemode   = MODULEMODE_HWCTRL,
1315                 },
1316         },
1317         .opt_clks       = gpio6_opt_clks,
1318         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1319         .dev_attr       = &gpio_dev_attr,
1320 };
1321
1322 /*
1323  * 'gpmc' class
1324  * general purpose memory controller
1325  */
1326
1327 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1328         .rev_offs       = 0x0000,
1329         .sysc_offs      = 0x0010,
1330         .syss_offs      = 0x0014,
1331         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1332                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1334         .sysc_fields    = &omap_hwmod_sysc_type1,
1335 };
1336
1337 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1338         .name   = "gpmc",
1339         .sysc   = &omap44xx_gpmc_sysc,
1340 };
1341
1342 /* gpmc */
1343 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1344         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1345         { .irq = -1 }
1346 };
1347
1348 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1349         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1350         { .dma_req = -1 }
1351 };
1352
1353 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1354         .name           = "gpmc",
1355         .class          = &omap44xx_gpmc_hwmod_class,
1356         .clkdm_name     = "l3_2_clkdm",
1357         /*
1358          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1359          * block.  It is not being added due to any known bugs with
1360          * resetting the GPMC IP block, but rather because any timings
1361          * set by the bootloader are not being correctly programmed by
1362          * the kernel from the board file or DT data.
1363          * HWMOD_INIT_NO_RESET should be removed ASAP.
1364          */
1365         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1366         .mpu_irqs       = omap44xx_gpmc_irqs,
1367         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_HWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'gpu' class
1379  * 2d/3d graphics accelerator
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1383         .rev_offs       = 0x1fc00,
1384         .sysc_offs      = 0x1fc10,
1385         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1386         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1387                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1388                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1389         .sysc_fields    = &omap_hwmod_sysc_type2,
1390 };
1391
1392 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1393         .name   = "gpu",
1394         .sysc   = &omap44xx_gpu_sysc,
1395 };
1396
1397 /* gpu */
1398 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1399         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1400         { .irq = -1 }
1401 };
1402
1403 static struct omap_hwmod omap44xx_gpu_hwmod = {
1404         .name           = "gpu",
1405         .class          = &omap44xx_gpu_hwmod_class,
1406         .clkdm_name     = "l3_gfx_clkdm",
1407         .mpu_irqs       = omap44xx_gpu_irqs,
1408         .main_clk       = "gpu_fck",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hdq1w' class
1420  * hdq / 1-wire serial interface controller
1421  */
1422
1423 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1424         .rev_offs       = 0x0000,
1425         .sysc_offs      = 0x0014,
1426         .syss_offs      = 0x0018,
1427         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1428                            SYSS_HAS_RESET_STATUS),
1429         .sysc_fields    = &omap_hwmod_sysc_type1,
1430 };
1431
1432 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1433         .name   = "hdq1w",
1434         .sysc   = &omap44xx_hdq1w_sysc,
1435 };
1436
1437 /* hdq1w */
1438 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1439         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1440         { .irq = -1 }
1441 };
1442
1443 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1444         .name           = "hdq1w",
1445         .class          = &omap44xx_hdq1w_hwmod_class,
1446         .clkdm_name     = "l4_per_clkdm",
1447         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1448         .mpu_irqs       = omap44xx_hdq1w_irqs,
1449         .main_clk       = "hdq1w_fck",
1450         .prcm = {
1451                 .omap4 = {
1452                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1453                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1454                         .modulemode   = MODULEMODE_SWCTRL,
1455                 },
1456         },
1457 };
1458
1459 /*
1460  * 'hsi' class
1461  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1462  * serial if)
1463  */
1464
1465 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1466         .rev_offs       = 0x0000,
1467         .sysc_offs      = 0x0010,
1468         .syss_offs      = 0x0014,
1469         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1470                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1471                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1474                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1475         .sysc_fields    = &omap_hwmod_sysc_type1,
1476 };
1477
1478 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1479         .name   = "hsi",
1480         .sysc   = &omap44xx_hsi_sysc,
1481 };
1482
1483 /* hsi */
1484 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1485         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1488         { .irq = -1 }
1489 };
1490
1491 static struct omap_hwmod omap44xx_hsi_hwmod = {
1492         .name           = "hsi",
1493         .class          = &omap44xx_hsi_hwmod_class,
1494         .clkdm_name     = "l3_init_clkdm",
1495         .mpu_irqs       = omap44xx_hsi_irqs,
1496         .main_clk       = "hsi_fck",
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1500                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1501                         .modulemode   = MODULEMODE_HWCTRL,
1502                 },
1503         },
1504 };
1505
1506 /*
1507  * 'i2c' class
1508  * multimaster high-speed i2c controller
1509  */
1510
1511 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1512         .sysc_offs      = 0x0010,
1513         .syss_offs      = 0x0090,
1514         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1515                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1516                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1517         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1518                            SIDLE_SMART_WKUP),
1519         .clockact       = CLOCKACT_TEST_ICLK,
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1524         .name   = "i2c",
1525         .sysc   = &omap44xx_i2c_sysc,
1526         .rev    = OMAP_I2C_IP_VERSION_2,
1527         .reset  = &omap_i2c_reset,
1528 };
1529
1530 static struct omap_i2c_dev_attr i2c_dev_attr = {
1531         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1532                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1533 };
1534
1535 /* i2c1 */
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1537         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1538         { .irq = -1 }
1539 };
1540
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1542         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1543         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1544         { .dma_req = -1 }
1545 };
1546
1547 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .class          = &omap44xx_i2c_hwmod_class,
1550         .clkdm_name     = "l4_per_clkdm",
1551         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1552         .mpu_irqs       = omap44xx_i2c1_irqs,
1553         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1554         .main_clk       = "i2c1_fck",
1555         .prcm = {
1556                 .omap4 = {
1557                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1558                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1559                         .modulemode   = MODULEMODE_SWCTRL,
1560                 },
1561         },
1562         .dev_attr       = &i2c_dev_attr,
1563 };
1564
1565 /* i2c2 */
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1567         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1568         { .irq = -1 }
1569 };
1570
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1572         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1573         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1574         { .dma_req = -1 }
1575 };
1576
1577 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578         .name           = "i2c2",
1579         .class          = &omap44xx_i2c_hwmod_class,
1580         .clkdm_name     = "l4_per_clkdm",
1581         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1582         .mpu_irqs       = omap44xx_i2c2_irqs,
1583         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1584         .main_clk       = "i2c2_fck",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1588                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .dev_attr       = &i2c_dev_attr,
1593 };
1594
1595 /* i2c3 */
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1597         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1598         { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1602         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1603         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1604         { .dma_req = -1 }
1605 };
1606
1607 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608         .name           = "i2c3",
1609         .class          = &omap44xx_i2c_hwmod_class,
1610         .clkdm_name     = "l4_per_clkdm",
1611         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1612         .mpu_irqs       = omap44xx_i2c3_irqs,
1613         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1614         .main_clk       = "i2c3_fck",
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1618                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1619                         .modulemode   = MODULEMODE_SWCTRL,
1620                 },
1621         },
1622         .dev_attr       = &i2c_dev_attr,
1623 };
1624
1625 /* i2c4 */
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1627         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1628         { .irq = -1 }
1629 };
1630
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1632         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1633         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1634         { .dma_req = -1 }
1635 };
1636
1637 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638         .name           = "i2c4",
1639         .class          = &omap44xx_i2c_hwmod_class,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1642         .mpu_irqs       = omap44xx_i2c4_irqs,
1643         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1644         .main_clk       = "i2c4_fck",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1648                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1649                         .modulemode   = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .dev_attr       = &i2c_dev_attr,
1653 };
1654
1655 /*
1656  * 'ipu' class
1657  * imaging processor unit
1658  */
1659
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1661         .name   = "ipu",
1662 };
1663
1664 /* ipu */
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1666         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1667         { .irq = -1 }
1668 };
1669
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1671         { .name = "cpu0", .rst_shift = 0 },
1672         { .name = "cpu1", .rst_shift = 1 },
1673 };
1674
1675 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676         .name           = "ipu",
1677         .class          = &omap44xx_ipu_hwmod_class,
1678         .clkdm_name     = "ducati_clkdm",
1679         .mpu_irqs       = omap44xx_ipu_irqs,
1680         .rst_lines      = omap44xx_ipu_resets,
1681         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1682         .main_clk       = "ipu_fck",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1686                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_HWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /*
1694  * 'iss' class
1695  * external images sensor pixel data processor
1696  */
1697
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699         .rev_offs       = 0x0000,
1700         .sysc_offs      = 0x0010,
1701         /*
1702          * ISS needs 100 OCP clk cycles delay after a softreset before
1703          * accessing sysconfig again.
1704          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706          *
1707          * TODO: Indicate errata when available.
1708          */
1709         .srst_udelay    = 2,
1710         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1711                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1713                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1714                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1715         .sysc_fields    = &omap_hwmod_sysc_type2,
1716 };
1717
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719         .name   = "iss",
1720         .sysc   = &omap44xx_iss_sysc,
1721 };
1722
1723 /* iss */
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1725         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1726         { .irq = -1 }
1727 };
1728
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1730         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1731         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1732         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1733         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1734         { .dma_req = -1 }
1735 };
1736
1737 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1738         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739 };
1740
1741 static struct omap_hwmod omap44xx_iss_hwmod = {
1742         .name           = "iss",
1743         .class          = &omap44xx_iss_hwmod_class,
1744         .clkdm_name     = "iss_clkdm",
1745         .mpu_irqs       = omap44xx_iss_irqs,
1746         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1747         .main_clk       = "iss_fck",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1751                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1752                         .modulemode   = MODULEMODE_SWCTRL,
1753                 },
1754         },
1755         .opt_clks       = iss_opt_clks,
1756         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1757 };
1758
1759 /*
1760  * 'iva' class
1761  * multi-standard video encoder/decoder hardware accelerator
1762  */
1763
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1765         .name   = "iva",
1766 };
1767
1768 /* iva */
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1770         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1773         { .irq = -1 }
1774 };
1775
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1777         { .name = "seq0", .rst_shift = 0 },
1778         { .name = "seq1", .rst_shift = 1 },
1779         { .name = "logic", .rst_shift = 2 },
1780 };
1781
1782 static struct omap_hwmod omap44xx_iva_hwmod = {
1783         .name           = "iva",
1784         .class          = &omap44xx_iva_hwmod_class,
1785         .clkdm_name     = "ivahd_clkdm",
1786         .mpu_irqs       = omap44xx_iva_irqs,
1787         .rst_lines      = omap44xx_iva_resets,
1788         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1789         .main_clk       = "iva_fck",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1793                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1794                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_HWCTRL,
1796                 },
1797         },
1798 };
1799
1800 /*
1801  * 'kbd' class
1802  * keyboard controller
1803  */
1804
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806         .rev_offs       = 0x0000,
1807         .sysc_offs      = 0x0010,
1808         .syss_offs      = 0x0014,
1809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1810                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1811                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1812                            SYSS_HAS_RESET_STATUS),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1814         .sysc_fields    = &omap_hwmod_sysc_type1,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818         .name   = "kbd",
1819         .sysc   = &omap44xx_kbd_sysc,
1820 };
1821
1822 /* kbd */
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1824         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829         .name           = "kbd",
1830         .class          = &omap44xx_kbd_hwmod_class,
1831         .clkdm_name     = "l4_wkup_clkdm",
1832         .mpu_irqs       = omap44xx_kbd_irqs,
1833         .main_clk       = "kbd_fck",
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1838                         .modulemode   = MODULEMODE_SWCTRL,
1839                 },
1840         },
1841 };
1842
1843 /*
1844  * 'mailbox' class
1845  * mailbox module allowing communication between the on-chip processors using a
1846  * queued mailbox-interrupt mechanism.
1847  */
1848
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850         .rev_offs       = 0x0000,
1851         .sysc_offs      = 0x0010,
1852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1853                            SYSC_HAS_SOFTRESET),
1854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1855         .sysc_fields    = &omap_hwmod_sysc_type2,
1856 };
1857
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859         .name   = "mailbox",
1860         .sysc   = &omap44xx_mailbox_sysc,
1861 };
1862
1863 /* mailbox */
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1865         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1866         { .irq = -1 }
1867 };
1868
1869 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870         .name           = "mailbox",
1871         .class          = &omap44xx_mailbox_hwmod_class,
1872         .clkdm_name     = "l4_cfg_clkdm",
1873         .mpu_irqs       = omap44xx_mailbox_irqs,
1874         .prcm = {
1875                 .omap4 = {
1876                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1877                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1878                 },
1879         },
1880 };
1881
1882 /*
1883  * 'mcasp' class
1884  * multi-channel audio serial port controller
1885  */
1886
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1889         .sidle_shift    = 0,
1890 };
1891
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1893         .sysc_offs      = 0x0004,
1894         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896                            SIDLE_SMART_WKUP),
1897         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1898 };
1899
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901         .name   = "mcasp",
1902         .sysc   = &omap44xx_mcasp_sysc,
1903 };
1904
1905 /* mcasp */
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1907         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1908         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1909         { .irq = -1 }
1910 };
1911
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1913         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1914         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1915         { .dma_req = -1 }
1916 };
1917
1918 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919         .name           = "mcasp",
1920         .class          = &omap44xx_mcasp_hwmod_class,
1921         .clkdm_name     = "abe_clkdm",
1922         .mpu_irqs       = omap44xx_mcasp_irqs,
1923         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1924         .main_clk       = "mcasp_fck",
1925         .prcm = {
1926                 .omap4 = {
1927                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1928                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1929                         .modulemode   = MODULEMODE_SWCTRL,
1930                 },
1931         },
1932 };
1933
1934 /*
1935  * 'mcbsp' class
1936  * multi channel buffered serial port controller
1937  */
1938
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1940         .sysc_offs      = 0x008c,
1941         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1942                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1944         .sysc_fields    = &omap_hwmod_sysc_type1,
1945 };
1946
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948         .name   = "mcbsp",
1949         .sysc   = &omap44xx_mcbsp_sysc,
1950         .rev    = MCBSP_CONFIG_TYPE4,
1951 };
1952
1953 /* mcbsp1 */
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1955         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1956         { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1960         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1961         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1962         { .dma_req = -1 }
1963 };
1964
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1966         { .role = "pad_fck", .clk = "pad_clks_ck" },
1967         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971         .name           = "mcbsp1",
1972         .class          = &omap44xx_mcbsp_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1975         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1976         .main_clk       = "mcbsp1_fck",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_SWCTRL,
1982                 },
1983         },
1984         .opt_clks       = mcbsp1_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1986 };
1987
1988 /* mcbsp2 */
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1990         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1991         { .irq = -1 }
1992 };
1993
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1995         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1996         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1997         { .dma_req = -1 }
1998 };
1999
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2001         { .role = "pad_fck", .clk = "pad_clks_ck" },
2002         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2003 };
2004
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006         .name           = "mcbsp2",
2007         .class          = &omap44xx_mcbsp_hwmod_class,
2008         .clkdm_name     = "abe_clkdm",
2009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2011         .main_clk       = "mcbsp2_fck",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2015                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019         .opt_clks       = mcbsp2_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2021 };
2022
2023 /* mcbsp3 */
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2025         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2030         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2031         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2032         { .dma_req = -1 }
2033 };
2034
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2036         { .role = "pad_fck", .clk = "pad_clks_ck" },
2037         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2038 };
2039
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041         .name           = "mcbsp3",
2042         .class          = &omap44xx_mcbsp_hwmod_class,
2043         .clkdm_name     = "abe_clkdm",
2044         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2045         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2046         .main_clk       = "mcbsp3_fck",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054         .opt_clks       = mcbsp3_opt_clks,
2055         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2056 };
2057
2058 /* mcbsp4 */
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2060         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2061         { .irq = -1 }
2062 };
2063
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2065         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2066         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2067         { .dma_req = -1 }
2068 };
2069
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2071         { .role = "pad_fck", .clk = "pad_clks_ck" },
2072         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2073 };
2074
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076         .name           = "mcbsp4",
2077         .class          = &omap44xx_mcbsp_hwmod_class,
2078         .clkdm_name     = "l4_per_clkdm",
2079         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2080         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2081         .main_clk       = "mcbsp4_fck",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2085                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_SWCTRL,
2087                 },
2088         },
2089         .opt_clks       = mcbsp4_opt_clks,
2090         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2091 };
2092
2093 /*
2094  * 'mcpdm' class
2095  * multi channel pdm controller (proprietary interface with phoenix power
2096  * ic)
2097  */
2098
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100         .rev_offs       = 0x0000,
2101         .sysc_offs      = 0x0010,
2102         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105                            SIDLE_SMART_WKUP),
2106         .sysc_fields    = &omap_hwmod_sysc_type2,
2107 };
2108
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110         .name   = "mcpdm",
2111         .sysc   = &omap44xx_mcpdm_sysc,
2112 };
2113
2114 /* mcpdm */
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2116         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2117         { .irq = -1 }
2118 };
2119
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2121         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2122         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2123         { .dma_req = -1 }
2124 };
2125
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127         .name           = "mcpdm",
2128         .class          = &omap44xx_mcpdm_hwmod_class,
2129         .clkdm_name     = "abe_clkdm",
2130         .mpu_irqs       = omap44xx_mcpdm_irqs,
2131         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2132         .main_clk       = "mcpdm_fck",
2133         .prcm = {
2134                 .omap4 = {
2135                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2136                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2137                         .modulemode   = MODULEMODE_SWCTRL,
2138                 },
2139         },
2140 };
2141
2142 /*
2143  * 'mcspi' class
2144  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2145  * bus
2146  */
2147
2148 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2149         .rev_offs       = 0x0000,
2150         .sysc_offs      = 0x0010,
2151         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2152                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2153         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2154                            SIDLE_SMART_WKUP),
2155         .sysc_fields    = &omap_hwmod_sysc_type2,
2156 };
2157
2158 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2159         .name   = "mcspi",
2160         .sysc   = &omap44xx_mcspi_sysc,
2161         .rev    = OMAP4_MCSPI_REV,
2162 };
2163
2164 /* mcspi1 */
2165 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2166         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2167         { .irq = -1 }
2168 };
2169
2170 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2171         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2172         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2173         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2174         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2175         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2176         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2177         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2178         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2179         { .dma_req = -1 }
2180 };
2181
2182 /* mcspi1 dev_attr */
2183 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2184         .num_chipselect = 4,
2185 };
2186
2187 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2188         .name           = "mcspi1",
2189         .class          = &omap44xx_mcspi_hwmod_class,
2190         .clkdm_name     = "l4_per_clkdm",
2191         .mpu_irqs       = omap44xx_mcspi1_irqs,
2192         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2193         .main_clk       = "mcspi1_fck",
2194         .prcm = {
2195                 .omap4 = {
2196                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2197                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2198                         .modulemode   = MODULEMODE_SWCTRL,
2199                 },
2200         },
2201         .dev_attr       = &mcspi1_dev_attr,
2202 };
2203
2204 /* mcspi2 */
2205 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2206         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2207         { .irq = -1 }
2208 };
2209
2210 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2211         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2212         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2213         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2214         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2215         { .dma_req = -1 }
2216 };
2217
2218 /* mcspi2 dev_attr */
2219 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2220         .num_chipselect = 2,
2221 };
2222
2223 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2224         .name           = "mcspi2",
2225         .class          = &omap44xx_mcspi_hwmod_class,
2226         .clkdm_name     = "l4_per_clkdm",
2227         .mpu_irqs       = omap44xx_mcspi2_irqs,
2228         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2229         .main_clk       = "mcspi2_fck",
2230         .prcm = {
2231                 .omap4 = {
2232                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2233                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2234                         .modulemode   = MODULEMODE_SWCTRL,
2235                 },
2236         },
2237         .dev_attr       = &mcspi2_dev_attr,
2238 };
2239
2240 /* mcspi3 */
2241 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2242         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2243         { .irq = -1 }
2244 };
2245
2246 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2247         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2248         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2249         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2250         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2251         { .dma_req = -1 }
2252 };
2253
2254 /* mcspi3 dev_attr */
2255 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2256         .num_chipselect = 2,
2257 };
2258
2259 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2260         .name           = "mcspi3",
2261         .class          = &omap44xx_mcspi_hwmod_class,
2262         .clkdm_name     = "l4_per_clkdm",
2263         .mpu_irqs       = omap44xx_mcspi3_irqs,
2264         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2265         .main_clk       = "mcspi3_fck",
2266         .prcm = {
2267                 .omap4 = {
2268                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2269                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2270                         .modulemode   = MODULEMODE_SWCTRL,
2271                 },
2272         },
2273         .dev_attr       = &mcspi3_dev_attr,
2274 };
2275
2276 /* mcspi4 */
2277 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2278         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2279         { .irq = -1 }
2280 };
2281
2282 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2283         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2284         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2285         { .dma_req = -1 }
2286 };
2287
2288 /* mcspi4 dev_attr */
2289 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2290         .num_chipselect = 1,
2291 };
2292
2293 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2294         .name           = "mcspi4",
2295         .class          = &omap44xx_mcspi_hwmod_class,
2296         .clkdm_name     = "l4_per_clkdm",
2297         .mpu_irqs       = omap44xx_mcspi4_irqs,
2298         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2299         .main_clk       = "mcspi4_fck",
2300         .prcm = {
2301                 .omap4 = {
2302                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2303                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2304                         .modulemode   = MODULEMODE_SWCTRL,
2305                 },
2306         },
2307         .dev_attr       = &mcspi4_dev_attr,
2308 };
2309
2310 /*
2311  * 'mmc' class
2312  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2313  */
2314
2315 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2316         .rev_offs       = 0x0000,
2317         .sysc_offs      = 0x0010,
2318         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2319                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2320                            SYSC_HAS_SOFTRESET),
2321         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2322                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2323                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2324         .sysc_fields    = &omap_hwmod_sysc_type2,
2325 };
2326
2327 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2328         .name   = "mmc",
2329         .sysc   = &omap44xx_mmc_sysc,
2330 };
2331
2332 /* mmc1 */
2333 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2334         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2335         { .irq = -1 }
2336 };
2337
2338 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2339         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2340         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2341         { .dma_req = -1 }
2342 };
2343
2344 /* mmc1 dev_attr */
2345 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2346         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2347 };
2348
2349 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2350         .name           = "mmc1",
2351         .class          = &omap44xx_mmc_hwmod_class,
2352         .clkdm_name     = "l3_init_clkdm",
2353         .mpu_irqs       = omap44xx_mmc1_irqs,
2354         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2355         .main_clk       = "mmc1_fck",
2356         .prcm = {
2357                 .omap4 = {
2358                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2359                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2360                         .modulemode   = MODULEMODE_SWCTRL,
2361                 },
2362         },
2363         .dev_attr       = &mmc1_dev_attr,
2364 };
2365
2366 /* mmc2 */
2367 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2368         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2369         { .irq = -1 }
2370 };
2371
2372 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2373         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2374         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2375         { .dma_req = -1 }
2376 };
2377
2378 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2379         .name           = "mmc2",
2380         .class          = &omap44xx_mmc_hwmod_class,
2381         .clkdm_name     = "l3_init_clkdm",
2382         .mpu_irqs       = omap44xx_mmc2_irqs,
2383         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2384         .main_clk       = "mmc2_fck",
2385         .prcm = {
2386                 .omap4 = {
2387                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2388                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2389                         .modulemode   = MODULEMODE_SWCTRL,
2390                 },
2391         },
2392 };
2393
2394 /* mmc3 */
2395 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2396         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2397         { .irq = -1 }
2398 };
2399
2400 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2401         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2402         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2403         { .dma_req = -1 }
2404 };
2405
2406 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2407         .name           = "mmc3",
2408         .class          = &omap44xx_mmc_hwmod_class,
2409         .clkdm_name     = "l4_per_clkdm",
2410         .mpu_irqs       = omap44xx_mmc3_irqs,
2411         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2412         .main_clk       = "mmc3_fck",
2413         .prcm = {
2414                 .omap4 = {
2415                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2416                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2417                         .modulemode   = MODULEMODE_SWCTRL,
2418                 },
2419         },
2420 };
2421
2422 /* mmc4 */
2423 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2424         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2425         { .irq = -1 }
2426 };
2427
2428 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2429         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2430         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2431         { .dma_req = -1 }
2432 };
2433
2434 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2435         .name           = "mmc4",
2436         .class          = &omap44xx_mmc_hwmod_class,
2437         .clkdm_name     = "l4_per_clkdm",
2438         .mpu_irqs       = omap44xx_mmc4_irqs,
2439         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2440         .main_clk       = "mmc4_fck",
2441         .prcm = {
2442                 .omap4 = {
2443                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2444                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2445                         .modulemode   = MODULEMODE_SWCTRL,
2446                 },
2447         },
2448 };
2449
2450 /* mmc5 */
2451 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2452         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2453         { .irq = -1 }
2454 };
2455
2456 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2457         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2458         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2459         { .dma_req = -1 }
2460 };
2461
2462 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2463         .name           = "mmc5",
2464         .class          = &omap44xx_mmc_hwmod_class,
2465         .clkdm_name     = "l4_per_clkdm",
2466         .mpu_irqs       = omap44xx_mmc5_irqs,
2467         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2468         .main_clk       = "mmc5_fck",
2469         .prcm = {
2470                 .omap4 = {
2471                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2472                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2473                         .modulemode   = MODULEMODE_SWCTRL,
2474                 },
2475         },
2476 };
2477
2478 /*
2479  * 'mmu' class
2480  * The memory management unit performs virtual to physical address translation
2481  * for its requestors.
2482  */
2483
2484 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2485         .rev_offs       = 0x000,
2486         .sysc_offs      = 0x010,
2487         .syss_offs      = 0x014,
2488         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2489                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2490         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2491         .sysc_fields    = &omap_hwmod_sysc_type1,
2492 };
2493
2494 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2495         .name = "mmu",
2496         .sysc = &mmu_sysc,
2497 };
2498
2499 /* mmu ipu */
2500
2501 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2502         .da_start       = 0x0,
2503         .da_end         = 0xfffff000,
2504         .nr_tlb_entries = 32,
2505 };
2506
2507 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2508 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2509         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2510         { .irq = -1 }
2511 };
2512
2513 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2514         { .name = "mmu_cache", .rst_shift = 2 },
2515 };
2516
2517 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2518         {
2519                 .pa_start       = 0x55082000,
2520                 .pa_end         = 0x550820ff,
2521                 .flags          = ADDR_TYPE_RT,
2522         },
2523         { }
2524 };
2525
2526 /* l3_main_2 -> mmu_ipu */
2527 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2528         .master         = &omap44xx_l3_main_2_hwmod,
2529         .slave          = &omap44xx_mmu_ipu_hwmod,
2530         .clk            = "l3_div_ck",
2531         .addr           = omap44xx_mmu_ipu_addrs,
2532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2533 };
2534
2535 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2536         .name           = "mmu_ipu",
2537         .class          = &omap44xx_mmu_hwmod_class,
2538         .clkdm_name     = "ducati_clkdm",
2539         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2540         .rst_lines      = omap44xx_mmu_ipu_resets,
2541         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2542         .main_clk       = "ducati_clk_mux_ck",
2543         .prcm = {
2544                 .omap4 = {
2545                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2546                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2547                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2548                         .modulemode   = MODULEMODE_HWCTRL,
2549                 },
2550         },
2551         .dev_attr       = &mmu_ipu_dev_attr,
2552 };
2553
2554 /* mmu dsp */
2555
2556 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2557         .da_start       = 0x0,
2558         .da_end         = 0xfffff000,
2559         .nr_tlb_entries = 32,
2560 };
2561
2562 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2563 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2564         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2565         { .irq = -1 }
2566 };
2567
2568 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2569         { .name = "mmu_cache", .rst_shift = 1 },
2570 };
2571
2572 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2573         {
2574                 .pa_start       = 0x4a066000,
2575                 .pa_end         = 0x4a0660ff,
2576                 .flags          = ADDR_TYPE_RT,
2577         },
2578         { }
2579 };
2580
2581 /* l4_cfg -> dsp */
2582 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2583         .master         = &omap44xx_l4_cfg_hwmod,
2584         .slave          = &omap44xx_mmu_dsp_hwmod,
2585         .clk            = "l4_div_ck",
2586         .addr           = omap44xx_mmu_dsp_addrs,
2587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2588 };
2589
2590 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2591         .name           = "mmu_dsp",
2592         .class          = &omap44xx_mmu_hwmod_class,
2593         .clkdm_name     = "tesla_clkdm",
2594         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2595         .rst_lines      = omap44xx_mmu_dsp_resets,
2596         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2597         .main_clk       = "dpll_iva_m4x2_ck",
2598         .prcm = {
2599                 .omap4 = {
2600                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2601                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2602                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2603                         .modulemode   = MODULEMODE_HWCTRL,
2604                 },
2605         },
2606         .dev_attr       = &mmu_dsp_dev_attr,
2607 };
2608
2609 /*
2610  * 'mpu' class
2611  * mpu sub-system
2612  */
2613
2614 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2615         .name   = "mpu",
2616 };
2617
2618 /* mpu */
2619 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2620         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2621         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2622         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2623         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2624         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2625         { .irq = -1 }
2626 };
2627
2628 static struct omap_hwmod omap44xx_mpu_hwmod = {
2629         .name           = "mpu",
2630         .class          = &omap44xx_mpu_hwmod_class,
2631         .clkdm_name     = "mpuss_clkdm",
2632         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2633         .mpu_irqs       = omap44xx_mpu_irqs,
2634         .main_clk       = "dpll_mpu_m2_ck",
2635         .prcm = {
2636                 .omap4 = {
2637                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2638                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2639                 },
2640         },
2641 };
2642
2643 /*
2644  * 'ocmc_ram' class
2645  * top-level core on-chip ram
2646  */
2647
2648 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2649         .name   = "ocmc_ram",
2650 };
2651
2652 /* ocmc_ram */
2653 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2654         .name           = "ocmc_ram",
2655         .class          = &omap44xx_ocmc_ram_hwmod_class,
2656         .clkdm_name     = "l3_2_clkdm",
2657         .prcm = {
2658                 .omap4 = {
2659                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2660                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2661                 },
2662         },
2663 };
2664
2665 /*
2666  * 'ocp2scp' class
2667  * bridge to transform ocp interface protocol to scp (serial control port)
2668  * protocol
2669  */
2670
2671 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2672         .rev_offs       = 0x0000,
2673         .sysc_offs      = 0x0010,
2674         .syss_offs      = 0x0014,
2675         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2676                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2677         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2678         .sysc_fields    = &omap_hwmod_sysc_type1,
2679 };
2680
2681 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2682         .name   = "ocp2scp",
2683         .sysc   = &omap44xx_ocp2scp_sysc,
2684 };
2685
2686 /* ocp2scp_usb_phy */
2687 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2688         .name           = "ocp2scp_usb_phy",
2689         .class          = &omap44xx_ocp2scp_hwmod_class,
2690         .clkdm_name     = "l3_init_clkdm",
2691         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2692         .prcm = {
2693                 .omap4 = {
2694                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2695                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2696                         .modulemode   = MODULEMODE_HWCTRL,
2697                 },
2698         },
2699 };
2700
2701 /*
2702  * 'prcm' class
2703  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2704  * + clock manager 1 (in always on power domain) + local prm in mpu
2705  */
2706
2707 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2708         .name   = "prcm",
2709 };
2710
2711 /* prcm_mpu */
2712 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2713         .name           = "prcm_mpu",
2714         .class          = &omap44xx_prcm_hwmod_class,
2715         .clkdm_name     = "l4_wkup_clkdm",
2716         .flags          = HWMOD_NO_IDLEST,
2717         .prcm = {
2718                 .omap4 = {
2719                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2720                 },
2721         },
2722 };
2723
2724 /* cm_core_aon */
2725 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2726         .name           = "cm_core_aon",
2727         .class          = &omap44xx_prcm_hwmod_class,
2728         .flags          = HWMOD_NO_IDLEST,
2729         .prcm = {
2730                 .omap4 = {
2731                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2732                 },
2733         },
2734 };
2735
2736 /* cm_core */
2737 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2738         .name           = "cm_core",
2739         .class          = &omap44xx_prcm_hwmod_class,
2740         .flags          = HWMOD_NO_IDLEST,
2741         .prcm = {
2742                 .omap4 = {
2743                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2744                 },
2745         },
2746 };
2747
2748 /* prm */
2749 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2750         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2751         { .irq = -1 }
2752 };
2753
2754 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2755         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2756         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2757 };
2758
2759 static struct omap_hwmod omap44xx_prm_hwmod = {
2760         .name           = "prm",
2761         .class          = &omap44xx_prcm_hwmod_class,
2762         .mpu_irqs       = omap44xx_prm_irqs,
2763         .rst_lines      = omap44xx_prm_resets,
2764         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2765 };
2766
2767 /*
2768  * 'scrm' class
2769  * system clock and reset manager
2770  */
2771
2772 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2773         .name   = "scrm",
2774 };
2775
2776 /* scrm */
2777 static struct omap_hwmod omap44xx_scrm_hwmod = {
2778         .name           = "scrm",
2779         .class          = &omap44xx_scrm_hwmod_class,
2780         .clkdm_name     = "l4_wkup_clkdm",
2781         .prcm = {
2782                 .omap4 = {
2783                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2784                 },
2785         },
2786 };
2787
2788 /*
2789  * 'sl2if' class
2790  * shared level 2 memory interface
2791  */
2792
2793 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2794         .name   = "sl2if",
2795 };
2796
2797 /* sl2if */
2798 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2799         .name           = "sl2if",
2800         .class          = &omap44xx_sl2if_hwmod_class,
2801         .clkdm_name     = "ivahd_clkdm",
2802         .prcm = {
2803                 .omap4 = {
2804                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2805                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2806                         .modulemode   = MODULEMODE_HWCTRL,
2807                 },
2808         },
2809 };
2810
2811 /*
2812  * 'slimbus' class
2813  * bidirectional, multi-drop, multi-channel two-line serial interface between
2814  * the device and external components
2815  */
2816
2817 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2818         .rev_offs       = 0x0000,
2819         .sysc_offs      = 0x0010,
2820         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2821                            SYSC_HAS_SOFTRESET),
2822         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2823                            SIDLE_SMART_WKUP),
2824         .sysc_fields    = &omap_hwmod_sysc_type2,
2825 };
2826
2827 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2828         .name   = "slimbus",
2829         .sysc   = &omap44xx_slimbus_sysc,
2830 };
2831
2832 /* slimbus1 */
2833 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2834         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2835         { .irq = -1 }
2836 };
2837
2838 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2839         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2840         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2841         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2842         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2843         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2844         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2845         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2846         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2847         { .dma_req = -1 }
2848 };
2849
2850 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2851         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2852         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2853         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2854         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2855 };
2856
2857 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2858         .name           = "slimbus1",
2859         .class          = &omap44xx_slimbus_hwmod_class,
2860         .clkdm_name     = "abe_clkdm",
2861         .mpu_irqs       = omap44xx_slimbus1_irqs,
2862         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2863         .prcm = {
2864                 .omap4 = {
2865                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2866                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2867                         .modulemode   = MODULEMODE_SWCTRL,
2868                 },
2869         },
2870         .opt_clks       = slimbus1_opt_clks,
2871         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2872 };
2873
2874 /* slimbus2 */
2875 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2876         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2877         { .irq = -1 }
2878 };
2879
2880 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2881         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2882         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2883         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2884         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2885         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2886         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2887         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2888         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2889         { .dma_req = -1 }
2890 };
2891
2892 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2893         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2894         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2895         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2896 };
2897
2898 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2899         .name           = "slimbus2",
2900         .class          = &omap44xx_slimbus_hwmod_class,
2901         .clkdm_name     = "l4_per_clkdm",
2902         .mpu_irqs       = omap44xx_slimbus2_irqs,
2903         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2904         .prcm = {
2905                 .omap4 = {
2906                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2907                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2908                         .modulemode   = MODULEMODE_SWCTRL,
2909                 },
2910         },
2911         .opt_clks       = slimbus2_opt_clks,
2912         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2913 };
2914
2915 /*
2916  * 'smartreflex' class
2917  * smartreflex module (monitor silicon performance and outputs a measure of
2918  * performance error)
2919  */
2920
2921 /* The IP is not compliant to type1 / type2 scheme */
2922 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2923         .sidle_shift    = 24,
2924         .enwkup_shift   = 26,
2925 };
2926
2927 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2928         .sysc_offs      = 0x0038,
2929         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2930         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2931                            SIDLE_SMART_WKUP),
2932         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2933 };
2934
2935 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2936         .name   = "smartreflex",
2937         .sysc   = &omap44xx_smartreflex_sysc,
2938         .rev    = 2,
2939 };
2940
2941 /* smartreflex_core */
2942 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2943         .sensor_voltdm_name   = "core",
2944 };
2945
2946 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2947         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2948         { .irq = -1 }
2949 };
2950
2951 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2952         .name           = "smartreflex_core",
2953         .class          = &omap44xx_smartreflex_hwmod_class,
2954         .clkdm_name     = "l4_ao_clkdm",
2955         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2956
2957         .main_clk       = "smartreflex_core_fck",
2958         .prcm = {
2959                 .omap4 = {
2960                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2961                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2962                         .modulemode   = MODULEMODE_SWCTRL,
2963                 },
2964         },
2965         .dev_attr       = &smartreflex_core_dev_attr,
2966 };
2967
2968 /* smartreflex_iva */
2969 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2970         .sensor_voltdm_name     = "iva",
2971 };
2972
2973 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2974         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2975         { .irq = -1 }
2976 };
2977
2978 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2979         .name           = "smartreflex_iva",
2980         .class          = &omap44xx_smartreflex_hwmod_class,
2981         .clkdm_name     = "l4_ao_clkdm",
2982         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2983         .main_clk       = "smartreflex_iva_fck",
2984         .prcm = {
2985                 .omap4 = {
2986                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2987                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2988                         .modulemode   = MODULEMODE_SWCTRL,
2989                 },
2990         },
2991         .dev_attr       = &smartreflex_iva_dev_attr,
2992 };
2993
2994 /* smartreflex_mpu */
2995 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2996         .sensor_voltdm_name     = "mpu",
2997 };
2998
2999 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3000         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3001         { .irq = -1 }
3002 };
3003
3004 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3005         .name           = "smartreflex_mpu",
3006         .class          = &omap44xx_smartreflex_hwmod_class,
3007         .clkdm_name     = "l4_ao_clkdm",
3008         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3009         .main_clk       = "smartreflex_mpu_fck",
3010         .prcm = {
3011                 .omap4 = {
3012                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3013                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3014                         .modulemode   = MODULEMODE_SWCTRL,
3015                 },
3016         },
3017         .dev_attr       = &smartreflex_mpu_dev_attr,
3018 };
3019
3020 /*
3021  * 'spinlock' class
3022  * spinlock provides hardware assistance for synchronizing the processes
3023  * running on multiple processors
3024  */
3025
3026 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3027         .rev_offs       = 0x0000,
3028         .sysc_offs      = 0x0010,
3029         .syss_offs      = 0x0014,
3030         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3031                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3032                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3033         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3034                            SIDLE_SMART_WKUP),
3035         .sysc_fields    = &omap_hwmod_sysc_type1,
3036 };
3037
3038 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3039         .name   = "spinlock",
3040         .sysc   = &omap44xx_spinlock_sysc,
3041 };
3042
3043 /* spinlock */
3044 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3045         .name           = "spinlock",
3046         .class          = &omap44xx_spinlock_hwmod_class,
3047         .clkdm_name     = "l4_cfg_clkdm",
3048         .prcm = {
3049                 .omap4 = {
3050                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3051                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3052                 },
3053         },
3054 };
3055
3056 /*
3057  * 'timer' class
3058  * general purpose timer module with accurate 1ms tick
3059  * This class contains several variants: ['timer_1ms', 'timer']
3060  */
3061
3062 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3063         .rev_offs       = 0x0000,
3064         .sysc_offs      = 0x0010,
3065         .syss_offs      = 0x0014,
3066         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3067                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3068                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3069                            SYSS_HAS_RESET_STATUS),
3070         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3071         .sysc_fields    = &omap_hwmod_sysc_type1,
3072 };
3073
3074 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3075         .name   = "timer",
3076         .sysc   = &omap44xx_timer_1ms_sysc,
3077 };
3078
3079 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3080         .rev_offs       = 0x0000,
3081         .sysc_offs      = 0x0010,
3082         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3083                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3084         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3085                            SIDLE_SMART_WKUP),
3086         .sysc_fields    = &omap_hwmod_sysc_type2,
3087 };
3088
3089 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3090         .name   = "timer",
3091         .sysc   = &omap44xx_timer_sysc,
3092 };
3093
3094 /* always-on timers dev attribute */
3095 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3096         .timer_capability       = OMAP_TIMER_ALWON,
3097 };
3098
3099 /* pwm timers dev attribute */
3100 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3101         .timer_capability       = OMAP_TIMER_HAS_PWM,
3102 };
3103
3104 /* timers with DSP interrupt dev attribute */
3105 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3106         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3107 };
3108
3109 /* pwm timers with DSP interrupt dev attribute */
3110 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3111         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3112 };
3113
3114 /* timer1 */
3115 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3116         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3117         { .irq = -1 }
3118 };
3119
3120 static struct omap_hwmod omap44xx_timer1_hwmod = {
3121         .name           = "timer1",
3122         .class          = &omap44xx_timer_1ms_hwmod_class,
3123         .clkdm_name     = "l4_wkup_clkdm",
3124         .mpu_irqs       = omap44xx_timer1_irqs,
3125         .main_clk       = "timer1_fck",
3126         .prcm = {
3127                 .omap4 = {
3128                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3129                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3130                         .modulemode   = MODULEMODE_SWCTRL,
3131                 },
3132         },
3133         .dev_attr       = &capability_alwon_dev_attr,
3134 };
3135
3136 /* timer2 */
3137 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3138         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3139         { .irq = -1 }
3140 };
3141
3142 static struct omap_hwmod omap44xx_timer2_hwmod = {
3143         .name           = "timer2",
3144         .class          = &omap44xx_timer_1ms_hwmod_class,
3145         .clkdm_name     = "l4_per_clkdm",
3146         .mpu_irqs       = omap44xx_timer2_irqs,
3147         .main_clk       = "timer2_fck",
3148         .prcm = {
3149                 .omap4 = {
3150                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3151                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3152                         .modulemode   = MODULEMODE_SWCTRL,
3153                 },
3154         },
3155 };
3156
3157 /* timer3 */
3158 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3159         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3160         { .irq = -1 }
3161 };
3162
3163 static struct omap_hwmod omap44xx_timer3_hwmod = {
3164         .name           = "timer3",
3165         .class          = &omap44xx_timer_hwmod_class,
3166         .clkdm_name     = "l4_per_clkdm",
3167         .mpu_irqs       = omap44xx_timer3_irqs,
3168         .main_clk       = "timer3_fck",
3169         .prcm = {
3170                 .omap4 = {
3171                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3172                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3173                         .modulemode   = MODULEMODE_SWCTRL,
3174                 },
3175         },
3176 };
3177
3178 /* timer4 */
3179 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3180         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3181         { .irq = -1 }
3182 };
3183
3184 static struct omap_hwmod omap44xx_timer4_hwmod = {
3185         .name           = "timer4",
3186         .class          = &omap44xx_timer_hwmod_class,
3187         .clkdm_name     = "l4_per_clkdm",
3188         .mpu_irqs       = omap44xx_timer4_irqs,
3189         .main_clk       = "timer4_fck",
3190         .prcm = {
3191                 .omap4 = {
3192                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3193                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3194                         .modulemode   = MODULEMODE_SWCTRL,
3195                 },
3196         },
3197 };
3198
3199 /* timer5 */
3200 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3201         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3202         { .irq = -1 }
3203 };
3204
3205 static struct omap_hwmod omap44xx_timer5_hwmod = {
3206         .name           = "timer5",
3207         .class          = &omap44xx_timer_hwmod_class,
3208         .clkdm_name     = "abe_clkdm",
3209         .mpu_irqs       = omap44xx_timer5_irqs,
3210         .main_clk       = "timer5_fck",
3211         .prcm = {
3212                 .omap4 = {
3213                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3214                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3215                         .modulemode   = MODULEMODE_SWCTRL,
3216                 },
3217         },
3218         .dev_attr       = &capability_dsp_dev_attr,
3219 };
3220
3221 /* timer6 */
3222 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3223         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3224         { .irq = -1 }
3225 };
3226
3227 static struct omap_hwmod omap44xx_timer6_hwmod = {
3228         .name           = "timer6",
3229         .class          = &omap44xx_timer_hwmod_class,
3230         .clkdm_name     = "abe_clkdm",
3231         .mpu_irqs       = omap44xx_timer6_irqs,
3232
3233         .main_clk       = "timer6_fck",
3234         .prcm = {
3235                 .omap4 = {
3236                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3237                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3238                         .modulemode   = MODULEMODE_SWCTRL,
3239                 },
3240         },
3241         .dev_attr       = &capability_dsp_dev_attr,
3242 };
3243
3244 /* timer7 */
3245 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3246         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3247         { .irq = -1 }
3248 };
3249
3250 static struct omap_hwmod omap44xx_timer7_hwmod = {
3251         .name           = "timer7",
3252         .class          = &omap44xx_timer_hwmod_class,
3253         .clkdm_name     = "abe_clkdm",
3254         .mpu_irqs       = omap44xx_timer7_irqs,
3255         .main_clk       = "timer7_fck",
3256         .prcm = {
3257                 .omap4 = {
3258                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3259                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3260                         .modulemode   = MODULEMODE_SWCTRL,
3261                 },
3262         },
3263         .dev_attr       = &capability_dsp_dev_attr,
3264 };
3265
3266 /* timer8 */
3267 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3268         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3269         { .irq = -1 }
3270 };
3271
3272 static struct omap_hwmod omap44xx_timer8_hwmod = {
3273         .name           = "timer8",
3274         .class          = &omap44xx_timer_hwmod_class,
3275         .clkdm_name     = "abe_clkdm",
3276         .mpu_irqs       = omap44xx_timer8_irqs,
3277         .main_clk       = "timer8_fck",
3278         .prcm = {
3279                 .omap4 = {
3280                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3281                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3282                         .modulemode   = MODULEMODE_SWCTRL,
3283                 },
3284         },
3285         .dev_attr       = &capability_dsp_pwm_dev_attr,
3286 };
3287
3288 /* timer9 */
3289 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3290         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3291         { .irq = -1 }
3292 };
3293
3294 static struct omap_hwmod omap44xx_timer9_hwmod = {
3295         .name           = "timer9",
3296         .class          = &omap44xx_timer_hwmod_class,
3297         .clkdm_name     = "l4_per_clkdm",
3298         .mpu_irqs       = omap44xx_timer9_irqs,
3299         .main_clk       = "timer9_fck",
3300         .prcm = {
3301                 .omap4 = {
3302                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3303                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3304                         .modulemode   = MODULEMODE_SWCTRL,
3305                 },
3306         },
3307         .dev_attr       = &capability_pwm_dev_attr,
3308 };
3309
3310 /* timer10 */
3311 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3312         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3313         { .irq = -1 }
3314 };
3315
3316 static struct omap_hwmod omap44xx_timer10_hwmod = {
3317         .name           = "timer10",
3318         .class          = &omap44xx_timer_1ms_hwmod_class,
3319         .clkdm_name     = "l4_per_clkdm",
3320         .mpu_irqs       = omap44xx_timer10_irqs,
3321         .main_clk       = "timer10_fck",
3322         .prcm = {
3323                 .omap4 = {
3324                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3325                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3326                         .modulemode   = MODULEMODE_SWCTRL,
3327                 },
3328         },
3329         .dev_attr       = &capability_pwm_dev_attr,
3330 };
3331
3332 /* timer11 */
3333 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3334         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3335         { .irq = -1 }
3336 };
3337
3338 static struct omap_hwmod omap44xx_timer11_hwmod = {
3339         .name           = "timer11",
3340         .class          = &omap44xx_timer_hwmod_class,
3341         .clkdm_name     = "l4_per_clkdm",
3342         .mpu_irqs       = omap44xx_timer11_irqs,
3343         .main_clk       = "timer11_fck",
3344         .prcm = {
3345                 .omap4 = {
3346                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3347                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3348                         .modulemode   = MODULEMODE_SWCTRL,
3349                 },
3350         },
3351         .dev_attr       = &capability_pwm_dev_attr,
3352 };
3353
3354 /*
3355  * 'uart' class
3356  * universal asynchronous receiver/transmitter (uart)
3357  */
3358
3359 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3360         .rev_offs       = 0x0050,
3361         .sysc_offs      = 0x0054,
3362         .syss_offs      = 0x0058,
3363         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3364                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3365                            SYSS_HAS_RESET_STATUS),
3366         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3367                            SIDLE_SMART_WKUP),
3368         .sysc_fields    = &omap_hwmod_sysc_type1,
3369 };
3370
3371 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3372         .name   = "uart",
3373         .sysc   = &omap44xx_uart_sysc,
3374 };
3375
3376 /* uart1 */
3377 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3378         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3379         { .irq = -1 }
3380 };
3381
3382 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3383         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3384         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3385         { .dma_req = -1 }
3386 };
3387
3388 static struct omap_hwmod omap44xx_uart1_hwmod = {
3389         .name           = "uart1",
3390         .class          = &omap44xx_uart_hwmod_class,
3391         .clkdm_name     = "l4_per_clkdm",
3392         .mpu_irqs       = omap44xx_uart1_irqs,
3393         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3394         .main_clk       = "uart1_fck",
3395         .prcm = {
3396                 .omap4 = {
3397                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3398                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3399                         .modulemode   = MODULEMODE_SWCTRL,
3400                 },
3401         },
3402 };
3403
3404 /* uart2 */
3405 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3406         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3407         { .irq = -1 }
3408 };
3409
3410 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3411         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3412         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3413         { .dma_req = -1 }
3414 };
3415
3416 static struct omap_hwmod omap44xx_uart2_hwmod = {
3417         .name           = "uart2",
3418         .class          = &omap44xx_uart_hwmod_class,
3419         .clkdm_name     = "l4_per_clkdm",
3420         .mpu_irqs       = omap44xx_uart2_irqs,
3421         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3422         .main_clk       = "uart2_fck",
3423         .prcm = {
3424                 .omap4 = {
3425                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3426                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3427                         .modulemode   = MODULEMODE_SWCTRL,
3428                 },
3429         },
3430 };
3431
3432 /* uart3 */
3433 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3434         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3435         { .irq = -1 }
3436 };
3437
3438 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3439         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3440         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3441         { .dma_req = -1 }
3442 };
3443
3444 static struct omap_hwmod omap44xx_uart3_hwmod = {
3445         .name           = "uart3",
3446         .class          = &omap44xx_uart_hwmod_class,
3447         .clkdm_name     = "l4_per_clkdm",
3448         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3449         .mpu_irqs       = omap44xx_uart3_irqs,
3450         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3451         .main_clk       = "uart3_fck",
3452         .prcm = {
3453                 .omap4 = {
3454                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3455                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3456                         .modulemode   = MODULEMODE_SWCTRL,
3457                 },
3458         },
3459 };
3460
3461 /* uart4 */
3462 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3463         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3464         { .irq = -1 }
3465 };
3466
3467 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3468         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3469         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3470         { .dma_req = -1 }
3471 };
3472
3473 static struct omap_hwmod omap44xx_uart4_hwmod = {
3474         .name           = "uart4",
3475         .class          = &omap44xx_uart_hwmod_class,
3476         .clkdm_name     = "l4_per_clkdm",
3477         .mpu_irqs       = omap44xx_uart4_irqs,
3478         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3479         .main_clk       = "uart4_fck",
3480         .prcm = {
3481                 .omap4 = {
3482                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3483                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3484                         .modulemode   = MODULEMODE_SWCTRL,
3485                 },
3486         },
3487 };
3488
3489 /*
3490  * 'usb_host_fs' class
3491  * full-speed usb host controller
3492  */
3493
3494 /* The IP is not compliant to type1 / type2 scheme */
3495 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3496         .midle_shift    = 4,
3497         .sidle_shift    = 2,
3498         .srst_shift     = 1,
3499 };
3500
3501 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3502         .rev_offs       = 0x0000,
3503         .sysc_offs      = 0x0210,
3504         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3505                            SYSC_HAS_SOFTRESET),
3506         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3507                            SIDLE_SMART_WKUP),
3508         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3509 };
3510
3511 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3512         .name   = "usb_host_fs",
3513         .sysc   = &omap44xx_usb_host_fs_sysc,
3514 };
3515
3516 /* usb_host_fs */
3517 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3518         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3519         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3520         { .irq = -1 }
3521 };
3522
3523 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3524         .name           = "usb_host_fs",
3525         .class          = &omap44xx_usb_host_fs_hwmod_class,
3526         .clkdm_name     = "l3_init_clkdm",
3527         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3528         .main_clk       = "usb_host_fs_fck",
3529         .prcm = {
3530                 .omap4 = {
3531                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3532                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3533                         .modulemode   = MODULEMODE_SWCTRL,
3534                 },
3535         },
3536 };
3537
3538 /*
3539  * 'usb_host_hs' class
3540  * high-speed multi-port usb host controller
3541  */
3542
3543 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3544         .rev_offs       = 0x0000,
3545         .sysc_offs      = 0x0010,
3546         .syss_offs      = 0x0014,
3547         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3548                            SYSC_HAS_SOFTRESET),
3549         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3550                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3551                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3552         .sysc_fields    = &omap_hwmod_sysc_type2,
3553 };
3554
3555 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3556         .name   = "usb_host_hs",
3557         .sysc   = &omap44xx_usb_host_hs_sysc,
3558 };
3559
3560 /* usb_host_hs */
3561 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3562         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3563         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3564         { .irq = -1 }
3565 };
3566
3567 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3568         .name           = "usb_host_hs",
3569         .class          = &omap44xx_usb_host_hs_hwmod_class,
3570         .clkdm_name     = "l3_init_clkdm",
3571         .main_clk       = "usb_host_hs_fck",
3572         .prcm = {
3573                 .omap4 = {
3574                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3575                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3576                         .modulemode   = MODULEMODE_SWCTRL,
3577                 },
3578         },
3579         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3580
3581         /*
3582          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3583          * id: i660
3584          *
3585          * Description:
3586          * In the following configuration :
3587          * - USBHOST module is set to smart-idle mode
3588          * - PRCM asserts idle_req to the USBHOST module ( This typically
3589          *   happens when the system is going to a low power mode : all ports
3590          *   have been suspended, the master part of the USBHOST module has
3591          *   entered the standby state, and SW has cut the functional clocks)
3592          * - an USBHOST interrupt occurs before the module is able to answer
3593          *   idle_ack, typically a remote wakeup IRQ.
3594          * Then the USB HOST module will enter a deadlock situation where it
3595          * is no more accessible nor functional.
3596          *
3597          * Workaround:
3598          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3599          */
3600
3601         /*
3602          * Errata: USB host EHCI may stall when entering smart-standby mode
3603          * Id: i571
3604          *
3605          * Description:
3606          * When the USBHOST module is set to smart-standby mode, and when it is
3607          * ready to enter the standby state (i.e. all ports are suspended and
3608          * all attached devices are in suspend mode), then it can wrongly assert
3609          * the Mstandby signal too early while there are still some residual OCP
3610          * transactions ongoing. If this condition occurs, the internal state
3611          * machine may go to an undefined state and the USB link may be stuck
3612          * upon the next resume.
3613          *
3614          * Workaround:
3615          * Don't use smart standby; use only force standby,
3616          * hence HWMOD_SWSUP_MSTANDBY
3617          */
3618
3619         /*
3620          * During system boot; If the hwmod framework resets the module
3621          * the module will have smart idle settings; which can lead to deadlock
3622          * (above Errata Id:i660); so, dont reset the module during boot;
3623          * Use HWMOD_INIT_NO_RESET.
3624          */
3625
3626         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3627                           HWMOD_INIT_NO_RESET,
3628 };
3629
3630 /*
3631  * 'usb_otg_hs' class
3632  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3633  */
3634
3635 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3636         .rev_offs       = 0x0400,
3637         .sysc_offs      = 0x0404,
3638         .syss_offs      = 0x0408,
3639         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3640                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3641                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3642         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3643                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3644                            MSTANDBY_SMART),
3645         .sysc_fields    = &omap_hwmod_sysc_type1,
3646 };
3647
3648 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3649         .name   = "usb_otg_hs",
3650         .sysc   = &omap44xx_usb_otg_hs_sysc,
3651 };
3652
3653 /* usb_otg_hs */
3654 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3655         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3656         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3657         { .irq = -1 }
3658 };
3659
3660 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3661         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3662 };
3663
3664 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3665         .name           = "usb_otg_hs",
3666         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3667         .clkdm_name     = "l3_init_clkdm",
3668         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3669         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3670         .main_clk       = "usb_otg_hs_ick",
3671         .prcm = {
3672                 .omap4 = {
3673                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3674                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3675                         .modulemode   = MODULEMODE_HWCTRL,
3676                 },
3677         },
3678         .opt_clks       = usb_otg_hs_opt_clks,
3679         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3680 };
3681
3682 /*
3683  * 'usb_tll_hs' class
3684  * usb_tll_hs module is the adapter on the usb_host_hs ports
3685  */
3686
3687 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3688         .rev_offs       = 0x0000,
3689         .sysc_offs      = 0x0010,
3690         .syss_offs      = 0x0014,
3691         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3692                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3693                            SYSC_HAS_AUTOIDLE),
3694         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3695         .sysc_fields    = &omap_hwmod_sysc_type1,
3696 };
3697
3698 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3699         .name   = "usb_tll_hs",
3700         .sysc   = &omap44xx_usb_tll_hs_sysc,
3701 };
3702
3703 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3704         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3705         { .irq = -1 }
3706 };
3707
3708 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3709         .name           = "usb_tll_hs",
3710         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3711         .clkdm_name     = "l3_init_clkdm",
3712         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3713         .main_clk       = "usb_tll_hs_ick",
3714         .prcm = {
3715                 .omap4 = {
3716                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3717                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3718                         .modulemode   = MODULEMODE_HWCTRL,
3719                 },
3720         },
3721 };
3722
3723 /*
3724  * 'wd_timer' class
3725  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3726  * overflow condition
3727  */
3728
3729 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3730         .rev_offs       = 0x0000,
3731         .sysc_offs      = 0x0010,
3732         .syss_offs      = 0x0014,
3733         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3734                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3736                            SIDLE_SMART_WKUP),
3737         .sysc_fields    = &omap_hwmod_sysc_type1,
3738 };
3739
3740 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3741         .name           = "wd_timer",
3742         .sysc           = &omap44xx_wd_timer_sysc,
3743         .pre_shutdown   = &omap2_wd_timer_disable,
3744         .reset          = &omap2_wd_timer_reset,
3745 };
3746
3747 /* wd_timer2 */
3748 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3749         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3750         { .irq = -1 }
3751 };
3752
3753 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3754         .name           = "wd_timer2",
3755         .class          = &omap44xx_wd_timer_hwmod_class,
3756         .clkdm_name     = "l4_wkup_clkdm",
3757         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3758         .main_clk       = "wd_timer2_fck",
3759         .prcm = {
3760                 .omap4 = {
3761                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3762                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3763                         .modulemode   = MODULEMODE_SWCTRL,
3764                 },
3765         },
3766 };
3767
3768 /* wd_timer3 */
3769 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3770         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3771         { .irq = -1 }
3772 };
3773
3774 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3775         .name           = "wd_timer3",
3776         .class          = &omap44xx_wd_timer_hwmod_class,
3777         .clkdm_name     = "abe_clkdm",
3778         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3779         .main_clk       = "wd_timer3_fck",
3780         .prcm = {
3781                 .omap4 = {
3782                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3783                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3784                         .modulemode   = MODULEMODE_SWCTRL,
3785                 },
3786         },
3787 };
3788
3789
3790 /*
3791  * interfaces
3792  */
3793
3794 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3795         {
3796                 .pa_start       = 0x4a204000,
3797                 .pa_end         = 0x4a2040ff,
3798                 .flags          = ADDR_TYPE_RT
3799         },
3800         { }
3801 };
3802
3803 /* c2c -> c2c_target_fw */
3804 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3805         .master         = &omap44xx_c2c_hwmod,
3806         .slave          = &omap44xx_c2c_target_fw_hwmod,
3807         .clk            = "div_core_ck",
3808         .addr           = omap44xx_c2c_target_fw_addrs,
3809         .user           = OCP_USER_MPU,
3810 };
3811
3812 /* l4_cfg -> c2c_target_fw */
3813 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3814         .master         = &omap44xx_l4_cfg_hwmod,
3815         .slave          = &omap44xx_c2c_target_fw_hwmod,
3816         .clk            = "l4_div_ck",
3817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3818 };
3819
3820 /* l3_main_1 -> dmm */
3821 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3822         .master         = &omap44xx_l3_main_1_hwmod,
3823         .slave          = &omap44xx_dmm_hwmod,
3824         .clk            = "l3_div_ck",
3825         .user           = OCP_USER_SDMA,
3826 };
3827
3828 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3829         {
3830                 .pa_start       = 0x4e000000,
3831                 .pa_end         = 0x4e0007ff,
3832                 .flags          = ADDR_TYPE_RT
3833         },
3834         { }
3835 };
3836
3837 /* mpu -> dmm */
3838 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3839         .master         = &omap44xx_mpu_hwmod,
3840         .slave          = &omap44xx_dmm_hwmod,
3841         .clk            = "l3_div_ck",
3842         .addr           = omap44xx_dmm_addrs,
3843         .user           = OCP_USER_MPU,
3844 };
3845
3846 /* c2c -> emif_fw */
3847 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3848         .master         = &omap44xx_c2c_hwmod,
3849         .slave          = &omap44xx_emif_fw_hwmod,
3850         .clk            = "div_core_ck",
3851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3852 };
3853
3854 /* dmm -> emif_fw */
3855 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3856         .master         = &omap44xx_dmm_hwmod,
3857         .slave          = &omap44xx_emif_fw_hwmod,
3858         .clk            = "l3_div_ck",
3859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3860 };
3861
3862 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3863         {
3864                 .pa_start       = 0x4a20c000,
3865                 .pa_end         = 0x4a20c0ff,
3866                 .flags          = ADDR_TYPE_RT
3867         },
3868         { }
3869 };
3870
3871 /* l4_cfg -> emif_fw */
3872 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3873         .master         = &omap44xx_l4_cfg_hwmod,
3874         .slave          = &omap44xx_emif_fw_hwmod,
3875         .clk            = "l4_div_ck",
3876         .addr           = omap44xx_emif_fw_addrs,
3877         .user           = OCP_USER_MPU,
3878 };
3879
3880 /* iva -> l3_instr */
3881 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3882         .master         = &omap44xx_iva_hwmod,
3883         .slave          = &omap44xx_l3_instr_hwmod,
3884         .clk            = "l3_div_ck",
3885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3886 };
3887
3888 /* l3_main_3 -> l3_instr */
3889 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3890         .master         = &omap44xx_l3_main_3_hwmod,
3891         .slave          = &omap44xx_l3_instr_hwmod,
3892         .clk            = "l3_div_ck",
3893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3894 };
3895
3896 /* ocp_wp_noc -> l3_instr */
3897 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3898         .master         = &omap44xx_ocp_wp_noc_hwmod,
3899         .slave          = &omap44xx_l3_instr_hwmod,
3900         .clk            = "l3_div_ck",
3901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3902 };
3903
3904 /* dsp -> l3_main_1 */
3905 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3906         .master         = &omap44xx_dsp_hwmod,
3907         .slave          = &omap44xx_l3_main_1_hwmod,
3908         .clk            = "l3_div_ck",
3909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3910 };
3911
3912 /* dss -> l3_main_1 */
3913 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3914         .master         = &omap44xx_dss_hwmod,
3915         .slave          = &omap44xx_l3_main_1_hwmod,
3916         .clk            = "l3_div_ck",
3917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3918 };
3919
3920 /* l3_main_2 -> l3_main_1 */
3921 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3922         .master         = &omap44xx_l3_main_2_hwmod,
3923         .slave          = &omap44xx_l3_main_1_hwmod,
3924         .clk            = "l3_div_ck",
3925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3926 };
3927
3928 /* l4_cfg -> l3_main_1 */
3929 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3930         .master         = &omap44xx_l4_cfg_hwmod,
3931         .slave          = &omap44xx_l3_main_1_hwmod,
3932         .clk            = "l4_div_ck",
3933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3934 };
3935
3936 /* mmc1 -> l3_main_1 */
3937 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3938         .master         = &omap44xx_mmc1_hwmod,
3939         .slave          = &omap44xx_l3_main_1_hwmod,
3940         .clk            = "l3_div_ck",
3941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3942 };
3943
3944 /* mmc2 -> l3_main_1 */
3945 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3946         .master         = &omap44xx_mmc2_hwmod,
3947         .slave          = &omap44xx_l3_main_1_hwmod,
3948         .clk            = "l3_div_ck",
3949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3950 };
3951
3952 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3953         {
3954                 .pa_start       = 0x44000000,
3955                 .pa_end         = 0x44000fff,
3956                 .flags          = ADDR_TYPE_RT
3957         },
3958         { }
3959 };
3960
3961 /* mpu -> l3_main_1 */
3962 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3963         .master         = &omap44xx_mpu_hwmod,
3964         .slave          = &omap44xx_l3_main_1_hwmod,
3965         .clk            = "l3_div_ck",
3966         .addr           = omap44xx_l3_main_1_addrs,
3967         .user           = OCP_USER_MPU,
3968 };
3969
3970 /* c2c_target_fw -> l3_main_2 */
3971 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3972         .master         = &omap44xx_c2c_target_fw_hwmod,
3973         .slave          = &omap44xx_l3_main_2_hwmod,
3974         .clk            = "l3_div_ck",
3975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 /* debugss -> l3_main_2 */
3979 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3980         .master         = &omap44xx_debugss_hwmod,
3981         .slave          = &omap44xx_l3_main_2_hwmod,
3982         .clk            = "dbgclk_mux_ck",
3983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3984 };
3985
3986 /* dma_system -> l3_main_2 */
3987 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3988         .master         = &omap44xx_dma_system_hwmod,
3989         .slave          = &omap44xx_l3_main_2_hwmod,
3990         .clk            = "l3_div_ck",
3991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3992 };
3993
3994 /* fdif -> l3_main_2 */
3995 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3996         .master         = &omap44xx_fdif_hwmod,
3997         .slave          = &omap44xx_l3_main_2_hwmod,
3998         .clk            = "l3_div_ck",
3999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4000 };
4001
4002 /* gpu -> l3_main_2 */
4003 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4004         .master         = &omap44xx_gpu_hwmod,
4005         .slave          = &omap44xx_l3_main_2_hwmod,
4006         .clk            = "l3_div_ck",
4007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4008 };
4009
4010 /* hsi -> l3_main_2 */
4011 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4012         .master         = &omap44xx_hsi_hwmod,
4013         .slave          = &omap44xx_l3_main_2_hwmod,
4014         .clk            = "l3_div_ck",
4015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4016 };
4017
4018 /* ipu -> l3_main_2 */
4019 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4020         .master         = &omap44xx_ipu_hwmod,
4021         .slave          = &omap44xx_l3_main_2_hwmod,
4022         .clk            = "l3_div_ck",
4023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4024 };
4025
4026 /* iss -> l3_main_2 */
4027 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4028         .master         = &omap44xx_iss_hwmod,
4029         .slave          = &omap44xx_l3_main_2_hwmod,
4030         .clk            = "l3_div_ck",
4031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4032 };
4033
4034 /* iva -> l3_main_2 */
4035 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4036         .master         = &omap44xx_iva_hwmod,
4037         .slave          = &omap44xx_l3_main_2_hwmod,
4038         .clk            = "l3_div_ck",
4039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4040 };
4041
4042 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4043         {
4044                 .pa_start       = 0x44800000,
4045                 .pa_end         = 0x44801fff,
4046                 .flags          = ADDR_TYPE_RT
4047         },
4048         { }
4049 };
4050
4051 /* l3_main_1 -> l3_main_2 */
4052 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4053         .master         = &omap44xx_l3_main_1_hwmod,
4054         .slave          = &omap44xx_l3_main_2_hwmod,
4055         .clk            = "l3_div_ck",
4056         .addr           = omap44xx_l3_main_2_addrs,
4057         .user           = OCP_USER_MPU,
4058 };
4059
4060 /* l4_cfg -> l3_main_2 */
4061 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4062         .master         = &omap44xx_l4_cfg_hwmod,
4063         .slave          = &omap44xx_l3_main_2_hwmod,
4064         .clk            = "l4_div_ck",
4065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4066 };
4067
4068 /* usb_host_fs -> l3_main_2 */
4069 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4070         .master         = &omap44xx_usb_host_fs_hwmod,
4071         .slave          = &omap44xx_l3_main_2_hwmod,
4072         .clk            = "l3_div_ck",
4073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4075
4076 /* usb_host_hs -> l3_main_2 */
4077 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4078         .master         = &omap44xx_usb_host_hs_hwmod,
4079         .slave          = &omap44xx_l3_main_2_hwmod,
4080         .clk            = "l3_div_ck",
4081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4082 };
4083
4084 /* usb_otg_hs -> l3_main_2 */
4085 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4086         .master         = &omap44xx_usb_otg_hs_hwmod,
4087         .slave          = &omap44xx_l3_main_2_hwmod,
4088         .clk            = "l3_div_ck",
4089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4090 };
4091
4092 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4093         {
4094                 .pa_start       = 0x45000000,
4095                 .pa_end         = 0x45000fff,
4096                 .flags          = ADDR_TYPE_RT
4097         },
4098         { }
4099 };
4100
4101 /* l3_main_1 -> l3_main_3 */
4102 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4103         .master         = &omap44xx_l3_main_1_hwmod,
4104         .slave          = &omap44xx_l3_main_3_hwmod,
4105         .clk            = "l3_div_ck",
4106         .addr           = omap44xx_l3_main_3_addrs,
4107         .user           = OCP_USER_MPU,
4108 };
4109
4110 /* l3_main_2 -> l3_main_3 */
4111 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4112         .master         = &omap44xx_l3_main_2_hwmod,
4113         .slave          = &omap44xx_l3_main_3_hwmod,
4114         .clk            = "l3_div_ck",
4115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4116 };
4117
4118 /* l4_cfg -> l3_main_3 */
4119 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4120         .master         = &omap44xx_l4_cfg_hwmod,
4121         .slave          = &omap44xx_l3_main_3_hwmod,
4122         .clk            = "l4_div_ck",
4123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4124 };
4125
4126 /* aess -> l4_abe */
4127 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4128         .master         = &omap44xx_aess_hwmod,
4129         .slave          = &omap44xx_l4_abe_hwmod,
4130         .clk            = "ocp_abe_iclk",
4131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4132 };
4133
4134 /* dsp -> l4_abe */
4135 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4136         .master         = &omap44xx_dsp_hwmod,
4137         .slave          = &omap44xx_l4_abe_hwmod,
4138         .clk            = "ocp_abe_iclk",
4139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4140 };
4141
4142 /* l3_main_1 -> l4_abe */
4143 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4144         .master         = &omap44xx_l3_main_1_hwmod,
4145         .slave          = &omap44xx_l4_abe_hwmod,
4146         .clk            = "l3_div_ck",
4147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4148 };
4149
4150 /* mpu -> l4_abe */
4151 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4152         .master         = &omap44xx_mpu_hwmod,
4153         .slave          = &omap44xx_l4_abe_hwmod,
4154         .clk            = "ocp_abe_iclk",
4155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4156 };
4157
4158 /* l3_main_1 -> l4_cfg */
4159 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4160         .master         = &omap44xx_l3_main_1_hwmod,
4161         .slave          = &omap44xx_l4_cfg_hwmod,
4162         .clk            = "l3_div_ck",
4163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4164 };
4165
4166 /* l3_main_2 -> l4_per */
4167 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4168         .master         = &omap44xx_l3_main_2_hwmod,
4169         .slave          = &omap44xx_l4_per_hwmod,
4170         .clk            = "l3_div_ck",
4171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4172 };
4173
4174 /* l4_cfg -> l4_wkup */
4175 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4176         .master         = &omap44xx_l4_cfg_hwmod,
4177         .slave          = &omap44xx_l4_wkup_hwmod,
4178         .clk            = "l4_div_ck",
4179         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4180 };
4181
4182 /* mpu -> mpu_private */
4183 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4184         .master         = &omap44xx_mpu_hwmod,
4185         .slave          = &omap44xx_mpu_private_hwmod,
4186         .clk            = "l3_div_ck",
4187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4188 };
4189
4190 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4191         {
4192                 .pa_start       = 0x4a102000,
4193                 .pa_end         = 0x4a10207f,
4194                 .flags          = ADDR_TYPE_RT
4195         },
4196         { }
4197 };
4198
4199 /* l4_cfg -> ocp_wp_noc */
4200 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4201         .master         = &omap44xx_l4_cfg_hwmod,
4202         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4203         .clk            = "l4_div_ck",
4204         .addr           = omap44xx_ocp_wp_noc_addrs,
4205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4206 };
4207
4208 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4209         {
4210                 .pa_start       = 0x401f1000,
4211                 .pa_end         = 0x401f13ff,
4212                 .flags          = ADDR_TYPE_RT
4213         },
4214         { }
4215 };
4216
4217 /* l4_abe -> aess */
4218 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4219         .master         = &omap44xx_l4_abe_hwmod,
4220         .slave          = &omap44xx_aess_hwmod,
4221         .clk            = "ocp_abe_iclk",
4222         .addr           = omap44xx_aess_addrs,
4223         .user           = OCP_USER_MPU,
4224 };
4225
4226 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4227         {
4228                 .pa_start       = 0x490f1000,
4229                 .pa_end         = 0x490f13ff,
4230                 .flags          = ADDR_TYPE_RT
4231         },
4232         { }
4233 };
4234
4235 /* l4_abe -> aess (dma) */
4236 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4237         .master         = &omap44xx_l4_abe_hwmod,
4238         .slave          = &omap44xx_aess_hwmod,
4239         .clk            = "ocp_abe_iclk",
4240         .addr           = omap44xx_aess_dma_addrs,
4241         .user           = OCP_USER_SDMA,
4242 };
4243
4244 /* l3_main_2 -> c2c */
4245 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4246         .master         = &omap44xx_l3_main_2_hwmod,
4247         .slave          = &omap44xx_c2c_hwmod,
4248         .clk            = "l3_div_ck",
4249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4250 };
4251
4252 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4253         {
4254                 .pa_start       = 0x4a304000,
4255                 .pa_end         = 0x4a30401f,
4256                 .flags          = ADDR_TYPE_RT
4257         },
4258         { }
4259 };
4260
4261 /* l4_wkup -> counter_32k */
4262 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4263         .master         = &omap44xx_l4_wkup_hwmod,
4264         .slave          = &omap44xx_counter_32k_hwmod,
4265         .clk            = "l4_wkup_clk_mux_ck",
4266         .addr           = omap44xx_counter_32k_addrs,
4267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4268 };
4269
4270 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4271         {
4272                 .pa_start       = 0x4a002000,
4273                 .pa_end         = 0x4a0027ff,
4274                 .flags          = ADDR_TYPE_RT
4275         },
4276         { }
4277 };
4278
4279 /* l4_cfg -> ctrl_module_core */
4280 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4281         .master         = &omap44xx_l4_cfg_hwmod,
4282         .slave          = &omap44xx_ctrl_module_core_hwmod,
4283         .clk            = "l4_div_ck",
4284         .addr           = omap44xx_ctrl_module_core_addrs,
4285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4286 };
4287
4288 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4289         {
4290                 .pa_start       = 0x4a100000,
4291                 .pa_end         = 0x4a1007ff,
4292                 .flags          = ADDR_TYPE_RT
4293         },
4294         { }
4295 };
4296
4297 /* l4_cfg -> ctrl_module_pad_core */
4298 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4299         .master         = &omap44xx_l4_cfg_hwmod,
4300         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4301         .clk            = "l4_div_ck",
4302         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4304 };
4305
4306 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4307         {
4308                 .pa_start       = 0x4a30c000,
4309                 .pa_end         = 0x4a30c7ff,
4310                 .flags          = ADDR_TYPE_RT
4311         },
4312         { }
4313 };
4314
4315 /* l4_wkup -> ctrl_module_wkup */
4316 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4317         .master         = &omap44xx_l4_wkup_hwmod,
4318         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4319         .clk            = "l4_wkup_clk_mux_ck",
4320         .addr           = omap44xx_ctrl_module_wkup_addrs,
4321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4322 };
4323
4324 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4325         {
4326                 .pa_start       = 0x4a31e000,
4327                 .pa_end         = 0x4a31e7ff,
4328                 .flags          = ADDR_TYPE_RT
4329         },
4330         { }
4331 };
4332
4333 /* l4_wkup -> ctrl_module_pad_wkup */
4334 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4335         .master         = &omap44xx_l4_wkup_hwmod,
4336         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4337         .clk            = "l4_wkup_clk_mux_ck",
4338         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4340 };
4341
4342 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4343         {
4344                 .pa_start       = 0x54160000,
4345                 .pa_end         = 0x54167fff,
4346                 .flags          = ADDR_TYPE_RT
4347         },
4348         { }
4349 };
4350
4351 /* l3_instr -> debugss */
4352 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4353         .master         = &omap44xx_l3_instr_hwmod,
4354         .slave          = &omap44xx_debugss_hwmod,
4355         .clk            = "l3_div_ck",
4356         .addr           = omap44xx_debugss_addrs,
4357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4358 };
4359
4360 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4361         {
4362                 .pa_start       = 0x4a056000,
4363                 .pa_end         = 0x4a056fff,
4364                 .flags          = ADDR_TYPE_RT
4365         },
4366         { }
4367 };
4368
4369 /* l4_cfg -> dma_system */
4370 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4371         .master         = &omap44xx_l4_cfg_hwmod,
4372         .slave          = &omap44xx_dma_system_hwmod,
4373         .clk            = "l4_div_ck",
4374         .addr           = omap44xx_dma_system_addrs,
4375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4376 };
4377
4378 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4379         {
4380                 .name           = "mpu",
4381                 .pa_start       = 0x4012e000,
4382                 .pa_end         = 0x4012e07f,
4383                 .flags          = ADDR_TYPE_RT
4384         },
4385         { }
4386 };
4387
4388 /* l4_abe -> dmic */
4389 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4390         .master         = &omap44xx_l4_abe_hwmod,
4391         .slave          = &omap44xx_dmic_hwmod,
4392         .clk            = "ocp_abe_iclk",
4393         .addr           = omap44xx_dmic_addrs,
4394         .user           = OCP_USER_MPU,
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4398         {
4399                 .name           = "dma",
4400                 .pa_start       = 0x4902e000,
4401                 .pa_end         = 0x4902e07f,
4402                 .flags          = ADDR_TYPE_RT
4403         },
4404         { }
4405 };
4406
4407 /* l4_abe -> dmic (dma) */
4408 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4409         .master         = &omap44xx_l4_abe_hwmod,
4410         .slave          = &omap44xx_dmic_hwmod,
4411         .clk            = "ocp_abe_iclk",
4412         .addr           = omap44xx_dmic_dma_addrs,
4413         .user           = OCP_USER_SDMA,
4414 };
4415
4416 /* dsp -> iva */
4417 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4418         .master         = &omap44xx_dsp_hwmod,
4419         .slave          = &omap44xx_iva_hwmod,
4420         .clk            = "dpll_iva_m5x2_ck",
4421         .user           = OCP_USER_DSP,
4422 };
4423
4424 /* dsp -> sl2if */
4425 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4426         .master         = &omap44xx_dsp_hwmod,
4427         .slave          = &omap44xx_sl2if_hwmod,
4428         .clk            = "dpll_iva_m5x2_ck",
4429         .user           = OCP_USER_DSP,
4430 };
4431
4432 /* l4_cfg -> dsp */
4433 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4434         .master         = &omap44xx_l4_cfg_hwmod,
4435         .slave          = &omap44xx_dsp_hwmod,
4436         .clk            = "l4_div_ck",
4437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4438 };
4439
4440 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4441         {
4442                 .pa_start       = 0x58000000,
4443                 .pa_end         = 0x5800007f,
4444                 .flags          = ADDR_TYPE_RT
4445         },
4446         { }
4447 };
4448
4449 /* l3_main_2 -> dss */
4450 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4451         .master         = &omap44xx_l3_main_2_hwmod,
4452         .slave          = &omap44xx_dss_hwmod,
4453         .clk            = "dss_fck",
4454         .addr           = omap44xx_dss_dma_addrs,
4455         .user           = OCP_USER_SDMA,
4456 };
4457
4458 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4459         {
4460                 .pa_start       = 0x48040000,
4461                 .pa_end         = 0x4804007f,
4462                 .flags          = ADDR_TYPE_RT
4463         },
4464         { }
4465 };
4466
4467 /* l4_per -> dss */
4468 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4469         .master         = &omap44xx_l4_per_hwmod,
4470         .slave          = &omap44xx_dss_hwmod,
4471         .clk            = "l4_div_ck",
4472         .addr           = omap44xx_dss_addrs,
4473         .user           = OCP_USER_MPU,
4474 };
4475
4476 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4477         {
4478                 .pa_start       = 0x58001000,
4479                 .pa_end         = 0x58001fff,
4480                 .flags          = ADDR_TYPE_RT
4481         },
4482         { }
4483 };
4484
4485 /* l3_main_2 -> dss_dispc */
4486 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4487         .master         = &omap44xx_l3_main_2_hwmod,
4488         .slave          = &omap44xx_dss_dispc_hwmod,
4489         .clk            = "dss_fck",
4490         .addr           = omap44xx_dss_dispc_dma_addrs,
4491         .user           = OCP_USER_SDMA,
4492 };
4493
4494 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4495         {
4496                 .pa_start       = 0x48041000,
4497                 .pa_end         = 0x48041fff,
4498                 .flags          = ADDR_TYPE_RT
4499         },
4500         { }
4501 };
4502
4503 /* l4_per -> dss_dispc */
4504 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4505         .master         = &omap44xx_l4_per_hwmod,
4506         .slave          = &omap44xx_dss_dispc_hwmod,
4507         .clk            = "l4_div_ck",
4508         .addr           = omap44xx_dss_dispc_addrs,
4509         .user           = OCP_USER_MPU,
4510 };
4511
4512 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4513         {
4514                 .pa_start       = 0x58004000,
4515                 .pa_end         = 0x580041ff,
4516                 .flags          = ADDR_TYPE_RT
4517         },
4518         { }
4519 };
4520
4521 /* l3_main_2 -> dss_dsi1 */
4522 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4523         .master         = &omap44xx_l3_main_2_hwmod,
4524         .slave          = &omap44xx_dss_dsi1_hwmod,
4525         .clk            = "dss_fck",
4526         .addr           = omap44xx_dss_dsi1_dma_addrs,
4527         .user           = OCP_USER_SDMA,
4528 };
4529
4530 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4531         {
4532                 .pa_start       = 0x48044000,
4533                 .pa_end         = 0x480441ff,
4534                 .flags          = ADDR_TYPE_RT
4535         },
4536         { }
4537 };
4538
4539 /* l4_per -> dss_dsi1 */
4540 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4541         .master         = &omap44xx_l4_per_hwmod,
4542         .slave          = &omap44xx_dss_dsi1_hwmod,
4543         .clk            = "l4_div_ck",
4544         .addr           = omap44xx_dss_dsi1_addrs,
4545         .user           = OCP_USER_MPU,
4546 };
4547
4548 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4549         {
4550                 .pa_start       = 0x58005000,
4551                 .pa_end         = 0x580051ff,
4552                 .flags          = ADDR_TYPE_RT
4553         },
4554         { }
4555 };
4556
4557 /* l3_main_2 -> dss_dsi2 */
4558 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4559         .master         = &omap44xx_l3_main_2_hwmod,
4560         .slave          = &omap44xx_dss_dsi2_hwmod,
4561         .clk            = "dss_fck",
4562         .addr           = omap44xx_dss_dsi2_dma_addrs,
4563         .user           = OCP_USER_SDMA,
4564 };
4565
4566 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4567         {
4568                 .pa_start       = 0x48045000,
4569                 .pa_end         = 0x480451ff,
4570                 .flags          = ADDR_TYPE_RT
4571         },
4572         { }
4573 };
4574
4575 /* l4_per -> dss_dsi2 */
4576 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4577         .master         = &omap44xx_l4_per_hwmod,
4578         .slave          = &omap44xx_dss_dsi2_hwmod,
4579         .clk            = "l4_div_ck",
4580         .addr           = omap44xx_dss_dsi2_addrs,
4581         .user           = OCP_USER_MPU,
4582 };
4583
4584 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4585         {
4586                 .pa_start       = 0x58006000,
4587                 .pa_end         = 0x58006fff,
4588                 .flags          = ADDR_TYPE_RT
4589         },
4590         { }
4591 };
4592
4593 /* l3_main_2 -> dss_hdmi */
4594 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4595         .master         = &omap44xx_l3_main_2_hwmod,
4596         .slave          = &omap44xx_dss_hdmi_hwmod,
4597         .clk            = "dss_fck",
4598         .addr           = omap44xx_dss_hdmi_dma_addrs,
4599         .user           = OCP_USER_SDMA,
4600 };
4601
4602 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4603         {
4604                 .pa_start       = 0x48046000,
4605                 .pa_end         = 0x48046fff,
4606                 .flags          = ADDR_TYPE_RT
4607         },
4608         { }
4609 };
4610
4611 /* l4_per -> dss_hdmi */
4612 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4613         .master         = &omap44xx_l4_per_hwmod,
4614         .slave          = &omap44xx_dss_hdmi_hwmod,
4615         .clk            = "l4_div_ck",
4616         .addr           = omap44xx_dss_hdmi_addrs,
4617         .user           = OCP_USER_MPU,
4618 };
4619
4620 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4621         {
4622                 .pa_start       = 0x58002000,
4623                 .pa_end         = 0x580020ff,
4624                 .flags          = ADDR_TYPE_RT
4625         },
4626         { }
4627 };
4628
4629 /* l3_main_2 -> dss_rfbi */
4630 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4631         .master         = &omap44xx_l3_main_2_hwmod,
4632         .slave          = &omap44xx_dss_rfbi_hwmod,
4633         .clk            = "dss_fck",
4634         .addr           = omap44xx_dss_rfbi_dma_addrs,
4635         .user           = OCP_USER_SDMA,
4636 };
4637
4638 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4639         {
4640                 .pa_start       = 0x48042000,
4641                 .pa_end         = 0x480420ff,
4642                 .flags          = ADDR_TYPE_RT
4643         },
4644         { }
4645 };
4646
4647 /* l4_per -> dss_rfbi */
4648 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4649         .master         = &omap44xx_l4_per_hwmod,
4650         .slave          = &omap44xx_dss_rfbi_hwmod,
4651         .clk            = "l4_div_ck",
4652         .addr           = omap44xx_dss_rfbi_addrs,
4653         .user           = OCP_USER_MPU,
4654 };
4655
4656 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4657         {
4658                 .pa_start       = 0x58003000,
4659                 .pa_end         = 0x580030ff,
4660                 .flags          = ADDR_TYPE_RT
4661         },
4662         { }
4663 };
4664
4665 /* l3_main_2 -> dss_venc */
4666 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4667         .master         = &omap44xx_l3_main_2_hwmod,
4668         .slave          = &omap44xx_dss_venc_hwmod,
4669         .clk            = "dss_fck",
4670         .addr           = omap44xx_dss_venc_dma_addrs,
4671         .user           = OCP_USER_SDMA,
4672 };
4673
4674 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4675         {
4676                 .pa_start       = 0x48043000,
4677                 .pa_end         = 0x480430ff,
4678                 .flags          = ADDR_TYPE_RT
4679         },
4680         { }
4681 };
4682
4683 /* l4_per -> dss_venc */
4684 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4685         .master         = &omap44xx_l4_per_hwmod,
4686         .slave          = &omap44xx_dss_venc_hwmod,
4687         .clk            = "l4_div_ck",
4688         .addr           = omap44xx_dss_venc_addrs,
4689         .user           = OCP_USER_MPU,
4690 };
4691
4692 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4693         {
4694                 .pa_start       = 0x48078000,
4695                 .pa_end         = 0x48078fff,
4696                 .flags          = ADDR_TYPE_RT
4697         },
4698         { }
4699 };
4700
4701 /* l4_per -> elm */
4702 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4703         .master         = &omap44xx_l4_per_hwmod,
4704         .slave          = &omap44xx_elm_hwmod,
4705         .clk            = "l4_div_ck",
4706         .addr           = omap44xx_elm_addrs,
4707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4708 };
4709
4710 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4711         {
4712                 .pa_start       = 0x4c000000,
4713                 .pa_end         = 0x4c0000ff,
4714                 .flags          = ADDR_TYPE_RT
4715         },
4716         { }
4717 };
4718
4719 /* emif_fw -> emif1 */
4720 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4721         .master         = &omap44xx_emif_fw_hwmod,
4722         .slave          = &omap44xx_emif1_hwmod,
4723         .clk            = "l3_div_ck",
4724         .addr           = omap44xx_emif1_addrs,
4725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4726 };
4727
4728 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4729         {
4730                 .pa_start       = 0x4d000000,
4731                 .pa_end         = 0x4d0000ff,
4732                 .flags          = ADDR_TYPE_RT
4733         },
4734         { }
4735 };
4736
4737 /* emif_fw -> emif2 */
4738 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4739         .master         = &omap44xx_emif_fw_hwmod,
4740         .slave          = &omap44xx_emif2_hwmod,
4741         .clk            = "l3_div_ck",
4742         .addr           = omap44xx_emif2_addrs,
4743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4744 };
4745
4746 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4747         {
4748                 .pa_start       = 0x4a10a000,
4749                 .pa_end         = 0x4a10a1ff,
4750                 .flags          = ADDR_TYPE_RT
4751         },
4752         { }
4753 };
4754
4755 /* l4_cfg -> fdif */
4756 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4757         .master         = &omap44xx_l4_cfg_hwmod,
4758         .slave          = &omap44xx_fdif_hwmod,
4759         .clk            = "l4_div_ck",
4760         .addr           = omap44xx_fdif_addrs,
4761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4762 };
4763
4764 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4765         {
4766                 .pa_start       = 0x4a310000,
4767                 .pa_end         = 0x4a3101ff,
4768                 .flags          = ADDR_TYPE_RT
4769         },
4770         { }
4771 };
4772
4773 /* l4_wkup -> gpio1 */
4774 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4775         .master         = &omap44xx_l4_wkup_hwmod,
4776         .slave          = &omap44xx_gpio1_hwmod,
4777         .clk            = "l4_wkup_clk_mux_ck",
4778         .addr           = omap44xx_gpio1_addrs,
4779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4780 };
4781
4782 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4783         {
4784                 .pa_start       = 0x48055000,
4785                 .pa_end         = 0x480551ff,
4786                 .flags          = ADDR_TYPE_RT
4787         },
4788         { }
4789 };
4790
4791 /* l4_per -> gpio2 */
4792 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4793         .master         = &omap44xx_l4_per_hwmod,
4794         .slave          = &omap44xx_gpio2_hwmod,
4795         .clk            = "l4_div_ck",
4796         .addr           = omap44xx_gpio2_addrs,
4797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4798 };
4799
4800 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4801         {
4802                 .pa_start       = 0x48057000,
4803                 .pa_end         = 0x480571ff,
4804                 .flags          = ADDR_TYPE_RT
4805         },
4806         { }
4807 };
4808
4809 /* l4_per -> gpio3 */
4810 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4811         .master         = &omap44xx_l4_per_hwmod,
4812         .slave          = &omap44xx_gpio3_hwmod,
4813         .clk            = "l4_div_ck",
4814         .addr           = omap44xx_gpio3_addrs,
4815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4816 };
4817
4818 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4819         {
4820                 .pa_start       = 0x48059000,
4821                 .pa_end         = 0x480591ff,
4822                 .flags          = ADDR_TYPE_RT
4823         },
4824         { }
4825 };
4826
4827 /* l4_per -> gpio4 */
4828 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4829         .master         = &omap44xx_l4_per_hwmod,
4830         .slave          = &omap44xx_gpio4_hwmod,
4831         .clk            = "l4_div_ck",
4832         .addr           = omap44xx_gpio4_addrs,
4833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4834 };
4835
4836 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4837         {
4838                 .pa_start       = 0x4805b000,
4839                 .pa_end         = 0x4805b1ff,
4840                 .flags          = ADDR_TYPE_RT
4841         },
4842         { }
4843 };
4844
4845 /* l4_per -> gpio5 */
4846 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4847         .master         = &omap44xx_l4_per_hwmod,
4848         .slave          = &omap44xx_gpio5_hwmod,
4849         .clk            = "l4_div_ck",
4850         .addr           = omap44xx_gpio5_addrs,
4851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4852 };
4853
4854 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4855         {
4856                 .pa_start       = 0x4805d000,
4857                 .pa_end         = 0x4805d1ff,
4858                 .flags          = ADDR_TYPE_RT
4859         },
4860         { }
4861 };
4862
4863 /* l4_per -> gpio6 */
4864 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4865         .master         = &omap44xx_l4_per_hwmod,
4866         .slave          = &omap44xx_gpio6_hwmod,
4867         .clk            = "l4_div_ck",
4868         .addr           = omap44xx_gpio6_addrs,
4869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4870 };
4871
4872 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4873         {
4874                 .pa_start       = 0x50000000,
4875                 .pa_end         = 0x500003ff,
4876                 .flags          = ADDR_TYPE_RT
4877         },
4878         { }
4879 };
4880
4881 /* l3_main_2 -> gpmc */
4882 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4883         .master         = &omap44xx_l3_main_2_hwmod,
4884         .slave          = &omap44xx_gpmc_hwmod,
4885         .clk            = "l3_div_ck",
4886         .addr           = omap44xx_gpmc_addrs,
4887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4888 };
4889
4890 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4891         {
4892                 .pa_start       = 0x56000000,
4893                 .pa_end         = 0x5600ffff,
4894                 .flags          = ADDR_TYPE_RT
4895         },
4896         { }
4897 };
4898
4899 /* l3_main_2 -> gpu */
4900 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4901         .master         = &omap44xx_l3_main_2_hwmod,
4902         .slave          = &omap44xx_gpu_hwmod,
4903         .clk            = "l3_div_ck",
4904         .addr           = omap44xx_gpu_addrs,
4905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4906 };
4907
4908 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4909         {
4910                 .pa_start       = 0x480b2000,
4911                 .pa_end         = 0x480b201f,
4912                 .flags          = ADDR_TYPE_RT
4913         },
4914         { }
4915 };
4916
4917 /* l4_per -> hdq1w */
4918 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4919         .master         = &omap44xx_l4_per_hwmod,
4920         .slave          = &omap44xx_hdq1w_hwmod,
4921         .clk            = "l4_div_ck",
4922         .addr           = omap44xx_hdq1w_addrs,
4923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4924 };
4925
4926 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4927         {
4928                 .pa_start       = 0x4a058000,
4929                 .pa_end         = 0x4a05bfff,
4930                 .flags          = ADDR_TYPE_RT
4931         },
4932         { }
4933 };
4934
4935 /* l4_cfg -> hsi */
4936 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4937         .master         = &omap44xx_l4_cfg_hwmod,
4938         .slave          = &omap44xx_hsi_hwmod,
4939         .clk            = "l4_div_ck",
4940         .addr           = omap44xx_hsi_addrs,
4941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4942 };
4943
4944 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4945         {
4946                 .pa_start       = 0x48070000,
4947                 .pa_end         = 0x480700ff,
4948                 .flags          = ADDR_TYPE_RT
4949         },
4950         { }
4951 };
4952
4953 /* l4_per -> i2c1 */
4954 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4955         .master         = &omap44xx_l4_per_hwmod,
4956         .slave          = &omap44xx_i2c1_hwmod,
4957         .clk            = "l4_div_ck",
4958         .addr           = omap44xx_i2c1_addrs,
4959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4960 };
4961
4962 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4963         {
4964                 .pa_start       = 0x48072000,
4965                 .pa_end         = 0x480720ff,
4966                 .flags          = ADDR_TYPE_RT
4967         },
4968         { }
4969 };
4970
4971 /* l4_per -> i2c2 */
4972 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4973         .master         = &omap44xx_l4_per_hwmod,
4974         .slave          = &omap44xx_i2c2_hwmod,
4975         .clk            = "l4_div_ck",
4976         .addr           = omap44xx_i2c2_addrs,
4977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4978 };
4979
4980 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4981         {
4982                 .pa_start       = 0x48060000,
4983                 .pa_end         = 0x480600ff,
4984                 .flags          = ADDR_TYPE_RT
4985         },
4986         { }
4987 };
4988
4989 /* l4_per -> i2c3 */
4990 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4991         .master         = &omap44xx_l4_per_hwmod,
4992         .slave          = &omap44xx_i2c3_hwmod,
4993         .clk            = "l4_div_ck",
4994         .addr           = omap44xx_i2c3_addrs,
4995         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4996 };
4997
4998 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4999         {
5000                 .pa_start       = 0x48350000,
5001                 .pa_end         = 0x483500ff,
5002                 .flags          = ADDR_TYPE_RT
5003         },
5004         { }
5005 };
5006
5007 /* l4_per -> i2c4 */
5008 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5009         .master         = &omap44xx_l4_per_hwmod,
5010         .slave          = &omap44xx_i2c4_hwmod,
5011         .clk            = "l4_div_ck",
5012         .addr           = omap44xx_i2c4_addrs,
5013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5014 };
5015
5016 /* l3_main_2 -> ipu */
5017 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5018         .master         = &omap44xx_l3_main_2_hwmod,
5019         .slave          = &omap44xx_ipu_hwmod,
5020         .clk            = "l3_div_ck",
5021         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5022 };
5023
5024 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5025         {
5026                 .pa_start       = 0x52000000,
5027                 .pa_end         = 0x520000ff,
5028                 .flags          = ADDR_TYPE_RT
5029         },
5030         { }
5031 };
5032
5033 /* l3_main_2 -> iss */
5034 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5035         .master         = &omap44xx_l3_main_2_hwmod,
5036         .slave          = &omap44xx_iss_hwmod,
5037         .clk            = "l3_div_ck",
5038         .addr           = omap44xx_iss_addrs,
5039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5040 };
5041
5042 /* iva -> sl2if */
5043 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5044         .master         = &omap44xx_iva_hwmod,
5045         .slave          = &omap44xx_sl2if_hwmod,
5046         .clk            = "dpll_iva_m5x2_ck",
5047         .user           = OCP_USER_IVA,
5048 };
5049
5050 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5051         {
5052                 .pa_start       = 0x5a000000,
5053                 .pa_end         = 0x5a07ffff,
5054                 .flags          = ADDR_TYPE_RT
5055         },
5056         { }
5057 };
5058
5059 /* l3_main_2 -> iva */
5060 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5061         .master         = &omap44xx_l3_main_2_hwmod,
5062         .slave          = &omap44xx_iva_hwmod,
5063         .clk            = "l3_div_ck",
5064         .addr           = omap44xx_iva_addrs,
5065         .user           = OCP_USER_MPU,
5066 };
5067
5068 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5069         {
5070                 .pa_start       = 0x4a31c000,
5071                 .pa_end         = 0x4a31c07f,
5072                 .flags          = ADDR_TYPE_RT
5073         },
5074         { }
5075 };
5076
5077 /* l4_wkup -> kbd */
5078 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5079         .master         = &omap44xx_l4_wkup_hwmod,
5080         .slave          = &omap44xx_kbd_hwmod,
5081         .clk            = "l4_wkup_clk_mux_ck",
5082         .addr           = omap44xx_kbd_addrs,
5083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5084 };
5085
5086 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5087         {
5088                 .pa_start       = 0x4a0f4000,
5089                 .pa_end         = 0x4a0f41ff,
5090                 .flags          = ADDR_TYPE_RT
5091         },
5092         { }
5093 };
5094
5095 /* l4_cfg -> mailbox */
5096 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5097         .master         = &omap44xx_l4_cfg_hwmod,
5098         .slave          = &omap44xx_mailbox_hwmod,
5099         .clk            = "l4_div_ck",
5100         .addr           = omap44xx_mailbox_addrs,
5101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5102 };
5103
5104 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5105         {
5106                 .pa_start       = 0x40128000,
5107                 .pa_end         = 0x401283ff,
5108                 .flags          = ADDR_TYPE_RT
5109         },
5110         { }
5111 };
5112
5113 /* l4_abe -> mcasp */
5114 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5115         .master         = &omap44xx_l4_abe_hwmod,
5116         .slave          = &omap44xx_mcasp_hwmod,
5117         .clk            = "ocp_abe_iclk",
5118         .addr           = omap44xx_mcasp_addrs,
5119         .user           = OCP_USER_MPU,
5120 };
5121
5122 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5123         {
5124                 .pa_start       = 0x49028000,
5125                 .pa_end         = 0x490283ff,
5126                 .flags          = ADDR_TYPE_RT
5127         },
5128         { }
5129 };
5130
5131 /* l4_abe -> mcasp (dma) */
5132 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5133         .master         = &omap44xx_l4_abe_hwmod,
5134         .slave          = &omap44xx_mcasp_hwmod,
5135         .clk            = "ocp_abe_iclk",
5136         .addr           = omap44xx_mcasp_dma_addrs,
5137         .user           = OCP_USER_SDMA,
5138 };
5139
5140 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5141         {
5142                 .name           = "mpu",
5143                 .pa_start       = 0x40122000,
5144                 .pa_end         = 0x401220ff,
5145                 .flags          = ADDR_TYPE_RT
5146         },
5147         { }
5148 };
5149
5150 /* l4_abe -> mcbsp1 */
5151 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5152         .master         = &omap44xx_l4_abe_hwmod,
5153         .slave          = &omap44xx_mcbsp1_hwmod,
5154         .clk            = "ocp_abe_iclk",
5155         .addr           = omap44xx_mcbsp1_addrs,
5156         .user           = OCP_USER_MPU,
5157 };
5158
5159 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5160         {
5161                 .name           = "dma",
5162                 .pa_start       = 0x49022000,
5163                 .pa_end         = 0x490220ff,
5164                 .flags          = ADDR_TYPE_RT
5165         },
5166         { }
5167 };
5168
5169 /* l4_abe -> mcbsp1 (dma) */
5170 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5171         .master         = &omap44xx_l4_abe_hwmod,
5172         .slave          = &omap44xx_mcbsp1_hwmod,
5173         .clk            = "ocp_abe_iclk",
5174         .addr           = omap44xx_mcbsp1_dma_addrs,
5175         .user           = OCP_USER_SDMA,
5176 };
5177
5178 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5179         {
5180                 .name           = "mpu",
5181                 .pa_start       = 0x40124000,
5182                 .pa_end         = 0x401240ff,
5183                 .flags          = ADDR_TYPE_RT
5184         },
5185         { }
5186 };
5187
5188 /* l4_abe -> mcbsp2 */
5189 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5190         .master         = &omap44xx_l4_abe_hwmod,
5191         .slave          = &omap44xx_mcbsp2_hwmod,
5192         .clk            = "ocp_abe_iclk",
5193         .addr           = omap44xx_mcbsp2_addrs,
5194         .user           = OCP_USER_MPU,
5195 };
5196
5197 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5198         {
5199                 .name           = "dma",
5200                 .pa_start       = 0x49024000,
5201                 .pa_end         = 0x490240ff,
5202                 .flags          = ADDR_TYPE_RT
5203         },
5204         { }
5205 };
5206
5207 /* l4_abe -> mcbsp2 (dma) */
5208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5209         .master         = &omap44xx_l4_abe_hwmod,
5210         .slave          = &omap44xx_mcbsp2_hwmod,
5211         .clk            = "ocp_abe_iclk",
5212         .addr           = omap44xx_mcbsp2_dma_addrs,
5213         .user           = OCP_USER_SDMA,
5214 };
5215
5216 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5217         {
5218                 .name           = "mpu",
5219                 .pa_start       = 0x40126000,
5220                 .pa_end         = 0x401260ff,
5221                 .flags          = ADDR_TYPE_RT
5222         },
5223         { }
5224 };
5225
5226 /* l4_abe -> mcbsp3 */
5227 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5228         .master         = &omap44xx_l4_abe_hwmod,
5229         .slave          = &omap44xx_mcbsp3_hwmod,
5230         .clk            = "ocp_abe_iclk",
5231         .addr           = omap44xx_mcbsp3_addrs,
5232         .user           = OCP_USER_MPU,
5233 };
5234
5235 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5236         {
5237                 .name           = "dma",
5238                 .pa_start       = 0x49026000,
5239                 .pa_end         = 0x490260ff,
5240                 .flags          = ADDR_TYPE_RT
5241         },
5242         { }
5243 };
5244
5245 /* l4_abe -> mcbsp3 (dma) */
5246 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5247         .master         = &omap44xx_l4_abe_hwmod,
5248         .slave          = &omap44xx_mcbsp3_hwmod,
5249         .clk            = "ocp_abe_iclk",
5250         .addr           = omap44xx_mcbsp3_dma_addrs,
5251         .user           = OCP_USER_SDMA,
5252 };
5253
5254 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5255         {
5256                 .pa_start       = 0x48096000,
5257                 .pa_end         = 0x480960ff,
5258                 .flags          = ADDR_TYPE_RT
5259         },
5260         { }
5261 };
5262
5263 /* l4_per -> mcbsp4 */
5264 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5265         .master         = &omap44xx_l4_per_hwmod,
5266         .slave          = &omap44xx_mcbsp4_hwmod,
5267         .clk            = "l4_div_ck",
5268         .addr           = omap44xx_mcbsp4_addrs,
5269         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5270 };
5271
5272 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5273         {
5274                 .name           = "mpu",
5275                 .pa_start       = 0x40132000,
5276                 .pa_end         = 0x4013207f,
5277                 .flags          = ADDR_TYPE_RT
5278         },
5279         { }
5280 };
5281
5282 /* l4_abe -> mcpdm */
5283 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5284         .master         = &omap44xx_l4_abe_hwmod,
5285         .slave          = &omap44xx_mcpdm_hwmod,
5286         .clk            = "ocp_abe_iclk",
5287         .addr           = omap44xx_mcpdm_addrs,
5288         .user           = OCP_USER_MPU,
5289 };
5290
5291 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5292         {
5293                 .name           = "dma",
5294                 .pa_start       = 0x49032000,
5295                 .pa_end         = 0x4903207f,
5296                 .flags          = ADDR_TYPE_RT
5297         },
5298         { }
5299 };
5300
5301 /* l4_abe -> mcpdm (dma) */
5302 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5303         .master         = &omap44xx_l4_abe_hwmod,
5304         .slave          = &omap44xx_mcpdm_hwmod,
5305         .clk            = "ocp_abe_iclk",
5306         .addr           = omap44xx_mcpdm_dma_addrs,
5307         .user           = OCP_USER_SDMA,
5308 };
5309
5310 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5311         {
5312                 .pa_start       = 0x48098000,
5313                 .pa_end         = 0x480981ff,
5314                 .flags          = ADDR_TYPE_RT
5315         },
5316         { }
5317 };
5318
5319 /* l4_per -> mcspi1 */
5320 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5321         .master         = &omap44xx_l4_per_hwmod,
5322         .slave          = &omap44xx_mcspi1_hwmod,
5323         .clk            = "l4_div_ck",
5324         .addr           = omap44xx_mcspi1_addrs,
5325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5326 };
5327
5328 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5329         {
5330                 .pa_start       = 0x4809a000,
5331                 .pa_end         = 0x4809a1ff,
5332                 .flags          = ADDR_TYPE_RT
5333         },
5334         { }
5335 };
5336
5337 /* l4_per -> mcspi2 */
5338 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5339         .master         = &omap44xx_l4_per_hwmod,
5340         .slave          = &omap44xx_mcspi2_hwmod,
5341         .clk            = "l4_div_ck",
5342         .addr           = omap44xx_mcspi2_addrs,
5343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5344 };
5345
5346 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5347         {
5348                 .pa_start       = 0x480b8000,
5349                 .pa_end         = 0x480b81ff,
5350                 .flags          = ADDR_TYPE_RT
5351         },
5352         { }
5353 };
5354
5355 /* l4_per -> mcspi3 */
5356 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5357         .master         = &omap44xx_l4_per_hwmod,
5358         .slave          = &omap44xx_mcspi3_hwmod,
5359         .clk            = "l4_div_ck",
5360         .addr           = omap44xx_mcspi3_addrs,
5361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5362 };
5363
5364 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5365         {
5366                 .pa_start       = 0x480ba000,
5367                 .pa_end         = 0x480ba1ff,
5368                 .flags          = ADDR_TYPE_RT
5369         },
5370         { }
5371 };
5372
5373 /* l4_per -> mcspi4 */
5374 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5375         .master         = &omap44xx_l4_per_hwmod,
5376         .slave          = &omap44xx_mcspi4_hwmod,
5377         .clk            = "l4_div_ck",
5378         .addr           = omap44xx_mcspi4_addrs,
5379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5380 };
5381
5382 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5383         {
5384                 .pa_start       = 0x4809c000,
5385                 .pa_end         = 0x4809c3ff,
5386                 .flags          = ADDR_TYPE_RT
5387         },
5388         { }
5389 };
5390
5391 /* l4_per -> mmc1 */
5392 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5393         .master         = &omap44xx_l4_per_hwmod,
5394         .slave          = &omap44xx_mmc1_hwmod,
5395         .clk            = "l4_div_ck",
5396         .addr           = omap44xx_mmc1_addrs,
5397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5398 };
5399
5400 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5401         {
5402                 .pa_start       = 0x480b4000,
5403                 .pa_end         = 0x480b43ff,
5404                 .flags          = ADDR_TYPE_RT
5405         },
5406         { }
5407 };
5408
5409 /* l4_per -> mmc2 */
5410 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5411         .master         = &omap44xx_l4_per_hwmod,
5412         .slave          = &omap44xx_mmc2_hwmod,
5413         .clk            = "l4_div_ck",
5414         .addr           = omap44xx_mmc2_addrs,
5415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5416 };
5417
5418 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5419         {
5420                 .pa_start       = 0x480ad000,
5421                 .pa_end         = 0x480ad3ff,
5422                 .flags          = ADDR_TYPE_RT
5423         },
5424         { }
5425 };
5426
5427 /* l4_per -> mmc3 */
5428 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5429         .master         = &omap44xx_l4_per_hwmod,
5430         .slave          = &omap44xx_mmc3_hwmod,
5431         .clk            = "l4_div_ck",
5432         .addr           = omap44xx_mmc3_addrs,
5433         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5434 };
5435
5436 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5437         {
5438                 .pa_start       = 0x480d1000,
5439                 .pa_end         = 0x480d13ff,
5440                 .flags          = ADDR_TYPE_RT
5441         },
5442         { }
5443 };
5444
5445 /* l4_per -> mmc4 */
5446 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5447         .master         = &omap44xx_l4_per_hwmod,
5448         .slave          = &omap44xx_mmc4_hwmod,
5449         .clk            = "l4_div_ck",
5450         .addr           = omap44xx_mmc4_addrs,
5451         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5452 };
5453
5454 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5455         {
5456                 .pa_start       = 0x480d5000,
5457                 .pa_end         = 0x480d53ff,
5458                 .flags          = ADDR_TYPE_RT
5459         },
5460         { }
5461 };
5462
5463 /* l4_per -> mmc5 */
5464 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5465         .master         = &omap44xx_l4_per_hwmod,
5466         .slave          = &omap44xx_mmc5_hwmod,
5467         .clk            = "l4_div_ck",
5468         .addr           = omap44xx_mmc5_addrs,
5469         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5470 };
5471
5472 /* l3_main_2 -> ocmc_ram */
5473 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5474         .master         = &omap44xx_l3_main_2_hwmod,
5475         .slave          = &omap44xx_ocmc_ram_hwmod,
5476         .clk            = "l3_div_ck",
5477         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5478 };
5479
5480 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5481         {
5482                 .pa_start       = 0x4a0ad000,
5483                 .pa_end         = 0x4a0ad01f,
5484                 .flags          = ADDR_TYPE_RT
5485         },
5486         { }
5487 };
5488
5489 /* l4_cfg -> ocp2scp_usb_phy */
5490 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5491         .master         = &omap44xx_l4_cfg_hwmod,
5492         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5493         .clk            = "l4_div_ck",
5494         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5496 };
5497
5498 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5499         {
5500                 .pa_start       = 0x48243000,
5501                 .pa_end         = 0x48243fff,
5502                 .flags          = ADDR_TYPE_RT
5503         },
5504         { }
5505 };
5506
5507 /* mpu_private -> prcm_mpu */
5508 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5509         .master         = &omap44xx_mpu_private_hwmod,
5510         .slave          = &omap44xx_prcm_mpu_hwmod,
5511         .clk            = "l3_div_ck",
5512         .addr           = omap44xx_prcm_mpu_addrs,
5513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5514 };
5515
5516 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5517         {
5518                 .pa_start       = 0x4a004000,
5519                 .pa_end         = 0x4a004fff,
5520                 .flags          = ADDR_TYPE_RT
5521         },
5522         { }
5523 };
5524
5525 /* l4_wkup -> cm_core_aon */
5526 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5527         .master         = &omap44xx_l4_wkup_hwmod,
5528         .slave          = &omap44xx_cm_core_aon_hwmod,
5529         .clk            = "l4_wkup_clk_mux_ck",
5530         .addr           = omap44xx_cm_core_aon_addrs,
5531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5532 };
5533
5534 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5535         {
5536                 .pa_start       = 0x4a008000,
5537                 .pa_end         = 0x4a009fff,
5538                 .flags          = ADDR_TYPE_RT
5539         },
5540         { }
5541 };
5542
5543 /* l4_cfg -> cm_core */
5544 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5545         .master         = &omap44xx_l4_cfg_hwmod,
5546         .slave          = &omap44xx_cm_core_hwmod,
5547         .clk            = "l4_div_ck",
5548         .addr           = omap44xx_cm_core_addrs,
5549         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5550 };
5551
5552 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5553         {
5554                 .pa_start       = 0x4a306000,
5555                 .pa_end         = 0x4a307fff,
5556                 .flags          = ADDR_TYPE_RT
5557         },
5558         { }
5559 };
5560
5561 /* l4_wkup -> prm */
5562 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5563         .master         = &omap44xx_l4_wkup_hwmod,
5564         .slave          = &omap44xx_prm_hwmod,
5565         .clk            = "l4_wkup_clk_mux_ck",
5566         .addr           = omap44xx_prm_addrs,
5567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5568 };
5569
5570 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5571         {
5572                 .pa_start       = 0x4a30a000,
5573                 .pa_end         = 0x4a30a7ff,
5574                 .flags          = ADDR_TYPE_RT
5575         },
5576         { }
5577 };
5578
5579 /* l4_wkup -> scrm */
5580 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5581         .master         = &omap44xx_l4_wkup_hwmod,
5582         .slave          = &omap44xx_scrm_hwmod,
5583         .clk            = "l4_wkup_clk_mux_ck",
5584         .addr           = omap44xx_scrm_addrs,
5585         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5586 };
5587
5588 /* l3_main_2 -> sl2if */
5589 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5590         .master         = &omap44xx_l3_main_2_hwmod,
5591         .slave          = &omap44xx_sl2if_hwmod,
5592         .clk            = "l3_div_ck",
5593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5594 };
5595
5596 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5597         {
5598                 .pa_start       = 0x4012c000,
5599                 .pa_end         = 0x4012c3ff,
5600                 .flags          = ADDR_TYPE_RT
5601         },
5602         { }
5603 };
5604
5605 /* l4_abe -> slimbus1 */
5606 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5607         .master         = &omap44xx_l4_abe_hwmod,
5608         .slave          = &omap44xx_slimbus1_hwmod,
5609         .clk            = "ocp_abe_iclk",
5610         .addr           = omap44xx_slimbus1_addrs,
5611         .user           = OCP_USER_MPU,
5612 };
5613
5614 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5615         {
5616                 .pa_start       = 0x4902c000,
5617                 .pa_end         = 0x4902c3ff,
5618                 .flags          = ADDR_TYPE_RT
5619         },
5620         { }
5621 };
5622
5623 /* l4_abe -> slimbus1 (dma) */
5624 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5625         .master         = &omap44xx_l4_abe_hwmod,
5626         .slave          = &omap44xx_slimbus1_hwmod,
5627         .clk            = "ocp_abe_iclk",
5628         .addr           = omap44xx_slimbus1_dma_addrs,
5629         .user           = OCP_USER_SDMA,
5630 };
5631
5632 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5633         {
5634                 .pa_start       = 0x48076000,
5635                 .pa_end         = 0x480763ff,
5636                 .flags          = ADDR_TYPE_RT
5637         },
5638         { }
5639 };
5640
5641 /* l4_per -> slimbus2 */
5642 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5643         .master         = &omap44xx_l4_per_hwmod,
5644         .slave          = &omap44xx_slimbus2_hwmod,
5645         .clk            = "l4_div_ck",
5646         .addr           = omap44xx_slimbus2_addrs,
5647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5648 };
5649
5650 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5651         {
5652                 .pa_start       = 0x4a0dd000,
5653                 .pa_end         = 0x4a0dd03f,
5654                 .flags          = ADDR_TYPE_RT
5655         },
5656         { }
5657 };
5658
5659 /* l4_cfg -> smartreflex_core */
5660 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5661         .master         = &omap44xx_l4_cfg_hwmod,
5662         .slave          = &omap44xx_smartreflex_core_hwmod,
5663         .clk            = "l4_div_ck",
5664         .addr           = omap44xx_smartreflex_core_addrs,
5665         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5666 };
5667
5668 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5669         {
5670                 .pa_start       = 0x4a0db000,
5671                 .pa_end         = 0x4a0db03f,
5672                 .flags          = ADDR_TYPE_RT
5673         },
5674         { }
5675 };
5676
5677 /* l4_cfg -> smartreflex_iva */
5678 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5679         .master         = &omap44xx_l4_cfg_hwmod,
5680         .slave          = &omap44xx_smartreflex_iva_hwmod,
5681         .clk            = "l4_div_ck",
5682         .addr           = omap44xx_smartreflex_iva_addrs,
5683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5684 };
5685
5686 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5687         {
5688                 .pa_start       = 0x4a0d9000,
5689                 .pa_end         = 0x4a0d903f,
5690                 .flags          = ADDR_TYPE_RT
5691         },
5692         { }
5693 };
5694
5695 /* l4_cfg -> smartreflex_mpu */
5696 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5697         .master         = &omap44xx_l4_cfg_hwmod,
5698         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5699         .clk            = "l4_div_ck",
5700         .addr           = omap44xx_smartreflex_mpu_addrs,
5701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5702 };
5703
5704 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5705         {
5706                 .pa_start       = 0x4a0f6000,
5707                 .pa_end         = 0x4a0f6fff,
5708                 .flags          = ADDR_TYPE_RT
5709         },
5710         { }
5711 };
5712
5713 /* l4_cfg -> spinlock */
5714 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5715         .master         = &omap44xx_l4_cfg_hwmod,
5716         .slave          = &omap44xx_spinlock_hwmod,
5717         .clk            = "l4_div_ck",
5718         .addr           = omap44xx_spinlock_addrs,
5719         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5720 };
5721
5722 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5723         {
5724                 .pa_start       = 0x4a318000,
5725                 .pa_end         = 0x4a31807f,
5726                 .flags          = ADDR_TYPE_RT
5727         },
5728         { }
5729 };
5730
5731 /* l4_wkup -> timer1 */
5732 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5733         .master         = &omap44xx_l4_wkup_hwmod,
5734         .slave          = &omap44xx_timer1_hwmod,
5735         .clk            = "l4_wkup_clk_mux_ck",
5736         .addr           = omap44xx_timer1_addrs,
5737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5738 };
5739
5740 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5741         {
5742                 .pa_start       = 0x48032000,
5743                 .pa_end         = 0x4803207f,
5744                 .flags          = ADDR_TYPE_RT
5745         },
5746         { }
5747 };
5748
5749 /* l4_per -> timer2 */
5750 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5751         .master         = &omap44xx_l4_per_hwmod,
5752         .slave          = &omap44xx_timer2_hwmod,
5753         .clk            = "l4_div_ck",
5754         .addr           = omap44xx_timer2_addrs,
5755         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5756 };
5757
5758 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5759         {
5760                 .pa_start       = 0x48034000,
5761                 .pa_end         = 0x4803407f,
5762                 .flags          = ADDR_TYPE_RT
5763         },
5764         { }
5765 };
5766
5767 /* l4_per -> timer3 */
5768 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5769         .master         = &omap44xx_l4_per_hwmod,
5770         .slave          = &omap44xx_timer3_hwmod,
5771         .clk            = "l4_div_ck",
5772         .addr           = omap44xx_timer3_addrs,
5773         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5774 };
5775
5776 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5777         {
5778                 .pa_start       = 0x48036000,
5779                 .pa_end         = 0x4803607f,
5780                 .flags          = ADDR_TYPE_RT
5781         },
5782         { }
5783 };
5784
5785 /* l4_per -> timer4 */
5786 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5787         .master         = &omap44xx_l4_per_hwmod,
5788         .slave          = &omap44xx_timer4_hwmod,
5789         .clk            = "l4_div_ck",
5790         .addr           = omap44xx_timer4_addrs,
5791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5792 };
5793
5794 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5795         {
5796                 .pa_start       = 0x40138000,
5797                 .pa_end         = 0x4013807f,
5798                 .flags          = ADDR_TYPE_RT
5799         },
5800         { }
5801 };
5802
5803 /* l4_abe -> timer5 */
5804 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5805         .master         = &omap44xx_l4_abe_hwmod,
5806         .slave          = &omap44xx_timer5_hwmod,
5807         .clk            = "ocp_abe_iclk",
5808         .addr           = omap44xx_timer5_addrs,
5809         .user           = OCP_USER_MPU,
5810 };
5811
5812 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5813         {
5814                 .pa_start       = 0x49038000,
5815                 .pa_end         = 0x4903807f,
5816                 .flags          = ADDR_TYPE_RT
5817         },
5818         { }
5819 };
5820
5821 /* l4_abe -> timer5 (dma) */
5822 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5823         .master         = &omap44xx_l4_abe_hwmod,
5824         .slave          = &omap44xx_timer5_hwmod,
5825         .clk            = "ocp_abe_iclk",
5826         .addr           = omap44xx_timer5_dma_addrs,
5827         .user           = OCP_USER_SDMA,
5828 };
5829
5830 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5831         {
5832                 .pa_start       = 0x4013a000,
5833                 .pa_end         = 0x4013a07f,
5834                 .flags          = ADDR_TYPE_RT
5835         },
5836         { }
5837 };
5838
5839 /* l4_abe -> timer6 */
5840 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5841         .master         = &omap44xx_l4_abe_hwmod,
5842         .slave          = &omap44xx_timer6_hwmod,
5843         .clk            = "ocp_abe_iclk",
5844         .addr           = omap44xx_timer6_addrs,
5845         .user           = OCP_USER_MPU,
5846 };
5847
5848 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5849         {
5850                 .pa_start       = 0x4903a000,
5851                 .pa_end         = 0x4903a07f,
5852                 .flags          = ADDR_TYPE_RT
5853         },
5854         { }
5855 };
5856
5857 /* l4_abe -> timer6 (dma) */
5858 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5859         .master         = &omap44xx_l4_abe_hwmod,
5860         .slave          = &omap44xx_timer6_hwmod,
5861         .clk            = "ocp_abe_iclk",
5862         .addr           = omap44xx_timer6_dma_addrs,
5863         .user           = OCP_USER_SDMA,
5864 };
5865
5866 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5867         {
5868                 .pa_start       = 0x4013c000,
5869                 .pa_end         = 0x4013c07f,
5870                 .flags          = ADDR_TYPE_RT
5871         },
5872         { }
5873 };
5874
5875 /* l4_abe -> timer7 */
5876 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5877         .master         = &omap44xx_l4_abe_hwmod,
5878         .slave          = &omap44xx_timer7_hwmod,
5879         .clk            = "ocp_abe_iclk",
5880         .addr           = omap44xx_timer7_addrs,
5881         .user           = OCP_USER_MPU,
5882 };
5883
5884 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5885         {
5886                 .pa_start       = 0x4903c000,
5887                 .pa_end         = 0x4903c07f,
5888                 .flags          = ADDR_TYPE_RT
5889         },
5890         { }
5891 };
5892
5893 /* l4_abe -> timer7 (dma) */
5894 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5895         .master         = &omap44xx_l4_abe_hwmod,
5896         .slave          = &omap44xx_timer7_hwmod,
5897         .clk            = "ocp_abe_iclk",
5898         .addr           = omap44xx_timer7_dma_addrs,
5899         .user           = OCP_USER_SDMA,
5900 };
5901
5902 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5903         {
5904                 .pa_start       = 0x4013e000,
5905                 .pa_end         = 0x4013e07f,
5906                 .flags          = ADDR_TYPE_RT
5907         },
5908         { }
5909 };
5910
5911 /* l4_abe -> timer8 */
5912 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5913         .master         = &omap44xx_l4_abe_hwmod,
5914         .slave          = &omap44xx_timer8_hwmod,
5915         .clk            = "ocp_abe_iclk",
5916         .addr           = omap44xx_timer8_addrs,
5917         .user           = OCP_USER_MPU,
5918 };
5919
5920 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5921         {
5922                 .pa_start       = 0x4903e000,
5923                 .pa_end         = 0x4903e07f,
5924                 .flags          = ADDR_TYPE_RT
5925         },
5926         { }
5927 };
5928
5929 /* l4_abe -> timer8 (dma) */
5930 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5931         .master         = &omap44xx_l4_abe_hwmod,
5932         .slave          = &omap44xx_timer8_hwmod,
5933         .clk            = "ocp_abe_iclk",
5934         .addr           = omap44xx_timer8_dma_addrs,
5935         .user           = OCP_USER_SDMA,
5936 };
5937
5938 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5939         {
5940                 .pa_start       = 0x4803e000,
5941                 .pa_end         = 0x4803e07f,
5942                 .flags          = ADDR_TYPE_RT
5943         },
5944         { }
5945 };
5946
5947 /* l4_per -> timer9 */
5948 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5949         .master         = &omap44xx_l4_per_hwmod,
5950         .slave          = &omap44xx_timer9_hwmod,
5951         .clk            = "l4_div_ck",
5952         .addr           = omap44xx_timer9_addrs,
5953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5954 };
5955
5956 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5957         {
5958                 .pa_start       = 0x48086000,
5959                 .pa_end         = 0x4808607f,
5960                 .flags          = ADDR_TYPE_RT
5961         },
5962         { }
5963 };
5964
5965 /* l4_per -> timer10 */
5966 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5967         .master         = &omap44xx_l4_per_hwmod,
5968         .slave          = &omap44xx_timer10_hwmod,
5969         .clk            = "l4_div_ck",
5970         .addr           = omap44xx_timer10_addrs,
5971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5972 };
5973
5974 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5975         {
5976                 .pa_start       = 0x48088000,
5977                 .pa_end         = 0x4808807f,
5978                 .flags          = ADDR_TYPE_RT
5979         },
5980         { }
5981 };
5982
5983 /* l4_per -> timer11 */
5984 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5985         .master         = &omap44xx_l4_per_hwmod,
5986         .slave          = &omap44xx_timer11_hwmod,
5987         .clk            = "l4_div_ck",
5988         .addr           = omap44xx_timer11_addrs,
5989         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5990 };
5991
5992 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5993         {
5994                 .pa_start       = 0x4806a000,
5995                 .pa_end         = 0x4806a0ff,
5996                 .flags          = ADDR_TYPE_RT
5997         },
5998         { }
5999 };
6000
6001 /* l4_per -> uart1 */
6002 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6003         .master         = &omap44xx_l4_per_hwmod,
6004         .slave          = &omap44xx_uart1_hwmod,
6005         .clk            = "l4_div_ck",
6006         .addr           = omap44xx_uart1_addrs,
6007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6008 };
6009
6010 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6011         {
6012                 .pa_start       = 0x4806c000,
6013                 .pa_end         = 0x4806c0ff,
6014                 .flags          = ADDR_TYPE_RT
6015         },
6016         { }
6017 };
6018
6019 /* l4_per -> uart2 */
6020 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6021         .master         = &omap44xx_l4_per_hwmod,
6022         .slave          = &omap44xx_uart2_hwmod,
6023         .clk            = "l4_div_ck",
6024         .addr           = omap44xx_uart2_addrs,
6025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6026 };
6027
6028 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6029         {
6030                 .pa_start       = 0x48020000,
6031                 .pa_end         = 0x480200ff,
6032                 .flags          = ADDR_TYPE_RT
6033         },
6034         { }
6035 };
6036
6037 /* l4_per -> uart3 */
6038 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6039         .master         = &omap44xx_l4_per_hwmod,
6040         .slave          = &omap44xx_uart3_hwmod,
6041         .clk            = "l4_div_ck",
6042         .addr           = omap44xx_uart3_addrs,
6043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6044 };
6045
6046 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6047         {
6048                 .pa_start       = 0x4806e000,
6049                 .pa_end         = 0x4806e0ff,
6050                 .flags          = ADDR_TYPE_RT
6051         },
6052         { }
6053 };
6054
6055 /* l4_per -> uart4 */
6056 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6057         .master         = &omap44xx_l4_per_hwmod,
6058         .slave          = &omap44xx_uart4_hwmod,
6059         .clk            = "l4_div_ck",
6060         .addr           = omap44xx_uart4_addrs,
6061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6062 };
6063
6064 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6065         {
6066                 .pa_start       = 0x4a0a9000,
6067                 .pa_end         = 0x4a0a93ff,
6068                 .flags          = ADDR_TYPE_RT
6069         },
6070         { }
6071 };
6072
6073 /* l4_cfg -> usb_host_fs */
6074 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6075         .master         = &omap44xx_l4_cfg_hwmod,
6076         .slave          = &omap44xx_usb_host_fs_hwmod,
6077         .clk            = "l4_div_ck",
6078         .addr           = omap44xx_usb_host_fs_addrs,
6079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6080 };
6081
6082 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6083         {
6084                 .name           = "uhh",
6085                 .pa_start       = 0x4a064000,
6086                 .pa_end         = 0x4a0647ff,
6087                 .flags          = ADDR_TYPE_RT
6088         },
6089         {
6090                 .name           = "ohci",
6091                 .pa_start       = 0x4a064800,
6092                 .pa_end         = 0x4a064bff,
6093         },
6094         {
6095                 .name           = "ehci",
6096                 .pa_start       = 0x4a064c00,
6097                 .pa_end         = 0x4a064fff,
6098         },
6099         {}
6100 };
6101
6102 /* l4_cfg -> usb_host_hs */
6103 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6104         .master         = &omap44xx_l4_cfg_hwmod,
6105         .slave          = &omap44xx_usb_host_hs_hwmod,
6106         .clk            = "l4_div_ck",
6107         .addr           = omap44xx_usb_host_hs_addrs,
6108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6109 };
6110
6111 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6112         {
6113                 .pa_start       = 0x4a0ab000,
6114                 .pa_end         = 0x4a0ab7ff,
6115                 .flags          = ADDR_TYPE_RT
6116         },
6117         {
6118                 /* XXX: Remove this once control module driver is in place */
6119                 .pa_start       = 0x4a00233c,
6120                 .pa_end         = 0x4a00233f,
6121                 .flags          = ADDR_TYPE_RT
6122         },
6123         { }
6124 };
6125
6126 /* l4_cfg -> usb_otg_hs */
6127 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6128         .master         = &omap44xx_l4_cfg_hwmod,
6129         .slave          = &omap44xx_usb_otg_hs_hwmod,
6130         .clk            = "l4_div_ck",
6131         .addr           = omap44xx_usb_otg_hs_addrs,
6132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6133 };
6134
6135 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6136         {
6137                 .name           = "tll",
6138                 .pa_start       = 0x4a062000,
6139                 .pa_end         = 0x4a063fff,
6140                 .flags          = ADDR_TYPE_RT
6141         },
6142         {}
6143 };
6144
6145 /* l4_cfg -> usb_tll_hs */
6146 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6147         .master         = &omap44xx_l4_cfg_hwmod,
6148         .slave          = &omap44xx_usb_tll_hs_hwmod,
6149         .clk            = "l4_div_ck",
6150         .addr           = omap44xx_usb_tll_hs_addrs,
6151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6152 };
6153
6154 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6155         {
6156                 .pa_start       = 0x4a314000,
6157                 .pa_end         = 0x4a31407f,
6158                 .flags          = ADDR_TYPE_RT
6159         },
6160         { }
6161 };
6162
6163 /* l4_wkup -> wd_timer2 */
6164 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6165         .master         = &omap44xx_l4_wkup_hwmod,
6166         .slave          = &omap44xx_wd_timer2_hwmod,
6167         .clk            = "l4_wkup_clk_mux_ck",
6168         .addr           = omap44xx_wd_timer2_addrs,
6169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6170 };
6171
6172 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6173         {
6174                 .pa_start       = 0x40130000,
6175                 .pa_end         = 0x4013007f,
6176                 .flags          = ADDR_TYPE_RT
6177         },
6178         { }
6179 };
6180
6181 /* l4_abe -> wd_timer3 */
6182 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6183         .master         = &omap44xx_l4_abe_hwmod,
6184         .slave          = &omap44xx_wd_timer3_hwmod,
6185         .clk            = "ocp_abe_iclk",
6186         .addr           = omap44xx_wd_timer3_addrs,
6187         .user           = OCP_USER_MPU,
6188 };
6189
6190 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6191         {
6192                 .pa_start       = 0x49030000,
6193                 .pa_end         = 0x4903007f,
6194                 .flags          = ADDR_TYPE_RT
6195         },
6196         { }
6197 };
6198
6199 /* l4_abe -> wd_timer3 (dma) */
6200 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6201         .master         = &omap44xx_l4_abe_hwmod,
6202         .slave          = &omap44xx_wd_timer3_hwmod,
6203         .clk            = "ocp_abe_iclk",
6204         .addr           = omap44xx_wd_timer3_dma_addrs,
6205         .user           = OCP_USER_SDMA,
6206 };
6207
6208 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6209         &omap44xx_c2c__c2c_target_fw,
6210         &omap44xx_l4_cfg__c2c_target_fw,
6211         &omap44xx_l3_main_1__dmm,
6212         &omap44xx_mpu__dmm,
6213         &omap44xx_c2c__emif_fw,
6214         &omap44xx_dmm__emif_fw,
6215         &omap44xx_l4_cfg__emif_fw,
6216         &omap44xx_iva__l3_instr,
6217         &omap44xx_l3_main_3__l3_instr,
6218         &omap44xx_ocp_wp_noc__l3_instr,
6219         &omap44xx_dsp__l3_main_1,
6220         &omap44xx_dss__l3_main_1,
6221         &omap44xx_l3_main_2__l3_main_1,
6222         &omap44xx_l4_cfg__l3_main_1,
6223         &omap44xx_mmc1__l3_main_1,
6224         &omap44xx_mmc2__l3_main_1,
6225         &omap44xx_mpu__l3_main_1,
6226         &omap44xx_c2c_target_fw__l3_main_2,
6227         &omap44xx_debugss__l3_main_2,
6228         &omap44xx_dma_system__l3_main_2,
6229         &omap44xx_fdif__l3_main_2,
6230         &omap44xx_gpu__l3_main_2,
6231         &omap44xx_hsi__l3_main_2,
6232         &omap44xx_ipu__l3_main_2,
6233         &omap44xx_iss__l3_main_2,
6234         &omap44xx_iva__l3_main_2,
6235         &omap44xx_l3_main_1__l3_main_2,
6236         &omap44xx_l4_cfg__l3_main_2,
6237         /* &omap44xx_usb_host_fs__l3_main_2, */
6238         &omap44xx_usb_host_hs__l3_main_2,
6239         &omap44xx_usb_otg_hs__l3_main_2,
6240         &omap44xx_l3_main_1__l3_main_3,
6241         &omap44xx_l3_main_2__l3_main_3,
6242         &omap44xx_l4_cfg__l3_main_3,
6243         /* &omap44xx_aess__l4_abe, */
6244         &omap44xx_dsp__l4_abe,
6245         &omap44xx_l3_main_1__l4_abe,
6246         &omap44xx_mpu__l4_abe,
6247         &omap44xx_l3_main_1__l4_cfg,
6248         &omap44xx_l3_main_2__l4_per,
6249         &omap44xx_l4_cfg__l4_wkup,
6250         &omap44xx_mpu__mpu_private,
6251         &omap44xx_l4_cfg__ocp_wp_noc,
6252         /* &omap44xx_l4_abe__aess, */
6253         /* &omap44xx_l4_abe__aess_dma, */
6254         &omap44xx_l3_main_2__c2c,
6255         &omap44xx_l4_wkup__counter_32k,
6256         &omap44xx_l4_cfg__ctrl_module_core,
6257         &omap44xx_l4_cfg__ctrl_module_pad_core,
6258         &omap44xx_l4_wkup__ctrl_module_wkup,
6259         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6260         &omap44xx_l3_instr__debugss,
6261         &omap44xx_l4_cfg__dma_system,
6262         &omap44xx_l4_abe__dmic,
6263         &omap44xx_l4_abe__dmic_dma,
6264         &omap44xx_dsp__iva,
6265         /* &omap44xx_dsp__sl2if, */
6266         &omap44xx_l4_cfg__dsp,
6267         &omap44xx_l3_main_2__dss,
6268         &omap44xx_l4_per__dss,
6269         &omap44xx_l3_main_2__dss_dispc,
6270         &omap44xx_l4_per__dss_dispc,
6271         &omap44xx_l3_main_2__dss_dsi1,
6272         &omap44xx_l4_per__dss_dsi1,
6273         &omap44xx_l3_main_2__dss_dsi2,
6274         &omap44xx_l4_per__dss_dsi2,
6275         &omap44xx_l3_main_2__dss_hdmi,
6276         &omap44xx_l4_per__dss_hdmi,
6277         &omap44xx_l3_main_2__dss_rfbi,
6278         &omap44xx_l4_per__dss_rfbi,
6279         &omap44xx_l3_main_2__dss_venc,
6280         &omap44xx_l4_per__dss_venc,
6281         &omap44xx_l4_per__elm,
6282         &omap44xx_emif_fw__emif1,
6283         &omap44xx_emif_fw__emif2,
6284         &omap44xx_l4_cfg__fdif,
6285         &omap44xx_l4_wkup__gpio1,
6286         &omap44xx_l4_per__gpio2,
6287         &omap44xx_l4_per__gpio3,
6288         &omap44xx_l4_per__gpio4,
6289         &omap44xx_l4_per__gpio5,
6290         &omap44xx_l4_per__gpio6,
6291         &omap44xx_l3_main_2__gpmc,
6292         &omap44xx_l3_main_2__gpu,
6293         &omap44xx_l4_per__hdq1w,
6294         &omap44xx_l4_cfg__hsi,
6295         &omap44xx_l4_per__i2c1,
6296         &omap44xx_l4_per__i2c2,
6297         &omap44xx_l4_per__i2c3,
6298         &omap44xx_l4_per__i2c4,
6299         &omap44xx_l3_main_2__ipu,
6300         &omap44xx_l3_main_2__iss,
6301         /* &omap44xx_iva__sl2if, */
6302         &omap44xx_l3_main_2__iva,
6303         &omap44xx_l4_wkup__kbd,
6304         &omap44xx_l4_cfg__mailbox,
6305         &omap44xx_l4_abe__mcasp,
6306         &omap44xx_l4_abe__mcasp_dma,
6307         &omap44xx_l4_abe__mcbsp1,
6308         &omap44xx_l4_abe__mcbsp1_dma,
6309         &omap44xx_l4_abe__mcbsp2,
6310         &omap44xx_l4_abe__mcbsp2_dma,
6311         &omap44xx_l4_abe__mcbsp3,
6312         &omap44xx_l4_abe__mcbsp3_dma,
6313         &omap44xx_l4_per__mcbsp4,
6314         &omap44xx_l4_abe__mcpdm,
6315         &omap44xx_l4_abe__mcpdm_dma,
6316         &omap44xx_l4_per__mcspi1,
6317         &omap44xx_l4_per__mcspi2,
6318         &omap44xx_l4_per__mcspi3,
6319         &omap44xx_l4_per__mcspi4,
6320         &omap44xx_l4_per__mmc1,
6321         &omap44xx_l4_per__mmc2,
6322         &omap44xx_l4_per__mmc3,
6323         &omap44xx_l4_per__mmc4,
6324         &omap44xx_l4_per__mmc5,
6325         &omap44xx_l3_main_2__mmu_ipu,
6326         &omap44xx_l4_cfg__mmu_dsp,
6327         &omap44xx_l3_main_2__ocmc_ram,
6328         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6329         &omap44xx_mpu_private__prcm_mpu,
6330         &omap44xx_l4_wkup__cm_core_aon,
6331         &omap44xx_l4_cfg__cm_core,
6332         &omap44xx_l4_wkup__prm,
6333         &omap44xx_l4_wkup__scrm,
6334         /* &omap44xx_l3_main_2__sl2if, */
6335         &omap44xx_l4_abe__slimbus1,
6336         &omap44xx_l4_abe__slimbus1_dma,
6337         &omap44xx_l4_per__slimbus2,
6338         &omap44xx_l4_cfg__smartreflex_core,
6339         &omap44xx_l4_cfg__smartreflex_iva,
6340         &omap44xx_l4_cfg__smartreflex_mpu,
6341         &omap44xx_l4_cfg__spinlock,
6342         &omap44xx_l4_wkup__timer1,
6343         &omap44xx_l4_per__timer2,
6344         &omap44xx_l4_per__timer3,
6345         &omap44xx_l4_per__timer4,
6346         &omap44xx_l4_abe__timer5,
6347         &omap44xx_l4_abe__timer5_dma,
6348         &omap44xx_l4_abe__timer6,
6349         &omap44xx_l4_abe__timer6_dma,
6350         &omap44xx_l4_abe__timer7,
6351         &omap44xx_l4_abe__timer7_dma,
6352         &omap44xx_l4_abe__timer8,
6353         &omap44xx_l4_abe__timer8_dma,
6354         &omap44xx_l4_per__timer9,
6355         &omap44xx_l4_per__timer10,
6356         &omap44xx_l4_per__timer11,
6357         &omap44xx_l4_per__uart1,
6358         &omap44xx_l4_per__uart2,
6359         &omap44xx_l4_per__uart3,
6360         &omap44xx_l4_per__uart4,
6361         /* &omap44xx_l4_cfg__usb_host_fs, */
6362         &omap44xx_l4_cfg__usb_host_hs,
6363         &omap44xx_l4_cfg__usb_otg_hs,
6364         &omap44xx_l4_cfg__usb_tll_hs,
6365         &omap44xx_l4_wkup__wd_timer2,
6366         &omap44xx_l4_abe__wd_timer3,
6367         &omap44xx_l4_abe__wd_timer3_dma,
6368         NULL,
6369 };
6370
6371 int __init omap44xx_hwmod_init(void)
6372 {
6373         omap_hwmod_init();
6374         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6375 }
6376