2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
25 #include <plat/omap_hwmod.h>
28 #include <linux/platform_data/spi-omap2-mcspi.h>
29 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/common.h>
34 #include "omap_hwmod_common_data.h"
38 #include "prm-regbits-44xx.h"
41 /* Base offset for all OMAP4 interrupts external to MPUSS */
42 #define OMAP44XX_IRQ_GIC_START 32
44 /* Base offset for all OMAP4 dma requests */
45 #define OMAP44XX_DMA_REQ_START 1
52 * 'c2c_target_fw' class
53 * instance(s): c2c_target_fw
55 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
56 .name = "c2c_target_fw",
60 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
61 .name = "c2c_target_fw",
62 .class = &omap44xx_c2c_target_fw_hwmod_class,
63 .clkdm_name = "d2d_clkdm",
66 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
67 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
76 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
81 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
82 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
86 static struct omap_hwmod omap44xx_dmm_hwmod = {
88 .class = &omap44xx_dmm_hwmod_class,
89 .clkdm_name = "l3_emif_clkdm",
90 .mpu_irqs = omap44xx_dmm_irqs,
93 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
94 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
101 * instance(s): emif_fw
103 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
108 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
110 .class = &omap44xx_emif_fw_hwmod_class,
111 .clkdm_name = "l3_emif_clkdm",
114 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
115 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
122 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
124 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
129 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
131 .class = &omap44xx_l3_hwmod_class,
132 .clkdm_name = "l3_instr_clkdm",
135 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
136 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
137 .modulemode = MODULEMODE_HWCTRL,
143 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
144 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
145 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
149 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
151 .class = &omap44xx_l3_hwmod_class,
152 .clkdm_name = "l3_1_clkdm",
153 .mpu_irqs = omap44xx_l3_main_1_irqs,
156 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
157 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
163 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
165 .class = &omap44xx_l3_hwmod_class,
166 .clkdm_name = "l3_2_clkdm",
169 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
170 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
176 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
178 .class = &omap44xx_l3_hwmod_class,
179 .clkdm_name = "l3_instr_clkdm",
182 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
183 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
184 .modulemode = MODULEMODE_HWCTRL,
191 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
193 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
198 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
200 .class = &omap44xx_l4_hwmod_class,
201 .clkdm_name = "abe_clkdm",
204 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
210 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
212 .class = &omap44xx_l4_hwmod_class,
213 .clkdm_name = "l4_cfg_clkdm",
216 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
217 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
223 static struct omap_hwmod omap44xx_l4_per_hwmod = {
225 .class = &omap44xx_l4_hwmod_class,
226 .clkdm_name = "l4_per_clkdm",
229 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
230 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
236 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
238 .class = &omap44xx_l4_hwmod_class,
239 .clkdm_name = "l4_wkup_clkdm",
242 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
243 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
250 * instance(s): mpu_private
252 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
257 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
258 .name = "mpu_private",
259 .class = &omap44xx_mpu_bus_hwmod_class,
260 .clkdm_name = "mpuss_clkdm",
265 * instance(s): ocp_wp_noc
267 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
268 .name = "ocp_wp_noc",
272 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
273 .name = "ocp_wp_noc",
274 .class = &omap44xx_ocp_wp_noc_hwmod_class,
275 .clkdm_name = "l3_instr_clkdm",
278 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
279 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
280 .modulemode = MODULEMODE_HWCTRL,
286 * Modules omap_hwmod structures
288 * The following IPs are excluded for the moment because:
289 * - They do not need an explicit SW control using omap_hwmod API.
290 * - They still need to be validated with the driver
291 * properly adapted to omap_hwmod / omap_device
298 * audio engine sub system
301 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
304 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
305 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
306 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
307 MSTANDBY_SMART_WKUP),
308 .sysc_fields = &omap_hwmod_sysc_type2,
311 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
313 .sysc = &omap44xx_aess_sysc,
317 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
318 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
322 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
323 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
324 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
325 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
326 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
327 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
328 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
329 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
330 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
334 static struct omap_hwmod omap44xx_aess_hwmod = {
336 .class = &omap44xx_aess_hwmod_class,
337 .clkdm_name = "abe_clkdm",
338 .mpu_irqs = omap44xx_aess_irqs,
339 .sdma_reqs = omap44xx_aess_sdma_reqs,
340 .main_clk = "aess_fck",
343 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
344 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_SWCTRL,
352 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
356 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
361 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
362 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
366 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
367 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
371 static struct omap_hwmod omap44xx_c2c_hwmod = {
373 .class = &omap44xx_c2c_hwmod_class,
374 .clkdm_name = "d2d_clkdm",
375 .mpu_irqs = omap44xx_c2c_irqs,
376 .sdma_reqs = omap44xx_c2c_sdma_reqs,
379 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
380 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
387 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
390 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
393 .sysc_flags = SYSC_HAS_SIDLEMODE,
394 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
395 .sysc_fields = &omap_hwmod_sysc_type1,
398 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
400 .sysc = &omap44xx_counter_sysc,
404 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
405 .name = "counter_32k",
406 .class = &omap44xx_counter_hwmod_class,
407 .clkdm_name = "l4_wkup_clkdm",
408 .flags = HWMOD_SWSUP_SIDLE,
409 .main_clk = "sys_32k_ck",
412 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
413 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
419 * 'ctrl_module' class
420 * attila core control module + core pad control module + wkup pad control
421 * module + attila wkup control module
424 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
427 .sysc_flags = SYSC_HAS_SIDLEMODE,
428 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
430 .sysc_fields = &omap_hwmod_sysc_type2,
433 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
434 .name = "ctrl_module",
435 .sysc = &omap44xx_ctrl_module_sysc,
438 /* ctrl_module_core */
439 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
440 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
444 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
445 .name = "ctrl_module_core",
446 .class = &omap44xx_ctrl_module_hwmod_class,
447 .clkdm_name = "l4_cfg_clkdm",
448 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
451 /* ctrl_module_pad_core */
452 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
453 .name = "ctrl_module_pad_core",
454 .class = &omap44xx_ctrl_module_hwmod_class,
455 .clkdm_name = "l4_cfg_clkdm",
458 /* ctrl_module_wkup */
459 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
460 .name = "ctrl_module_wkup",
461 .class = &omap44xx_ctrl_module_hwmod_class,
462 .clkdm_name = "l4_wkup_clkdm",
465 /* ctrl_module_pad_wkup */
466 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
467 .name = "ctrl_module_pad_wkup",
468 .class = &omap44xx_ctrl_module_hwmod_class,
469 .clkdm_name = "l4_wkup_clkdm",
474 * debug and emulation sub system
477 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
482 static struct omap_hwmod omap44xx_debugss_hwmod = {
484 .class = &omap44xx_debugss_hwmod_class,
485 .clkdm_name = "emu_sys_clkdm",
486 .main_clk = "trace_clk_div_ck",
489 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
490 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
497 * dma controller for data exchange between memory to memory (i.e. internal or
498 * external memory) and gp peripherals to memory or memory to gp peripherals
501 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
505 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
506 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
507 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
508 SYSS_HAS_RESET_STATUS),
509 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
510 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
511 .sysc_fields = &omap_hwmod_sysc_type1,
514 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
516 .sysc = &omap44xx_dma_sysc,
520 static struct omap_dma_dev_attr dma_dev_attr = {
521 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
522 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
527 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
528 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
529 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
530 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
531 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
535 static struct omap_hwmod omap44xx_dma_system_hwmod = {
536 .name = "dma_system",
537 .class = &omap44xx_dma_hwmod_class,
538 .clkdm_name = "l3_dma_clkdm",
539 .mpu_irqs = omap44xx_dma_system_irqs,
540 .main_clk = "l3_div_ck",
543 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
544 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
547 .dev_attr = &dma_dev_attr,
552 * digital microphone controller
555 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
558 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
559 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
560 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
562 .sysc_fields = &omap_hwmod_sysc_type2,
565 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
567 .sysc = &omap44xx_dmic_sysc,
571 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
572 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
576 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
577 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
581 static struct omap_hwmod omap44xx_dmic_hwmod = {
583 .class = &omap44xx_dmic_hwmod_class,
584 .clkdm_name = "abe_clkdm",
585 .mpu_irqs = omap44xx_dmic_irqs,
586 .sdma_reqs = omap44xx_dmic_sdma_reqs,
587 .main_clk = "dmic_fck",
590 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
592 .modulemode = MODULEMODE_SWCTRL,
602 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
607 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
608 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
612 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
613 { .name = "dsp", .rst_shift = 0 },
614 { .name = "mmu_cache", .rst_shift = 1 },
617 static struct omap_hwmod omap44xx_dsp_hwmod = {
619 .class = &omap44xx_dsp_hwmod_class,
620 .clkdm_name = "tesla_clkdm",
621 .mpu_irqs = omap44xx_dsp_irqs,
622 .rst_lines = omap44xx_dsp_resets,
623 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
624 .main_clk = "dsp_fck",
627 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
628 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
629 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
640 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
643 .sysc_flags = SYSS_HAS_RESET_STATUS,
646 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
648 .sysc = &omap44xx_dss_sysc,
649 .reset = omap_dss_reset,
653 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
654 { .role = "sys_clk", .clk = "dss_sys_clk" },
655 { .role = "tv_clk", .clk = "dss_tv_clk" },
656 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
659 static struct omap_hwmod omap44xx_dss_hwmod = {
661 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
662 .class = &omap44xx_dss_hwmod_class,
663 .clkdm_name = "l3_dss_clkdm",
664 .main_clk = "dss_dss_clk",
667 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
668 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
671 .opt_clks = dss_opt_clks,
672 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
680 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
684 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
685 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
686 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
687 SYSS_HAS_RESET_STATUS),
688 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
689 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
690 .sysc_fields = &omap_hwmod_sysc_type1,
693 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
695 .sysc = &omap44xx_dispc_sysc,
699 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
700 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
704 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
705 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
709 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
711 .has_framedonetv_irq = 1
714 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
716 .class = &omap44xx_dispc_hwmod_class,
717 .clkdm_name = "l3_dss_clkdm",
718 .mpu_irqs = omap44xx_dss_dispc_irqs,
719 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
720 .main_clk = "dss_dss_clk",
723 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
724 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
727 .dev_attr = &omap44xx_dss_dispc_dev_attr
732 * display serial interface controller
735 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
739 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
740 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
741 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
742 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
743 .sysc_fields = &omap_hwmod_sysc_type1,
746 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
748 .sysc = &omap44xx_dsi_sysc,
752 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
753 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
757 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
758 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
762 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
763 { .role = "sys_clk", .clk = "dss_sys_clk" },
766 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
768 .class = &omap44xx_dsi_hwmod_class,
769 .clkdm_name = "l3_dss_clkdm",
770 .mpu_irqs = omap44xx_dss_dsi1_irqs,
771 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
772 .main_clk = "dss_dss_clk",
775 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
776 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
779 .opt_clks = dss_dsi1_opt_clks,
780 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
784 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
785 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
789 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
790 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
794 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
795 { .role = "sys_clk", .clk = "dss_sys_clk" },
798 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
800 .class = &omap44xx_dsi_hwmod_class,
801 .clkdm_name = "l3_dss_clkdm",
802 .mpu_irqs = omap44xx_dss_dsi2_irqs,
803 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
804 .main_clk = "dss_dss_clk",
807 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
808 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
811 .opt_clks = dss_dsi2_opt_clks,
812 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
820 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
823 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
825 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
827 .sysc_fields = &omap_hwmod_sysc_type2,
830 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
832 .sysc = &omap44xx_hdmi_sysc,
836 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
837 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
841 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
842 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
846 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
847 { .role = "sys_clk", .clk = "dss_sys_clk" },
850 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
852 .class = &omap44xx_hdmi_hwmod_class,
853 .clkdm_name = "l3_dss_clkdm",
855 * HDMI audio requires to use no-idle mode. Hence,
856 * set idle mode by software.
858 .flags = HWMOD_SWSUP_SIDLE,
859 .mpu_irqs = omap44xx_dss_hdmi_irqs,
860 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
861 .main_clk = "dss_48mhz_clk",
864 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
865 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
868 .opt_clks = dss_hdmi_opt_clks,
869 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
874 * remote frame buffer interface
877 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
881 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
882 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
883 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
884 .sysc_fields = &omap_hwmod_sysc_type1,
887 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
889 .sysc = &omap44xx_rfbi_sysc,
893 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
894 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
898 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
899 { .role = "ick", .clk = "dss_fck" },
902 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
904 .class = &omap44xx_rfbi_hwmod_class,
905 .clkdm_name = "l3_dss_clkdm",
906 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
907 .main_clk = "dss_dss_clk",
910 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
911 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
914 .opt_clks = dss_rfbi_opt_clks,
915 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
923 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
928 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
930 .class = &omap44xx_venc_hwmod_class,
931 .clkdm_name = "l3_dss_clkdm",
932 .main_clk = "dss_tv_clk",
935 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
936 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
943 * bch error location module
946 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
950 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
951 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
952 SYSS_HAS_RESET_STATUS),
953 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
954 .sysc_fields = &omap_hwmod_sysc_type1,
957 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
959 .sysc = &omap44xx_elm_sysc,
963 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
964 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
968 static struct omap_hwmod omap44xx_elm_hwmod = {
970 .class = &omap44xx_elm_hwmod_class,
971 .clkdm_name = "l4_per_clkdm",
972 .mpu_irqs = omap44xx_elm_irqs,
975 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
976 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
983 * external memory interface no1
986 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
990 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
992 .sysc = &omap44xx_emif_sysc,
996 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
997 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1001 static struct omap_hwmod omap44xx_emif1_hwmod = {
1003 .class = &omap44xx_emif_hwmod_class,
1004 .clkdm_name = "l3_emif_clkdm",
1005 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1006 .mpu_irqs = omap44xx_emif1_irqs,
1007 .main_clk = "ddrphy_ck",
1010 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1011 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1012 .modulemode = MODULEMODE_HWCTRL,
1018 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1019 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1023 static struct omap_hwmod omap44xx_emif2_hwmod = {
1025 .class = &omap44xx_emif_hwmod_class,
1026 .clkdm_name = "l3_emif_clkdm",
1027 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1028 .mpu_irqs = omap44xx_emif2_irqs,
1029 .main_clk = "ddrphy_ck",
1032 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1033 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1034 .modulemode = MODULEMODE_HWCTRL,
1041 * face detection hw accelerator module
1044 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1046 .sysc_offs = 0x0010,
1048 * FDIF needs 100 OCP clk cycles delay after a softreset before
1049 * accessing sysconfig again.
1050 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1051 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1053 * TODO: Indicate errata when available.
1056 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1057 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1058 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1059 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1063 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1065 .sysc = &omap44xx_fdif_sysc,
1069 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1070 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1074 static struct omap_hwmod omap44xx_fdif_hwmod = {
1076 .class = &omap44xx_fdif_hwmod_class,
1077 .clkdm_name = "iss_clkdm",
1078 .mpu_irqs = omap44xx_fdif_irqs,
1079 .main_clk = "fdif_fck",
1082 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1083 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1084 .modulemode = MODULEMODE_SWCTRL,
1091 * general purpose io module
1094 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1096 .sysc_offs = 0x0010,
1097 .syss_offs = 0x0114,
1098 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1099 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1100 SYSS_HAS_RESET_STATUS),
1101 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1103 .sysc_fields = &omap_hwmod_sysc_type1,
1106 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1108 .sysc = &omap44xx_gpio_sysc,
1113 static struct omap_gpio_dev_attr gpio_dev_attr = {
1119 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1120 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1124 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1125 { .role = "dbclk", .clk = "gpio1_dbclk" },
1128 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1130 .class = &omap44xx_gpio_hwmod_class,
1131 .clkdm_name = "l4_wkup_clkdm",
1132 .mpu_irqs = omap44xx_gpio1_irqs,
1133 .main_clk = "gpio1_ick",
1136 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1137 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1138 .modulemode = MODULEMODE_HWCTRL,
1141 .opt_clks = gpio1_opt_clks,
1142 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1143 .dev_attr = &gpio_dev_attr,
1147 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1148 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1152 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1153 { .role = "dbclk", .clk = "gpio2_dbclk" },
1156 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1158 .class = &omap44xx_gpio_hwmod_class,
1159 .clkdm_name = "l4_per_clkdm",
1160 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1161 .mpu_irqs = omap44xx_gpio2_irqs,
1162 .main_clk = "gpio2_ick",
1165 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1166 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1167 .modulemode = MODULEMODE_HWCTRL,
1170 .opt_clks = gpio2_opt_clks,
1171 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1172 .dev_attr = &gpio_dev_attr,
1176 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1177 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1181 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1182 { .role = "dbclk", .clk = "gpio3_dbclk" },
1185 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1187 .class = &omap44xx_gpio_hwmod_class,
1188 .clkdm_name = "l4_per_clkdm",
1189 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190 .mpu_irqs = omap44xx_gpio3_irqs,
1191 .main_clk = "gpio3_ick",
1194 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1195 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1196 .modulemode = MODULEMODE_HWCTRL,
1199 .opt_clks = gpio3_opt_clks,
1200 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1201 .dev_attr = &gpio_dev_attr,
1205 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1206 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1210 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1211 { .role = "dbclk", .clk = "gpio4_dbclk" },
1214 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1216 .class = &omap44xx_gpio_hwmod_class,
1217 .clkdm_name = "l4_per_clkdm",
1218 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1219 .mpu_irqs = omap44xx_gpio4_irqs,
1220 .main_clk = "gpio4_ick",
1223 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1224 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1225 .modulemode = MODULEMODE_HWCTRL,
1228 .opt_clks = gpio4_opt_clks,
1229 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1230 .dev_attr = &gpio_dev_attr,
1234 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1235 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1239 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1240 { .role = "dbclk", .clk = "gpio5_dbclk" },
1243 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1245 .class = &omap44xx_gpio_hwmod_class,
1246 .clkdm_name = "l4_per_clkdm",
1247 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1248 .mpu_irqs = omap44xx_gpio5_irqs,
1249 .main_clk = "gpio5_ick",
1252 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1253 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1254 .modulemode = MODULEMODE_HWCTRL,
1257 .opt_clks = gpio5_opt_clks,
1258 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1259 .dev_attr = &gpio_dev_attr,
1263 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1264 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1268 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1269 { .role = "dbclk", .clk = "gpio6_dbclk" },
1272 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1274 .class = &omap44xx_gpio_hwmod_class,
1275 .clkdm_name = "l4_per_clkdm",
1276 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1277 .mpu_irqs = omap44xx_gpio6_irqs,
1278 .main_clk = "gpio6_ick",
1281 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1282 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1283 .modulemode = MODULEMODE_HWCTRL,
1286 .opt_clks = gpio6_opt_clks,
1287 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1288 .dev_attr = &gpio_dev_attr,
1293 * general purpose memory controller
1296 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1298 .sysc_offs = 0x0010,
1299 .syss_offs = 0x0014,
1300 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1301 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1302 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1303 .sysc_fields = &omap_hwmod_sysc_type1,
1306 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1308 .sysc = &omap44xx_gpmc_sysc,
1312 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1313 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1317 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1318 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1322 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1324 .class = &omap44xx_gpmc_hwmod_class,
1325 .clkdm_name = "l3_2_clkdm",
1326 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1327 .mpu_irqs = omap44xx_gpmc_irqs,
1328 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1331 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1332 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1333 .modulemode = MODULEMODE_HWCTRL,
1340 * 2d/3d graphics accelerator
1343 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1344 .rev_offs = 0x1fc00,
1345 .sysc_offs = 0x1fc10,
1346 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1347 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1348 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1349 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1350 .sysc_fields = &omap_hwmod_sysc_type2,
1353 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1355 .sysc = &omap44xx_gpu_sysc,
1359 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1360 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1364 static struct omap_hwmod omap44xx_gpu_hwmod = {
1366 .class = &omap44xx_gpu_hwmod_class,
1367 .clkdm_name = "l3_gfx_clkdm",
1368 .mpu_irqs = omap44xx_gpu_irqs,
1369 .main_clk = "gpu_fck",
1372 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1373 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1374 .modulemode = MODULEMODE_SWCTRL,
1381 * hdq / 1-wire serial interface controller
1384 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1386 .sysc_offs = 0x0014,
1387 .syss_offs = 0x0018,
1388 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1389 SYSS_HAS_RESET_STATUS),
1390 .sysc_fields = &omap_hwmod_sysc_type1,
1393 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1395 .sysc = &omap44xx_hdq1w_sysc,
1399 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1400 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1404 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1406 .class = &omap44xx_hdq1w_hwmod_class,
1407 .clkdm_name = "l4_per_clkdm",
1408 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1409 .mpu_irqs = omap44xx_hdq1w_irqs,
1410 .main_clk = "hdq1w_fck",
1413 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1414 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1415 .modulemode = MODULEMODE_SWCTRL,
1422 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1426 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1428 .sysc_offs = 0x0010,
1429 .syss_offs = 0x0014,
1430 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1431 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1432 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1433 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1434 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1435 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1436 .sysc_fields = &omap_hwmod_sysc_type1,
1439 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1441 .sysc = &omap44xx_hsi_sysc,
1445 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1446 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1447 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1448 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1452 static struct omap_hwmod omap44xx_hsi_hwmod = {
1454 .class = &omap44xx_hsi_hwmod_class,
1455 .clkdm_name = "l3_init_clkdm",
1456 .mpu_irqs = omap44xx_hsi_irqs,
1457 .main_clk = "hsi_fck",
1460 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1461 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1462 .modulemode = MODULEMODE_HWCTRL,
1469 * multimaster high-speed i2c controller
1472 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1473 .sysc_offs = 0x0010,
1474 .syss_offs = 0x0090,
1475 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1476 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1477 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1478 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1480 .clockact = CLOCKACT_TEST_ICLK,
1481 .sysc_fields = &omap_hwmod_sysc_type1,
1484 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1486 .sysc = &omap44xx_i2c_sysc,
1487 .rev = OMAP_I2C_IP_VERSION_2,
1488 .reset = &omap_i2c_reset,
1491 static struct omap_i2c_dev_attr i2c_dev_attr = {
1492 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1493 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1497 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1498 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1502 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1503 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1504 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1508 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1510 .class = &omap44xx_i2c_hwmod_class,
1511 .clkdm_name = "l4_per_clkdm",
1512 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1513 .mpu_irqs = omap44xx_i2c1_irqs,
1514 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1515 .main_clk = "i2c1_fck",
1518 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1519 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1520 .modulemode = MODULEMODE_SWCTRL,
1523 .dev_attr = &i2c_dev_attr,
1527 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1528 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1532 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1533 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1534 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1538 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1540 .class = &omap44xx_i2c_hwmod_class,
1541 .clkdm_name = "l4_per_clkdm",
1542 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1543 .mpu_irqs = omap44xx_i2c2_irqs,
1544 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1545 .main_clk = "i2c2_fck",
1548 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1549 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1550 .modulemode = MODULEMODE_SWCTRL,
1553 .dev_attr = &i2c_dev_attr,
1557 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1558 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1562 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1563 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1564 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1568 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1570 .class = &omap44xx_i2c_hwmod_class,
1571 .clkdm_name = "l4_per_clkdm",
1572 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1573 .mpu_irqs = omap44xx_i2c3_irqs,
1574 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1575 .main_clk = "i2c3_fck",
1578 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1579 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1580 .modulemode = MODULEMODE_SWCTRL,
1583 .dev_attr = &i2c_dev_attr,
1587 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1588 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1592 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1593 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1594 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1598 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1600 .class = &omap44xx_i2c_hwmod_class,
1601 .clkdm_name = "l4_per_clkdm",
1602 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1603 .mpu_irqs = omap44xx_i2c4_irqs,
1604 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1605 .main_clk = "i2c4_fck",
1608 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1609 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1610 .modulemode = MODULEMODE_SWCTRL,
1613 .dev_attr = &i2c_dev_attr,
1618 * imaging processor unit
1621 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1626 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1627 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1631 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1632 { .name = "cpu0", .rst_shift = 0 },
1633 { .name = "cpu1", .rst_shift = 1 },
1634 { .name = "mmu_cache", .rst_shift = 2 },
1637 static struct omap_hwmod omap44xx_ipu_hwmod = {
1639 .class = &omap44xx_ipu_hwmod_class,
1640 .clkdm_name = "ducati_clkdm",
1641 .mpu_irqs = omap44xx_ipu_irqs,
1642 .rst_lines = omap44xx_ipu_resets,
1643 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1644 .main_clk = "ipu_fck",
1647 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1648 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1649 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1650 .modulemode = MODULEMODE_HWCTRL,
1657 * external images sensor pixel data processor
1660 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1662 .sysc_offs = 0x0010,
1664 * ISS needs 100 OCP clk cycles delay after a softreset before
1665 * accessing sysconfig again.
1666 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1667 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1669 * TODO: Indicate errata when available.
1672 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1673 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1674 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1675 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1676 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1677 .sysc_fields = &omap_hwmod_sysc_type2,
1680 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1682 .sysc = &omap44xx_iss_sysc,
1686 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1687 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1691 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1692 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1693 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1694 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1695 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1699 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1700 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1703 static struct omap_hwmod omap44xx_iss_hwmod = {
1705 .class = &omap44xx_iss_hwmod_class,
1706 .clkdm_name = "iss_clkdm",
1707 .mpu_irqs = omap44xx_iss_irqs,
1708 .sdma_reqs = omap44xx_iss_sdma_reqs,
1709 .main_clk = "iss_fck",
1712 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1713 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1714 .modulemode = MODULEMODE_SWCTRL,
1717 .opt_clks = iss_opt_clks,
1718 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1723 * multi-standard video encoder/decoder hardware accelerator
1726 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1731 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1732 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1733 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1734 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1738 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1739 { .name = "seq0", .rst_shift = 0 },
1740 { .name = "seq1", .rst_shift = 1 },
1741 { .name = "logic", .rst_shift = 2 },
1744 static struct omap_hwmod omap44xx_iva_hwmod = {
1746 .class = &omap44xx_iva_hwmod_class,
1747 .clkdm_name = "ivahd_clkdm",
1748 .mpu_irqs = omap44xx_iva_irqs,
1749 .rst_lines = omap44xx_iva_resets,
1750 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1751 .main_clk = "iva_fck",
1754 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1755 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1756 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1757 .modulemode = MODULEMODE_HWCTRL,
1764 * keyboard controller
1767 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1769 .sysc_offs = 0x0010,
1770 .syss_offs = 0x0014,
1771 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1772 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1773 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1774 SYSS_HAS_RESET_STATUS),
1775 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1776 .sysc_fields = &omap_hwmod_sysc_type1,
1779 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1781 .sysc = &omap44xx_kbd_sysc,
1785 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1786 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1790 static struct omap_hwmod omap44xx_kbd_hwmod = {
1792 .class = &omap44xx_kbd_hwmod_class,
1793 .clkdm_name = "l4_wkup_clkdm",
1794 .mpu_irqs = omap44xx_kbd_irqs,
1795 .main_clk = "kbd_fck",
1798 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1799 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1800 .modulemode = MODULEMODE_SWCTRL,
1807 * mailbox module allowing communication between the on-chip processors using a
1808 * queued mailbox-interrupt mechanism.
1811 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1813 .sysc_offs = 0x0010,
1814 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1815 SYSC_HAS_SOFTRESET),
1816 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1817 .sysc_fields = &omap_hwmod_sysc_type2,
1820 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1822 .sysc = &omap44xx_mailbox_sysc,
1826 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1827 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1831 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1833 .class = &omap44xx_mailbox_hwmod_class,
1834 .clkdm_name = "l4_cfg_clkdm",
1835 .mpu_irqs = omap44xx_mailbox_irqs,
1838 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1839 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1846 * multi-channel audio serial port controller
1849 /* The IP is not compliant to type1 / type2 scheme */
1850 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1854 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1855 .sysc_offs = 0x0004,
1856 .sysc_flags = SYSC_HAS_SIDLEMODE,
1857 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1859 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1862 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1864 .sysc = &omap44xx_mcasp_sysc,
1868 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1869 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1870 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1874 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1875 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1876 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1880 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1882 .class = &omap44xx_mcasp_hwmod_class,
1883 .clkdm_name = "abe_clkdm",
1884 .mpu_irqs = omap44xx_mcasp_irqs,
1885 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1886 .main_clk = "mcasp_fck",
1889 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1890 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1891 .modulemode = MODULEMODE_SWCTRL,
1898 * multi channel buffered serial port controller
1901 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1902 .sysc_offs = 0x008c,
1903 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1904 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1905 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1906 .sysc_fields = &omap_hwmod_sysc_type1,
1909 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1911 .sysc = &omap44xx_mcbsp_sysc,
1912 .rev = MCBSP_CONFIG_TYPE4,
1916 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1917 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1921 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1922 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1923 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1927 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1928 { .role = "pad_fck", .clk = "pad_clks_ck" },
1929 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1932 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1934 .class = &omap44xx_mcbsp_hwmod_class,
1935 .clkdm_name = "abe_clkdm",
1936 .mpu_irqs = omap44xx_mcbsp1_irqs,
1937 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
1938 .main_clk = "mcbsp1_fck",
1941 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1942 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1943 .modulemode = MODULEMODE_SWCTRL,
1946 .opt_clks = mcbsp1_opt_clks,
1947 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1951 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1952 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1956 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1957 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1958 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1962 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1963 { .role = "pad_fck", .clk = "pad_clks_ck" },
1964 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1967 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1969 .class = &omap44xx_mcbsp_hwmod_class,
1970 .clkdm_name = "abe_clkdm",
1971 .mpu_irqs = omap44xx_mcbsp2_irqs,
1972 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
1973 .main_clk = "mcbsp2_fck",
1976 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1977 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1978 .modulemode = MODULEMODE_SWCTRL,
1981 .opt_clks = mcbsp2_opt_clks,
1982 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1986 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1987 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1991 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1992 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1993 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1997 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1998 { .role = "pad_fck", .clk = "pad_clks_ck" },
1999 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2002 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2004 .class = &omap44xx_mcbsp_hwmod_class,
2005 .clkdm_name = "abe_clkdm",
2006 .mpu_irqs = omap44xx_mcbsp3_irqs,
2007 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2008 .main_clk = "mcbsp3_fck",
2011 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2012 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2013 .modulemode = MODULEMODE_SWCTRL,
2016 .opt_clks = mcbsp3_opt_clks,
2017 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
2021 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2022 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2026 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2027 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2028 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2032 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2033 { .role = "pad_fck", .clk = "pad_clks_ck" },
2034 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2037 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2039 .class = &omap44xx_mcbsp_hwmod_class,
2040 .clkdm_name = "l4_per_clkdm",
2041 .mpu_irqs = omap44xx_mcbsp4_irqs,
2042 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2043 .main_clk = "mcbsp4_fck",
2046 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2047 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2048 .modulemode = MODULEMODE_SWCTRL,
2051 .opt_clks = mcbsp4_opt_clks,
2052 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
2057 * multi channel pdm controller (proprietary interface with phoenix power
2061 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2063 .sysc_offs = 0x0010,
2064 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2065 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2066 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2068 .sysc_fields = &omap_hwmod_sysc_type2,
2071 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2073 .sysc = &omap44xx_mcpdm_sysc,
2077 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2078 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2082 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2083 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2084 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2088 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2090 .class = &omap44xx_mcpdm_hwmod_class,
2091 .clkdm_name = "abe_clkdm",
2092 .mpu_irqs = omap44xx_mcpdm_irqs,
2093 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2094 .main_clk = "mcpdm_fck",
2097 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2098 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2099 .modulemode = MODULEMODE_SWCTRL,
2106 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2110 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2112 .sysc_offs = 0x0010,
2113 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2114 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2115 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2117 .sysc_fields = &omap_hwmod_sysc_type2,
2120 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2122 .sysc = &omap44xx_mcspi_sysc,
2123 .rev = OMAP4_MCSPI_REV,
2127 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2128 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2132 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2133 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2134 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2135 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2136 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2137 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2138 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2139 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2140 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2144 /* mcspi1 dev_attr */
2145 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2146 .num_chipselect = 4,
2149 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2151 .class = &omap44xx_mcspi_hwmod_class,
2152 .clkdm_name = "l4_per_clkdm",
2153 .mpu_irqs = omap44xx_mcspi1_irqs,
2154 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2155 .main_clk = "mcspi1_fck",
2158 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2159 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2160 .modulemode = MODULEMODE_SWCTRL,
2163 .dev_attr = &mcspi1_dev_attr,
2167 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2168 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2172 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2173 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2174 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2175 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2176 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2180 /* mcspi2 dev_attr */
2181 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2182 .num_chipselect = 2,
2185 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2187 .class = &omap44xx_mcspi_hwmod_class,
2188 .clkdm_name = "l4_per_clkdm",
2189 .mpu_irqs = omap44xx_mcspi2_irqs,
2190 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2191 .main_clk = "mcspi2_fck",
2194 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2195 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2196 .modulemode = MODULEMODE_SWCTRL,
2199 .dev_attr = &mcspi2_dev_attr,
2203 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2204 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2208 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2209 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2210 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2211 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2212 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2216 /* mcspi3 dev_attr */
2217 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2218 .num_chipselect = 2,
2221 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2223 .class = &omap44xx_mcspi_hwmod_class,
2224 .clkdm_name = "l4_per_clkdm",
2225 .mpu_irqs = omap44xx_mcspi3_irqs,
2226 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2227 .main_clk = "mcspi3_fck",
2230 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2231 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2232 .modulemode = MODULEMODE_SWCTRL,
2235 .dev_attr = &mcspi3_dev_attr,
2239 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2240 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2244 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2245 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2246 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2250 /* mcspi4 dev_attr */
2251 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2252 .num_chipselect = 1,
2255 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2257 .class = &omap44xx_mcspi_hwmod_class,
2258 .clkdm_name = "l4_per_clkdm",
2259 .mpu_irqs = omap44xx_mcspi4_irqs,
2260 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2261 .main_clk = "mcspi4_fck",
2264 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2265 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2266 .modulemode = MODULEMODE_SWCTRL,
2269 .dev_attr = &mcspi4_dev_attr,
2274 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2277 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2279 .sysc_offs = 0x0010,
2280 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2281 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2282 SYSC_HAS_SOFTRESET),
2283 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2284 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2285 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2286 .sysc_fields = &omap_hwmod_sysc_type2,
2289 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2291 .sysc = &omap44xx_mmc_sysc,
2295 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2296 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2300 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2301 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2302 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2307 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2308 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2311 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2313 .class = &omap44xx_mmc_hwmod_class,
2314 .clkdm_name = "l3_init_clkdm",
2315 .mpu_irqs = omap44xx_mmc1_irqs,
2316 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
2317 .main_clk = "mmc1_fck",
2320 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2321 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2322 .modulemode = MODULEMODE_SWCTRL,
2325 .dev_attr = &mmc1_dev_attr,
2329 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2330 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2334 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2335 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2336 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2340 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2342 .class = &omap44xx_mmc_hwmod_class,
2343 .clkdm_name = "l3_init_clkdm",
2344 .mpu_irqs = omap44xx_mmc2_irqs,
2345 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
2346 .main_clk = "mmc2_fck",
2349 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2350 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2351 .modulemode = MODULEMODE_SWCTRL,
2357 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2358 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2362 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2363 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2364 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2368 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2370 .class = &omap44xx_mmc_hwmod_class,
2371 .clkdm_name = "l4_per_clkdm",
2372 .mpu_irqs = omap44xx_mmc3_irqs,
2373 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2374 .main_clk = "mmc3_fck",
2377 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2378 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2379 .modulemode = MODULEMODE_SWCTRL,
2385 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2386 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2390 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2391 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2392 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2396 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2398 .class = &omap44xx_mmc_hwmod_class,
2399 .clkdm_name = "l4_per_clkdm",
2400 .mpu_irqs = omap44xx_mmc4_irqs,
2401 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2402 .main_clk = "mmc4_fck",
2405 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2406 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2407 .modulemode = MODULEMODE_SWCTRL,
2413 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2414 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2418 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2419 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2420 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2424 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2426 .class = &omap44xx_mmc_hwmod_class,
2427 .clkdm_name = "l4_per_clkdm",
2428 .mpu_irqs = omap44xx_mmc5_irqs,
2429 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2430 .main_clk = "mmc5_fck",
2433 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2434 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2435 .modulemode = MODULEMODE_SWCTRL,
2445 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2450 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2451 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2452 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2453 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2457 static struct omap_hwmod omap44xx_mpu_hwmod = {
2459 .class = &omap44xx_mpu_hwmod_class,
2460 .clkdm_name = "mpuss_clkdm",
2461 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2462 .mpu_irqs = omap44xx_mpu_irqs,
2463 .main_clk = "dpll_mpu_m2_ck",
2466 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2467 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2474 * top-level core on-chip ram
2477 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2482 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2484 .class = &omap44xx_ocmc_ram_hwmod_class,
2485 .clkdm_name = "l3_2_clkdm",
2488 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2489 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2496 * bridge to transform ocp interface protocol to scp (serial control port)
2500 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2504 /* ocp2scp_usb_phy */
2505 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2506 { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2509 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2510 .name = "ocp2scp_usb_phy",
2511 .class = &omap44xx_ocp2scp_hwmod_class,
2512 .clkdm_name = "l3_init_clkdm",
2515 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2516 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2517 .modulemode = MODULEMODE_HWCTRL,
2520 .opt_clks = ocp2scp_usb_phy_opt_clks,
2521 .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2526 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2527 * + clock manager 1 (in always on power domain) + local prm in mpu
2530 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2535 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2537 .class = &omap44xx_prcm_hwmod_class,
2538 .clkdm_name = "l4_wkup_clkdm",
2542 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2543 .name = "cm_core_aon",
2544 .class = &omap44xx_prcm_hwmod_class,
2548 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2550 .class = &omap44xx_prcm_hwmod_class,
2554 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2555 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2559 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2560 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2561 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2564 static struct omap_hwmod omap44xx_prm_hwmod = {
2566 .class = &omap44xx_prcm_hwmod_class,
2567 .mpu_irqs = omap44xx_prm_irqs,
2568 .rst_lines = omap44xx_prm_resets,
2569 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2574 * system clock and reset manager
2577 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2582 static struct omap_hwmod omap44xx_scrm_hwmod = {
2584 .class = &omap44xx_scrm_hwmod_class,
2585 .clkdm_name = "l4_wkup_clkdm",
2590 * shared level 2 memory interface
2593 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2598 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2600 .class = &omap44xx_sl2if_hwmod_class,
2601 .clkdm_name = "ivahd_clkdm",
2604 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2605 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2606 .modulemode = MODULEMODE_HWCTRL,
2613 * bidirectional, multi-drop, multi-channel two-line serial interface between
2614 * the device and external components
2617 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2619 .sysc_offs = 0x0010,
2620 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2621 SYSC_HAS_SOFTRESET),
2622 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2624 .sysc_fields = &omap_hwmod_sysc_type2,
2627 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2629 .sysc = &omap44xx_slimbus_sysc,
2633 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2634 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2638 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2639 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2640 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2641 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2642 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2643 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2644 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2645 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2646 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2650 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2651 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2652 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2653 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2654 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2657 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2659 .class = &omap44xx_slimbus_hwmod_class,
2660 .clkdm_name = "abe_clkdm",
2661 .mpu_irqs = omap44xx_slimbus1_irqs,
2662 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2665 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2666 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2667 .modulemode = MODULEMODE_SWCTRL,
2670 .opt_clks = slimbus1_opt_clks,
2671 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2675 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2676 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2680 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2681 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2682 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2683 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2684 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2685 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2686 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2687 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2688 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2692 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2693 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2694 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2695 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2698 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2700 .class = &omap44xx_slimbus_hwmod_class,
2701 .clkdm_name = "l4_per_clkdm",
2702 .mpu_irqs = omap44xx_slimbus2_irqs,
2703 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2706 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2707 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2708 .modulemode = MODULEMODE_SWCTRL,
2711 .opt_clks = slimbus2_opt_clks,
2712 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2716 * 'smartreflex' class
2717 * smartreflex module (monitor silicon performance and outputs a measure of
2718 * performance error)
2721 /* The IP is not compliant to type1 / type2 scheme */
2722 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2727 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2728 .sysc_offs = 0x0038,
2729 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2730 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2732 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2735 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2736 .name = "smartreflex",
2737 .sysc = &omap44xx_smartreflex_sysc,
2741 /* smartreflex_core */
2742 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2743 .sensor_voltdm_name = "core",
2746 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2747 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2751 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2752 .name = "smartreflex_core",
2753 .class = &omap44xx_smartreflex_hwmod_class,
2754 .clkdm_name = "l4_ao_clkdm",
2755 .mpu_irqs = omap44xx_smartreflex_core_irqs,
2757 .main_clk = "smartreflex_core_fck",
2760 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2761 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2762 .modulemode = MODULEMODE_SWCTRL,
2765 .dev_attr = &smartreflex_core_dev_attr,
2768 /* smartreflex_iva */
2769 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2770 .sensor_voltdm_name = "iva",
2773 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2774 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2778 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2779 .name = "smartreflex_iva",
2780 .class = &omap44xx_smartreflex_hwmod_class,
2781 .clkdm_name = "l4_ao_clkdm",
2782 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
2783 .main_clk = "smartreflex_iva_fck",
2786 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2787 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2788 .modulemode = MODULEMODE_SWCTRL,
2791 .dev_attr = &smartreflex_iva_dev_attr,
2794 /* smartreflex_mpu */
2795 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2796 .sensor_voltdm_name = "mpu",
2799 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2800 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2804 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2805 .name = "smartreflex_mpu",
2806 .class = &omap44xx_smartreflex_hwmod_class,
2807 .clkdm_name = "l4_ao_clkdm",
2808 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
2809 .main_clk = "smartreflex_mpu_fck",
2812 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2813 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2814 .modulemode = MODULEMODE_SWCTRL,
2817 .dev_attr = &smartreflex_mpu_dev_attr,
2822 * spinlock provides hardware assistance for synchronizing the processes
2823 * running on multiple processors
2826 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2828 .sysc_offs = 0x0010,
2829 .syss_offs = 0x0014,
2830 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2831 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2832 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2833 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2835 .sysc_fields = &omap_hwmod_sysc_type1,
2838 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2840 .sysc = &omap44xx_spinlock_sysc,
2844 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2846 .class = &omap44xx_spinlock_hwmod_class,
2847 .clkdm_name = "l4_cfg_clkdm",
2850 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2851 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2858 * general purpose timer module with accurate 1ms tick
2859 * This class contains several variants: ['timer_1ms', 'timer']
2862 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2864 .sysc_offs = 0x0010,
2865 .syss_offs = 0x0014,
2866 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2867 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2868 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2869 SYSS_HAS_RESET_STATUS),
2870 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2871 .sysc_fields = &omap_hwmod_sysc_type1,
2874 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2876 .sysc = &omap44xx_timer_1ms_sysc,
2879 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2881 .sysc_offs = 0x0010,
2882 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2883 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2884 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2886 .sysc_fields = &omap_hwmod_sysc_type2,
2889 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2891 .sysc = &omap44xx_timer_sysc,
2894 /* always-on timers dev attribute */
2895 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2896 .timer_capability = OMAP_TIMER_ALWON,
2899 /* pwm timers dev attribute */
2900 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2901 .timer_capability = OMAP_TIMER_HAS_PWM,
2905 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2906 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2910 static struct omap_hwmod omap44xx_timer1_hwmod = {
2912 .class = &omap44xx_timer_1ms_hwmod_class,
2913 .clkdm_name = "l4_wkup_clkdm",
2914 .mpu_irqs = omap44xx_timer1_irqs,
2915 .main_clk = "timer1_fck",
2918 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2919 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2920 .modulemode = MODULEMODE_SWCTRL,
2923 .dev_attr = &capability_alwon_dev_attr,
2927 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2928 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2932 static struct omap_hwmod omap44xx_timer2_hwmod = {
2934 .class = &omap44xx_timer_1ms_hwmod_class,
2935 .clkdm_name = "l4_per_clkdm",
2936 .mpu_irqs = omap44xx_timer2_irqs,
2937 .main_clk = "timer2_fck",
2940 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2941 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2942 .modulemode = MODULEMODE_SWCTRL,
2948 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2949 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2953 static struct omap_hwmod omap44xx_timer3_hwmod = {
2955 .class = &omap44xx_timer_hwmod_class,
2956 .clkdm_name = "l4_per_clkdm",
2957 .mpu_irqs = omap44xx_timer3_irqs,
2958 .main_clk = "timer3_fck",
2961 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2962 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2963 .modulemode = MODULEMODE_SWCTRL,
2969 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2970 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2974 static struct omap_hwmod omap44xx_timer4_hwmod = {
2976 .class = &omap44xx_timer_hwmod_class,
2977 .clkdm_name = "l4_per_clkdm",
2978 .mpu_irqs = omap44xx_timer4_irqs,
2979 .main_clk = "timer4_fck",
2982 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2983 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2984 .modulemode = MODULEMODE_SWCTRL,
2990 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2991 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2995 static struct omap_hwmod omap44xx_timer5_hwmod = {
2997 .class = &omap44xx_timer_hwmod_class,
2998 .clkdm_name = "abe_clkdm",
2999 .mpu_irqs = omap44xx_timer5_irqs,
3000 .main_clk = "timer5_fck",
3003 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3004 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3005 .modulemode = MODULEMODE_SWCTRL,
3011 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3012 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3016 static struct omap_hwmod omap44xx_timer6_hwmod = {
3018 .class = &omap44xx_timer_hwmod_class,
3019 .clkdm_name = "abe_clkdm",
3020 .mpu_irqs = omap44xx_timer6_irqs,
3022 .main_clk = "timer6_fck",
3025 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3026 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3027 .modulemode = MODULEMODE_SWCTRL,
3033 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3034 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3038 static struct omap_hwmod omap44xx_timer7_hwmod = {
3040 .class = &omap44xx_timer_hwmod_class,
3041 .clkdm_name = "abe_clkdm",
3042 .mpu_irqs = omap44xx_timer7_irqs,
3043 .main_clk = "timer7_fck",
3046 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3047 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3048 .modulemode = MODULEMODE_SWCTRL,
3054 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3055 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3059 static struct omap_hwmod omap44xx_timer8_hwmod = {
3061 .class = &omap44xx_timer_hwmod_class,
3062 .clkdm_name = "abe_clkdm",
3063 .mpu_irqs = omap44xx_timer8_irqs,
3064 .main_clk = "timer8_fck",
3067 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3068 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3069 .modulemode = MODULEMODE_SWCTRL,
3072 .dev_attr = &capability_pwm_dev_attr,
3076 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3077 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3081 static struct omap_hwmod omap44xx_timer9_hwmod = {
3083 .class = &omap44xx_timer_hwmod_class,
3084 .clkdm_name = "l4_per_clkdm",
3085 .mpu_irqs = omap44xx_timer9_irqs,
3086 .main_clk = "timer9_fck",
3089 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3090 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3091 .modulemode = MODULEMODE_SWCTRL,
3094 .dev_attr = &capability_pwm_dev_attr,
3098 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3099 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3103 static struct omap_hwmod omap44xx_timer10_hwmod = {
3105 .class = &omap44xx_timer_1ms_hwmod_class,
3106 .clkdm_name = "l4_per_clkdm",
3107 .mpu_irqs = omap44xx_timer10_irqs,
3108 .main_clk = "timer10_fck",
3111 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3112 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3113 .modulemode = MODULEMODE_SWCTRL,
3116 .dev_attr = &capability_pwm_dev_attr,
3120 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3121 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3125 static struct omap_hwmod omap44xx_timer11_hwmod = {
3127 .class = &omap44xx_timer_hwmod_class,
3128 .clkdm_name = "l4_per_clkdm",
3129 .mpu_irqs = omap44xx_timer11_irqs,
3130 .main_clk = "timer11_fck",
3133 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3134 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3135 .modulemode = MODULEMODE_SWCTRL,
3138 .dev_attr = &capability_pwm_dev_attr,
3143 * universal asynchronous receiver/transmitter (uart)
3146 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3148 .sysc_offs = 0x0054,
3149 .syss_offs = 0x0058,
3150 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3151 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3152 SYSS_HAS_RESET_STATUS),
3153 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3155 .sysc_fields = &omap_hwmod_sysc_type1,
3158 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3160 .sysc = &omap44xx_uart_sysc,
3164 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3165 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3169 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3170 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3171 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3175 static struct omap_hwmod omap44xx_uart1_hwmod = {
3177 .class = &omap44xx_uart_hwmod_class,
3178 .clkdm_name = "l4_per_clkdm",
3179 .mpu_irqs = omap44xx_uart1_irqs,
3180 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3181 .main_clk = "uart1_fck",
3184 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3185 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3186 .modulemode = MODULEMODE_SWCTRL,
3192 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3193 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3197 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3198 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3199 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3203 static struct omap_hwmod omap44xx_uart2_hwmod = {
3205 .class = &omap44xx_uart_hwmod_class,
3206 .clkdm_name = "l4_per_clkdm",
3207 .mpu_irqs = omap44xx_uart2_irqs,
3208 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3209 .main_clk = "uart2_fck",
3212 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3213 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3214 .modulemode = MODULEMODE_SWCTRL,
3220 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3221 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3225 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3226 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3227 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3231 static struct omap_hwmod omap44xx_uart3_hwmod = {
3233 .class = &omap44xx_uart_hwmod_class,
3234 .clkdm_name = "l4_per_clkdm",
3235 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3236 .mpu_irqs = omap44xx_uart3_irqs,
3237 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3238 .main_clk = "uart3_fck",
3241 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3242 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3243 .modulemode = MODULEMODE_SWCTRL,
3249 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3250 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3254 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3255 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3256 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3260 static struct omap_hwmod omap44xx_uart4_hwmod = {
3262 .class = &omap44xx_uart_hwmod_class,
3263 .clkdm_name = "l4_per_clkdm",
3264 .mpu_irqs = omap44xx_uart4_irqs,
3265 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3266 .main_clk = "uart4_fck",
3269 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3270 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3271 .modulemode = MODULEMODE_SWCTRL,
3277 * 'usb_host_fs' class
3278 * full-speed usb host controller
3281 /* The IP is not compliant to type1 / type2 scheme */
3282 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3288 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3290 .sysc_offs = 0x0210,
3291 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3292 SYSC_HAS_SOFTRESET),
3293 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3295 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
3298 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3299 .name = "usb_host_fs",
3300 .sysc = &omap44xx_usb_host_fs_sysc,
3304 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3305 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3306 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3310 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3311 .name = "usb_host_fs",
3312 .class = &omap44xx_usb_host_fs_hwmod_class,
3313 .clkdm_name = "l3_init_clkdm",
3314 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3315 .main_clk = "usb_host_fs_fck",
3318 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3319 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3320 .modulemode = MODULEMODE_SWCTRL,
3326 * 'usb_host_hs' class
3327 * high-speed multi-port usb host controller
3330 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3332 .sysc_offs = 0x0010,
3333 .syss_offs = 0x0014,
3334 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3335 SYSC_HAS_SOFTRESET),
3336 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3337 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3338 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3339 .sysc_fields = &omap_hwmod_sysc_type2,
3342 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3343 .name = "usb_host_hs",
3344 .sysc = &omap44xx_usb_host_hs_sysc,
3348 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3349 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3350 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3354 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3355 .name = "usb_host_hs",
3356 .class = &omap44xx_usb_host_hs_hwmod_class,
3357 .clkdm_name = "l3_init_clkdm",
3358 .main_clk = "usb_host_hs_fck",
3361 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3362 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3363 .modulemode = MODULEMODE_SWCTRL,
3366 .mpu_irqs = omap44xx_usb_host_hs_irqs,
3369 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3373 * In the following configuration :
3374 * - USBHOST module is set to smart-idle mode
3375 * - PRCM asserts idle_req to the USBHOST module ( This typically
3376 * happens when the system is going to a low power mode : all ports
3377 * have been suspended, the master part of the USBHOST module has
3378 * entered the standby state, and SW has cut the functional clocks)
3379 * - an USBHOST interrupt occurs before the module is able to answer
3380 * idle_ack, typically a remote wakeup IRQ.
3381 * Then the USB HOST module will enter a deadlock situation where it
3382 * is no more accessible nor functional.
3385 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3389 * Errata: USB host EHCI may stall when entering smart-standby mode
3393 * When the USBHOST module is set to smart-standby mode, and when it is
3394 * ready to enter the standby state (i.e. all ports are suspended and
3395 * all attached devices are in suspend mode), then it can wrongly assert
3396 * the Mstandby signal too early while there are still some residual OCP
3397 * transactions ongoing. If this condition occurs, the internal state
3398 * machine may go to an undefined state and the USB link may be stuck
3399 * upon the next resume.
3402 * Don't use smart standby; use only force standby,
3403 * hence HWMOD_SWSUP_MSTANDBY
3407 * During system boot; If the hwmod framework resets the module
3408 * the module will have smart idle settings; which can lead to deadlock
3409 * (above Errata Id:i660); so, dont reset the module during boot;
3410 * Use HWMOD_INIT_NO_RESET.
3413 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3414 HWMOD_INIT_NO_RESET,
3418 * 'usb_otg_hs' class
3419 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3422 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3424 .sysc_offs = 0x0404,
3425 .syss_offs = 0x0408,
3426 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3427 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3428 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3429 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3430 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3432 .sysc_fields = &omap_hwmod_sysc_type1,
3435 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3436 .name = "usb_otg_hs",
3437 .sysc = &omap44xx_usb_otg_hs_sysc,
3441 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3442 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3443 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3447 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3448 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3451 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3452 .name = "usb_otg_hs",
3453 .class = &omap44xx_usb_otg_hs_hwmod_class,
3454 .clkdm_name = "l3_init_clkdm",
3455 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3456 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
3457 .main_clk = "usb_otg_hs_ick",
3460 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3461 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3462 .modulemode = MODULEMODE_HWCTRL,
3465 .opt_clks = usb_otg_hs_opt_clks,
3466 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3470 * 'usb_tll_hs' class
3471 * usb_tll_hs module is the adapter on the usb_host_hs ports
3474 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3476 .sysc_offs = 0x0010,
3477 .syss_offs = 0x0014,
3478 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3479 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3481 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3482 .sysc_fields = &omap_hwmod_sysc_type1,
3485 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3486 .name = "usb_tll_hs",
3487 .sysc = &omap44xx_usb_tll_hs_sysc,
3490 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3491 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3495 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3496 .name = "usb_tll_hs",
3497 .class = &omap44xx_usb_tll_hs_hwmod_class,
3498 .clkdm_name = "l3_init_clkdm",
3499 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
3500 .main_clk = "usb_tll_hs_ick",
3503 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3504 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3505 .modulemode = MODULEMODE_HWCTRL,
3512 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3513 * overflow condition
3516 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3518 .sysc_offs = 0x0010,
3519 .syss_offs = 0x0014,
3520 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3521 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3522 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3524 .sysc_fields = &omap_hwmod_sysc_type1,
3527 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3529 .sysc = &omap44xx_wd_timer_sysc,
3530 .pre_shutdown = &omap2_wd_timer_disable,
3531 .reset = &omap2_wd_timer_reset,
3535 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3536 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3540 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3541 .name = "wd_timer2",
3542 .class = &omap44xx_wd_timer_hwmod_class,
3543 .clkdm_name = "l4_wkup_clkdm",
3544 .mpu_irqs = omap44xx_wd_timer2_irqs,
3545 .main_clk = "wd_timer2_fck",
3548 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3549 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3550 .modulemode = MODULEMODE_SWCTRL,
3556 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3557 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3561 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3562 .name = "wd_timer3",
3563 .class = &omap44xx_wd_timer_hwmod_class,
3564 .clkdm_name = "abe_clkdm",
3565 .mpu_irqs = omap44xx_wd_timer3_irqs,
3566 .main_clk = "wd_timer3_fck",
3569 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3570 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3571 .modulemode = MODULEMODE_SWCTRL,
3581 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3583 .pa_start = 0x4a204000,
3584 .pa_end = 0x4a2040ff,
3585 .flags = ADDR_TYPE_RT
3590 /* c2c -> c2c_target_fw */
3591 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3592 .master = &omap44xx_c2c_hwmod,
3593 .slave = &omap44xx_c2c_target_fw_hwmod,
3594 .clk = "div_core_ck",
3595 .addr = omap44xx_c2c_target_fw_addrs,
3596 .user = OCP_USER_MPU,
3599 /* l4_cfg -> c2c_target_fw */
3600 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3601 .master = &omap44xx_l4_cfg_hwmod,
3602 .slave = &omap44xx_c2c_target_fw_hwmod,
3604 .user = OCP_USER_MPU | OCP_USER_SDMA,
3607 /* l3_main_1 -> dmm */
3608 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3609 .master = &omap44xx_l3_main_1_hwmod,
3610 .slave = &omap44xx_dmm_hwmod,
3612 .user = OCP_USER_SDMA,
3615 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3617 .pa_start = 0x4e000000,
3618 .pa_end = 0x4e0007ff,
3619 .flags = ADDR_TYPE_RT
3625 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3626 .master = &omap44xx_mpu_hwmod,
3627 .slave = &omap44xx_dmm_hwmod,
3629 .addr = omap44xx_dmm_addrs,
3630 .user = OCP_USER_MPU,
3633 /* c2c -> emif_fw */
3634 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3635 .master = &omap44xx_c2c_hwmod,
3636 .slave = &omap44xx_emif_fw_hwmod,
3637 .clk = "div_core_ck",
3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3641 /* dmm -> emif_fw */
3642 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3643 .master = &omap44xx_dmm_hwmod,
3644 .slave = &omap44xx_emif_fw_hwmod,
3646 .user = OCP_USER_MPU | OCP_USER_SDMA,
3649 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3651 .pa_start = 0x4a20c000,
3652 .pa_end = 0x4a20c0ff,
3653 .flags = ADDR_TYPE_RT
3658 /* l4_cfg -> emif_fw */
3659 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3660 .master = &omap44xx_l4_cfg_hwmod,
3661 .slave = &omap44xx_emif_fw_hwmod,
3663 .addr = omap44xx_emif_fw_addrs,
3664 .user = OCP_USER_MPU,
3667 /* iva -> l3_instr */
3668 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3669 .master = &omap44xx_iva_hwmod,
3670 .slave = &omap44xx_l3_instr_hwmod,
3672 .user = OCP_USER_MPU | OCP_USER_SDMA,
3675 /* l3_main_3 -> l3_instr */
3676 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3677 .master = &omap44xx_l3_main_3_hwmod,
3678 .slave = &omap44xx_l3_instr_hwmod,
3680 .user = OCP_USER_MPU | OCP_USER_SDMA,
3683 /* ocp_wp_noc -> l3_instr */
3684 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3685 .master = &omap44xx_ocp_wp_noc_hwmod,
3686 .slave = &omap44xx_l3_instr_hwmod,
3688 .user = OCP_USER_MPU | OCP_USER_SDMA,
3691 /* dsp -> l3_main_1 */
3692 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3693 .master = &omap44xx_dsp_hwmod,
3694 .slave = &omap44xx_l3_main_1_hwmod,
3696 .user = OCP_USER_MPU | OCP_USER_SDMA,
3699 /* dss -> l3_main_1 */
3700 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3701 .master = &omap44xx_dss_hwmod,
3702 .slave = &omap44xx_l3_main_1_hwmod,
3704 .user = OCP_USER_MPU | OCP_USER_SDMA,
3707 /* l3_main_2 -> l3_main_1 */
3708 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3709 .master = &omap44xx_l3_main_2_hwmod,
3710 .slave = &omap44xx_l3_main_1_hwmod,
3712 .user = OCP_USER_MPU | OCP_USER_SDMA,
3715 /* l4_cfg -> l3_main_1 */
3716 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3717 .master = &omap44xx_l4_cfg_hwmod,
3718 .slave = &omap44xx_l3_main_1_hwmod,
3720 .user = OCP_USER_MPU | OCP_USER_SDMA,
3723 /* mmc1 -> l3_main_1 */
3724 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3725 .master = &omap44xx_mmc1_hwmod,
3726 .slave = &omap44xx_l3_main_1_hwmod,
3728 .user = OCP_USER_MPU | OCP_USER_SDMA,
3731 /* mmc2 -> l3_main_1 */
3732 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3733 .master = &omap44xx_mmc2_hwmod,
3734 .slave = &omap44xx_l3_main_1_hwmod,
3736 .user = OCP_USER_MPU | OCP_USER_SDMA,
3739 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3741 .pa_start = 0x44000000,
3742 .pa_end = 0x44000fff,
3743 .flags = ADDR_TYPE_RT
3748 /* mpu -> l3_main_1 */
3749 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3750 .master = &omap44xx_mpu_hwmod,
3751 .slave = &omap44xx_l3_main_1_hwmod,
3753 .addr = omap44xx_l3_main_1_addrs,
3754 .user = OCP_USER_MPU,
3757 /* c2c_target_fw -> l3_main_2 */
3758 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3759 .master = &omap44xx_c2c_target_fw_hwmod,
3760 .slave = &omap44xx_l3_main_2_hwmod,
3762 .user = OCP_USER_MPU | OCP_USER_SDMA,
3765 /* debugss -> l3_main_2 */
3766 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3767 .master = &omap44xx_debugss_hwmod,
3768 .slave = &omap44xx_l3_main_2_hwmod,
3769 .clk = "dbgclk_mux_ck",
3770 .user = OCP_USER_MPU | OCP_USER_SDMA,
3773 /* dma_system -> l3_main_2 */
3774 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3775 .master = &omap44xx_dma_system_hwmod,
3776 .slave = &omap44xx_l3_main_2_hwmod,
3778 .user = OCP_USER_MPU | OCP_USER_SDMA,
3781 /* fdif -> l3_main_2 */
3782 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3783 .master = &omap44xx_fdif_hwmod,
3784 .slave = &omap44xx_l3_main_2_hwmod,
3786 .user = OCP_USER_MPU | OCP_USER_SDMA,
3789 /* gpu -> l3_main_2 */
3790 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3791 .master = &omap44xx_gpu_hwmod,
3792 .slave = &omap44xx_l3_main_2_hwmod,
3794 .user = OCP_USER_MPU | OCP_USER_SDMA,
3797 /* hsi -> l3_main_2 */
3798 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3799 .master = &omap44xx_hsi_hwmod,
3800 .slave = &omap44xx_l3_main_2_hwmod,
3802 .user = OCP_USER_MPU | OCP_USER_SDMA,
3805 /* ipu -> l3_main_2 */
3806 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3807 .master = &omap44xx_ipu_hwmod,
3808 .slave = &omap44xx_l3_main_2_hwmod,
3810 .user = OCP_USER_MPU | OCP_USER_SDMA,
3813 /* iss -> l3_main_2 */
3814 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3815 .master = &omap44xx_iss_hwmod,
3816 .slave = &omap44xx_l3_main_2_hwmod,
3818 .user = OCP_USER_MPU | OCP_USER_SDMA,
3821 /* iva -> l3_main_2 */
3822 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3823 .master = &omap44xx_iva_hwmod,
3824 .slave = &omap44xx_l3_main_2_hwmod,
3826 .user = OCP_USER_MPU | OCP_USER_SDMA,
3829 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3831 .pa_start = 0x44800000,
3832 .pa_end = 0x44801fff,
3833 .flags = ADDR_TYPE_RT
3838 /* l3_main_1 -> l3_main_2 */
3839 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3840 .master = &omap44xx_l3_main_1_hwmod,
3841 .slave = &omap44xx_l3_main_2_hwmod,
3843 .addr = omap44xx_l3_main_2_addrs,
3844 .user = OCP_USER_MPU,
3847 /* l4_cfg -> l3_main_2 */
3848 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3849 .master = &omap44xx_l4_cfg_hwmod,
3850 .slave = &omap44xx_l3_main_2_hwmod,
3852 .user = OCP_USER_MPU | OCP_USER_SDMA,
3855 /* usb_host_fs -> l3_main_2 */
3856 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3857 .master = &omap44xx_usb_host_fs_hwmod,
3858 .slave = &omap44xx_l3_main_2_hwmod,
3860 .user = OCP_USER_MPU | OCP_USER_SDMA,
3863 /* usb_host_hs -> l3_main_2 */
3864 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3865 .master = &omap44xx_usb_host_hs_hwmod,
3866 .slave = &omap44xx_l3_main_2_hwmod,
3868 .user = OCP_USER_MPU | OCP_USER_SDMA,
3871 /* usb_otg_hs -> l3_main_2 */
3872 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3873 .master = &omap44xx_usb_otg_hs_hwmod,
3874 .slave = &omap44xx_l3_main_2_hwmod,
3876 .user = OCP_USER_MPU | OCP_USER_SDMA,
3879 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3881 .pa_start = 0x45000000,
3882 .pa_end = 0x45000fff,
3883 .flags = ADDR_TYPE_RT
3888 /* l3_main_1 -> l3_main_3 */
3889 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3890 .master = &omap44xx_l3_main_1_hwmod,
3891 .slave = &omap44xx_l3_main_3_hwmod,
3893 .addr = omap44xx_l3_main_3_addrs,
3894 .user = OCP_USER_MPU,
3897 /* l3_main_2 -> l3_main_3 */
3898 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3899 .master = &omap44xx_l3_main_2_hwmod,
3900 .slave = &omap44xx_l3_main_3_hwmod,
3902 .user = OCP_USER_MPU | OCP_USER_SDMA,
3905 /* l4_cfg -> l3_main_3 */
3906 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3907 .master = &omap44xx_l4_cfg_hwmod,
3908 .slave = &omap44xx_l3_main_3_hwmod,
3910 .user = OCP_USER_MPU | OCP_USER_SDMA,
3913 /* aess -> l4_abe */
3914 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3915 .master = &omap44xx_aess_hwmod,
3916 .slave = &omap44xx_l4_abe_hwmod,
3917 .clk = "ocp_abe_iclk",
3918 .user = OCP_USER_MPU | OCP_USER_SDMA,
3922 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3923 .master = &omap44xx_dsp_hwmod,
3924 .slave = &omap44xx_l4_abe_hwmod,
3925 .clk = "ocp_abe_iclk",
3926 .user = OCP_USER_MPU | OCP_USER_SDMA,
3929 /* l3_main_1 -> l4_abe */
3930 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3931 .master = &omap44xx_l3_main_1_hwmod,
3932 .slave = &omap44xx_l4_abe_hwmod,
3934 .user = OCP_USER_MPU | OCP_USER_SDMA,
3938 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3939 .master = &omap44xx_mpu_hwmod,
3940 .slave = &omap44xx_l4_abe_hwmod,
3941 .clk = "ocp_abe_iclk",
3942 .user = OCP_USER_MPU | OCP_USER_SDMA,
3945 /* l3_main_1 -> l4_cfg */
3946 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3947 .master = &omap44xx_l3_main_1_hwmod,
3948 .slave = &omap44xx_l4_cfg_hwmod,
3950 .user = OCP_USER_MPU | OCP_USER_SDMA,
3953 /* l3_main_2 -> l4_per */
3954 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3955 .master = &omap44xx_l3_main_2_hwmod,
3956 .slave = &omap44xx_l4_per_hwmod,
3958 .user = OCP_USER_MPU | OCP_USER_SDMA,
3961 /* l4_cfg -> l4_wkup */
3962 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3963 .master = &omap44xx_l4_cfg_hwmod,
3964 .slave = &omap44xx_l4_wkup_hwmod,
3966 .user = OCP_USER_MPU | OCP_USER_SDMA,
3969 /* mpu -> mpu_private */
3970 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3971 .master = &omap44xx_mpu_hwmod,
3972 .slave = &omap44xx_mpu_private_hwmod,
3974 .user = OCP_USER_MPU | OCP_USER_SDMA,
3977 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3979 .pa_start = 0x4a102000,
3980 .pa_end = 0x4a10207f,
3981 .flags = ADDR_TYPE_RT
3986 /* l4_cfg -> ocp_wp_noc */
3987 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3988 .master = &omap44xx_l4_cfg_hwmod,
3989 .slave = &omap44xx_ocp_wp_noc_hwmod,
3991 .addr = omap44xx_ocp_wp_noc_addrs,
3992 .user = OCP_USER_MPU | OCP_USER_SDMA,
3995 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3997 .pa_start = 0x401f1000,
3998 .pa_end = 0x401f13ff,
3999 .flags = ADDR_TYPE_RT
4004 /* l4_abe -> aess */
4005 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4006 .master = &omap44xx_l4_abe_hwmod,
4007 .slave = &omap44xx_aess_hwmod,
4008 .clk = "ocp_abe_iclk",
4009 .addr = omap44xx_aess_addrs,
4010 .user = OCP_USER_MPU,
4013 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4015 .pa_start = 0x490f1000,
4016 .pa_end = 0x490f13ff,
4017 .flags = ADDR_TYPE_RT
4022 /* l4_abe -> aess (dma) */
4023 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4024 .master = &omap44xx_l4_abe_hwmod,
4025 .slave = &omap44xx_aess_hwmod,
4026 .clk = "ocp_abe_iclk",
4027 .addr = omap44xx_aess_dma_addrs,
4028 .user = OCP_USER_SDMA,
4031 /* l3_main_2 -> c2c */
4032 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4033 .master = &omap44xx_l3_main_2_hwmod,
4034 .slave = &omap44xx_c2c_hwmod,
4036 .user = OCP_USER_MPU | OCP_USER_SDMA,
4039 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4041 .pa_start = 0x4a304000,
4042 .pa_end = 0x4a30401f,
4043 .flags = ADDR_TYPE_RT
4048 /* l4_wkup -> counter_32k */
4049 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4050 .master = &omap44xx_l4_wkup_hwmod,
4051 .slave = &omap44xx_counter_32k_hwmod,
4052 .clk = "l4_wkup_clk_mux_ck",
4053 .addr = omap44xx_counter_32k_addrs,
4054 .user = OCP_USER_MPU | OCP_USER_SDMA,
4057 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4059 .pa_start = 0x4a002000,
4060 .pa_end = 0x4a0027ff,
4061 .flags = ADDR_TYPE_RT
4066 /* l4_cfg -> ctrl_module_core */
4067 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4068 .master = &omap44xx_l4_cfg_hwmod,
4069 .slave = &omap44xx_ctrl_module_core_hwmod,
4071 .addr = omap44xx_ctrl_module_core_addrs,
4072 .user = OCP_USER_MPU | OCP_USER_SDMA,
4075 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4077 .pa_start = 0x4a100000,
4078 .pa_end = 0x4a1007ff,
4079 .flags = ADDR_TYPE_RT
4084 /* l4_cfg -> ctrl_module_pad_core */
4085 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4086 .master = &omap44xx_l4_cfg_hwmod,
4087 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
4089 .addr = omap44xx_ctrl_module_pad_core_addrs,
4090 .user = OCP_USER_MPU | OCP_USER_SDMA,
4093 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4095 .pa_start = 0x4a30c000,
4096 .pa_end = 0x4a30c7ff,
4097 .flags = ADDR_TYPE_RT
4102 /* l4_wkup -> ctrl_module_wkup */
4103 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4104 .master = &omap44xx_l4_wkup_hwmod,
4105 .slave = &omap44xx_ctrl_module_wkup_hwmod,
4106 .clk = "l4_wkup_clk_mux_ck",
4107 .addr = omap44xx_ctrl_module_wkup_addrs,
4108 .user = OCP_USER_MPU | OCP_USER_SDMA,
4111 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4113 .pa_start = 0x4a31e000,
4114 .pa_end = 0x4a31e7ff,
4115 .flags = ADDR_TYPE_RT
4120 /* l4_wkup -> ctrl_module_pad_wkup */
4121 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4122 .master = &omap44xx_l4_wkup_hwmod,
4123 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
4124 .clk = "l4_wkup_clk_mux_ck",
4125 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
4126 .user = OCP_USER_MPU | OCP_USER_SDMA,
4129 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4131 .pa_start = 0x54160000,
4132 .pa_end = 0x54167fff,
4133 .flags = ADDR_TYPE_RT
4138 /* l3_instr -> debugss */
4139 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4140 .master = &omap44xx_l3_instr_hwmod,
4141 .slave = &omap44xx_debugss_hwmod,
4143 .addr = omap44xx_debugss_addrs,
4144 .user = OCP_USER_MPU | OCP_USER_SDMA,
4147 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4149 .pa_start = 0x4a056000,
4150 .pa_end = 0x4a056fff,
4151 .flags = ADDR_TYPE_RT
4156 /* l4_cfg -> dma_system */
4157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4158 .master = &omap44xx_l4_cfg_hwmod,
4159 .slave = &omap44xx_dma_system_hwmod,
4161 .addr = omap44xx_dma_system_addrs,
4162 .user = OCP_USER_MPU | OCP_USER_SDMA,
4165 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4168 .pa_start = 0x4012e000,
4169 .pa_end = 0x4012e07f,
4170 .flags = ADDR_TYPE_RT
4175 /* l4_abe -> dmic */
4176 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4177 .master = &omap44xx_l4_abe_hwmod,
4178 .slave = &omap44xx_dmic_hwmod,
4179 .clk = "ocp_abe_iclk",
4180 .addr = omap44xx_dmic_addrs,
4181 .user = OCP_USER_MPU,
4184 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4187 .pa_start = 0x4902e000,
4188 .pa_end = 0x4902e07f,
4189 .flags = ADDR_TYPE_RT
4194 /* l4_abe -> dmic (dma) */
4195 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4196 .master = &omap44xx_l4_abe_hwmod,
4197 .slave = &omap44xx_dmic_hwmod,
4198 .clk = "ocp_abe_iclk",
4199 .addr = omap44xx_dmic_dma_addrs,
4200 .user = OCP_USER_SDMA,
4204 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4205 .master = &omap44xx_dsp_hwmod,
4206 .slave = &omap44xx_iva_hwmod,
4207 .clk = "dpll_iva_m5x2_ck",
4208 .user = OCP_USER_DSP,
4212 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4213 .master = &omap44xx_dsp_hwmod,
4214 .slave = &omap44xx_sl2if_hwmod,
4215 .clk = "dpll_iva_m5x2_ck",
4216 .user = OCP_USER_DSP,
4220 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4221 .master = &omap44xx_l4_cfg_hwmod,
4222 .slave = &omap44xx_dsp_hwmod,
4224 .user = OCP_USER_MPU | OCP_USER_SDMA,
4227 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4229 .pa_start = 0x58000000,
4230 .pa_end = 0x5800007f,
4231 .flags = ADDR_TYPE_RT
4236 /* l3_main_2 -> dss */
4237 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4238 .master = &omap44xx_l3_main_2_hwmod,
4239 .slave = &omap44xx_dss_hwmod,
4241 .addr = omap44xx_dss_dma_addrs,
4242 .user = OCP_USER_SDMA,
4245 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4247 .pa_start = 0x48040000,
4248 .pa_end = 0x4804007f,
4249 .flags = ADDR_TYPE_RT
4255 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4256 .master = &omap44xx_l4_per_hwmod,
4257 .slave = &omap44xx_dss_hwmod,
4259 .addr = omap44xx_dss_addrs,
4260 .user = OCP_USER_MPU,
4263 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4265 .pa_start = 0x58001000,
4266 .pa_end = 0x58001fff,
4267 .flags = ADDR_TYPE_RT
4272 /* l3_main_2 -> dss_dispc */
4273 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4274 .master = &omap44xx_l3_main_2_hwmod,
4275 .slave = &omap44xx_dss_dispc_hwmod,
4277 .addr = omap44xx_dss_dispc_dma_addrs,
4278 .user = OCP_USER_SDMA,
4281 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4283 .pa_start = 0x48041000,
4284 .pa_end = 0x48041fff,
4285 .flags = ADDR_TYPE_RT
4290 /* l4_per -> dss_dispc */
4291 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4292 .master = &omap44xx_l4_per_hwmod,
4293 .slave = &omap44xx_dss_dispc_hwmod,
4295 .addr = omap44xx_dss_dispc_addrs,
4296 .user = OCP_USER_MPU,
4299 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4301 .pa_start = 0x58004000,
4302 .pa_end = 0x580041ff,
4303 .flags = ADDR_TYPE_RT
4308 /* l3_main_2 -> dss_dsi1 */
4309 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4310 .master = &omap44xx_l3_main_2_hwmod,
4311 .slave = &omap44xx_dss_dsi1_hwmod,
4313 .addr = omap44xx_dss_dsi1_dma_addrs,
4314 .user = OCP_USER_SDMA,
4317 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4319 .pa_start = 0x48044000,
4320 .pa_end = 0x480441ff,
4321 .flags = ADDR_TYPE_RT
4326 /* l4_per -> dss_dsi1 */
4327 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4328 .master = &omap44xx_l4_per_hwmod,
4329 .slave = &omap44xx_dss_dsi1_hwmod,
4331 .addr = omap44xx_dss_dsi1_addrs,
4332 .user = OCP_USER_MPU,
4335 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4337 .pa_start = 0x58005000,
4338 .pa_end = 0x580051ff,
4339 .flags = ADDR_TYPE_RT
4344 /* l3_main_2 -> dss_dsi2 */
4345 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4346 .master = &omap44xx_l3_main_2_hwmod,
4347 .slave = &omap44xx_dss_dsi2_hwmod,
4349 .addr = omap44xx_dss_dsi2_dma_addrs,
4350 .user = OCP_USER_SDMA,
4353 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4355 .pa_start = 0x48045000,
4356 .pa_end = 0x480451ff,
4357 .flags = ADDR_TYPE_RT
4362 /* l4_per -> dss_dsi2 */
4363 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4364 .master = &omap44xx_l4_per_hwmod,
4365 .slave = &omap44xx_dss_dsi2_hwmod,
4367 .addr = omap44xx_dss_dsi2_addrs,
4368 .user = OCP_USER_MPU,
4371 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4373 .pa_start = 0x58006000,
4374 .pa_end = 0x58006fff,
4375 .flags = ADDR_TYPE_RT
4380 /* l3_main_2 -> dss_hdmi */
4381 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4382 .master = &omap44xx_l3_main_2_hwmod,
4383 .slave = &omap44xx_dss_hdmi_hwmod,
4385 .addr = omap44xx_dss_hdmi_dma_addrs,
4386 .user = OCP_USER_SDMA,
4389 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4391 .pa_start = 0x48046000,
4392 .pa_end = 0x48046fff,
4393 .flags = ADDR_TYPE_RT
4398 /* l4_per -> dss_hdmi */
4399 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4400 .master = &omap44xx_l4_per_hwmod,
4401 .slave = &omap44xx_dss_hdmi_hwmod,
4403 .addr = omap44xx_dss_hdmi_addrs,
4404 .user = OCP_USER_MPU,
4407 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4409 .pa_start = 0x58002000,
4410 .pa_end = 0x580020ff,
4411 .flags = ADDR_TYPE_RT
4416 /* l3_main_2 -> dss_rfbi */
4417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4418 .master = &omap44xx_l3_main_2_hwmod,
4419 .slave = &omap44xx_dss_rfbi_hwmod,
4421 .addr = omap44xx_dss_rfbi_dma_addrs,
4422 .user = OCP_USER_SDMA,
4425 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4427 .pa_start = 0x48042000,
4428 .pa_end = 0x480420ff,
4429 .flags = ADDR_TYPE_RT
4434 /* l4_per -> dss_rfbi */
4435 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4436 .master = &omap44xx_l4_per_hwmod,
4437 .slave = &omap44xx_dss_rfbi_hwmod,
4439 .addr = omap44xx_dss_rfbi_addrs,
4440 .user = OCP_USER_MPU,
4443 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4445 .pa_start = 0x58003000,
4446 .pa_end = 0x580030ff,
4447 .flags = ADDR_TYPE_RT
4452 /* l3_main_2 -> dss_venc */
4453 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4454 .master = &omap44xx_l3_main_2_hwmod,
4455 .slave = &omap44xx_dss_venc_hwmod,
4457 .addr = omap44xx_dss_venc_dma_addrs,
4458 .user = OCP_USER_SDMA,
4461 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4463 .pa_start = 0x48043000,
4464 .pa_end = 0x480430ff,
4465 .flags = ADDR_TYPE_RT
4470 /* l4_per -> dss_venc */
4471 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4472 .master = &omap44xx_l4_per_hwmod,
4473 .slave = &omap44xx_dss_venc_hwmod,
4475 .addr = omap44xx_dss_venc_addrs,
4476 .user = OCP_USER_MPU,
4479 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4481 .pa_start = 0x48078000,
4482 .pa_end = 0x48078fff,
4483 .flags = ADDR_TYPE_RT
4489 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4490 .master = &omap44xx_l4_per_hwmod,
4491 .slave = &omap44xx_elm_hwmod,
4493 .addr = omap44xx_elm_addrs,
4494 .user = OCP_USER_MPU | OCP_USER_SDMA,
4497 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4499 .pa_start = 0x4c000000,
4500 .pa_end = 0x4c0000ff,
4501 .flags = ADDR_TYPE_RT
4506 /* emif_fw -> emif1 */
4507 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4508 .master = &omap44xx_emif_fw_hwmod,
4509 .slave = &omap44xx_emif1_hwmod,
4511 .addr = omap44xx_emif1_addrs,
4512 .user = OCP_USER_MPU | OCP_USER_SDMA,
4515 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4517 .pa_start = 0x4d000000,
4518 .pa_end = 0x4d0000ff,
4519 .flags = ADDR_TYPE_RT
4524 /* emif_fw -> emif2 */
4525 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4526 .master = &omap44xx_emif_fw_hwmod,
4527 .slave = &omap44xx_emif2_hwmod,
4529 .addr = omap44xx_emif2_addrs,
4530 .user = OCP_USER_MPU | OCP_USER_SDMA,
4533 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4535 .pa_start = 0x4a10a000,
4536 .pa_end = 0x4a10a1ff,
4537 .flags = ADDR_TYPE_RT
4542 /* l4_cfg -> fdif */
4543 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4544 .master = &omap44xx_l4_cfg_hwmod,
4545 .slave = &omap44xx_fdif_hwmod,
4547 .addr = omap44xx_fdif_addrs,
4548 .user = OCP_USER_MPU | OCP_USER_SDMA,
4551 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4553 .pa_start = 0x4a310000,
4554 .pa_end = 0x4a3101ff,
4555 .flags = ADDR_TYPE_RT
4560 /* l4_wkup -> gpio1 */
4561 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4562 .master = &omap44xx_l4_wkup_hwmod,
4563 .slave = &omap44xx_gpio1_hwmod,
4564 .clk = "l4_wkup_clk_mux_ck",
4565 .addr = omap44xx_gpio1_addrs,
4566 .user = OCP_USER_MPU | OCP_USER_SDMA,
4569 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4571 .pa_start = 0x48055000,
4572 .pa_end = 0x480551ff,
4573 .flags = ADDR_TYPE_RT
4578 /* l4_per -> gpio2 */
4579 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4580 .master = &omap44xx_l4_per_hwmod,
4581 .slave = &omap44xx_gpio2_hwmod,
4583 .addr = omap44xx_gpio2_addrs,
4584 .user = OCP_USER_MPU | OCP_USER_SDMA,
4587 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4589 .pa_start = 0x48057000,
4590 .pa_end = 0x480571ff,
4591 .flags = ADDR_TYPE_RT
4596 /* l4_per -> gpio3 */
4597 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4598 .master = &omap44xx_l4_per_hwmod,
4599 .slave = &omap44xx_gpio3_hwmod,
4601 .addr = omap44xx_gpio3_addrs,
4602 .user = OCP_USER_MPU | OCP_USER_SDMA,
4605 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4607 .pa_start = 0x48059000,
4608 .pa_end = 0x480591ff,
4609 .flags = ADDR_TYPE_RT
4614 /* l4_per -> gpio4 */
4615 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4616 .master = &omap44xx_l4_per_hwmod,
4617 .slave = &omap44xx_gpio4_hwmod,
4619 .addr = omap44xx_gpio4_addrs,
4620 .user = OCP_USER_MPU | OCP_USER_SDMA,
4623 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4625 .pa_start = 0x4805b000,
4626 .pa_end = 0x4805b1ff,
4627 .flags = ADDR_TYPE_RT
4632 /* l4_per -> gpio5 */
4633 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4634 .master = &omap44xx_l4_per_hwmod,
4635 .slave = &omap44xx_gpio5_hwmod,
4637 .addr = omap44xx_gpio5_addrs,
4638 .user = OCP_USER_MPU | OCP_USER_SDMA,
4641 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4643 .pa_start = 0x4805d000,
4644 .pa_end = 0x4805d1ff,
4645 .flags = ADDR_TYPE_RT
4650 /* l4_per -> gpio6 */
4651 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4652 .master = &omap44xx_l4_per_hwmod,
4653 .slave = &omap44xx_gpio6_hwmod,
4655 .addr = omap44xx_gpio6_addrs,
4656 .user = OCP_USER_MPU | OCP_USER_SDMA,
4659 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4661 .pa_start = 0x50000000,
4662 .pa_end = 0x500003ff,
4663 .flags = ADDR_TYPE_RT
4668 /* l3_main_2 -> gpmc */
4669 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4670 .master = &omap44xx_l3_main_2_hwmod,
4671 .slave = &omap44xx_gpmc_hwmod,
4673 .addr = omap44xx_gpmc_addrs,
4674 .user = OCP_USER_MPU | OCP_USER_SDMA,
4677 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4679 .pa_start = 0x56000000,
4680 .pa_end = 0x5600ffff,
4681 .flags = ADDR_TYPE_RT
4686 /* l3_main_2 -> gpu */
4687 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4688 .master = &omap44xx_l3_main_2_hwmod,
4689 .slave = &omap44xx_gpu_hwmod,
4691 .addr = omap44xx_gpu_addrs,
4692 .user = OCP_USER_MPU | OCP_USER_SDMA,
4695 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4697 .pa_start = 0x480b2000,
4698 .pa_end = 0x480b201f,
4699 .flags = ADDR_TYPE_RT
4704 /* l4_per -> hdq1w */
4705 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4706 .master = &omap44xx_l4_per_hwmod,
4707 .slave = &omap44xx_hdq1w_hwmod,
4709 .addr = omap44xx_hdq1w_addrs,
4710 .user = OCP_USER_MPU | OCP_USER_SDMA,
4713 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4715 .pa_start = 0x4a058000,
4716 .pa_end = 0x4a05bfff,
4717 .flags = ADDR_TYPE_RT
4723 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4724 .master = &omap44xx_l4_cfg_hwmod,
4725 .slave = &omap44xx_hsi_hwmod,
4727 .addr = omap44xx_hsi_addrs,
4728 .user = OCP_USER_MPU | OCP_USER_SDMA,
4731 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4733 .pa_start = 0x48070000,
4734 .pa_end = 0x480700ff,
4735 .flags = ADDR_TYPE_RT
4740 /* l4_per -> i2c1 */
4741 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4742 .master = &omap44xx_l4_per_hwmod,
4743 .slave = &omap44xx_i2c1_hwmod,
4745 .addr = omap44xx_i2c1_addrs,
4746 .user = OCP_USER_MPU | OCP_USER_SDMA,
4749 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4751 .pa_start = 0x48072000,
4752 .pa_end = 0x480720ff,
4753 .flags = ADDR_TYPE_RT
4758 /* l4_per -> i2c2 */
4759 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4760 .master = &omap44xx_l4_per_hwmod,
4761 .slave = &omap44xx_i2c2_hwmod,
4763 .addr = omap44xx_i2c2_addrs,
4764 .user = OCP_USER_MPU | OCP_USER_SDMA,
4767 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4769 .pa_start = 0x48060000,
4770 .pa_end = 0x480600ff,
4771 .flags = ADDR_TYPE_RT
4776 /* l4_per -> i2c3 */
4777 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4778 .master = &omap44xx_l4_per_hwmod,
4779 .slave = &omap44xx_i2c3_hwmod,
4781 .addr = omap44xx_i2c3_addrs,
4782 .user = OCP_USER_MPU | OCP_USER_SDMA,
4785 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4787 .pa_start = 0x48350000,
4788 .pa_end = 0x483500ff,
4789 .flags = ADDR_TYPE_RT
4794 /* l4_per -> i2c4 */
4795 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4796 .master = &omap44xx_l4_per_hwmod,
4797 .slave = &omap44xx_i2c4_hwmod,
4799 .addr = omap44xx_i2c4_addrs,
4800 .user = OCP_USER_MPU | OCP_USER_SDMA,
4803 /* l3_main_2 -> ipu */
4804 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4805 .master = &omap44xx_l3_main_2_hwmod,
4806 .slave = &omap44xx_ipu_hwmod,
4808 .user = OCP_USER_MPU | OCP_USER_SDMA,
4811 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4813 .pa_start = 0x52000000,
4814 .pa_end = 0x520000ff,
4815 .flags = ADDR_TYPE_RT
4820 /* l3_main_2 -> iss */
4821 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4822 .master = &omap44xx_l3_main_2_hwmod,
4823 .slave = &omap44xx_iss_hwmod,
4825 .addr = omap44xx_iss_addrs,
4826 .user = OCP_USER_MPU | OCP_USER_SDMA,
4830 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4831 .master = &omap44xx_iva_hwmod,
4832 .slave = &omap44xx_sl2if_hwmod,
4833 .clk = "dpll_iva_m5x2_ck",
4834 .user = OCP_USER_IVA,
4837 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4839 .pa_start = 0x5a000000,
4840 .pa_end = 0x5a07ffff,
4841 .flags = ADDR_TYPE_RT
4846 /* l3_main_2 -> iva */
4847 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4848 .master = &omap44xx_l3_main_2_hwmod,
4849 .slave = &omap44xx_iva_hwmod,
4851 .addr = omap44xx_iva_addrs,
4852 .user = OCP_USER_MPU,
4855 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4857 .pa_start = 0x4a31c000,
4858 .pa_end = 0x4a31c07f,
4859 .flags = ADDR_TYPE_RT
4864 /* l4_wkup -> kbd */
4865 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4866 .master = &omap44xx_l4_wkup_hwmod,
4867 .slave = &omap44xx_kbd_hwmod,
4868 .clk = "l4_wkup_clk_mux_ck",
4869 .addr = omap44xx_kbd_addrs,
4870 .user = OCP_USER_MPU | OCP_USER_SDMA,
4873 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4875 .pa_start = 0x4a0f4000,
4876 .pa_end = 0x4a0f41ff,
4877 .flags = ADDR_TYPE_RT
4882 /* l4_cfg -> mailbox */
4883 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4884 .master = &omap44xx_l4_cfg_hwmod,
4885 .slave = &omap44xx_mailbox_hwmod,
4887 .addr = omap44xx_mailbox_addrs,
4888 .user = OCP_USER_MPU | OCP_USER_SDMA,
4891 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4893 .pa_start = 0x40128000,
4894 .pa_end = 0x401283ff,
4895 .flags = ADDR_TYPE_RT
4900 /* l4_abe -> mcasp */
4901 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4902 .master = &omap44xx_l4_abe_hwmod,
4903 .slave = &omap44xx_mcasp_hwmod,
4904 .clk = "ocp_abe_iclk",
4905 .addr = omap44xx_mcasp_addrs,
4906 .user = OCP_USER_MPU,
4909 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4911 .pa_start = 0x49028000,
4912 .pa_end = 0x490283ff,
4913 .flags = ADDR_TYPE_RT
4918 /* l4_abe -> mcasp (dma) */
4919 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4920 .master = &omap44xx_l4_abe_hwmod,
4921 .slave = &omap44xx_mcasp_hwmod,
4922 .clk = "ocp_abe_iclk",
4923 .addr = omap44xx_mcasp_dma_addrs,
4924 .user = OCP_USER_SDMA,
4927 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4930 .pa_start = 0x40122000,
4931 .pa_end = 0x401220ff,
4932 .flags = ADDR_TYPE_RT
4937 /* l4_abe -> mcbsp1 */
4938 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4939 .master = &omap44xx_l4_abe_hwmod,
4940 .slave = &omap44xx_mcbsp1_hwmod,
4941 .clk = "ocp_abe_iclk",
4942 .addr = omap44xx_mcbsp1_addrs,
4943 .user = OCP_USER_MPU,
4946 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4949 .pa_start = 0x49022000,
4950 .pa_end = 0x490220ff,
4951 .flags = ADDR_TYPE_RT
4956 /* l4_abe -> mcbsp1 (dma) */
4957 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4958 .master = &omap44xx_l4_abe_hwmod,
4959 .slave = &omap44xx_mcbsp1_hwmod,
4960 .clk = "ocp_abe_iclk",
4961 .addr = omap44xx_mcbsp1_dma_addrs,
4962 .user = OCP_USER_SDMA,
4965 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4968 .pa_start = 0x40124000,
4969 .pa_end = 0x401240ff,
4970 .flags = ADDR_TYPE_RT
4975 /* l4_abe -> mcbsp2 */
4976 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4977 .master = &omap44xx_l4_abe_hwmod,
4978 .slave = &omap44xx_mcbsp2_hwmod,
4979 .clk = "ocp_abe_iclk",
4980 .addr = omap44xx_mcbsp2_addrs,
4981 .user = OCP_USER_MPU,
4984 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4987 .pa_start = 0x49024000,
4988 .pa_end = 0x490240ff,
4989 .flags = ADDR_TYPE_RT
4994 /* l4_abe -> mcbsp2 (dma) */
4995 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4996 .master = &omap44xx_l4_abe_hwmod,
4997 .slave = &omap44xx_mcbsp2_hwmod,
4998 .clk = "ocp_abe_iclk",
4999 .addr = omap44xx_mcbsp2_dma_addrs,
5000 .user = OCP_USER_SDMA,
5003 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5006 .pa_start = 0x40126000,
5007 .pa_end = 0x401260ff,
5008 .flags = ADDR_TYPE_RT
5013 /* l4_abe -> mcbsp3 */
5014 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5015 .master = &omap44xx_l4_abe_hwmod,
5016 .slave = &omap44xx_mcbsp3_hwmod,
5017 .clk = "ocp_abe_iclk",
5018 .addr = omap44xx_mcbsp3_addrs,
5019 .user = OCP_USER_MPU,
5022 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5025 .pa_start = 0x49026000,
5026 .pa_end = 0x490260ff,
5027 .flags = ADDR_TYPE_RT
5032 /* l4_abe -> mcbsp3 (dma) */
5033 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5034 .master = &omap44xx_l4_abe_hwmod,
5035 .slave = &omap44xx_mcbsp3_hwmod,
5036 .clk = "ocp_abe_iclk",
5037 .addr = omap44xx_mcbsp3_dma_addrs,
5038 .user = OCP_USER_SDMA,
5041 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5043 .pa_start = 0x48096000,
5044 .pa_end = 0x480960ff,
5045 .flags = ADDR_TYPE_RT
5050 /* l4_per -> mcbsp4 */
5051 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5052 .master = &omap44xx_l4_per_hwmod,
5053 .slave = &omap44xx_mcbsp4_hwmod,
5055 .addr = omap44xx_mcbsp4_addrs,
5056 .user = OCP_USER_MPU | OCP_USER_SDMA,
5059 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5061 .pa_start = 0x40132000,
5062 .pa_end = 0x4013207f,
5063 .flags = ADDR_TYPE_RT
5068 /* l4_abe -> mcpdm */
5069 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5070 .master = &omap44xx_l4_abe_hwmod,
5071 .slave = &omap44xx_mcpdm_hwmod,
5072 .clk = "ocp_abe_iclk",
5073 .addr = omap44xx_mcpdm_addrs,
5074 .user = OCP_USER_MPU,
5077 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5079 .pa_start = 0x49032000,
5080 .pa_end = 0x4903207f,
5081 .flags = ADDR_TYPE_RT
5086 /* l4_abe -> mcpdm (dma) */
5087 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5088 .master = &omap44xx_l4_abe_hwmod,
5089 .slave = &omap44xx_mcpdm_hwmod,
5090 .clk = "ocp_abe_iclk",
5091 .addr = omap44xx_mcpdm_dma_addrs,
5092 .user = OCP_USER_SDMA,
5095 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5097 .pa_start = 0x48098000,
5098 .pa_end = 0x480981ff,
5099 .flags = ADDR_TYPE_RT
5104 /* l4_per -> mcspi1 */
5105 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5106 .master = &omap44xx_l4_per_hwmod,
5107 .slave = &omap44xx_mcspi1_hwmod,
5109 .addr = omap44xx_mcspi1_addrs,
5110 .user = OCP_USER_MPU | OCP_USER_SDMA,
5113 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5115 .pa_start = 0x4809a000,
5116 .pa_end = 0x4809a1ff,
5117 .flags = ADDR_TYPE_RT
5122 /* l4_per -> mcspi2 */
5123 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5124 .master = &omap44xx_l4_per_hwmod,
5125 .slave = &omap44xx_mcspi2_hwmod,
5127 .addr = omap44xx_mcspi2_addrs,
5128 .user = OCP_USER_MPU | OCP_USER_SDMA,
5131 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5133 .pa_start = 0x480b8000,
5134 .pa_end = 0x480b81ff,
5135 .flags = ADDR_TYPE_RT
5140 /* l4_per -> mcspi3 */
5141 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5142 .master = &omap44xx_l4_per_hwmod,
5143 .slave = &omap44xx_mcspi3_hwmod,
5145 .addr = omap44xx_mcspi3_addrs,
5146 .user = OCP_USER_MPU | OCP_USER_SDMA,
5149 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5151 .pa_start = 0x480ba000,
5152 .pa_end = 0x480ba1ff,
5153 .flags = ADDR_TYPE_RT
5158 /* l4_per -> mcspi4 */
5159 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5160 .master = &omap44xx_l4_per_hwmod,
5161 .slave = &omap44xx_mcspi4_hwmod,
5163 .addr = omap44xx_mcspi4_addrs,
5164 .user = OCP_USER_MPU | OCP_USER_SDMA,
5167 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5169 .pa_start = 0x4809c000,
5170 .pa_end = 0x4809c3ff,
5171 .flags = ADDR_TYPE_RT
5176 /* l4_per -> mmc1 */
5177 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5178 .master = &omap44xx_l4_per_hwmod,
5179 .slave = &omap44xx_mmc1_hwmod,
5181 .addr = omap44xx_mmc1_addrs,
5182 .user = OCP_USER_MPU | OCP_USER_SDMA,
5185 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5187 .pa_start = 0x480b4000,
5188 .pa_end = 0x480b43ff,
5189 .flags = ADDR_TYPE_RT
5194 /* l4_per -> mmc2 */
5195 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5196 .master = &omap44xx_l4_per_hwmod,
5197 .slave = &omap44xx_mmc2_hwmod,
5199 .addr = omap44xx_mmc2_addrs,
5200 .user = OCP_USER_MPU | OCP_USER_SDMA,
5203 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5205 .pa_start = 0x480ad000,
5206 .pa_end = 0x480ad3ff,
5207 .flags = ADDR_TYPE_RT
5212 /* l4_per -> mmc3 */
5213 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5214 .master = &omap44xx_l4_per_hwmod,
5215 .slave = &omap44xx_mmc3_hwmod,
5217 .addr = omap44xx_mmc3_addrs,
5218 .user = OCP_USER_MPU | OCP_USER_SDMA,
5221 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5223 .pa_start = 0x480d1000,
5224 .pa_end = 0x480d13ff,
5225 .flags = ADDR_TYPE_RT
5230 /* l4_per -> mmc4 */
5231 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5232 .master = &omap44xx_l4_per_hwmod,
5233 .slave = &omap44xx_mmc4_hwmod,
5235 .addr = omap44xx_mmc4_addrs,
5236 .user = OCP_USER_MPU | OCP_USER_SDMA,
5239 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5241 .pa_start = 0x480d5000,
5242 .pa_end = 0x480d53ff,
5243 .flags = ADDR_TYPE_RT
5248 /* l4_per -> mmc5 */
5249 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5250 .master = &omap44xx_l4_per_hwmod,
5251 .slave = &omap44xx_mmc5_hwmod,
5253 .addr = omap44xx_mmc5_addrs,
5254 .user = OCP_USER_MPU | OCP_USER_SDMA,
5257 /* l3_main_2 -> ocmc_ram */
5258 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5259 .master = &omap44xx_l3_main_2_hwmod,
5260 .slave = &omap44xx_ocmc_ram_hwmod,
5262 .user = OCP_USER_MPU | OCP_USER_SDMA,
5265 /* l4_cfg -> ocp2scp_usb_phy */
5266 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5267 .master = &omap44xx_l4_cfg_hwmod,
5268 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5270 .user = OCP_USER_MPU | OCP_USER_SDMA,
5273 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5275 .pa_start = 0x48243000,
5276 .pa_end = 0x48243fff,
5277 .flags = ADDR_TYPE_RT
5282 /* mpu_private -> prcm_mpu */
5283 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5284 .master = &omap44xx_mpu_private_hwmod,
5285 .slave = &omap44xx_prcm_mpu_hwmod,
5287 .addr = omap44xx_prcm_mpu_addrs,
5288 .user = OCP_USER_MPU | OCP_USER_SDMA,
5291 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5293 .pa_start = 0x4a004000,
5294 .pa_end = 0x4a004fff,
5295 .flags = ADDR_TYPE_RT
5300 /* l4_wkup -> cm_core_aon */
5301 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5302 .master = &omap44xx_l4_wkup_hwmod,
5303 .slave = &omap44xx_cm_core_aon_hwmod,
5304 .clk = "l4_wkup_clk_mux_ck",
5305 .addr = omap44xx_cm_core_aon_addrs,
5306 .user = OCP_USER_MPU | OCP_USER_SDMA,
5309 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5311 .pa_start = 0x4a008000,
5312 .pa_end = 0x4a009fff,
5313 .flags = ADDR_TYPE_RT
5318 /* l4_cfg -> cm_core */
5319 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5320 .master = &omap44xx_l4_cfg_hwmod,
5321 .slave = &omap44xx_cm_core_hwmod,
5323 .addr = omap44xx_cm_core_addrs,
5324 .user = OCP_USER_MPU | OCP_USER_SDMA,
5327 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5329 .pa_start = 0x4a306000,
5330 .pa_end = 0x4a307fff,
5331 .flags = ADDR_TYPE_RT
5336 /* l4_wkup -> prm */
5337 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5338 .master = &omap44xx_l4_wkup_hwmod,
5339 .slave = &omap44xx_prm_hwmod,
5340 .clk = "l4_wkup_clk_mux_ck",
5341 .addr = omap44xx_prm_addrs,
5342 .user = OCP_USER_MPU | OCP_USER_SDMA,
5345 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5347 .pa_start = 0x4a30a000,
5348 .pa_end = 0x4a30a7ff,
5349 .flags = ADDR_TYPE_RT
5354 /* l4_wkup -> scrm */
5355 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5356 .master = &omap44xx_l4_wkup_hwmod,
5357 .slave = &omap44xx_scrm_hwmod,
5358 .clk = "l4_wkup_clk_mux_ck",
5359 .addr = omap44xx_scrm_addrs,
5360 .user = OCP_USER_MPU | OCP_USER_SDMA,
5363 /* l3_main_2 -> sl2if */
5364 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5365 .master = &omap44xx_l3_main_2_hwmod,
5366 .slave = &omap44xx_sl2if_hwmod,
5368 .user = OCP_USER_MPU | OCP_USER_SDMA,
5371 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5373 .pa_start = 0x4012c000,
5374 .pa_end = 0x4012c3ff,
5375 .flags = ADDR_TYPE_RT
5380 /* l4_abe -> slimbus1 */
5381 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5382 .master = &omap44xx_l4_abe_hwmod,
5383 .slave = &omap44xx_slimbus1_hwmod,
5384 .clk = "ocp_abe_iclk",
5385 .addr = omap44xx_slimbus1_addrs,
5386 .user = OCP_USER_MPU,
5389 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5391 .pa_start = 0x4902c000,
5392 .pa_end = 0x4902c3ff,
5393 .flags = ADDR_TYPE_RT
5398 /* l4_abe -> slimbus1 (dma) */
5399 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5400 .master = &omap44xx_l4_abe_hwmod,
5401 .slave = &omap44xx_slimbus1_hwmod,
5402 .clk = "ocp_abe_iclk",
5403 .addr = omap44xx_slimbus1_dma_addrs,
5404 .user = OCP_USER_SDMA,
5407 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5409 .pa_start = 0x48076000,
5410 .pa_end = 0x480763ff,
5411 .flags = ADDR_TYPE_RT
5416 /* l4_per -> slimbus2 */
5417 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5418 .master = &omap44xx_l4_per_hwmod,
5419 .slave = &omap44xx_slimbus2_hwmod,
5421 .addr = omap44xx_slimbus2_addrs,
5422 .user = OCP_USER_MPU | OCP_USER_SDMA,
5425 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5427 .pa_start = 0x4a0dd000,
5428 .pa_end = 0x4a0dd03f,
5429 .flags = ADDR_TYPE_RT
5434 /* l4_cfg -> smartreflex_core */
5435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5436 .master = &omap44xx_l4_cfg_hwmod,
5437 .slave = &omap44xx_smartreflex_core_hwmod,
5439 .addr = omap44xx_smartreflex_core_addrs,
5440 .user = OCP_USER_MPU | OCP_USER_SDMA,
5443 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5445 .pa_start = 0x4a0db000,
5446 .pa_end = 0x4a0db03f,
5447 .flags = ADDR_TYPE_RT
5452 /* l4_cfg -> smartreflex_iva */
5453 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5454 .master = &omap44xx_l4_cfg_hwmod,
5455 .slave = &omap44xx_smartreflex_iva_hwmod,
5457 .addr = omap44xx_smartreflex_iva_addrs,
5458 .user = OCP_USER_MPU | OCP_USER_SDMA,
5461 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5463 .pa_start = 0x4a0d9000,
5464 .pa_end = 0x4a0d903f,
5465 .flags = ADDR_TYPE_RT
5470 /* l4_cfg -> smartreflex_mpu */
5471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5472 .master = &omap44xx_l4_cfg_hwmod,
5473 .slave = &omap44xx_smartreflex_mpu_hwmod,
5475 .addr = omap44xx_smartreflex_mpu_addrs,
5476 .user = OCP_USER_MPU | OCP_USER_SDMA,
5479 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5481 .pa_start = 0x4a0f6000,
5482 .pa_end = 0x4a0f6fff,
5483 .flags = ADDR_TYPE_RT
5488 /* l4_cfg -> spinlock */
5489 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5490 .master = &omap44xx_l4_cfg_hwmod,
5491 .slave = &omap44xx_spinlock_hwmod,
5493 .addr = omap44xx_spinlock_addrs,
5494 .user = OCP_USER_MPU | OCP_USER_SDMA,
5497 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5499 .pa_start = 0x4a318000,
5500 .pa_end = 0x4a31807f,
5501 .flags = ADDR_TYPE_RT
5506 /* l4_wkup -> timer1 */
5507 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5508 .master = &omap44xx_l4_wkup_hwmod,
5509 .slave = &omap44xx_timer1_hwmod,
5510 .clk = "l4_wkup_clk_mux_ck",
5511 .addr = omap44xx_timer1_addrs,
5512 .user = OCP_USER_MPU | OCP_USER_SDMA,
5515 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5517 .pa_start = 0x48032000,
5518 .pa_end = 0x4803207f,
5519 .flags = ADDR_TYPE_RT
5524 /* l4_per -> timer2 */
5525 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5526 .master = &omap44xx_l4_per_hwmod,
5527 .slave = &omap44xx_timer2_hwmod,
5529 .addr = omap44xx_timer2_addrs,
5530 .user = OCP_USER_MPU | OCP_USER_SDMA,
5533 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5535 .pa_start = 0x48034000,
5536 .pa_end = 0x4803407f,
5537 .flags = ADDR_TYPE_RT
5542 /* l4_per -> timer3 */
5543 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5544 .master = &omap44xx_l4_per_hwmod,
5545 .slave = &omap44xx_timer3_hwmod,
5547 .addr = omap44xx_timer3_addrs,
5548 .user = OCP_USER_MPU | OCP_USER_SDMA,
5551 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5553 .pa_start = 0x48036000,
5554 .pa_end = 0x4803607f,
5555 .flags = ADDR_TYPE_RT
5560 /* l4_per -> timer4 */
5561 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5562 .master = &omap44xx_l4_per_hwmod,
5563 .slave = &omap44xx_timer4_hwmod,
5565 .addr = omap44xx_timer4_addrs,
5566 .user = OCP_USER_MPU | OCP_USER_SDMA,
5569 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5571 .pa_start = 0x40138000,
5572 .pa_end = 0x4013807f,
5573 .flags = ADDR_TYPE_RT
5578 /* l4_abe -> timer5 */
5579 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5580 .master = &omap44xx_l4_abe_hwmod,
5581 .slave = &omap44xx_timer5_hwmod,
5582 .clk = "ocp_abe_iclk",
5583 .addr = omap44xx_timer5_addrs,
5584 .user = OCP_USER_MPU,
5587 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5589 .pa_start = 0x49038000,
5590 .pa_end = 0x4903807f,
5591 .flags = ADDR_TYPE_RT
5596 /* l4_abe -> timer5 (dma) */
5597 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5598 .master = &omap44xx_l4_abe_hwmod,
5599 .slave = &omap44xx_timer5_hwmod,
5600 .clk = "ocp_abe_iclk",
5601 .addr = omap44xx_timer5_dma_addrs,
5602 .user = OCP_USER_SDMA,
5605 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5607 .pa_start = 0x4013a000,
5608 .pa_end = 0x4013a07f,
5609 .flags = ADDR_TYPE_RT
5614 /* l4_abe -> timer6 */
5615 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5616 .master = &omap44xx_l4_abe_hwmod,
5617 .slave = &omap44xx_timer6_hwmod,
5618 .clk = "ocp_abe_iclk",
5619 .addr = omap44xx_timer6_addrs,
5620 .user = OCP_USER_MPU,
5623 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5625 .pa_start = 0x4903a000,
5626 .pa_end = 0x4903a07f,
5627 .flags = ADDR_TYPE_RT
5632 /* l4_abe -> timer6 (dma) */
5633 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5634 .master = &omap44xx_l4_abe_hwmod,
5635 .slave = &omap44xx_timer6_hwmod,
5636 .clk = "ocp_abe_iclk",
5637 .addr = omap44xx_timer6_dma_addrs,
5638 .user = OCP_USER_SDMA,
5641 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5643 .pa_start = 0x4013c000,
5644 .pa_end = 0x4013c07f,
5645 .flags = ADDR_TYPE_RT
5650 /* l4_abe -> timer7 */
5651 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5652 .master = &omap44xx_l4_abe_hwmod,
5653 .slave = &omap44xx_timer7_hwmod,
5654 .clk = "ocp_abe_iclk",
5655 .addr = omap44xx_timer7_addrs,
5656 .user = OCP_USER_MPU,
5659 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5661 .pa_start = 0x4903c000,
5662 .pa_end = 0x4903c07f,
5663 .flags = ADDR_TYPE_RT
5668 /* l4_abe -> timer7 (dma) */
5669 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5670 .master = &omap44xx_l4_abe_hwmod,
5671 .slave = &omap44xx_timer7_hwmod,
5672 .clk = "ocp_abe_iclk",
5673 .addr = omap44xx_timer7_dma_addrs,
5674 .user = OCP_USER_SDMA,
5677 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5679 .pa_start = 0x4013e000,
5680 .pa_end = 0x4013e07f,
5681 .flags = ADDR_TYPE_RT
5686 /* l4_abe -> timer8 */
5687 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5688 .master = &omap44xx_l4_abe_hwmod,
5689 .slave = &omap44xx_timer8_hwmod,
5690 .clk = "ocp_abe_iclk",
5691 .addr = omap44xx_timer8_addrs,
5692 .user = OCP_USER_MPU,
5695 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5697 .pa_start = 0x4903e000,
5698 .pa_end = 0x4903e07f,
5699 .flags = ADDR_TYPE_RT
5704 /* l4_abe -> timer8 (dma) */
5705 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5706 .master = &omap44xx_l4_abe_hwmod,
5707 .slave = &omap44xx_timer8_hwmod,
5708 .clk = "ocp_abe_iclk",
5709 .addr = omap44xx_timer8_dma_addrs,
5710 .user = OCP_USER_SDMA,
5713 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5715 .pa_start = 0x4803e000,
5716 .pa_end = 0x4803e07f,
5717 .flags = ADDR_TYPE_RT
5722 /* l4_per -> timer9 */
5723 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5724 .master = &omap44xx_l4_per_hwmod,
5725 .slave = &omap44xx_timer9_hwmod,
5727 .addr = omap44xx_timer9_addrs,
5728 .user = OCP_USER_MPU | OCP_USER_SDMA,
5731 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5733 .pa_start = 0x48086000,
5734 .pa_end = 0x4808607f,
5735 .flags = ADDR_TYPE_RT
5740 /* l4_per -> timer10 */
5741 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5742 .master = &omap44xx_l4_per_hwmod,
5743 .slave = &omap44xx_timer10_hwmod,
5745 .addr = omap44xx_timer10_addrs,
5746 .user = OCP_USER_MPU | OCP_USER_SDMA,
5749 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5751 .pa_start = 0x48088000,
5752 .pa_end = 0x4808807f,
5753 .flags = ADDR_TYPE_RT
5758 /* l4_per -> timer11 */
5759 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5760 .master = &omap44xx_l4_per_hwmod,
5761 .slave = &omap44xx_timer11_hwmod,
5763 .addr = omap44xx_timer11_addrs,
5764 .user = OCP_USER_MPU | OCP_USER_SDMA,
5767 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5769 .pa_start = 0x4806a000,
5770 .pa_end = 0x4806a0ff,
5771 .flags = ADDR_TYPE_RT
5776 /* l4_per -> uart1 */
5777 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5778 .master = &omap44xx_l4_per_hwmod,
5779 .slave = &omap44xx_uart1_hwmod,
5781 .addr = omap44xx_uart1_addrs,
5782 .user = OCP_USER_MPU | OCP_USER_SDMA,
5785 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5787 .pa_start = 0x4806c000,
5788 .pa_end = 0x4806c0ff,
5789 .flags = ADDR_TYPE_RT
5794 /* l4_per -> uart2 */
5795 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5796 .master = &omap44xx_l4_per_hwmod,
5797 .slave = &omap44xx_uart2_hwmod,
5799 .addr = omap44xx_uart2_addrs,
5800 .user = OCP_USER_MPU | OCP_USER_SDMA,
5803 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5805 .pa_start = 0x48020000,
5806 .pa_end = 0x480200ff,
5807 .flags = ADDR_TYPE_RT
5812 /* l4_per -> uart3 */
5813 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5814 .master = &omap44xx_l4_per_hwmod,
5815 .slave = &omap44xx_uart3_hwmod,
5817 .addr = omap44xx_uart3_addrs,
5818 .user = OCP_USER_MPU | OCP_USER_SDMA,
5821 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5823 .pa_start = 0x4806e000,
5824 .pa_end = 0x4806e0ff,
5825 .flags = ADDR_TYPE_RT
5830 /* l4_per -> uart4 */
5831 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5832 .master = &omap44xx_l4_per_hwmod,
5833 .slave = &omap44xx_uart4_hwmod,
5835 .addr = omap44xx_uart4_addrs,
5836 .user = OCP_USER_MPU | OCP_USER_SDMA,
5839 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5841 .pa_start = 0x4a0a9000,
5842 .pa_end = 0x4a0a93ff,
5843 .flags = ADDR_TYPE_RT
5848 /* l4_cfg -> usb_host_fs */
5849 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5850 .master = &omap44xx_l4_cfg_hwmod,
5851 .slave = &omap44xx_usb_host_fs_hwmod,
5853 .addr = omap44xx_usb_host_fs_addrs,
5854 .user = OCP_USER_MPU | OCP_USER_SDMA,
5857 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5860 .pa_start = 0x4a064000,
5861 .pa_end = 0x4a0647ff,
5862 .flags = ADDR_TYPE_RT
5866 .pa_start = 0x4a064800,
5867 .pa_end = 0x4a064bff,
5871 .pa_start = 0x4a064c00,
5872 .pa_end = 0x4a064fff,
5877 /* l4_cfg -> usb_host_hs */
5878 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5879 .master = &omap44xx_l4_cfg_hwmod,
5880 .slave = &omap44xx_usb_host_hs_hwmod,
5882 .addr = omap44xx_usb_host_hs_addrs,
5883 .user = OCP_USER_MPU | OCP_USER_SDMA,
5886 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5888 .pa_start = 0x4a0ab000,
5889 .pa_end = 0x4a0ab003,
5890 .flags = ADDR_TYPE_RT
5893 /* XXX: Remove this once control module driver is in place */
5894 .pa_start = 0x4a00233c,
5895 .pa_end = 0x4a00233f,
5896 .flags = ADDR_TYPE_RT
5901 /* l4_cfg -> usb_otg_hs */
5902 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5903 .master = &omap44xx_l4_cfg_hwmod,
5904 .slave = &omap44xx_usb_otg_hs_hwmod,
5906 .addr = omap44xx_usb_otg_hs_addrs,
5907 .user = OCP_USER_MPU | OCP_USER_SDMA,
5910 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5913 .pa_start = 0x4a062000,
5914 .pa_end = 0x4a063fff,
5915 .flags = ADDR_TYPE_RT
5920 /* l4_cfg -> usb_tll_hs */
5921 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5922 .master = &omap44xx_l4_cfg_hwmod,
5923 .slave = &omap44xx_usb_tll_hs_hwmod,
5925 .addr = omap44xx_usb_tll_hs_addrs,
5926 .user = OCP_USER_MPU | OCP_USER_SDMA,
5929 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5931 .pa_start = 0x4a314000,
5932 .pa_end = 0x4a31407f,
5933 .flags = ADDR_TYPE_RT
5938 /* l4_wkup -> wd_timer2 */
5939 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5940 .master = &omap44xx_l4_wkup_hwmod,
5941 .slave = &omap44xx_wd_timer2_hwmod,
5942 .clk = "l4_wkup_clk_mux_ck",
5943 .addr = omap44xx_wd_timer2_addrs,
5944 .user = OCP_USER_MPU | OCP_USER_SDMA,
5947 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5949 .pa_start = 0x40130000,
5950 .pa_end = 0x4013007f,
5951 .flags = ADDR_TYPE_RT
5956 /* l4_abe -> wd_timer3 */
5957 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5958 .master = &omap44xx_l4_abe_hwmod,
5959 .slave = &omap44xx_wd_timer3_hwmod,
5960 .clk = "ocp_abe_iclk",
5961 .addr = omap44xx_wd_timer3_addrs,
5962 .user = OCP_USER_MPU,
5965 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5967 .pa_start = 0x49030000,
5968 .pa_end = 0x4903007f,
5969 .flags = ADDR_TYPE_RT
5974 /* l4_abe -> wd_timer3 (dma) */
5975 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5976 .master = &omap44xx_l4_abe_hwmod,
5977 .slave = &omap44xx_wd_timer3_hwmod,
5978 .clk = "ocp_abe_iclk",
5979 .addr = omap44xx_wd_timer3_dma_addrs,
5980 .user = OCP_USER_SDMA,
5983 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5984 &omap44xx_c2c__c2c_target_fw,
5985 &omap44xx_l4_cfg__c2c_target_fw,
5986 &omap44xx_l3_main_1__dmm,
5988 &omap44xx_c2c__emif_fw,
5989 &omap44xx_dmm__emif_fw,
5990 &omap44xx_l4_cfg__emif_fw,
5991 &omap44xx_iva__l3_instr,
5992 &omap44xx_l3_main_3__l3_instr,
5993 &omap44xx_ocp_wp_noc__l3_instr,
5994 &omap44xx_dsp__l3_main_1,
5995 &omap44xx_dss__l3_main_1,
5996 &omap44xx_l3_main_2__l3_main_1,
5997 &omap44xx_l4_cfg__l3_main_1,
5998 &omap44xx_mmc1__l3_main_1,
5999 &omap44xx_mmc2__l3_main_1,
6000 &omap44xx_mpu__l3_main_1,
6001 &omap44xx_c2c_target_fw__l3_main_2,
6002 &omap44xx_debugss__l3_main_2,
6003 &omap44xx_dma_system__l3_main_2,
6004 &omap44xx_fdif__l3_main_2,
6005 &omap44xx_gpu__l3_main_2,
6006 &omap44xx_hsi__l3_main_2,
6007 &omap44xx_ipu__l3_main_2,
6008 &omap44xx_iss__l3_main_2,
6009 &omap44xx_iva__l3_main_2,
6010 &omap44xx_l3_main_1__l3_main_2,
6011 &omap44xx_l4_cfg__l3_main_2,
6012 /* &omap44xx_usb_host_fs__l3_main_2, */
6013 &omap44xx_usb_host_hs__l3_main_2,
6014 &omap44xx_usb_otg_hs__l3_main_2,
6015 &omap44xx_l3_main_1__l3_main_3,
6016 &omap44xx_l3_main_2__l3_main_3,
6017 &omap44xx_l4_cfg__l3_main_3,
6018 /* &omap44xx_aess__l4_abe, */
6019 &omap44xx_dsp__l4_abe,
6020 &omap44xx_l3_main_1__l4_abe,
6021 &omap44xx_mpu__l4_abe,
6022 &omap44xx_l3_main_1__l4_cfg,
6023 &omap44xx_l3_main_2__l4_per,
6024 &omap44xx_l4_cfg__l4_wkup,
6025 &omap44xx_mpu__mpu_private,
6026 &omap44xx_l4_cfg__ocp_wp_noc,
6027 /* &omap44xx_l4_abe__aess, */
6028 /* &omap44xx_l4_abe__aess_dma, */
6029 &omap44xx_l3_main_2__c2c,
6030 &omap44xx_l4_wkup__counter_32k,
6031 &omap44xx_l4_cfg__ctrl_module_core,
6032 &omap44xx_l4_cfg__ctrl_module_pad_core,
6033 &omap44xx_l4_wkup__ctrl_module_wkup,
6034 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6035 &omap44xx_l3_instr__debugss,
6036 &omap44xx_l4_cfg__dma_system,
6037 &omap44xx_l4_abe__dmic,
6038 &omap44xx_l4_abe__dmic_dma,
6040 /* &omap44xx_dsp__sl2if, */
6041 &omap44xx_l4_cfg__dsp,
6042 &omap44xx_l3_main_2__dss,
6043 &omap44xx_l4_per__dss,
6044 &omap44xx_l3_main_2__dss_dispc,
6045 &omap44xx_l4_per__dss_dispc,
6046 &omap44xx_l3_main_2__dss_dsi1,
6047 &omap44xx_l4_per__dss_dsi1,
6048 &omap44xx_l3_main_2__dss_dsi2,
6049 &omap44xx_l4_per__dss_dsi2,
6050 &omap44xx_l3_main_2__dss_hdmi,
6051 &omap44xx_l4_per__dss_hdmi,
6052 &omap44xx_l3_main_2__dss_rfbi,
6053 &omap44xx_l4_per__dss_rfbi,
6054 &omap44xx_l3_main_2__dss_venc,
6055 &omap44xx_l4_per__dss_venc,
6056 &omap44xx_l4_per__elm,
6057 &omap44xx_emif_fw__emif1,
6058 &omap44xx_emif_fw__emif2,
6059 &omap44xx_l4_cfg__fdif,
6060 &omap44xx_l4_wkup__gpio1,
6061 &omap44xx_l4_per__gpio2,
6062 &omap44xx_l4_per__gpio3,
6063 &omap44xx_l4_per__gpio4,
6064 &omap44xx_l4_per__gpio5,
6065 &omap44xx_l4_per__gpio6,
6066 &omap44xx_l3_main_2__gpmc,
6067 &omap44xx_l3_main_2__gpu,
6068 &omap44xx_l4_per__hdq1w,
6069 &omap44xx_l4_cfg__hsi,
6070 &omap44xx_l4_per__i2c1,
6071 &omap44xx_l4_per__i2c2,
6072 &omap44xx_l4_per__i2c3,
6073 &omap44xx_l4_per__i2c4,
6074 &omap44xx_l3_main_2__ipu,
6075 &omap44xx_l3_main_2__iss,
6076 /* &omap44xx_iva__sl2if, */
6077 &omap44xx_l3_main_2__iva,
6078 &omap44xx_l4_wkup__kbd,
6079 &omap44xx_l4_cfg__mailbox,
6080 &omap44xx_l4_abe__mcasp,
6081 &omap44xx_l4_abe__mcasp_dma,
6082 &omap44xx_l4_abe__mcbsp1,
6083 &omap44xx_l4_abe__mcbsp1_dma,
6084 &omap44xx_l4_abe__mcbsp2,
6085 &omap44xx_l4_abe__mcbsp2_dma,
6086 &omap44xx_l4_abe__mcbsp3,
6087 &omap44xx_l4_abe__mcbsp3_dma,
6088 &omap44xx_l4_per__mcbsp4,
6089 &omap44xx_l4_abe__mcpdm,
6090 &omap44xx_l4_abe__mcpdm_dma,
6091 &omap44xx_l4_per__mcspi1,
6092 &omap44xx_l4_per__mcspi2,
6093 &omap44xx_l4_per__mcspi3,
6094 &omap44xx_l4_per__mcspi4,
6095 &omap44xx_l4_per__mmc1,
6096 &omap44xx_l4_per__mmc2,
6097 &omap44xx_l4_per__mmc3,
6098 &omap44xx_l4_per__mmc4,
6099 &omap44xx_l4_per__mmc5,
6100 &omap44xx_l3_main_2__ocmc_ram,
6101 &omap44xx_l4_cfg__ocp2scp_usb_phy,
6102 &omap44xx_mpu_private__prcm_mpu,
6103 &omap44xx_l4_wkup__cm_core_aon,
6104 &omap44xx_l4_cfg__cm_core,
6105 &omap44xx_l4_wkup__prm,
6106 &omap44xx_l4_wkup__scrm,
6107 /* &omap44xx_l3_main_2__sl2if, */
6108 &omap44xx_l4_abe__slimbus1,
6109 &omap44xx_l4_abe__slimbus1_dma,
6110 &omap44xx_l4_per__slimbus2,
6111 &omap44xx_l4_cfg__smartreflex_core,
6112 &omap44xx_l4_cfg__smartreflex_iva,
6113 &omap44xx_l4_cfg__smartreflex_mpu,
6114 &omap44xx_l4_cfg__spinlock,
6115 &omap44xx_l4_wkup__timer1,
6116 &omap44xx_l4_per__timer2,
6117 &omap44xx_l4_per__timer3,
6118 &omap44xx_l4_per__timer4,
6119 &omap44xx_l4_abe__timer5,
6120 &omap44xx_l4_abe__timer5_dma,
6121 &omap44xx_l4_abe__timer6,
6122 &omap44xx_l4_abe__timer6_dma,
6123 &omap44xx_l4_abe__timer7,
6124 &omap44xx_l4_abe__timer7_dma,
6125 &omap44xx_l4_abe__timer8,
6126 &omap44xx_l4_abe__timer8_dma,
6127 &omap44xx_l4_per__timer9,
6128 &omap44xx_l4_per__timer10,
6129 &omap44xx_l4_per__timer11,
6130 &omap44xx_l4_per__uart1,
6131 &omap44xx_l4_per__uart2,
6132 &omap44xx_l4_per__uart3,
6133 &omap44xx_l4_per__uart4,
6134 /* &omap44xx_l4_cfg__usb_host_fs, */
6135 &omap44xx_l4_cfg__usb_host_hs,
6136 &omap44xx_l4_cfg__usb_otg_hs,
6137 &omap44xx_l4_cfg__usb_tll_hs,
6138 &omap44xx_l4_wkup__wd_timer2,
6139 &omap44xx_l4_abe__wd_timer3,
6140 &omap44xx_l4_abe__wd_timer3_dma,
6144 int __init omap44xx_hwmod_init(void)
6147 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);