arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25
  26 #include <plat/omap_hwmod.h>
  27 #include <plat/i2c.h>
  28 #include <plat/dma.h>
  29 #include <linux/platform_data/spi-omap2-mcspi.h>
  30 #include <linux/platform_data/asoc-ti-mcbsp.h>
  31 #include <plat/mmc.h>
  32 #include <plat/dmtimer.h>
  33 #include <plat/common.h>
  34 #include <plat/iommu.h>
  35
  36 #include "omap_hwmod_common_data.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 208                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 209                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 210                 },
 211         },
 212 };
 213
 214 /* l4_cfg */
 215 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 216         .name           = "l4_cfg",
 217         .class          = &omap44xx_l4_hwmod_class,
 218         .clkdm_name     = "l4_cfg_clkdm",
 219         .prcm = {
 220                 .omap4 = {
 221                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 222                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 223                 },
 224         },
 225 };
 226
 227 /* l4_per */
 228 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 229         .name           = "l4_per",
 230         .class          = &omap44xx_l4_hwmod_class,
 231         .clkdm_name     = "l4_per_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 236                 },
 237         },
 238 };
 239
 240 /* l4_wkup */
 241 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 242         .name           = "l4_wkup",
 243         .class          = &omap44xx_l4_hwmod_class,
 244         .clkdm_name     = "l4_wkup_clkdm",
 245         .prcm = {
 246                 .omap4 = {
 247                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 248                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 249                 },
 250         },
 251 };
 252
 253 /*
 254  * 'mpu_bus' class
 255  * instance(s): mpu_private
 256  */
 257 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 258         .name   = "mpu_bus",
 259 };
 260
 261 /* mpu_private */
 262 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 263         .name           = "mpu_private",
 264         .class          = &omap44xx_mpu_bus_hwmod_class,
 265         .clkdm_name     = "mpuss_clkdm",
 266         .prcm = {
 267                 .omap4 = {
 268                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 269                 },
 270         },
 271 };
 272
 273 /*
 274  * 'ocp_wp_noc' class
 275  * instance(s): ocp_wp_noc
 276  */
 277 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 278         .name   = "ocp_wp_noc",
 279 };
 280
 281 /* ocp_wp_noc */
 282 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 283         .name           = "ocp_wp_noc",
 284         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 285         .clkdm_name     = "l3_instr_clkdm",
 286         .prcm = {
 287                 .omap4 = {
 288                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 289                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 290                         .modulemode   = MODULEMODE_HWCTRL,
 291                 },
 292         },
 293 };
 294
 295 /*
 296  * Modules omap_hwmod structures
 297  *
 298  * The following IPs are excluded for the moment because:
 299  * - They do not need an explicit SW control using omap_hwmod API.
 300  * - They still need to be validated with the driver
 301  *   properly adapted to omap_hwmod / omap_device
 302  *
 303  * usim
 304  */
 305
 306 /*
 307  * 'aess' class
 308  * audio engine sub system
 309  */
 310
 311 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 312         .rev_offs       = 0x0000,
 313         .sysc_offs      = 0x0010,
 314         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 315         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 316                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 317                            MSTANDBY_SMART_WKUP),
 318         .sysc_fields    = &omap_hwmod_sysc_type2,
 319 };
 320
 321 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 322         .name   = "aess",
 323         .sysc   = &omap44xx_aess_sysc,
 324 };
 325
 326 /* aess */
 327 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 328         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 329         { .irq = -1 }
 330 };
 331
 332 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 333         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 334         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 341         { .dma_req = -1 }
 342 };
 343
 344 static struct omap_hwmod omap44xx_aess_hwmod = {
 345         .name           = "aess",
 346         .class          = &omap44xx_aess_hwmod_class,
 347         .clkdm_name     = "abe_clkdm",
 348         .mpu_irqs       = omap44xx_aess_irqs,
 349         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 350         .main_clk       = "aess_fck",
 351         .prcm = {
 352                 .omap4 = {
 353                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 354                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 355                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 356                         .modulemode   = MODULEMODE_SWCTRL,
 357                 },
 358         },
 359 };
 360
 361 /*
 362  * 'c2c' class
 363  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 364  * soc
 365  */
 366
 367 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 368         .name   = "c2c",
 369 };
 370
 371 /* c2c */
 372 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 373         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 374         { .irq = -1 }
 375 };
 376
 377 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 378         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 379         { .dma_req = -1 }
 380 };
 381
 382 static struct omap_hwmod omap44xx_c2c_hwmod = {
 383         .name           = "c2c",
 384         .class          = &omap44xx_c2c_hwmod_class,
 385         .clkdm_name     = "d2d_clkdm",
 386         .mpu_irqs       = omap44xx_c2c_irqs,
 387         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 388         .prcm = {
 389                 .omap4 = {
 390                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 391                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 392                 },
 393         },
 394 };
 395
 396 /*
 397  * 'counter' class
 398  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 399  */
 400
 401 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 402         .rev_offs       = 0x0000,
 403         .sysc_offs      = 0x0004,
 404         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 405         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 406         .sysc_fields    = &omap_hwmod_sysc_type1,
 407 };
 408
 409 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 410         .name   = "counter",
 411         .sysc   = &omap44xx_counter_sysc,
 412 };
 413
 414 /* counter_32k */
 415 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 416         .name           = "counter_32k",
 417         .class          = &omap44xx_counter_hwmod_class,
 418         .clkdm_name     = "l4_wkup_clkdm",
 419         .flags          = HWMOD_SWSUP_SIDLE,
 420         .main_clk       = "sys_32k_ck",
 421         .prcm = {
 422                 .omap4 = {
 423                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 424                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 425                 },
 426         },
 427 };
 428
 429 /*
 430  * 'ctrl_module' class
 431  * attila core control module + core pad control module + wkup pad control
 432  * module + attila wkup control module
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 439         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 440                            SIDLE_SMART_WKUP),
 441         .sysc_fields    = &omap_hwmod_sysc_type2,
 442 };
 443
 444 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 445         .name   = "ctrl_module",
 446         .sysc   = &omap44xx_ctrl_module_sysc,
 447 };
 448
 449 /* ctrl_module_core */
 450 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 451         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 452         { .irq = -1 }
 453 };
 454
 455 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 456         .name           = "ctrl_module_core",
 457         .class          = &omap44xx_ctrl_module_hwmod_class,
 458         .clkdm_name     = "l4_cfg_clkdm",
 459         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 460         .prcm = {
 461                 .omap4 = {
 462                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 463                 },
 464         },
 465 };
 466
 467 /* ctrl_module_pad_core */
 468 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 469         .name           = "ctrl_module_pad_core",
 470         .class          = &omap44xx_ctrl_module_hwmod_class,
 471         .clkdm_name     = "l4_cfg_clkdm",
 472         .prcm = {
 473                 .omap4 = {
 474                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 475                 },
 476         },
 477 };
 478
 479 /* ctrl_module_wkup */
 480 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 481         .name           = "ctrl_module_wkup",
 482         .class          = &omap44xx_ctrl_module_hwmod_class,
 483         .clkdm_name     = "l4_wkup_clkdm",
 484         .prcm = {
 485                 .omap4 = {
 486                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 487                 },
 488         },
 489 };
 490
 491 /* ctrl_module_pad_wkup */
 492 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 493         .name           = "ctrl_module_pad_wkup",
 494         .class          = &omap44xx_ctrl_module_hwmod_class,
 495         .clkdm_name     = "l4_wkup_clkdm",
 496         .prcm = {
 497                 .omap4 = {
 498                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 499                 },
 500         },
 501 };
 502
 503 /*
 504  * 'debugss' class
 505  * debug and emulation sub system
 506  */
 507
 508 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 509         .name   = "debugss",
 510 };
 511
 512 /* debugss */
 513 static struct omap_hwmod omap44xx_debugss_hwmod = {
 514         .name           = "debugss",
 515         .class          = &omap44xx_debugss_hwmod_class,
 516         .clkdm_name     = "emu_sys_clkdm",
 517         .main_clk       = "trace_clk_div_ck",
 518         .prcm = {
 519                 .omap4 = {
 520                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 521                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 522                 },
 523         },
 524 };
 525
 526 /*
 527  * 'dma' class
 528  * dma controller for data exchange between memory to memory (i.e. internal or
 529  * external memory) and gp peripherals to memory or memory to gp peripherals
 530  */
 531
 532 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 533         .rev_offs       = 0x0000,
 534         .sysc_offs      = 0x002c,
 535         .syss_offs      = 0x0028,
 536         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 537                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 538                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 539                            SYSS_HAS_RESET_STATUS),
 540         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 541                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 546         .name   = "dma",
 547         .sysc   = &omap44xx_dma_sysc,
 548 };
 549
 550 /* dma dev_attr */
 551 static struct omap_dma_dev_attr dma_dev_attr = {
 552         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 553                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 554         .lch_count      = 32,
 555 };
 556
 557 /* dma_system */
 558 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 559         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 560         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 563         { .irq = -1 }
 564 };
 565
 566 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 567         .name           = "dma_system",
 568         .class          = &omap44xx_dma_hwmod_class,
 569         .clkdm_name     = "l3_dma_clkdm",
 570         .mpu_irqs       = omap44xx_dma_system_irqs,
 571         .main_clk       = "l3_div_ck",
 572         .prcm = {
 573                 .omap4 = {
 574                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 575                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 576                 },
 577         },
 578         .dev_attr       = &dma_dev_attr,
 579 };
 580
 581 /*
 582  * 'dmic' class
 583  * digital microphone controller
 584  */
 585
 586 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 587         .rev_offs       = 0x0000,
 588         .sysc_offs      = 0x0010,
 589         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 590                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 591         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 592                            SIDLE_SMART_WKUP),
 593         .sysc_fields    = &omap_hwmod_sysc_type2,
 594 };
 595
 596 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 597         .name   = "dmic",
 598         .sysc   = &omap44xx_dmic_sysc,
 599 };
 600
 601 /* dmic */
 602 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 603         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 604         { .irq = -1 }
 605 };
 606
 607 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 608         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 609         { .dma_req = -1 }
 610 };
 611
 612 static struct omap_hwmod omap44xx_dmic_hwmod = {
 613         .name           = "dmic",
 614         .class          = &omap44xx_dmic_hwmod_class,
 615         .clkdm_name     = "abe_clkdm",
 616         .mpu_irqs       = omap44xx_dmic_irqs,
 617         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 618         .main_clk       = "dmic_fck",
 619         .prcm = {
 620                 .omap4 = {
 621                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 622                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 623                         .modulemode   = MODULEMODE_SWCTRL,
 624                 },
 625         },
 626 };
 627
 628 /*
 629  * 'dsp' class
 630  * dsp sub-system
 631  */
 632
 633 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 634         .name   = "dsp",
 635 };
 636
 637 /* dsp */
 638 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 639         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 640         { .irq = -1 }
 641 };
 642
 643 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 644         { .name = "dsp", .rst_shift = 0 },
 645 };
 646
 647 static struct omap_hwmod omap44xx_dsp_hwmod = {
 648         .name           = "dsp",
 649         .class          = &omap44xx_dsp_hwmod_class,
 650         .clkdm_name     = "tesla_clkdm",
 651         .mpu_irqs       = omap44xx_dsp_irqs,
 652         .rst_lines      = omap44xx_dsp_resets,
 653         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 654         .main_clk       = "dsp_fck",
 655         .prcm = {
 656                 .omap4 = {
 657                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 658                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 659                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 660                         .modulemode   = MODULEMODE_HWCTRL,
 661                 },
 662         },
 663 };
 664
 665 /*
 666  * 'dss' class
 667  * display sub-system
 668  */
 669
 670 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 671         .rev_offs       = 0x0000,
 672         .syss_offs      = 0x0014,
 673         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 674 };
 675
 676 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 677         .name   = "dss",
 678         .sysc   = &omap44xx_dss_sysc,
 679         .reset  = omap_dss_reset,
 680 };
 681
 682 /* dss */
 683 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 684         { .role = "sys_clk", .clk = "dss_sys_clk" },
 685         { .role = "tv_clk", .clk = "dss_tv_clk" },
 686         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 687 };
 688
 689 static struct omap_hwmod omap44xx_dss_hwmod = {
 690         .name           = "dss_core",
 691         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 692         .class          = &omap44xx_dss_hwmod_class,
 693         .clkdm_name     = "l3_dss_clkdm",
 694         .main_clk       = "dss_dss_clk",
 695         .prcm = {
 696                 .omap4 = {
 697                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 698                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 699                 },
 700         },
 701         .opt_clks       = dss_opt_clks,
 702         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 703 };
 704
 705 /*
 706  * 'dispc' class
 707  * display controller
 708  */
 709
 710 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 711         .rev_offs       = 0x0000,
 712         .sysc_offs      = 0x0010,
 713         .syss_offs      = 0x0014,
 714         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 715                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 716                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 717                            SYSS_HAS_RESET_STATUS),
 718         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 719                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 724         .name   = "dispc",
 725         .sysc   = &omap44xx_dispc_sysc,
 726 };
 727
 728 /* dss_dispc */
 729 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 730         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 731         { .irq = -1 }
 732 };
 733
 734 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 735         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 736         { .dma_req = -1 }
 737 };
 738
 739 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 740         .manager_count          = 3,
 741         .has_framedonetv_irq    = 1
 742 };
 743
 744 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 745         .name           = "dss_dispc",
 746         .class          = &omap44xx_dispc_hwmod_class,
 747         .clkdm_name     = "l3_dss_clkdm",
 748         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 749         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 750         .main_clk       = "dss_dss_clk",
 751         .prcm = {
 752                 .omap4 = {
 753                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 754                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 755                 },
 756         },
 757         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 758 };
 759
 760 /*
 761  * 'dsi' class
 762  * display serial interface controller
 763  */
 764
 765 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 766         .rev_offs       = 0x0000,
 767         .sysc_offs      = 0x0010,
 768         .syss_offs      = 0x0014,
 769         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 770                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 771                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 773         .sysc_fields    = &omap_hwmod_sysc_type1,
 774 };
 775
 776 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 777         .name   = "dsi",
 778         .sysc   = &omap44xx_dsi_sysc,
 779 };
 780
 781 /* dss_dsi1 */
 782 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 783         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 784         { .irq = -1 }
 785 };
 786
 787 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 788         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 789         { .dma_req = -1 }
 790 };
 791
 792 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 793         { .role = "sys_clk", .clk = "dss_sys_clk" },
 794 };
 795
 796 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 797         .name           = "dss_dsi1",
 798         .class          = &omap44xx_dsi_hwmod_class,
 799         .clkdm_name     = "l3_dss_clkdm",
 800         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 801         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 802         .main_clk       = "dss_dss_clk",
 803         .prcm = {
 804                 .omap4 = {
 805                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 806                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 807                 },
 808         },
 809         .opt_clks       = dss_dsi1_opt_clks,
 810         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 811 };
 812
 813 /* dss_dsi2 */
 814 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 815         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 816         { .irq = -1 }
 817 };
 818
 819 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 820         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 821         { .dma_req = -1 }
 822 };
 823
 824 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 825         { .role = "sys_clk", .clk = "dss_sys_clk" },
 826 };
 827
 828 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 829         .name           = "dss_dsi2",
 830         .class          = &omap44xx_dsi_hwmod_class,
 831         .clkdm_name     = "l3_dss_clkdm",
 832         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 833         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 834         .main_clk       = "dss_dss_clk",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 838                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 839                 },
 840         },
 841         .opt_clks       = dss_dsi2_opt_clks,
 842         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 843 };
 844
 845 /*
 846  * 'hdmi' class
 847  * hdmi controller
 848  */
 849
 850 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 851         .rev_offs       = 0x0000,
 852         .sysc_offs      = 0x0010,
 853         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 854                            SYSC_HAS_SOFTRESET),
 855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 856                            SIDLE_SMART_WKUP),
 857         .sysc_fields    = &omap_hwmod_sysc_type2,
 858 };
 859
 860 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 861         .name   = "hdmi",
 862         .sysc   = &omap44xx_hdmi_sysc,
 863 };
 864
 865 /* dss_hdmi */
 866 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 867         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 868         { .irq = -1 }
 869 };
 870
 871 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 872         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 873         { .dma_req = -1 }
 874 };
 875
 876 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 877         { .role = "sys_clk", .clk = "dss_sys_clk" },
 878 };
 879
 880 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 881         .name           = "dss_hdmi",
 882         .class          = &omap44xx_hdmi_hwmod_class,
 883         .clkdm_name     = "l3_dss_clkdm",
 884         /*
 885          * HDMI audio requires to use no-idle mode. Hence,
 886          * set idle mode by software.
 887          */
 888         .flags          = HWMOD_SWSUP_SIDLE,
 889         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 890         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 891         .main_clk       = "dss_48mhz_clk",
 892         .prcm = {
 893                 .omap4 = {
 894                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 895                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 896                 },
 897         },
 898         .opt_clks       = dss_hdmi_opt_clks,
 899         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 900 };
 901
 902 /*
 903  * 'rfbi' class
 904  * remote frame buffer interface
 905  */
 906
 907 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 908         .rev_offs       = 0x0000,
 909         .sysc_offs      = 0x0010,
 910         .syss_offs      = 0x0014,
 911         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 912                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 914         .sysc_fields    = &omap_hwmod_sysc_type1,
 915 };
 916
 917 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 918         .name   = "rfbi",
 919         .sysc   = &omap44xx_rfbi_sysc,
 920 };
 921
 922 /* dss_rfbi */
 923 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 924         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 925         { .dma_req = -1 }
 926 };
 927
 928 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 929         { .role = "ick", .clk = "dss_fck" },
 930 };
 931
 932 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 933         .name           = "dss_rfbi",
 934         .class          = &omap44xx_rfbi_hwmod_class,
 935         .clkdm_name     = "l3_dss_clkdm",
 936         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 937         .main_clk       = "dss_dss_clk",
 938         .prcm = {
 939                 .omap4 = {
 940                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 941                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 942                 },
 943         },
 944         .opt_clks       = dss_rfbi_opt_clks,
 945         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 946 };
 947
 948 /*
 949  * 'venc' class
 950  * video encoder
 951  */
 952
 953 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 954         .name   = "venc",
 955 };
 956
 957 /* dss_venc */
 958 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 959         .name           = "dss_venc",
 960         .class          = &omap44xx_venc_hwmod_class,
 961         .clkdm_name     = "l3_dss_clkdm",
 962         .main_clk       = "dss_tv_clk",
 963         .prcm = {
 964                 .omap4 = {
 965                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 966                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 967                 },
 968         },
 969 };
 970
 971 /*
 972  * 'elm' class
 973  * bch error location module
 974  */
 975
 976 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 977         .rev_offs       = 0x0000,
 978         .sysc_offs      = 0x0010,
 979         .syss_offs      = 0x0014,
 980         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 981                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 982                            SYSS_HAS_RESET_STATUS),
 983         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 984         .sysc_fields    = &omap_hwmod_sysc_type1,
 985 };
 986
 987 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 988         .name   = "elm",
 989         .sysc   = &omap44xx_elm_sysc,
 990 };
 991
 992 /* elm */
 993 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 994         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 995         { .irq = -1 }
 996 };
 997
 998 static struct omap_hwmod omap44xx_elm_hwmod = {
 999         .name           = "elm",
1000         .class          = &omap44xx_elm_hwmod_class,
1001         .clkdm_name     = "l4_per_clkdm",
1002         .mpu_irqs       = omap44xx_elm_irqs,
1003         .prcm = {
1004                 .omap4 = {
1005                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1006                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1007                 },
1008         },
1009 };
1010
1011 /*
1012  * 'emif' class
1013  * external memory interface no1
1014  */
1015
1016 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1017         .rev_offs       = 0x0000,
1018 };
1019
1020 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1021         .name   = "emif",
1022         .sysc   = &omap44xx_emif_sysc,
1023 };
1024
1025 /* emif1 */
1026 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1027         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1028         { .irq = -1 }
1029 };
1030
1031 static struct omap_hwmod omap44xx_emif1_hwmod = {
1032         .name           = "emif1",
1033         .class          = &omap44xx_emif_hwmod_class,
1034         .clkdm_name     = "l3_emif_clkdm",
1035         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1036         .mpu_irqs       = omap44xx_emif1_irqs,
1037         .main_clk       = "ddrphy_ck",
1038         .prcm = {
1039                 .omap4 = {
1040                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1041                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1042                         .modulemode   = MODULEMODE_HWCTRL,
1043                 },
1044         },
1045 };
1046
1047 /* emif2 */
1048 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1049         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1050         { .irq = -1 }
1051 };
1052
1053 static struct omap_hwmod omap44xx_emif2_hwmod = {
1054         .name           = "emif2",
1055         .class          = &omap44xx_emif_hwmod_class,
1056         .clkdm_name     = "l3_emif_clkdm",
1057         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1058         .mpu_irqs       = omap44xx_emif2_irqs,
1059         .main_clk       = "ddrphy_ck",
1060         .prcm = {
1061                 .omap4 = {
1062                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1063                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1064                         .modulemode   = MODULEMODE_HWCTRL,
1065                 },
1066         },
1067 };
1068
1069 /*
1070  * 'fdif' class
1071  * face detection hw accelerator module
1072  */
1073
1074 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1075         .rev_offs       = 0x0000,
1076         .sysc_offs      = 0x0010,
1077         /*
1078          * FDIF needs 100 OCP clk cycles delay after a softreset before
1079          * accessing sysconfig again.
1080          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1081          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1082          *
1083          * TODO: Indicate errata when available.
1084          */
1085         .srst_udelay    = 2,
1086         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1087                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1088         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1090         .sysc_fields    = &omap_hwmod_sysc_type2,
1091 };
1092
1093 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1094         .name   = "fdif",
1095         .sysc   = &omap44xx_fdif_sysc,
1096 };
1097
1098 /* fdif */
1099 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1100         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1101         { .irq = -1 }
1102 };
1103
1104 static struct omap_hwmod omap44xx_fdif_hwmod = {
1105         .name           = "fdif",
1106         .class          = &omap44xx_fdif_hwmod_class,
1107         .clkdm_name     = "iss_clkdm",
1108         .mpu_irqs       = omap44xx_fdif_irqs,
1109         .main_clk       = "fdif_fck",
1110         .prcm = {
1111                 .omap4 = {
1112                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1113                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1114                         .modulemode   = MODULEMODE_SWCTRL,
1115                 },
1116         },
1117 };
1118
1119 /*
1120  * 'gpio' class
1121  * general purpose io module
1122  */
1123
1124 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1125         .rev_offs       = 0x0000,
1126         .sysc_offs      = 0x0010,
1127         .syss_offs      = 0x0114,
1128         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1129                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1130                            SYSS_HAS_RESET_STATUS),
1131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1132                            SIDLE_SMART_WKUP),
1133         .sysc_fields    = &omap_hwmod_sysc_type1,
1134 };
1135
1136 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1137         .name   = "gpio",
1138         .sysc   = &omap44xx_gpio_sysc,
1139         .rev    = 2,
1140 };
1141
1142 /* gpio dev_attr */
1143 static struct omap_gpio_dev_attr gpio_dev_attr = {
1144         .bank_width     = 32,
1145         .dbck_flag      = true,
1146 };
1147
1148 /* gpio1 */
1149 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1150         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1151         { .irq = -1 }
1152 };
1153
1154 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1155         { .role = "dbclk", .clk = "gpio1_dbclk" },
1156 };
1157
1158 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1159         .name           = "gpio1",
1160         .class          = &omap44xx_gpio_hwmod_class,
1161         .clkdm_name     = "l4_wkup_clkdm",
1162         .mpu_irqs       = omap44xx_gpio1_irqs,
1163         .main_clk       = "gpio1_ick",
1164         .prcm = {
1165                 .omap4 = {
1166                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1167                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1168                         .modulemode   = MODULEMODE_HWCTRL,
1169                 },
1170         },
1171         .opt_clks       = gpio1_opt_clks,
1172         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1173         .dev_attr       = &gpio_dev_attr,
1174 };
1175
1176 /* gpio2 */
1177 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1178         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1179         { .irq = -1 }
1180 };
1181
1182 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1183         { .role = "dbclk", .clk = "gpio2_dbclk" },
1184 };
1185
1186 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1187         .name           = "gpio2",
1188         .class          = &omap44xx_gpio_hwmod_class,
1189         .clkdm_name     = "l4_per_clkdm",
1190         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1191         .mpu_irqs       = omap44xx_gpio2_irqs,
1192         .main_clk       = "gpio2_ick",
1193         .prcm = {
1194                 .omap4 = {
1195                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1196                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1197                         .modulemode   = MODULEMODE_HWCTRL,
1198                 },
1199         },
1200         .opt_clks       = gpio2_opt_clks,
1201         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1202         .dev_attr       = &gpio_dev_attr,
1203 };
1204
1205 /* gpio3 */
1206 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1207         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1208         { .irq = -1 }
1209 };
1210
1211 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1212         { .role = "dbclk", .clk = "gpio3_dbclk" },
1213 };
1214
1215 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1216         .name           = "gpio3",
1217         .class          = &omap44xx_gpio_hwmod_class,
1218         .clkdm_name     = "l4_per_clkdm",
1219         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1220         .mpu_irqs       = omap44xx_gpio3_irqs,
1221         .main_clk       = "gpio3_ick",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1225                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1226                         .modulemode   = MODULEMODE_HWCTRL,
1227                 },
1228         },
1229         .opt_clks       = gpio3_opt_clks,
1230         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1231         .dev_attr       = &gpio_dev_attr,
1232 };
1233
1234 /* gpio4 */
1235 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1236         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1237         { .irq = -1 }
1238 };
1239
1240 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1241         { .role = "dbclk", .clk = "gpio4_dbclk" },
1242 };
1243
1244 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1245         .name           = "gpio4",
1246         .class          = &omap44xx_gpio_hwmod_class,
1247         .clkdm_name     = "l4_per_clkdm",
1248         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249         .mpu_irqs       = omap44xx_gpio4_irqs,
1250         .main_clk       = "gpio4_ick",
1251         .prcm = {
1252                 .omap4 = {
1253                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1254                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1255                         .modulemode   = MODULEMODE_HWCTRL,
1256                 },
1257         },
1258         .opt_clks       = gpio4_opt_clks,
1259         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1260         .dev_attr       = &gpio_dev_attr,
1261 };
1262
1263 /* gpio5 */
1264 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1265         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1266         { .irq = -1 }
1267 };
1268
1269 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1270         { .role = "dbclk", .clk = "gpio5_dbclk" },
1271 };
1272
1273 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1274         .name           = "gpio5",
1275         .class          = &omap44xx_gpio_hwmod_class,
1276         .clkdm_name     = "l4_per_clkdm",
1277         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1278         .mpu_irqs       = omap44xx_gpio5_irqs,
1279         .main_clk       = "gpio5_ick",
1280         .prcm = {
1281                 .omap4 = {
1282                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1283                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1284                         .modulemode   = MODULEMODE_HWCTRL,
1285                 },
1286         },
1287         .opt_clks       = gpio5_opt_clks,
1288         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1289         .dev_attr       = &gpio_dev_attr,
1290 };
1291
1292 /* gpio6 */
1293 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1294         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1295         { .irq = -1 }
1296 };
1297
1298 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1299         { .role = "dbclk", .clk = "gpio6_dbclk" },
1300 };
1301
1302 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1303         .name           = "gpio6",
1304         .class          = &omap44xx_gpio_hwmod_class,
1305         .clkdm_name     = "l4_per_clkdm",
1306         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1307         .mpu_irqs       = omap44xx_gpio6_irqs,
1308         .main_clk       = "gpio6_ick",
1309         .prcm = {
1310                 .omap4 = {
1311                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1312                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1313                         .modulemode   = MODULEMODE_HWCTRL,
1314                 },
1315         },
1316         .opt_clks       = gpio6_opt_clks,
1317         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1318         .dev_attr       = &gpio_dev_attr,
1319 };
1320
1321 /*
1322  * 'gpmc' class
1323  * general purpose memory controller
1324  */
1325
1326 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1327         .rev_offs       = 0x0000,
1328         .sysc_offs      = 0x0010,
1329         .syss_offs      = 0x0014,
1330         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1331                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1332         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1333         .sysc_fields    = &omap_hwmod_sysc_type1,
1334 };
1335
1336 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1337         .name   = "gpmc",
1338         .sysc   = &omap44xx_gpmc_sysc,
1339 };
1340
1341 /* gpmc */
1342 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1343         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1344         { .irq = -1 }
1345 };
1346
1347 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1348         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1349         { .dma_req = -1 }
1350 };
1351
1352 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1353         .name           = "gpmc",
1354         .class          = &omap44xx_gpmc_hwmod_class,
1355         .clkdm_name     = "l3_2_clkdm",
1356         /*
1357          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1358          * block.  It is not being added due to any known bugs with
1359          * resetting the GPMC IP block, but rather because any timings
1360          * set by the bootloader are not being correctly programmed by
1361          * the kernel from the board file or DT data.
1362          * HWMOD_INIT_NO_RESET should be removed ASAP.
1363          */
1364         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1365         .mpu_irqs       = omap44xx_gpmc_irqs,
1366         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1367         .prcm = {
1368                 .omap4 = {
1369                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1370                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1371                         .modulemode   = MODULEMODE_HWCTRL,
1372                 },
1373         },
1374 };
1375
1376 /*
1377  * 'gpu' class
1378  * 2d/3d graphics accelerator
1379  */
1380
1381 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1382         .rev_offs       = 0x1fc00,
1383         .sysc_offs      = 0x1fc10,
1384         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1386                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1387                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1388         .sysc_fields    = &omap_hwmod_sysc_type2,
1389 };
1390
1391 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1392         .name   = "gpu",
1393         .sysc   = &omap44xx_gpu_sysc,
1394 };
1395
1396 /* gpu */
1397 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1398         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1399         { .irq = -1 }
1400 };
1401
1402 static struct omap_hwmod omap44xx_gpu_hwmod = {
1403         .name           = "gpu",
1404         .class          = &omap44xx_gpu_hwmod_class,
1405         .clkdm_name     = "l3_gfx_clkdm",
1406         .mpu_irqs       = omap44xx_gpu_irqs,
1407         .main_clk       = "gpu_fck",
1408         .prcm = {
1409                 .omap4 = {
1410                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1411                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1412                         .modulemode   = MODULEMODE_SWCTRL,
1413                 },
1414         },
1415 };
1416
1417 /*
1418  * 'hdq1w' class
1419  * hdq / 1-wire serial interface controller
1420  */
1421
1422 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1423         .rev_offs       = 0x0000,
1424         .sysc_offs      = 0x0014,
1425         .syss_offs      = 0x0018,
1426         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1427                            SYSS_HAS_RESET_STATUS),
1428         .sysc_fields    = &omap_hwmod_sysc_type1,
1429 };
1430
1431 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1432         .name   = "hdq1w",
1433         .sysc   = &omap44xx_hdq1w_sysc,
1434 };
1435
1436 /* hdq1w */
1437 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1438         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1439         { .irq = -1 }
1440 };
1441
1442 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1443         .name           = "hdq1w",
1444         .class          = &omap44xx_hdq1w_hwmod_class,
1445         .clkdm_name     = "l4_per_clkdm",
1446         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1447         .mpu_irqs       = omap44xx_hdq1w_irqs,
1448         .main_clk       = "hdq1w_fck",
1449         .prcm = {
1450                 .omap4 = {
1451                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1452                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1453                         .modulemode   = MODULEMODE_SWCTRL,
1454                 },
1455         },
1456 };
1457
1458 /*
1459  * 'hsi' class
1460  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1461  * serial if)
1462  */
1463
1464 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1465         .rev_offs       = 0x0000,
1466         .sysc_offs      = 0x0010,
1467         .syss_offs      = 0x0014,
1468         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1469                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1470                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1471         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1472                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1473                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1474         .sysc_fields    = &omap_hwmod_sysc_type1,
1475 };
1476
1477 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1478         .name   = "hsi",
1479         .sysc   = &omap44xx_hsi_sysc,
1480 };
1481
1482 /* hsi */
1483 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1484         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1485         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1487         { .irq = -1 }
1488 };
1489
1490 static struct omap_hwmod omap44xx_hsi_hwmod = {
1491         .name           = "hsi",
1492         .class          = &omap44xx_hsi_hwmod_class,
1493         .clkdm_name     = "l3_init_clkdm",
1494         .mpu_irqs       = omap44xx_hsi_irqs,
1495         .main_clk       = "hsi_fck",
1496         .prcm = {
1497                 .omap4 = {
1498                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1499                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1500                         .modulemode   = MODULEMODE_HWCTRL,
1501                 },
1502         },
1503 };
1504
1505 /*
1506  * 'i2c' class
1507  * multimaster high-speed i2c controller
1508  */
1509
1510 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1511         .sysc_offs      = 0x0010,
1512         .syss_offs      = 0x0090,
1513         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1514                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1515                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1516         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1517                            SIDLE_SMART_WKUP),
1518         .clockact       = CLOCKACT_TEST_ICLK,
1519         .sysc_fields    = &omap_hwmod_sysc_type1,
1520 };
1521
1522 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1523         .name   = "i2c",
1524         .sysc   = &omap44xx_i2c_sysc,
1525         .rev    = OMAP_I2C_IP_VERSION_2,
1526         .reset  = &omap_i2c_reset,
1527 };
1528
1529 static struct omap_i2c_dev_attr i2c_dev_attr = {
1530         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1531                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1532 };
1533
1534 /* i2c1 */
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1537         { .irq = -1 }
1538 };
1539
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1543         { .dma_req = -1 }
1544 };
1545
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1547         .name           = "i2c1",
1548         .class          = &omap44xx_i2c_hwmod_class,
1549         .clkdm_name     = "l4_per_clkdm",
1550         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551         .mpu_irqs       = omap44xx_i2c1_irqs,
1552         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1553         .main_clk       = "i2c1_fck",
1554         .prcm = {
1555                 .omap4 = {
1556                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558                         .modulemode   = MODULEMODE_SWCTRL,
1559                 },
1560         },
1561         .dev_attr       = &i2c_dev_attr,
1562 };
1563
1564 /* i2c2 */
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1567         { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1573         { .dma_req = -1 }
1574 };
1575
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1577         .name           = "i2c2",
1578         .class          = &omap44xx_i2c_hwmod_class,
1579         .clkdm_name     = "l4_per_clkdm",
1580         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581         .mpu_irqs       = omap44xx_i2c2_irqs,
1582         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1583         .main_clk       = "i2c2_fck",
1584         .prcm = {
1585                 .omap4 = {
1586                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588                         .modulemode   = MODULEMODE_SWCTRL,
1589                 },
1590         },
1591         .dev_attr       = &i2c_dev_attr,
1592 };
1593
1594 /* i2c3 */
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1597         { .irq = -1 }
1598 };
1599
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1603         { .dma_req = -1 }
1604 };
1605
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1607         .name           = "i2c3",
1608         .class          = &omap44xx_i2c_hwmod_class,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611         .mpu_irqs       = omap44xx_i2c3_irqs,
1612         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1613         .main_clk       = "i2c3_fck",
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618                         .modulemode   = MODULEMODE_SWCTRL,
1619                 },
1620         },
1621         .dev_attr       = &i2c_dev_attr,
1622 };
1623
1624 /* i2c4 */
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1627         { .irq = -1 }
1628 };
1629
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1633         { .dma_req = -1 }
1634 };
1635
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1637         .name           = "i2c4",
1638         .class          = &omap44xx_i2c_hwmod_class,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641         .mpu_irqs       = omap44xx_i2c4_irqs,
1642         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1643         .main_clk       = "i2c4_fck",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_SWCTRL,
1649                 },
1650         },
1651         .dev_attr       = &i2c_dev_attr,
1652 };
1653
1654 /*
1655  * 'ipu' class
1656  * imaging processor unit
1657  */
1658
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1660         .name   = "ipu",
1661 };
1662
1663 /* ipu */
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1666         { .irq = -1 }
1667 };
1668
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670         { .name = "cpu0", .rst_shift = 0 },
1671         { .name = "cpu1", .rst_shift = 1 },
1672 };
1673
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1675         .name           = "ipu",
1676         .class          = &omap44xx_ipu_hwmod_class,
1677         .clkdm_name     = "ducati_clkdm",
1678         .mpu_irqs       = omap44xx_ipu_irqs,
1679         .rst_lines      = omap44xx_ipu_resets,
1680         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1681         .main_clk       = "ipu_fck",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_HWCTRL,
1688                 },
1689         },
1690 };
1691
1692 /*
1693  * 'iss' class
1694  * external images sensor pixel data processor
1695  */
1696
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         /*
1701          * ISS needs 100 OCP clk cycles delay after a softreset before
1702          * accessing sysconfig again.
1703          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1705          *
1706          * TODO: Indicate errata when available.
1707          */
1708         .srst_udelay    = 2,
1709         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714         .sysc_fields    = &omap_hwmod_sysc_type2,
1715 };
1716
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1718         .name   = "iss",
1719         .sysc   = &omap44xx_iss_sysc,
1720 };
1721
1722 /* iss */
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1725         { .irq = -1 }
1726 };
1727
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1733         { .dma_req = -1 }
1734 };
1735
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1738 };
1739
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1741         .name           = "iss",
1742         .class          = &omap44xx_iss_hwmod_class,
1743         .clkdm_name     = "iss_clkdm",
1744         .mpu_irqs       = omap44xx_iss_irqs,
1745         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1746         .main_clk       = "iss_fck",
1747         .prcm = {
1748                 .omap4 = {
1749                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751                         .modulemode   = MODULEMODE_SWCTRL,
1752                 },
1753         },
1754         .opt_clks       = iss_opt_clks,
1755         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1756 };
1757
1758 /*
1759  * 'iva' class
1760  * multi-standard video encoder/decoder hardware accelerator
1761  */
1762
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1764         .name   = "iva",
1765 };
1766
1767 /* iva */
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776         { .name = "seq0", .rst_shift = 0 },
1777         { .name = "seq1", .rst_shift = 1 },
1778         { .name = "logic", .rst_shift = 2 },
1779 };
1780
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1782         .name           = "iva",
1783         .class          = &omap44xx_iva_hwmod_class,
1784         .clkdm_name     = "ivahd_clkdm",
1785         .mpu_irqs       = omap44xx_iva_irqs,
1786         .rst_lines      = omap44xx_iva_resets,
1787         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1788         .main_clk       = "iva_fck",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794                         .modulemode   = MODULEMODE_HWCTRL,
1795                 },
1796         },
1797 };
1798
1799 /*
1800  * 'kbd' class
1801  * keyboard controller
1802  */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0014,
1808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811                            SYSS_HAS_RESET_STATUS),
1812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813         .sysc_fields    = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1817         .name   = "kbd",
1818         .sysc   = &omap44xx_kbd_sysc,
1819 };
1820
1821 /* kbd */
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1828         .name           = "kbd",
1829         .class          = &omap44xx_kbd_hwmod_class,
1830         .clkdm_name     = "l4_wkup_clkdm",
1831         .mpu_irqs       = omap44xx_kbd_irqs,
1832         .main_clk       = "kbd_fck",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mailbox' class
1844  * mailbox module allowing communication between the on-chip processors using a
1845  * queued mailbox-interrupt mechanism.
1846  */
1847
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1849         .rev_offs       = 0x0000,
1850         .sysc_offs      = 0x0010,
1851         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852                            SYSC_HAS_SOFTRESET),
1853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854         .sysc_fields    = &omap_hwmod_sysc_type2,
1855 };
1856
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1858         .name   = "mailbox",
1859         .sysc   = &omap44xx_mailbox_sysc,
1860 };
1861
1862 /* mailbox */
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1865         { .irq = -1 }
1866 };
1867
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1869         .name           = "mailbox",
1870         .class          = &omap44xx_mailbox_hwmod_class,
1871         .clkdm_name     = "l4_cfg_clkdm",
1872         .mpu_irqs       = omap44xx_mailbox_irqs,
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'mcasp' class
1883  * multi-channel audio serial port controller
1884  */
1885
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1888         .sidle_shift    = 0,
1889 };
1890
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892         .sysc_offs      = 0x0004,
1893         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1895                            SIDLE_SMART_WKUP),
1896         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1897 };
1898
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1900         .name   = "mcasp",
1901         .sysc   = &omap44xx_mcasp_sysc,
1902 };
1903
1904 /* mcasp */
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1908         { .irq = -1 }
1909 };
1910
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1914         { .dma_req = -1 }
1915 };
1916
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1918         .name           = "mcasp",
1919         .class          = &omap44xx_mcasp_hwmod_class,
1920         .clkdm_name     = "abe_clkdm",
1921         .mpu_irqs       = omap44xx_mcasp_irqs,
1922         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1923         .main_clk       = "mcasp_fck",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931 };
1932
1933 /*
1934  * 'mcbsp' class
1935  * multi channel buffered serial port controller
1936  */
1937
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939         .sysc_offs      = 0x008c,
1940         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943         .sysc_fields    = &omap_hwmod_sysc_type1,
1944 };
1945
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1947         .name   = "mcbsp",
1948         .sysc   = &omap44xx_mcbsp_sysc,
1949         .rev    = MCBSP_CONFIG_TYPE4,
1950 };
1951
1952 /* mcbsp1 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1970         .name           = "mcbsp1",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1975         .main_clk       = "mcbsp1_fck",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp1_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1985 };
1986
1987 /* mcbsp2 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2005         .name           = "mcbsp2",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2010         .main_clk       = "mcbsp2_fck",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp2_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2020 };
2021
2022 /* mcbsp3 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2040         .name           = "mcbsp3",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "abe_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2045         .main_clk       = "mcbsp3_fck",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp3_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2055 };
2056
2057 /* mcbsp4 */
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2060         { .irq = -1 }
2061 };
2062
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2066         { .dma_req = -1 }
2067 };
2068
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070         { .role = "pad_fck", .clk = "pad_clks_ck" },
2071         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2072 };
2073
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2075         .name           = "mcbsp4",
2076         .class          = &omap44xx_mcbsp_hwmod_class,
2077         .clkdm_name     = "l4_per_clkdm",
2078         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2079         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2080         .main_clk       = "mcbsp4_fck",
2081         .prcm = {
2082                 .omap4 = {
2083                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085                         .modulemode   = MODULEMODE_SWCTRL,
2086                 },
2087         },
2088         .opt_clks       = mcbsp4_opt_clks,
2089         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2090 };
2091
2092 /*
2093  * 'mcpdm' class
2094  * multi channel pdm controller (proprietary interface with phoenix power
2095  * ic)
2096  */
2097
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2099         .rev_offs       = 0x0000,
2100         .sysc_offs      = 0x0010,
2101         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2104                            SIDLE_SMART_WKUP),
2105         .sysc_fields    = &omap_hwmod_sysc_type2,
2106 };
2107
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2109         .name   = "mcpdm",
2110         .sysc   = &omap44xx_mcpdm_sysc,
2111 };
2112
2113 /* mcpdm */
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2116         { .irq = -1 }
2117 };
2118
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2122         { .dma_req = -1 }
2123 };
2124
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2126         .name           = "mcpdm",
2127         .class          = &omap44xx_mcpdm_hwmod_class,
2128         .clkdm_name     = "abe_clkdm",
2129         .mpu_irqs       = omap44xx_mcpdm_irqs,
2130         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2131         .main_clk       = "mcpdm_fck",
2132         .prcm = {
2133                 .omap4 = {
2134                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2135                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2136                         .modulemode   = MODULEMODE_SWCTRL,
2137                 },
2138         },
2139 };
2140
2141 /*
2142  * 'mcspi' class
2143  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2144  * bus
2145  */
2146
2147 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2148         .rev_offs       = 0x0000,
2149         .sysc_offs      = 0x0010,
2150         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2151                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2153                            SIDLE_SMART_WKUP),
2154         .sysc_fields    = &omap_hwmod_sysc_type2,
2155 };
2156
2157 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2158         .name   = "mcspi",
2159         .sysc   = &omap44xx_mcspi_sysc,
2160         .rev    = OMAP4_MCSPI_REV,
2161 };
2162
2163 /* mcspi1 */
2164 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2165         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2166         { .irq = -1 }
2167 };
2168
2169 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2170         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2171         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2172         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2173         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2174         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2175         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2176         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2177         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2178         { .dma_req = -1 }
2179 };
2180
2181 /* mcspi1 dev_attr */
2182 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2183         .num_chipselect = 4,
2184 };
2185
2186 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2187         .name           = "mcspi1",
2188         .class          = &omap44xx_mcspi_hwmod_class,
2189         .clkdm_name     = "l4_per_clkdm",
2190         .mpu_irqs       = omap44xx_mcspi1_irqs,
2191         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2192         .main_clk       = "mcspi1_fck",
2193         .prcm = {
2194                 .omap4 = {
2195                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2196                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2197                         .modulemode   = MODULEMODE_SWCTRL,
2198                 },
2199         },
2200         .dev_attr       = &mcspi1_dev_attr,
2201 };
2202
2203 /* mcspi2 */
2204 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2205         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2206         { .irq = -1 }
2207 };
2208
2209 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2210         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2211         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2212         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2213         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2214         { .dma_req = -1 }
2215 };
2216
2217 /* mcspi2 dev_attr */
2218 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2219         .num_chipselect = 2,
2220 };
2221
2222 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2223         .name           = "mcspi2",
2224         .class          = &omap44xx_mcspi_hwmod_class,
2225         .clkdm_name     = "l4_per_clkdm",
2226         .mpu_irqs       = omap44xx_mcspi2_irqs,
2227         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2228         .main_clk       = "mcspi2_fck",
2229         .prcm = {
2230                 .omap4 = {
2231                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2232                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2233                         .modulemode   = MODULEMODE_SWCTRL,
2234                 },
2235         },
2236         .dev_attr       = &mcspi2_dev_attr,
2237 };
2238
2239 /* mcspi3 */
2240 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2241         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2242         { .irq = -1 }
2243 };
2244
2245 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2246         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2247         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2248         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2249         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2250         { .dma_req = -1 }
2251 };
2252
2253 /* mcspi3 dev_attr */
2254 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2255         .num_chipselect = 2,
2256 };
2257
2258 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2259         .name           = "mcspi3",
2260         .class          = &omap44xx_mcspi_hwmod_class,
2261         .clkdm_name     = "l4_per_clkdm",
2262         .mpu_irqs       = omap44xx_mcspi3_irqs,
2263         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2264         .main_clk       = "mcspi3_fck",
2265         .prcm = {
2266                 .omap4 = {
2267                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2268                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2269                         .modulemode   = MODULEMODE_SWCTRL,
2270                 },
2271         },
2272         .dev_attr       = &mcspi3_dev_attr,
2273 };
2274
2275 /* mcspi4 */
2276 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2277         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2278         { .irq = -1 }
2279 };
2280
2281 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2282         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2283         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2284         { .dma_req = -1 }
2285 };
2286
2287 /* mcspi4 dev_attr */
2288 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2289         .num_chipselect = 1,
2290 };
2291
2292 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2293         .name           = "mcspi4",
2294         .class          = &omap44xx_mcspi_hwmod_class,
2295         .clkdm_name     = "l4_per_clkdm",
2296         .mpu_irqs       = omap44xx_mcspi4_irqs,
2297         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2298         .main_clk       = "mcspi4_fck",
2299         .prcm = {
2300                 .omap4 = {
2301                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2302                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2303                         .modulemode   = MODULEMODE_SWCTRL,
2304                 },
2305         },
2306         .dev_attr       = &mcspi4_dev_attr,
2307 };
2308
2309 /*
2310  * 'mmc' class
2311  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2312  */
2313
2314 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2315         .rev_offs       = 0x0000,
2316         .sysc_offs      = 0x0010,
2317         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2318                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2319                            SYSC_HAS_SOFTRESET),
2320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2321                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2322                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2323         .sysc_fields    = &omap_hwmod_sysc_type2,
2324 };
2325
2326 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2327         .name   = "mmc",
2328         .sysc   = &omap44xx_mmc_sysc,
2329 };
2330
2331 /* mmc1 */
2332 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2333         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2334         { .irq = -1 }
2335 };
2336
2337 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2338         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2339         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2340         { .dma_req = -1 }
2341 };
2342
2343 /* mmc1 dev_attr */
2344 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2345         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2346 };
2347
2348 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2349         .name           = "mmc1",
2350         .class          = &omap44xx_mmc_hwmod_class,
2351         .clkdm_name     = "l3_init_clkdm",
2352         .mpu_irqs       = omap44xx_mmc1_irqs,
2353         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2354         .main_clk       = "mmc1_fck",
2355         .prcm = {
2356                 .omap4 = {
2357                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2358                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2359                         .modulemode   = MODULEMODE_SWCTRL,
2360                 },
2361         },
2362         .dev_attr       = &mmc1_dev_attr,
2363 };
2364
2365 /* mmc2 */
2366 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2367         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2368         { .irq = -1 }
2369 };
2370
2371 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2372         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2373         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2374         { .dma_req = -1 }
2375 };
2376
2377 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2378         .name           = "mmc2",
2379         .class          = &omap44xx_mmc_hwmod_class,
2380         .clkdm_name     = "l3_init_clkdm",
2381         .mpu_irqs       = omap44xx_mmc2_irqs,
2382         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2383         .main_clk       = "mmc2_fck",
2384         .prcm = {
2385                 .omap4 = {
2386                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2387                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2388                         .modulemode   = MODULEMODE_SWCTRL,
2389                 },
2390         },
2391 };
2392
2393 /* mmc3 */
2394 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2395         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2396         { .irq = -1 }
2397 };
2398
2399 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2400         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2401         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2402         { .dma_req = -1 }
2403 };
2404
2405 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2406         .name           = "mmc3",
2407         .class          = &omap44xx_mmc_hwmod_class,
2408         .clkdm_name     = "l4_per_clkdm",
2409         .mpu_irqs       = omap44xx_mmc3_irqs,
2410         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2411         .main_clk       = "mmc3_fck",
2412         .prcm = {
2413                 .omap4 = {
2414                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2415                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2416                         .modulemode   = MODULEMODE_SWCTRL,
2417                 },
2418         },
2419 };
2420
2421 /* mmc4 */
2422 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2423         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2424         { .irq = -1 }
2425 };
2426
2427 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2428         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2429         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2430         { .dma_req = -1 }
2431 };
2432
2433 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2434         .name           = "mmc4",
2435         .class          = &omap44xx_mmc_hwmod_class,
2436         .clkdm_name     = "l4_per_clkdm",
2437         .mpu_irqs       = omap44xx_mmc4_irqs,
2438         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2439         .main_clk       = "mmc4_fck",
2440         .prcm = {
2441                 .omap4 = {
2442                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2443                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2444                         .modulemode   = MODULEMODE_SWCTRL,
2445                 },
2446         },
2447 };
2448
2449 /* mmc5 */
2450 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2451         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2452         { .irq = -1 }
2453 };
2454
2455 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2456         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2457         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2458         { .dma_req = -1 }
2459 };
2460
2461 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2462         .name           = "mmc5",
2463         .class          = &omap44xx_mmc_hwmod_class,
2464         .clkdm_name     = "l4_per_clkdm",
2465         .mpu_irqs       = omap44xx_mmc5_irqs,
2466         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2467         .main_clk       = "mmc5_fck",
2468         .prcm = {
2469                 .omap4 = {
2470                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2471                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2472                         .modulemode   = MODULEMODE_SWCTRL,
2473                 },
2474         },
2475 };
2476
2477 /*
2478  * 'mmu' class
2479  * The memory management unit performs virtual to physical address translation
2480  * for its requestors.
2481  */
2482
2483 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2484         .rev_offs       = 0x000,
2485         .sysc_offs      = 0x010,
2486         .syss_offs      = 0x014,
2487         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2488                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2490         .sysc_fields    = &omap_hwmod_sysc_type1,
2491 };
2492
2493 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2494         .name = "mmu",
2495         .sysc = &mmu_sysc,
2496 };
2497
2498 /* mmu ipu */
2499
2500 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2501         .da_start       = 0x0,
2502         .da_end         = 0xfffff000,
2503         .nr_tlb_entries = 32,
2504 };
2505
2506 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2507 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2508         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2509         { .irq = -1 }
2510 };
2511
2512 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2513         { .name = "mmu_cache", .rst_shift = 2 },
2514 };
2515
2516 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2517         {
2518                 .pa_start       = 0x55082000,
2519                 .pa_end         = 0x550820ff,
2520                 .flags          = ADDR_TYPE_RT,
2521         },
2522         { }
2523 };
2524
2525 /* l3_main_2 -> mmu_ipu */
2526 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2527         .master         = &omap44xx_l3_main_2_hwmod,
2528         .slave          = &omap44xx_mmu_ipu_hwmod,
2529         .clk            = "l3_div_ck",
2530         .addr           = omap44xx_mmu_ipu_addrs,
2531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2532 };
2533
2534 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2535         .name           = "mmu_ipu",
2536         .class          = &omap44xx_mmu_hwmod_class,
2537         .clkdm_name     = "ducati_clkdm",
2538         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2539         .rst_lines      = omap44xx_mmu_ipu_resets,
2540         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2541         .main_clk       = "ducati_clk_mux_ck",
2542         .prcm = {
2543                 .omap4 = {
2544                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2545                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2546                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2547                         .modulemode   = MODULEMODE_HWCTRL,
2548                 },
2549         },
2550         .dev_attr       = &mmu_ipu_dev_attr,
2551 };
2552
2553 /* mmu dsp */
2554
2555 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2556         .da_start       = 0x0,
2557         .da_end         = 0xfffff000,
2558         .nr_tlb_entries = 32,
2559 };
2560
2561 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2562 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2563         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2564         { .irq = -1 }
2565 };
2566
2567 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2568         { .name = "mmu_cache", .rst_shift = 1 },
2569 };
2570
2571 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2572         {
2573                 .pa_start       = 0x4a066000,
2574                 .pa_end         = 0x4a0660ff,
2575                 .flags          = ADDR_TYPE_RT,
2576         },
2577         { }
2578 };
2579
2580 /* l4_cfg -> dsp */
2581 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2582         .master         = &omap44xx_l4_cfg_hwmod,
2583         .slave          = &omap44xx_mmu_dsp_hwmod,
2584         .clk            = "l4_div_ck",
2585         .addr           = omap44xx_mmu_dsp_addrs,
2586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588
2589 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2590         .name           = "mmu_dsp",
2591         .class          = &omap44xx_mmu_hwmod_class,
2592         .clkdm_name     = "tesla_clkdm",
2593         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2594         .rst_lines      = omap44xx_mmu_dsp_resets,
2595         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2596         .main_clk       = "dpll_iva_m4x2_ck",
2597         .prcm = {
2598                 .omap4 = {
2599                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2600                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2601                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2602                         .modulemode   = MODULEMODE_HWCTRL,
2603                 },
2604         },
2605         .dev_attr       = &mmu_dsp_dev_attr,
2606 };
2607
2608 /*
2609  * 'mpu' class
2610  * mpu sub-system
2611  */
2612
2613 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2614         .name   = "mpu",
2615 };
2616
2617 /* mpu */
2618 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2619         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2620         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2621         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2622         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2623         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2624         { .irq = -1 }
2625 };
2626
2627 static struct omap_hwmod omap44xx_mpu_hwmod = {
2628         .name           = "mpu",
2629         .class          = &omap44xx_mpu_hwmod_class,
2630         .clkdm_name     = "mpuss_clkdm",
2631         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2632         .mpu_irqs       = omap44xx_mpu_irqs,
2633         .main_clk       = "dpll_mpu_m2_ck",
2634         .prcm = {
2635                 .omap4 = {
2636                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2637                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2638                 },
2639         },
2640 };
2641
2642 /*
2643  * 'ocmc_ram' class
2644  * top-level core on-chip ram
2645  */
2646
2647 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2648         .name   = "ocmc_ram",
2649 };
2650
2651 /* ocmc_ram */
2652 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2653         .name           = "ocmc_ram",
2654         .class          = &omap44xx_ocmc_ram_hwmod_class,
2655         .clkdm_name     = "l3_2_clkdm",
2656         .prcm = {
2657                 .omap4 = {
2658                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2659                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2660                 },
2661         },
2662 };
2663
2664 /*
2665  * 'ocp2scp' class
2666  * bridge to transform ocp interface protocol to scp (serial control port)
2667  * protocol
2668  */
2669
2670 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2671         .rev_offs       = 0x0000,
2672         .sysc_offs      = 0x0010,
2673         .syss_offs      = 0x0014,
2674         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2675                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2676         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2677         .sysc_fields    = &omap_hwmod_sysc_type1,
2678 };
2679
2680 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2681         .name   = "ocp2scp",
2682         .sysc   = &omap44xx_ocp2scp_sysc,
2683 };
2684
2685 /* ocp2scp dev_attr */
2686 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2687         {
2688                 .name           = "usb_phy",
2689                 .start          = 0x4a0ad080,
2690                 .end            = 0x4a0ae000,
2691                 .flags          = IORESOURCE_MEM,
2692         },
2693         {
2694                 /* XXX: Remove this once control module driver is in place */
2695                 .name           = "ctrl_dev",
2696                 .start          = 0x4a002300,
2697                 .end            = 0x4a002303,
2698                 .flags          = IORESOURCE_MEM,
2699         },
2700         { }
2701 };
2702
2703 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2704         {
2705                 .drv_name       = "omap-usb2",
2706                 .res            = omap44xx_usb_phy_and_pll_addrs,
2707         },
2708         { }
2709 };
2710
2711 /* ocp2scp_usb_phy */
2712 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2713         .name           = "ocp2scp_usb_phy",
2714         .class          = &omap44xx_ocp2scp_hwmod_class,
2715         .clkdm_name     = "l3_init_clkdm",
2716         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2717         .prcm = {
2718                 .omap4 = {
2719                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2720                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2721                         .modulemode   = MODULEMODE_HWCTRL,
2722                 },
2723         },
2724         .dev_attr       = ocp2scp_dev_attr,
2725 };
2726
2727 /*
2728  * 'prcm' class
2729  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2730  * + clock manager 1 (in always on power domain) + local prm in mpu
2731  */
2732
2733 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2734         .name   = "prcm",
2735 };
2736
2737 /* prcm_mpu */
2738 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2739         .name           = "prcm_mpu",
2740         .class          = &omap44xx_prcm_hwmod_class,
2741         .clkdm_name     = "l4_wkup_clkdm",
2742         .flags          = HWMOD_NO_IDLEST,
2743         .prcm = {
2744                 .omap4 = {
2745                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2746                 },
2747         },
2748 };
2749
2750 /* cm_core_aon */
2751 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2752         .name           = "cm_core_aon",
2753         .class          = &omap44xx_prcm_hwmod_class,
2754         .flags          = HWMOD_NO_IDLEST,
2755         .prcm = {
2756                 .omap4 = {
2757                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2758                 },
2759         },
2760 };
2761
2762 /* cm_core */
2763 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2764         .name           = "cm_core",
2765         .class          = &omap44xx_prcm_hwmod_class,
2766         .flags          = HWMOD_NO_IDLEST,
2767         .prcm = {
2768                 .omap4 = {
2769                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2770                 },
2771         },
2772 };
2773
2774 /* prm */
2775 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2776         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2777         { .irq = -1 }
2778 };
2779
2780 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2781         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2782         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2783 };
2784
2785 static struct omap_hwmod omap44xx_prm_hwmod = {
2786         .name           = "prm",
2787         .class          = &omap44xx_prcm_hwmod_class,
2788         .mpu_irqs       = omap44xx_prm_irqs,
2789         .rst_lines      = omap44xx_prm_resets,
2790         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2791 };
2792
2793 /*
2794  * 'scrm' class
2795  * system clock and reset manager
2796  */
2797
2798 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2799         .name   = "scrm",
2800 };
2801
2802 /* scrm */
2803 static struct omap_hwmod omap44xx_scrm_hwmod = {
2804         .name           = "scrm",
2805         .class          = &omap44xx_scrm_hwmod_class,
2806         .clkdm_name     = "l4_wkup_clkdm",
2807         .prcm = {
2808                 .omap4 = {
2809                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2810                 },
2811         },
2812 };
2813
2814 /*
2815  * 'sl2if' class
2816  * shared level 2 memory interface
2817  */
2818
2819 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2820         .name   = "sl2if",
2821 };
2822
2823 /* sl2if */
2824 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2825         .name           = "sl2if",
2826         .class          = &omap44xx_sl2if_hwmod_class,
2827         .clkdm_name     = "ivahd_clkdm",
2828         .prcm = {
2829                 .omap4 = {
2830                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2831                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2832                         .modulemode   = MODULEMODE_HWCTRL,
2833                 },
2834         },
2835 };
2836
2837 /*
2838  * 'slimbus' class
2839  * bidirectional, multi-drop, multi-channel two-line serial interface between
2840  * the device and external components
2841  */
2842
2843 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2844         .rev_offs       = 0x0000,
2845         .sysc_offs      = 0x0010,
2846         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2847                            SYSC_HAS_SOFTRESET),
2848         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2849                            SIDLE_SMART_WKUP),
2850         .sysc_fields    = &omap_hwmod_sysc_type2,
2851 };
2852
2853 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2854         .name   = "slimbus",
2855         .sysc   = &omap44xx_slimbus_sysc,
2856 };
2857
2858 /* slimbus1 */
2859 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2860         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2861         { .irq = -1 }
2862 };
2863
2864 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2865         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2866         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2867         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2868         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2869         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2870         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2871         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2872         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2873         { .dma_req = -1 }
2874 };
2875
2876 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2877         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2878         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2879         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2880         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2881 };
2882
2883 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2884         .name           = "slimbus1",
2885         .class          = &omap44xx_slimbus_hwmod_class,
2886         .clkdm_name     = "abe_clkdm",
2887         .mpu_irqs       = omap44xx_slimbus1_irqs,
2888         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2889         .prcm = {
2890                 .omap4 = {
2891                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2892                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2893                         .modulemode   = MODULEMODE_SWCTRL,
2894                 },
2895         },
2896         .opt_clks       = slimbus1_opt_clks,
2897         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2898 };
2899
2900 /* slimbus2 */
2901 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2902         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2903         { .irq = -1 }
2904 };
2905
2906 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2907         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2908         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2909         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2910         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2911         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2912         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2913         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2914         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2915         { .dma_req = -1 }
2916 };
2917
2918 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2919         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2920         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2921         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2922 };
2923
2924 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2925         .name           = "slimbus2",
2926         .class          = &omap44xx_slimbus_hwmod_class,
2927         .clkdm_name     = "l4_per_clkdm",
2928         .mpu_irqs       = omap44xx_slimbus2_irqs,
2929         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2930         .prcm = {
2931                 .omap4 = {
2932                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2933                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2934                         .modulemode   = MODULEMODE_SWCTRL,
2935                 },
2936         },
2937         .opt_clks       = slimbus2_opt_clks,
2938         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2939 };
2940
2941 /*
2942  * 'smartreflex' class
2943  * smartreflex module (monitor silicon performance and outputs a measure of
2944  * performance error)
2945  */
2946
2947 /* The IP is not compliant to type1 / type2 scheme */
2948 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2949         .sidle_shift    = 24,
2950         .enwkup_shift   = 26,
2951 };
2952
2953 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2954         .sysc_offs      = 0x0038,
2955         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2956         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2957                            SIDLE_SMART_WKUP),
2958         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2959 };
2960
2961 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2962         .name   = "smartreflex",
2963         .sysc   = &omap44xx_smartreflex_sysc,
2964         .rev    = 2,
2965 };
2966
2967 /* smartreflex_core */
2968 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2969         .sensor_voltdm_name   = "core",
2970 };
2971
2972 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2973         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2974         { .irq = -1 }
2975 };
2976
2977 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2978         .name           = "smartreflex_core",
2979         .class          = &omap44xx_smartreflex_hwmod_class,
2980         .clkdm_name     = "l4_ao_clkdm",
2981         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2982
2983         .main_clk       = "smartreflex_core_fck",
2984         .prcm = {
2985                 .omap4 = {
2986                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2987                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2988                         .modulemode   = MODULEMODE_SWCTRL,
2989                 },
2990         },
2991         .dev_attr       = &smartreflex_core_dev_attr,
2992 };
2993
2994 /* smartreflex_iva */
2995 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2996         .sensor_voltdm_name     = "iva",
2997 };
2998
2999 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3000         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3001         { .irq = -1 }
3002 };
3003
3004 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3005         .name           = "smartreflex_iva",
3006         .class          = &omap44xx_smartreflex_hwmod_class,
3007         .clkdm_name     = "l4_ao_clkdm",
3008         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3009         .main_clk       = "smartreflex_iva_fck",
3010         .prcm = {
3011                 .omap4 = {
3012                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3013                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3014                         .modulemode   = MODULEMODE_SWCTRL,
3015                 },
3016         },
3017         .dev_attr       = &smartreflex_iva_dev_attr,
3018 };
3019
3020 /* smartreflex_mpu */
3021 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3022         .sensor_voltdm_name     = "mpu",
3023 };
3024
3025 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3026         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3027         { .irq = -1 }
3028 };
3029
3030 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3031         .name           = "smartreflex_mpu",
3032         .class          = &omap44xx_smartreflex_hwmod_class,
3033         .clkdm_name     = "l4_ao_clkdm",
3034         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3035         .main_clk       = "smartreflex_mpu_fck",
3036         .prcm = {
3037                 .omap4 = {
3038                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3039                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3040                         .modulemode   = MODULEMODE_SWCTRL,
3041                 },
3042         },
3043         .dev_attr       = &smartreflex_mpu_dev_attr,
3044 };
3045
3046 /*
3047  * 'spinlock' class
3048  * spinlock provides hardware assistance for synchronizing the processes
3049  * running on multiple processors
3050  */
3051
3052 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3053         .rev_offs       = 0x0000,
3054         .sysc_offs      = 0x0010,
3055         .syss_offs      = 0x0014,
3056         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3057                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3058                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3059         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3060                            SIDLE_SMART_WKUP),
3061         .sysc_fields    = &omap_hwmod_sysc_type1,
3062 };
3063
3064 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3065         .name   = "spinlock",
3066         .sysc   = &omap44xx_spinlock_sysc,
3067 };
3068
3069 /* spinlock */
3070 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3071         .name           = "spinlock",
3072         .class          = &omap44xx_spinlock_hwmod_class,
3073         .clkdm_name     = "l4_cfg_clkdm",
3074         .prcm = {
3075                 .omap4 = {
3076                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3077                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3078                 },
3079         },
3080 };
3081
3082 /*
3083  * 'timer' class
3084  * general purpose timer module with accurate 1ms tick
3085  * This class contains several variants: ['timer_1ms', 'timer']
3086  */
3087
3088 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3089         .rev_offs       = 0x0000,
3090         .sysc_offs      = 0x0010,
3091         .syss_offs      = 0x0014,
3092         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3093                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3094                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3095                            SYSS_HAS_RESET_STATUS),
3096         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3097         .sysc_fields    = &omap_hwmod_sysc_type1,
3098 };
3099
3100 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3101         .name   = "timer",
3102         .sysc   = &omap44xx_timer_1ms_sysc,
3103 };
3104
3105 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3106         .rev_offs       = 0x0000,
3107         .sysc_offs      = 0x0010,
3108         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3109                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3110         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3111                            SIDLE_SMART_WKUP),
3112         .sysc_fields    = &omap_hwmod_sysc_type2,
3113 };
3114
3115 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3116         .name   = "timer",
3117         .sysc   = &omap44xx_timer_sysc,
3118 };
3119
3120 /* always-on timers dev attribute */
3121 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3122         .timer_capability       = OMAP_TIMER_ALWON,
3123 };
3124
3125 /* pwm timers dev attribute */
3126 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3127         .timer_capability       = OMAP_TIMER_HAS_PWM,
3128 };
3129
3130 /* timers with DSP interrupt dev attribute */
3131 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3132         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3133 };
3134
3135 /* pwm timers with DSP interrupt dev attribute */
3136 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3137         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3138 };
3139
3140 /* timer1 */
3141 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3142         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3143         { .irq = -1 }
3144 };
3145
3146 static struct omap_hwmod omap44xx_timer1_hwmod = {
3147         .name           = "timer1",
3148         .class          = &omap44xx_timer_1ms_hwmod_class,
3149         .clkdm_name     = "l4_wkup_clkdm",
3150         .mpu_irqs       = omap44xx_timer1_irqs,
3151         .main_clk       = "timer1_fck",
3152         .prcm = {
3153                 .omap4 = {
3154                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3155                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3156                         .modulemode   = MODULEMODE_SWCTRL,
3157                 },
3158         },
3159         .dev_attr       = &capability_alwon_dev_attr,
3160 };
3161
3162 /* timer2 */
3163 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3164         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3165         { .irq = -1 }
3166 };
3167
3168 static struct omap_hwmod omap44xx_timer2_hwmod = {
3169         .name           = "timer2",
3170         .class          = &omap44xx_timer_1ms_hwmod_class,
3171         .clkdm_name     = "l4_per_clkdm",
3172         .mpu_irqs       = omap44xx_timer2_irqs,
3173         .main_clk       = "timer2_fck",
3174         .prcm = {
3175                 .omap4 = {
3176                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3177                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3178                         .modulemode   = MODULEMODE_SWCTRL,
3179                 },
3180         },
3181 };
3182
3183 /* timer3 */
3184 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3185         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3186         { .irq = -1 }
3187 };
3188
3189 static struct omap_hwmod omap44xx_timer3_hwmod = {
3190         .name           = "timer3",
3191         .class          = &omap44xx_timer_hwmod_class,
3192         .clkdm_name     = "l4_per_clkdm",
3193         .mpu_irqs       = omap44xx_timer3_irqs,
3194         .main_clk       = "timer3_fck",
3195         .prcm = {
3196                 .omap4 = {
3197                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3198                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3199                         .modulemode   = MODULEMODE_SWCTRL,
3200                 },
3201         },
3202 };
3203
3204 /* timer4 */
3205 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3206         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3207         { .irq = -1 }
3208 };
3209
3210 static struct omap_hwmod omap44xx_timer4_hwmod = {
3211         .name           = "timer4",
3212         .class          = &omap44xx_timer_hwmod_class,
3213         .clkdm_name     = "l4_per_clkdm",
3214         .mpu_irqs       = omap44xx_timer4_irqs,
3215         .main_clk       = "timer4_fck",
3216         .prcm = {
3217                 .omap4 = {
3218                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3219                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3220                         .modulemode   = MODULEMODE_SWCTRL,
3221                 },
3222         },
3223 };
3224
3225 /* timer5 */
3226 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3227         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3228         { .irq = -1 }
3229 };
3230
3231 static struct omap_hwmod omap44xx_timer5_hwmod = {
3232         .name           = "timer5",
3233         .class          = &omap44xx_timer_hwmod_class,
3234         .clkdm_name     = "abe_clkdm",
3235         .mpu_irqs       = omap44xx_timer5_irqs,
3236         .main_clk       = "timer5_fck",
3237         .prcm = {
3238                 .omap4 = {
3239                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3240                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3241                         .modulemode   = MODULEMODE_SWCTRL,
3242                 },
3243         },
3244         .dev_attr       = &capability_dsp_dev_attr,
3245 };
3246
3247 /* timer6 */
3248 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3249         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3250         { .irq = -1 }
3251 };
3252
3253 static struct omap_hwmod omap44xx_timer6_hwmod = {
3254         .name           = "timer6",
3255         .class          = &omap44xx_timer_hwmod_class,
3256         .clkdm_name     = "abe_clkdm",
3257         .mpu_irqs       = omap44xx_timer6_irqs,
3258
3259         .main_clk       = "timer6_fck",
3260         .prcm = {
3261                 .omap4 = {
3262                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3263                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3264                         .modulemode   = MODULEMODE_SWCTRL,
3265                 },
3266         },
3267         .dev_attr       = &capability_dsp_dev_attr,
3268 };
3269
3270 /* timer7 */
3271 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3272         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3273         { .irq = -1 }
3274 };
3275
3276 static struct omap_hwmod omap44xx_timer7_hwmod = {
3277         .name           = "timer7",
3278         .class          = &omap44xx_timer_hwmod_class,
3279         .clkdm_name     = "abe_clkdm",
3280         .mpu_irqs       = omap44xx_timer7_irqs,
3281         .main_clk       = "timer7_fck",
3282         .prcm = {
3283                 .omap4 = {
3284                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3285                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3286                         .modulemode   = MODULEMODE_SWCTRL,
3287                 },
3288         },
3289         .dev_attr       = &capability_dsp_dev_attr,
3290 };
3291
3292 /* timer8 */
3293 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3294         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3295         { .irq = -1 }
3296 };
3297
3298 static struct omap_hwmod omap44xx_timer8_hwmod = {
3299         .name           = "timer8",
3300         .class          = &omap44xx_timer_hwmod_class,
3301         .clkdm_name     = "abe_clkdm",
3302         .mpu_irqs       = omap44xx_timer8_irqs,
3303         .main_clk       = "timer8_fck",
3304         .prcm = {
3305                 .omap4 = {
3306                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3307                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3308                         .modulemode   = MODULEMODE_SWCTRL,
3309                 },
3310         },
3311         .dev_attr       = &capability_dsp_pwm_dev_attr,
3312 };
3313
3314 /* timer9 */
3315 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3316         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3317         { .irq = -1 }
3318 };
3319
3320 static struct omap_hwmod omap44xx_timer9_hwmod = {
3321         .name           = "timer9",
3322         .class          = &omap44xx_timer_hwmod_class,
3323         .clkdm_name     = "l4_per_clkdm",
3324         .mpu_irqs       = omap44xx_timer9_irqs,
3325         .main_clk       = "timer9_fck",
3326         .prcm = {
3327                 .omap4 = {
3328                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3329                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3330                         .modulemode   = MODULEMODE_SWCTRL,
3331                 },
3332         },
3333         .dev_attr       = &capability_pwm_dev_attr,
3334 };
3335
3336 /* timer10 */
3337 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3338         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3339         { .irq = -1 }
3340 };
3341
3342 static struct omap_hwmod omap44xx_timer10_hwmod = {
3343         .name           = "timer10",
3344         .class          = &omap44xx_timer_1ms_hwmod_class,
3345         .clkdm_name     = "l4_per_clkdm",
3346         .mpu_irqs       = omap44xx_timer10_irqs,
3347         .main_clk       = "timer10_fck",
3348         .prcm = {
3349                 .omap4 = {
3350                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3351                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3352                         .modulemode   = MODULEMODE_SWCTRL,
3353                 },
3354         },
3355         .dev_attr       = &capability_pwm_dev_attr,
3356 };
3357
3358 /* timer11 */
3359 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3360         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3361         { .irq = -1 }
3362 };
3363
3364 static struct omap_hwmod omap44xx_timer11_hwmod = {
3365         .name           = "timer11",
3366         .class          = &omap44xx_timer_hwmod_class,
3367         .clkdm_name     = "l4_per_clkdm",
3368         .mpu_irqs       = omap44xx_timer11_irqs,
3369         .main_clk       = "timer11_fck",
3370         .prcm = {
3371                 .omap4 = {
3372                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3373                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3374                         .modulemode   = MODULEMODE_SWCTRL,
3375                 },
3376         },
3377         .dev_attr       = &capability_pwm_dev_attr,
3378 };
3379
3380 /*
3381  * 'uart' class
3382  * universal asynchronous receiver/transmitter (uart)
3383  */
3384
3385 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3386         .rev_offs       = 0x0050,
3387         .sysc_offs      = 0x0054,
3388         .syss_offs      = 0x0058,
3389         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3390                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3391                            SYSS_HAS_RESET_STATUS),
3392         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3393                            SIDLE_SMART_WKUP),
3394         .sysc_fields    = &omap_hwmod_sysc_type1,
3395 };
3396
3397 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3398         .name   = "uart",
3399         .sysc   = &omap44xx_uart_sysc,
3400 };
3401
3402 /* uart1 */
3403 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3404         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3405         { .irq = -1 }
3406 };
3407
3408 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3409         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3410         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3411         { .dma_req = -1 }
3412 };
3413
3414 static struct omap_hwmod omap44xx_uart1_hwmod = {
3415         .name           = "uart1",
3416         .class          = &omap44xx_uart_hwmod_class,
3417         .clkdm_name     = "l4_per_clkdm",
3418         .mpu_irqs       = omap44xx_uart1_irqs,
3419         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3420         .main_clk       = "uart1_fck",
3421         .prcm = {
3422                 .omap4 = {
3423                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3424                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3425                         .modulemode   = MODULEMODE_SWCTRL,
3426                 },
3427         },
3428 };
3429
3430 /* uart2 */
3431 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3432         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3433         { .irq = -1 }
3434 };
3435
3436 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3437         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3438         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3439         { .dma_req = -1 }
3440 };
3441
3442 static struct omap_hwmod omap44xx_uart2_hwmod = {
3443         .name           = "uart2",
3444         .class          = &omap44xx_uart_hwmod_class,
3445         .clkdm_name     = "l4_per_clkdm",
3446         .mpu_irqs       = omap44xx_uart2_irqs,
3447         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3448         .main_clk       = "uart2_fck",
3449         .prcm = {
3450                 .omap4 = {
3451                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3452                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3453                         .modulemode   = MODULEMODE_SWCTRL,
3454                 },
3455         },
3456 };
3457
3458 /* uart3 */
3459 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3460         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3461         { .irq = -1 }
3462 };
3463
3464 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3465         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3466         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3467         { .dma_req = -1 }
3468 };
3469
3470 static struct omap_hwmod omap44xx_uart3_hwmod = {
3471         .name           = "uart3",
3472         .class          = &omap44xx_uart_hwmod_class,
3473         .clkdm_name     = "l4_per_clkdm",
3474         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3475         .mpu_irqs       = omap44xx_uart3_irqs,
3476         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3477         .main_clk       = "uart3_fck",
3478         .prcm = {
3479                 .omap4 = {
3480                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3481                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3482                         .modulemode   = MODULEMODE_SWCTRL,
3483                 },
3484         },
3485 };
3486
3487 /* uart4 */
3488 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3489         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3490         { .irq = -1 }
3491 };
3492
3493 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3494         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3495         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3496         { .dma_req = -1 }
3497 };
3498
3499 static struct omap_hwmod omap44xx_uart4_hwmod = {
3500         .name           = "uart4",
3501         .class          = &omap44xx_uart_hwmod_class,
3502         .clkdm_name     = "l4_per_clkdm",
3503         .mpu_irqs       = omap44xx_uart4_irqs,
3504         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3505         .main_clk       = "uart4_fck",
3506         .prcm = {
3507                 .omap4 = {
3508                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3509                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3510                         .modulemode   = MODULEMODE_SWCTRL,
3511                 },
3512         },
3513 };
3514
3515 /*
3516  * 'usb_host_fs' class
3517  * full-speed usb host controller
3518  */
3519
3520 /* The IP is not compliant to type1 / type2 scheme */
3521 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3522         .midle_shift    = 4,
3523         .sidle_shift    = 2,
3524         .srst_shift     = 1,
3525 };
3526
3527 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3528         .rev_offs       = 0x0000,
3529         .sysc_offs      = 0x0210,
3530         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3531                            SYSC_HAS_SOFTRESET),
3532         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3533                            SIDLE_SMART_WKUP),
3534         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3535 };
3536
3537 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3538         .name   = "usb_host_fs",
3539         .sysc   = &omap44xx_usb_host_fs_sysc,
3540 };
3541
3542 /* usb_host_fs */
3543 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3544         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3545         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3546         { .irq = -1 }
3547 };
3548
3549 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3550         .name           = "usb_host_fs",
3551         .class          = &omap44xx_usb_host_fs_hwmod_class,
3552         .clkdm_name     = "l3_init_clkdm",
3553         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3554         .main_clk       = "usb_host_fs_fck",
3555         .prcm = {
3556                 .omap4 = {
3557                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3558                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3559                         .modulemode   = MODULEMODE_SWCTRL,
3560                 },
3561         },
3562 };
3563
3564 /*
3565  * 'usb_host_hs' class
3566  * high-speed multi-port usb host controller
3567  */
3568
3569 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3570         .rev_offs       = 0x0000,
3571         .sysc_offs      = 0x0010,
3572         .syss_offs      = 0x0014,
3573         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3574                            SYSC_HAS_SOFTRESET),
3575         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3576                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3577                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3578         .sysc_fields    = &omap_hwmod_sysc_type2,
3579 };
3580
3581 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3582         .name   = "usb_host_hs",
3583         .sysc   = &omap44xx_usb_host_hs_sysc,
3584 };
3585
3586 /* usb_host_hs */
3587 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3588         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3589         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3590         { .irq = -1 }
3591 };
3592
3593 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3594         .name           = "usb_host_hs",
3595         .class          = &omap44xx_usb_host_hs_hwmod_class,
3596         .clkdm_name     = "l3_init_clkdm",
3597         .main_clk       = "usb_host_hs_fck",
3598         .prcm = {
3599                 .omap4 = {
3600                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3601                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3602                         .modulemode   = MODULEMODE_SWCTRL,
3603                 },
3604         },
3605         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3606
3607         /*
3608          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3609          * id: i660
3610          *
3611          * Description:
3612          * In the following configuration :
3613          * - USBHOST module is set to smart-idle mode
3614          * - PRCM asserts idle_req to the USBHOST module ( This typically
3615          *   happens when the system is going to a low power mode : all ports
3616          *   have been suspended, the master part of the USBHOST module has
3617          *   entered the standby state, and SW has cut the functional clocks)
3618          * - an USBHOST interrupt occurs before the module is able to answer
3619          *   idle_ack, typically a remote wakeup IRQ.
3620          * Then the USB HOST module will enter a deadlock situation where it
3621          * is no more accessible nor functional.
3622          *
3623          * Workaround:
3624          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3625          */
3626
3627         /*
3628          * Errata: USB host EHCI may stall when entering smart-standby mode
3629          * Id: i571
3630          *
3631          * Description:
3632          * When the USBHOST module is set to smart-standby mode, and when it is
3633          * ready to enter the standby state (i.e. all ports are suspended and
3634          * all attached devices are in suspend mode), then it can wrongly assert
3635          * the Mstandby signal too early while there are still some residual OCP
3636          * transactions ongoing. If this condition occurs, the internal state
3637          * machine may go to an undefined state and the USB link may be stuck
3638          * upon the next resume.
3639          *
3640          * Workaround:
3641          * Don't use smart standby; use only force standby,
3642          * hence HWMOD_SWSUP_MSTANDBY
3643          */
3644
3645         /*
3646          * During system boot; If the hwmod framework resets the module
3647          * the module will have smart idle settings; which can lead to deadlock
3648          * (above Errata Id:i660); so, dont reset the module during boot;
3649          * Use HWMOD_INIT_NO_RESET.
3650          */
3651
3652         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3653                           HWMOD_INIT_NO_RESET,
3654 };
3655
3656 /*
3657  * 'usb_otg_hs' class
3658  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3659  */
3660
3661 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3662         .rev_offs       = 0x0400,
3663         .sysc_offs      = 0x0404,
3664         .syss_offs      = 0x0408,
3665         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3666                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3667                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3668         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3669                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3670                            MSTANDBY_SMART),
3671         .sysc_fields    = &omap_hwmod_sysc_type1,
3672 };
3673
3674 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3675         .name   = "usb_otg_hs",
3676         .sysc   = &omap44xx_usb_otg_hs_sysc,
3677 };
3678
3679 /* usb_otg_hs */
3680 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3681         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3682         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3683         { .irq = -1 }
3684 };
3685
3686 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3687         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3688 };
3689
3690 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3691         .name           = "usb_otg_hs",
3692         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3693         .clkdm_name     = "l3_init_clkdm",
3694         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3695         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3696         .main_clk       = "usb_otg_hs_ick",
3697         .prcm = {
3698                 .omap4 = {
3699                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3700                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3701                         .modulemode   = MODULEMODE_HWCTRL,
3702                 },
3703         },
3704         .opt_clks       = usb_otg_hs_opt_clks,
3705         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3706 };
3707
3708 /*
3709  * 'usb_tll_hs' class
3710  * usb_tll_hs module is the adapter on the usb_host_hs ports
3711  */
3712
3713 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3714         .rev_offs       = 0x0000,
3715         .sysc_offs      = 0x0010,
3716         .syss_offs      = 0x0014,
3717         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3718                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3719                            SYSC_HAS_AUTOIDLE),
3720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3721         .sysc_fields    = &omap_hwmod_sysc_type1,
3722 };
3723
3724 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3725         .name   = "usb_tll_hs",
3726         .sysc   = &omap44xx_usb_tll_hs_sysc,
3727 };
3728
3729 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3730         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3731         { .irq = -1 }
3732 };
3733
3734 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3735         .name           = "usb_tll_hs",
3736         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3737         .clkdm_name     = "l3_init_clkdm",
3738         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3739         .main_clk       = "usb_tll_hs_ick",
3740         .prcm = {
3741                 .omap4 = {
3742                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3743                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3744                         .modulemode   = MODULEMODE_HWCTRL,
3745                 },
3746         },
3747 };
3748
3749 /*
3750  * 'wd_timer' class
3751  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3752  * overflow condition
3753  */
3754
3755 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3756         .rev_offs       = 0x0000,
3757         .sysc_offs      = 0x0010,
3758         .syss_offs      = 0x0014,
3759         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3760                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3761         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3762                            SIDLE_SMART_WKUP),
3763         .sysc_fields    = &omap_hwmod_sysc_type1,
3764 };
3765
3766 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3767         .name           = "wd_timer",
3768         .sysc           = &omap44xx_wd_timer_sysc,
3769         .pre_shutdown   = &omap2_wd_timer_disable,
3770         .reset          = &omap2_wd_timer_reset,
3771 };
3772
3773 /* wd_timer2 */
3774 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3775         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3776         { .irq = -1 }
3777 };
3778
3779 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3780         .name           = "wd_timer2",
3781         .class          = &omap44xx_wd_timer_hwmod_class,
3782         .clkdm_name     = "l4_wkup_clkdm",
3783         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3784         .main_clk       = "wd_timer2_fck",
3785         .prcm = {
3786                 .omap4 = {
3787                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3788                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3789                         .modulemode   = MODULEMODE_SWCTRL,
3790                 },
3791         },
3792 };
3793
3794 /* wd_timer3 */
3795 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3796         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3797         { .irq = -1 }
3798 };
3799
3800 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3801         .name           = "wd_timer3",
3802         .class          = &omap44xx_wd_timer_hwmod_class,
3803         .clkdm_name     = "abe_clkdm",
3804         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3805         .main_clk       = "wd_timer3_fck",
3806         .prcm = {
3807                 .omap4 = {
3808                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3809                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3810                         .modulemode   = MODULEMODE_SWCTRL,
3811                 },
3812         },
3813 };
3814
3815
3816 /*
3817  * interfaces
3818  */
3819
3820 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3821         {
3822                 .pa_start       = 0x4a204000,
3823                 .pa_end         = 0x4a2040ff,
3824                 .flags          = ADDR_TYPE_RT
3825         },
3826         { }
3827 };
3828
3829 /* c2c -> c2c_target_fw */
3830 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3831         .master         = &omap44xx_c2c_hwmod,
3832         .slave          = &omap44xx_c2c_target_fw_hwmod,
3833         .clk            = "div_core_ck",
3834         .addr           = omap44xx_c2c_target_fw_addrs,
3835         .user           = OCP_USER_MPU,
3836 };
3837
3838 /* l4_cfg -> c2c_target_fw */
3839 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3840         .master         = &omap44xx_l4_cfg_hwmod,
3841         .slave          = &omap44xx_c2c_target_fw_hwmod,
3842         .clk            = "l4_div_ck",
3843         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3844 };
3845
3846 /* l3_main_1 -> dmm */
3847 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3848         .master         = &omap44xx_l3_main_1_hwmod,
3849         .slave          = &omap44xx_dmm_hwmod,
3850         .clk            = "l3_div_ck",
3851         .user           = OCP_USER_SDMA,
3852 };
3853
3854 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3855         {
3856                 .pa_start       = 0x4e000000,
3857                 .pa_end         = 0x4e0007ff,
3858                 .flags          = ADDR_TYPE_RT
3859         },
3860         { }
3861 };
3862
3863 /* mpu -> dmm */
3864 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3865         .master         = &omap44xx_mpu_hwmod,
3866         .slave          = &omap44xx_dmm_hwmod,
3867         .clk            = "l3_div_ck",
3868         .addr           = omap44xx_dmm_addrs,
3869         .user           = OCP_USER_MPU,
3870 };
3871
3872 /* c2c -> emif_fw */
3873 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3874         .master         = &omap44xx_c2c_hwmod,
3875         .slave          = &omap44xx_emif_fw_hwmod,
3876         .clk            = "div_core_ck",
3877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3878 };
3879
3880 /* dmm -> emif_fw */
3881 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3882         .master         = &omap44xx_dmm_hwmod,
3883         .slave          = &omap44xx_emif_fw_hwmod,
3884         .clk            = "l3_div_ck",
3885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3886 };
3887
3888 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3889         {
3890                 .pa_start       = 0x4a20c000,
3891                 .pa_end         = 0x4a20c0ff,
3892                 .flags          = ADDR_TYPE_RT
3893         },
3894         { }
3895 };
3896
3897 /* l4_cfg -> emif_fw */
3898 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3899         .master         = &omap44xx_l4_cfg_hwmod,
3900         .slave          = &omap44xx_emif_fw_hwmod,
3901         .clk            = "l4_div_ck",
3902         .addr           = omap44xx_emif_fw_addrs,
3903         .user           = OCP_USER_MPU,
3904 };
3905
3906 /* iva -> l3_instr */
3907 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3908         .master         = &omap44xx_iva_hwmod,
3909         .slave          = &omap44xx_l3_instr_hwmod,
3910         .clk            = "l3_div_ck",
3911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3912 };
3913
3914 /* l3_main_3 -> l3_instr */
3915 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3916         .master         = &omap44xx_l3_main_3_hwmod,
3917         .slave          = &omap44xx_l3_instr_hwmod,
3918         .clk            = "l3_div_ck",
3919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3920 };
3921
3922 /* ocp_wp_noc -> l3_instr */
3923 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3924         .master         = &omap44xx_ocp_wp_noc_hwmod,
3925         .slave          = &omap44xx_l3_instr_hwmod,
3926         .clk            = "l3_div_ck",
3927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3928 };
3929
3930 /* dsp -> l3_main_1 */
3931 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3932         .master         = &omap44xx_dsp_hwmod,
3933         .slave          = &omap44xx_l3_main_1_hwmod,
3934         .clk            = "l3_div_ck",
3935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3936 };
3937
3938 /* dss -> l3_main_1 */
3939 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3940         .master         = &omap44xx_dss_hwmod,
3941         .slave          = &omap44xx_l3_main_1_hwmod,
3942         .clk            = "l3_div_ck",
3943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3944 };
3945
3946 /* l3_main_2 -> l3_main_1 */
3947 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3948         .master         = &omap44xx_l3_main_2_hwmod,
3949         .slave          = &omap44xx_l3_main_1_hwmod,
3950         .clk            = "l3_div_ck",
3951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3952 };
3953
3954 /* l4_cfg -> l3_main_1 */
3955 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3956         .master         = &omap44xx_l4_cfg_hwmod,
3957         .slave          = &omap44xx_l3_main_1_hwmod,
3958         .clk            = "l4_div_ck",
3959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3960 };
3961
3962 /* mmc1 -> l3_main_1 */
3963 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3964         .master         = &omap44xx_mmc1_hwmod,
3965         .slave          = &omap44xx_l3_main_1_hwmod,
3966         .clk            = "l3_div_ck",
3967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3969
3970 /* mmc2 -> l3_main_1 */
3971 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3972         .master         = &omap44xx_mmc2_hwmod,
3973         .slave          = &omap44xx_l3_main_1_hwmod,
3974         .clk            = "l3_div_ck",
3975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3979         {
3980                 .pa_start       = 0x44000000,
3981                 .pa_end         = 0x44000fff,
3982                 .flags          = ADDR_TYPE_RT
3983         },
3984         { }
3985 };
3986
3987 /* mpu -> l3_main_1 */
3988 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3989         .master         = &omap44xx_mpu_hwmod,
3990         .slave          = &omap44xx_l3_main_1_hwmod,
3991         .clk            = "l3_div_ck",
3992         .addr           = omap44xx_l3_main_1_addrs,
3993         .user           = OCP_USER_MPU,
3994 };
3995
3996 /* c2c_target_fw -> l3_main_2 */
3997 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3998         .master         = &omap44xx_c2c_target_fw_hwmod,
3999         .slave          = &omap44xx_l3_main_2_hwmod,
4000         .clk            = "l3_div_ck",
4001         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4002 };
4003
4004 /* debugss -> l3_main_2 */
4005 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4006         .master         = &omap44xx_debugss_hwmod,
4007         .slave          = &omap44xx_l3_main_2_hwmod,
4008         .clk            = "dbgclk_mux_ck",
4009         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4010 };
4011
4012 /* dma_system -> l3_main_2 */
4013 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4014         .master         = &omap44xx_dma_system_hwmod,
4015         .slave          = &omap44xx_l3_main_2_hwmod,
4016         .clk            = "l3_div_ck",
4017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4018 };
4019
4020 /* fdif -> l3_main_2 */
4021 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4022         .master         = &omap44xx_fdif_hwmod,
4023         .slave          = &omap44xx_l3_main_2_hwmod,
4024         .clk            = "l3_div_ck",
4025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4026 };
4027
4028 /* gpu -> l3_main_2 */
4029 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4030         .master         = &omap44xx_gpu_hwmod,
4031         .slave          = &omap44xx_l3_main_2_hwmod,
4032         .clk            = "l3_div_ck",
4033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4034 };
4035
4036 /* hsi -> l3_main_2 */
4037 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4038         .master         = &omap44xx_hsi_hwmod,
4039         .slave          = &omap44xx_l3_main_2_hwmod,
4040         .clk            = "l3_div_ck",
4041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 /* ipu -> l3_main_2 */
4045 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4046         .master         = &omap44xx_ipu_hwmod,
4047         .slave          = &omap44xx_l3_main_2_hwmod,
4048         .clk            = "l3_div_ck",
4049         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4050 };
4051
4052 /* iss -> l3_main_2 */
4053 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4054         .master         = &omap44xx_iss_hwmod,
4055         .slave          = &omap44xx_l3_main_2_hwmod,
4056         .clk            = "l3_div_ck",
4057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4058 };
4059
4060 /* iva -> l3_main_2 */
4061 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4062         .master         = &omap44xx_iva_hwmod,
4063         .slave          = &omap44xx_l3_main_2_hwmod,
4064         .clk            = "l3_div_ck",
4065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4066 };
4067
4068 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4069         {
4070                 .pa_start       = 0x44800000,
4071                 .pa_end         = 0x44801fff,
4072                 .flags          = ADDR_TYPE_RT
4073         },
4074         { }
4075 };
4076
4077 /* l3_main_1 -> l3_main_2 */
4078 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4079         .master         = &omap44xx_l3_main_1_hwmod,
4080         .slave          = &omap44xx_l3_main_2_hwmod,
4081         .clk            = "l3_div_ck",
4082         .addr           = omap44xx_l3_main_2_addrs,
4083         .user           = OCP_USER_MPU,
4084 };
4085
4086 /* l4_cfg -> l3_main_2 */
4087 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4088         .master         = &omap44xx_l4_cfg_hwmod,
4089         .slave          = &omap44xx_l3_main_2_hwmod,
4090         .clk            = "l4_div_ck",
4091         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4092 };
4093
4094 /* usb_host_fs -> l3_main_2 */
4095 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4096         .master         = &omap44xx_usb_host_fs_hwmod,
4097         .slave          = &omap44xx_l3_main_2_hwmod,
4098         .clk            = "l3_div_ck",
4099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4100 };
4101
4102 /* usb_host_hs -> l3_main_2 */
4103 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4104         .master         = &omap44xx_usb_host_hs_hwmod,
4105         .slave          = &omap44xx_l3_main_2_hwmod,
4106         .clk            = "l3_div_ck",
4107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4108 };
4109
4110 /* usb_otg_hs -> l3_main_2 */
4111 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4112         .master         = &omap44xx_usb_otg_hs_hwmod,
4113         .slave          = &omap44xx_l3_main_2_hwmod,
4114         .clk            = "l3_div_ck",
4115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4116 };
4117
4118 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4119         {
4120                 .pa_start       = 0x45000000,
4121                 .pa_end         = 0x45000fff,
4122                 .flags          = ADDR_TYPE_RT
4123         },
4124         { }
4125 };
4126
4127 /* l3_main_1 -> l3_main_3 */
4128 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4129         .master         = &omap44xx_l3_main_1_hwmod,
4130         .slave          = &omap44xx_l3_main_3_hwmod,
4131         .clk            = "l3_div_ck",
4132         .addr           = omap44xx_l3_main_3_addrs,
4133         .user           = OCP_USER_MPU,
4134 };
4135
4136 /* l3_main_2 -> l3_main_3 */
4137 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4138         .master         = &omap44xx_l3_main_2_hwmod,
4139         .slave          = &omap44xx_l3_main_3_hwmod,
4140         .clk            = "l3_div_ck",
4141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4142 };
4143
4144 /* l4_cfg -> l3_main_3 */
4145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4146         .master         = &omap44xx_l4_cfg_hwmod,
4147         .slave          = &omap44xx_l3_main_3_hwmod,
4148         .clk            = "l4_div_ck",
4149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4150 };
4151
4152 /* aess -> l4_abe */
4153 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4154         .master         = &omap44xx_aess_hwmod,
4155         .slave          = &omap44xx_l4_abe_hwmod,
4156         .clk            = "ocp_abe_iclk",
4157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4158 };
4159
4160 /* dsp -> l4_abe */
4161 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4162         .master         = &omap44xx_dsp_hwmod,
4163         .slave          = &omap44xx_l4_abe_hwmod,
4164         .clk            = "ocp_abe_iclk",
4165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4166 };
4167
4168 /* l3_main_1 -> l4_abe */
4169 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4170         .master         = &omap44xx_l3_main_1_hwmod,
4171         .slave          = &omap44xx_l4_abe_hwmod,
4172         .clk            = "l3_div_ck",
4173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4174 };
4175
4176 /* mpu -> l4_abe */
4177 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4178         .master         = &omap44xx_mpu_hwmod,
4179         .slave          = &omap44xx_l4_abe_hwmod,
4180         .clk            = "ocp_abe_iclk",
4181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4182 };
4183
4184 /* l3_main_1 -> l4_cfg */
4185 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4186         .master         = &omap44xx_l3_main_1_hwmod,
4187         .slave          = &omap44xx_l4_cfg_hwmod,
4188         .clk            = "l3_div_ck",
4189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4190 };
4191
4192 /* l3_main_2 -> l4_per */
4193 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4194         .master         = &omap44xx_l3_main_2_hwmod,
4195         .slave          = &omap44xx_l4_per_hwmod,
4196         .clk            = "l3_div_ck",
4197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4198 };
4199
4200 /* l4_cfg -> l4_wkup */
4201 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4202         .master         = &omap44xx_l4_cfg_hwmod,
4203         .slave          = &omap44xx_l4_wkup_hwmod,
4204         .clk            = "l4_div_ck",
4205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4206 };
4207
4208 /* mpu -> mpu_private */
4209 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4210         .master         = &omap44xx_mpu_hwmod,
4211         .slave          = &omap44xx_mpu_private_hwmod,
4212         .clk            = "l3_div_ck",
4213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4214 };
4215
4216 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4217         {
4218                 .pa_start       = 0x4a102000,
4219                 .pa_end         = 0x4a10207f,
4220                 .flags          = ADDR_TYPE_RT
4221         },
4222         { }
4223 };
4224
4225 /* l4_cfg -> ocp_wp_noc */
4226 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4227         .master         = &omap44xx_l4_cfg_hwmod,
4228         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4229         .clk            = "l4_div_ck",
4230         .addr           = omap44xx_ocp_wp_noc_addrs,
4231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4232 };
4233
4234 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4235         {
4236                 .pa_start       = 0x401f1000,
4237                 .pa_end         = 0x401f13ff,
4238                 .flags          = ADDR_TYPE_RT
4239         },
4240         { }
4241 };
4242
4243 /* l4_abe -> aess */
4244 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4245         .master         = &omap44xx_l4_abe_hwmod,
4246         .slave          = &omap44xx_aess_hwmod,
4247         .clk            = "ocp_abe_iclk",
4248         .addr           = omap44xx_aess_addrs,
4249         .user           = OCP_USER_MPU,
4250 };
4251
4252 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4253         {
4254                 .pa_start       = 0x490f1000,
4255                 .pa_end         = 0x490f13ff,
4256                 .flags          = ADDR_TYPE_RT
4257         },
4258         { }
4259 };
4260
4261 /* l4_abe -> aess (dma) */
4262 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4263         .master         = &omap44xx_l4_abe_hwmod,
4264         .slave          = &omap44xx_aess_hwmod,
4265         .clk            = "ocp_abe_iclk",
4266         .addr           = omap44xx_aess_dma_addrs,
4267         .user           = OCP_USER_SDMA,
4268 };
4269
4270 /* l3_main_2 -> c2c */
4271 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4272         .master         = &omap44xx_l3_main_2_hwmod,
4273         .slave          = &omap44xx_c2c_hwmod,
4274         .clk            = "l3_div_ck",
4275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4276 };
4277
4278 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4279         {
4280                 .pa_start       = 0x4a304000,
4281                 .pa_end         = 0x4a30401f,
4282                 .flags          = ADDR_TYPE_RT
4283         },
4284         { }
4285 };
4286
4287 /* l4_wkup -> counter_32k */
4288 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4289         .master         = &omap44xx_l4_wkup_hwmod,
4290         .slave          = &omap44xx_counter_32k_hwmod,
4291         .clk            = "l4_wkup_clk_mux_ck",
4292         .addr           = omap44xx_counter_32k_addrs,
4293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4294 };
4295
4296 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4297         {
4298                 .pa_start       = 0x4a002000,
4299                 .pa_end         = 0x4a0027ff,
4300                 .flags          = ADDR_TYPE_RT
4301         },
4302         { }
4303 };
4304
4305 /* l4_cfg -> ctrl_module_core */
4306 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4307         .master         = &omap44xx_l4_cfg_hwmod,
4308         .slave          = &omap44xx_ctrl_module_core_hwmod,
4309         .clk            = "l4_div_ck",
4310         .addr           = omap44xx_ctrl_module_core_addrs,
4311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4312 };
4313
4314 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4315         {
4316                 .pa_start       = 0x4a100000,
4317                 .pa_end         = 0x4a1007ff,
4318                 .flags          = ADDR_TYPE_RT
4319         },
4320         { }
4321 };
4322
4323 /* l4_cfg -> ctrl_module_pad_core */
4324 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4325         .master         = &omap44xx_l4_cfg_hwmod,
4326         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4327         .clk            = "l4_div_ck",
4328         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4330 };
4331
4332 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4333         {
4334                 .pa_start       = 0x4a30c000,
4335                 .pa_end         = 0x4a30c7ff,
4336                 .flags          = ADDR_TYPE_RT
4337         },
4338         { }
4339 };
4340
4341 /* l4_wkup -> ctrl_module_wkup */
4342 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4343         .master         = &omap44xx_l4_wkup_hwmod,
4344         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4345         .clk            = "l4_wkup_clk_mux_ck",
4346         .addr           = omap44xx_ctrl_module_wkup_addrs,
4347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4348 };
4349
4350 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4351         {
4352                 .pa_start       = 0x4a31e000,
4353                 .pa_end         = 0x4a31e7ff,
4354                 .flags          = ADDR_TYPE_RT
4355         },
4356         { }
4357 };
4358
4359 /* l4_wkup -> ctrl_module_pad_wkup */
4360 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4361         .master         = &omap44xx_l4_wkup_hwmod,
4362         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4363         .clk            = "l4_wkup_clk_mux_ck",
4364         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4366 };
4367
4368 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4369         {
4370                 .pa_start       = 0x54160000,
4371                 .pa_end         = 0x54167fff,
4372                 .flags          = ADDR_TYPE_RT
4373         },
4374         { }
4375 };
4376
4377 /* l3_instr -> debugss */
4378 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4379         .master         = &omap44xx_l3_instr_hwmod,
4380         .slave          = &omap44xx_debugss_hwmod,
4381         .clk            = "l3_div_ck",
4382         .addr           = omap44xx_debugss_addrs,
4383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4384 };
4385
4386 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4387         {
4388                 .pa_start       = 0x4a056000,
4389                 .pa_end         = 0x4a056fff,
4390                 .flags          = ADDR_TYPE_RT
4391         },
4392         { }
4393 };
4394
4395 /* l4_cfg -> dma_system */
4396 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4397         .master         = &omap44xx_l4_cfg_hwmod,
4398         .slave          = &omap44xx_dma_system_hwmod,
4399         .clk            = "l4_div_ck",
4400         .addr           = omap44xx_dma_system_addrs,
4401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4402 };
4403
4404 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4405         {
4406                 .name           = "mpu",
4407                 .pa_start       = 0x4012e000,
4408                 .pa_end         = 0x4012e07f,
4409                 .flags          = ADDR_TYPE_RT
4410         },
4411         { }
4412 };
4413
4414 /* l4_abe -> dmic */
4415 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4416         .master         = &omap44xx_l4_abe_hwmod,
4417         .slave          = &omap44xx_dmic_hwmod,
4418         .clk            = "ocp_abe_iclk",
4419         .addr           = omap44xx_dmic_addrs,
4420         .user           = OCP_USER_MPU,
4421 };
4422
4423 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4424         {
4425                 .name           = "dma",
4426                 .pa_start       = 0x4902e000,
4427                 .pa_end         = 0x4902e07f,
4428                 .flags          = ADDR_TYPE_RT
4429         },
4430         { }
4431 };
4432
4433 /* l4_abe -> dmic (dma) */
4434 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4435         .master         = &omap44xx_l4_abe_hwmod,
4436         .slave          = &omap44xx_dmic_hwmod,
4437         .clk            = "ocp_abe_iclk",
4438         .addr           = omap44xx_dmic_dma_addrs,
4439         .user           = OCP_USER_SDMA,
4440 };
4441
4442 /* dsp -> iva */
4443 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4444         .master         = &omap44xx_dsp_hwmod,
4445         .slave          = &omap44xx_iva_hwmod,
4446         .clk            = "dpll_iva_m5x2_ck",
4447         .user           = OCP_USER_DSP,
4448 };
4449
4450 /* dsp -> sl2if */
4451 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4452         .master         = &omap44xx_dsp_hwmod,
4453         .slave          = &omap44xx_sl2if_hwmod,
4454         .clk            = "dpll_iva_m5x2_ck",
4455         .user           = OCP_USER_DSP,
4456 };
4457
4458 /* l4_cfg -> dsp */
4459 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4460         .master         = &omap44xx_l4_cfg_hwmod,
4461         .slave          = &omap44xx_dsp_hwmod,
4462         .clk            = "l4_div_ck",
4463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4464 };
4465
4466 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4467         {
4468                 .pa_start       = 0x58000000,
4469                 .pa_end         = 0x5800007f,
4470                 .flags          = ADDR_TYPE_RT
4471         },
4472         { }
4473 };
4474
4475 /* l3_main_2 -> dss */
4476 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4477         .master         = &omap44xx_l3_main_2_hwmod,
4478         .slave          = &omap44xx_dss_hwmod,
4479         .clk            = "dss_fck",
4480         .addr           = omap44xx_dss_dma_addrs,
4481         .user           = OCP_USER_SDMA,
4482 };
4483
4484 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4485         {
4486                 .pa_start       = 0x48040000,
4487                 .pa_end         = 0x4804007f,
4488                 .flags          = ADDR_TYPE_RT
4489         },
4490         { }
4491 };
4492
4493 /* l4_per -> dss */
4494 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4495         .master         = &omap44xx_l4_per_hwmod,
4496         .slave          = &omap44xx_dss_hwmod,
4497         .clk            = "l4_div_ck",
4498         .addr           = omap44xx_dss_addrs,
4499         .user           = OCP_USER_MPU,
4500 };
4501
4502 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4503         {
4504                 .pa_start       = 0x58001000,
4505                 .pa_end         = 0x58001fff,
4506                 .flags          = ADDR_TYPE_RT
4507         },
4508         { }
4509 };
4510
4511 /* l3_main_2 -> dss_dispc */
4512 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4513         .master         = &omap44xx_l3_main_2_hwmod,
4514         .slave          = &omap44xx_dss_dispc_hwmod,
4515         .clk            = "dss_fck",
4516         .addr           = omap44xx_dss_dispc_dma_addrs,
4517         .user           = OCP_USER_SDMA,
4518 };
4519
4520 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4521         {
4522                 .pa_start       = 0x48041000,
4523                 .pa_end         = 0x48041fff,
4524                 .flags          = ADDR_TYPE_RT
4525         },
4526         { }
4527 };
4528
4529 /* l4_per -> dss_dispc */
4530 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4531         .master         = &omap44xx_l4_per_hwmod,
4532         .slave          = &omap44xx_dss_dispc_hwmod,
4533         .clk            = "l4_div_ck",
4534         .addr           = omap44xx_dss_dispc_addrs,
4535         .user           = OCP_USER_MPU,
4536 };
4537
4538 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4539         {
4540                 .pa_start       = 0x58004000,
4541                 .pa_end         = 0x580041ff,
4542                 .flags          = ADDR_TYPE_RT
4543         },
4544         { }
4545 };
4546
4547 /* l3_main_2 -> dss_dsi1 */
4548 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4549         .master         = &omap44xx_l3_main_2_hwmod,
4550         .slave          = &omap44xx_dss_dsi1_hwmod,
4551         .clk            = "dss_fck",
4552         .addr           = omap44xx_dss_dsi1_dma_addrs,
4553         .user           = OCP_USER_SDMA,
4554 };
4555
4556 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4557         {
4558                 .pa_start       = 0x48044000,
4559                 .pa_end         = 0x480441ff,
4560                 .flags          = ADDR_TYPE_RT
4561         },
4562         { }
4563 };
4564
4565 /* l4_per -> dss_dsi1 */
4566 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4567         .master         = &omap44xx_l4_per_hwmod,
4568         .slave          = &omap44xx_dss_dsi1_hwmod,
4569         .clk            = "l4_div_ck",
4570         .addr           = omap44xx_dss_dsi1_addrs,
4571         .user           = OCP_USER_MPU,
4572 };
4573
4574 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4575         {
4576                 .pa_start       = 0x58005000,
4577                 .pa_end         = 0x580051ff,
4578                 .flags          = ADDR_TYPE_RT
4579         },
4580         { }
4581 };
4582
4583 /* l3_main_2 -> dss_dsi2 */
4584 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4585         .master         = &omap44xx_l3_main_2_hwmod,
4586         .slave          = &omap44xx_dss_dsi2_hwmod,
4587         .clk            = "dss_fck",
4588         .addr           = omap44xx_dss_dsi2_dma_addrs,
4589         .user           = OCP_USER_SDMA,
4590 };
4591
4592 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4593         {
4594                 .pa_start       = 0x48045000,
4595                 .pa_end         = 0x480451ff,
4596                 .flags          = ADDR_TYPE_RT
4597         },
4598         { }
4599 };
4600
4601 /* l4_per -> dss_dsi2 */
4602 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4603         .master         = &omap44xx_l4_per_hwmod,
4604         .slave          = &omap44xx_dss_dsi2_hwmod,
4605         .clk            = "l4_div_ck",
4606         .addr           = omap44xx_dss_dsi2_addrs,
4607         .user           = OCP_USER_MPU,
4608 };
4609
4610 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4611         {
4612                 .pa_start       = 0x58006000,
4613                 .pa_end         = 0x58006fff,
4614                 .flags          = ADDR_TYPE_RT
4615         },
4616         { }
4617 };
4618
4619 /* l3_main_2 -> dss_hdmi */
4620 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4621         .master         = &omap44xx_l3_main_2_hwmod,
4622         .slave          = &omap44xx_dss_hdmi_hwmod,
4623         .clk            = "dss_fck",
4624         .addr           = omap44xx_dss_hdmi_dma_addrs,
4625         .user           = OCP_USER_SDMA,
4626 };
4627
4628 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4629         {
4630                 .pa_start       = 0x48046000,
4631                 .pa_end         = 0x48046fff,
4632                 .flags          = ADDR_TYPE_RT
4633         },
4634         { }
4635 };
4636
4637 /* l4_per -> dss_hdmi */
4638 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4639         .master         = &omap44xx_l4_per_hwmod,
4640         .slave          = &omap44xx_dss_hdmi_hwmod,
4641         .clk            = "l4_div_ck",
4642         .addr           = omap44xx_dss_hdmi_addrs,
4643         .user           = OCP_USER_MPU,
4644 };
4645
4646 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4647         {
4648                 .pa_start       = 0x58002000,
4649                 .pa_end         = 0x580020ff,
4650                 .flags          = ADDR_TYPE_RT
4651         },
4652         { }
4653 };
4654
4655 /* l3_main_2 -> dss_rfbi */
4656 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4657         .master         = &omap44xx_l3_main_2_hwmod,
4658         .slave          = &omap44xx_dss_rfbi_hwmod,
4659         .clk            = "dss_fck",
4660         .addr           = omap44xx_dss_rfbi_dma_addrs,
4661         .user           = OCP_USER_SDMA,
4662 };
4663
4664 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4665         {
4666                 .pa_start       = 0x48042000,
4667                 .pa_end         = 0x480420ff,
4668                 .flags          = ADDR_TYPE_RT
4669         },
4670         { }
4671 };
4672
4673 /* l4_per -> dss_rfbi */
4674 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4675         .master         = &omap44xx_l4_per_hwmod,
4676         .slave          = &omap44xx_dss_rfbi_hwmod,
4677         .clk            = "l4_div_ck",
4678         .addr           = omap44xx_dss_rfbi_addrs,
4679         .user           = OCP_USER_MPU,
4680 };
4681
4682 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4683         {
4684                 .pa_start       = 0x58003000,
4685                 .pa_end         = 0x580030ff,
4686                 .flags          = ADDR_TYPE_RT
4687         },
4688         { }
4689 };
4690
4691 /* l3_main_2 -> dss_venc */
4692 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4693         .master         = &omap44xx_l3_main_2_hwmod,
4694         .slave          = &omap44xx_dss_venc_hwmod,
4695         .clk            = "dss_fck",
4696         .addr           = omap44xx_dss_venc_dma_addrs,
4697         .user           = OCP_USER_SDMA,
4698 };
4699
4700 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4701         {
4702                 .pa_start       = 0x48043000,
4703                 .pa_end         = 0x480430ff,
4704                 .flags          = ADDR_TYPE_RT
4705         },
4706         { }
4707 };
4708
4709 /* l4_per -> dss_venc */
4710 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4711         .master         = &omap44xx_l4_per_hwmod,
4712         .slave          = &omap44xx_dss_venc_hwmod,
4713         .clk            = "l4_div_ck",
4714         .addr           = omap44xx_dss_venc_addrs,
4715         .user           = OCP_USER_MPU,
4716 };
4717
4718 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4719         {
4720                 .pa_start       = 0x48078000,
4721                 .pa_end         = 0x48078fff,
4722                 .flags          = ADDR_TYPE_RT
4723         },
4724         { }
4725 };
4726
4727 /* l4_per -> elm */
4728 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4729         .master         = &omap44xx_l4_per_hwmod,
4730         .slave          = &omap44xx_elm_hwmod,
4731         .clk            = "l4_div_ck",
4732         .addr           = omap44xx_elm_addrs,
4733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4734 };
4735
4736 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4737         {
4738                 .pa_start       = 0x4c000000,
4739                 .pa_end         = 0x4c0000ff,
4740                 .flags          = ADDR_TYPE_RT
4741         },
4742         { }
4743 };
4744
4745 /* emif_fw -> emif1 */
4746 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4747         .master         = &omap44xx_emif_fw_hwmod,
4748         .slave          = &omap44xx_emif1_hwmod,
4749         .clk            = "l3_div_ck",
4750         .addr           = omap44xx_emif1_addrs,
4751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4752 };
4753
4754 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4755         {
4756                 .pa_start       = 0x4d000000,
4757                 .pa_end         = 0x4d0000ff,
4758                 .flags          = ADDR_TYPE_RT
4759         },
4760         { }
4761 };
4762
4763 /* emif_fw -> emif2 */
4764 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4765         .master         = &omap44xx_emif_fw_hwmod,
4766         .slave          = &omap44xx_emif2_hwmod,
4767         .clk            = "l3_div_ck",
4768         .addr           = omap44xx_emif2_addrs,
4769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4770 };
4771
4772 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4773         {
4774                 .pa_start       = 0x4a10a000,
4775                 .pa_end         = 0x4a10a1ff,
4776                 .flags          = ADDR_TYPE_RT
4777         },
4778         { }
4779 };
4780
4781 /* l4_cfg -> fdif */
4782 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4783         .master         = &omap44xx_l4_cfg_hwmod,
4784         .slave          = &omap44xx_fdif_hwmod,
4785         .clk            = "l4_div_ck",
4786         .addr           = omap44xx_fdif_addrs,
4787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4788 };
4789
4790 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4791         {
4792                 .pa_start       = 0x4a310000,
4793                 .pa_end         = 0x4a3101ff,
4794                 .flags          = ADDR_TYPE_RT
4795         },
4796         { }
4797 };
4798
4799 /* l4_wkup -> gpio1 */
4800 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4801         .master         = &omap44xx_l4_wkup_hwmod,
4802         .slave          = &omap44xx_gpio1_hwmod,
4803         .clk            = "l4_wkup_clk_mux_ck",
4804         .addr           = omap44xx_gpio1_addrs,
4805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4806 };
4807
4808 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4809         {
4810                 .pa_start       = 0x48055000,
4811                 .pa_end         = 0x480551ff,
4812                 .flags          = ADDR_TYPE_RT
4813         },
4814         { }
4815 };
4816
4817 /* l4_per -> gpio2 */
4818 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4819         .master         = &omap44xx_l4_per_hwmod,
4820         .slave          = &omap44xx_gpio2_hwmod,
4821         .clk            = "l4_div_ck",
4822         .addr           = omap44xx_gpio2_addrs,
4823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4824 };
4825
4826 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4827         {
4828                 .pa_start       = 0x48057000,
4829                 .pa_end         = 0x480571ff,
4830                 .flags          = ADDR_TYPE_RT
4831         },
4832         { }
4833 };
4834
4835 /* l4_per -> gpio3 */
4836 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4837         .master         = &omap44xx_l4_per_hwmod,
4838         .slave          = &omap44xx_gpio3_hwmod,
4839         .clk            = "l4_div_ck",
4840         .addr           = omap44xx_gpio3_addrs,
4841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4842 };
4843
4844 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4845         {
4846                 .pa_start       = 0x48059000,
4847                 .pa_end         = 0x480591ff,
4848                 .flags          = ADDR_TYPE_RT
4849         },
4850         { }
4851 };
4852
4853 /* l4_per -> gpio4 */
4854 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4855         .master         = &omap44xx_l4_per_hwmod,
4856         .slave          = &omap44xx_gpio4_hwmod,
4857         .clk            = "l4_div_ck",
4858         .addr           = omap44xx_gpio4_addrs,
4859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4860 };
4861
4862 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4863         {
4864                 .pa_start       = 0x4805b000,
4865                 .pa_end         = 0x4805b1ff,
4866                 .flags          = ADDR_TYPE_RT
4867         },
4868         { }
4869 };
4870
4871 /* l4_per -> gpio5 */
4872 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4873         .master         = &omap44xx_l4_per_hwmod,
4874         .slave          = &omap44xx_gpio5_hwmod,
4875         .clk            = "l4_div_ck",
4876         .addr           = omap44xx_gpio5_addrs,
4877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4878 };
4879
4880 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4881         {
4882                 .pa_start       = 0x4805d000,
4883                 .pa_end         = 0x4805d1ff,
4884                 .flags          = ADDR_TYPE_RT
4885         },
4886         { }
4887 };
4888
4889 /* l4_per -> gpio6 */
4890 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4891         .master         = &omap44xx_l4_per_hwmod,
4892         .slave          = &omap44xx_gpio6_hwmod,
4893         .clk            = "l4_div_ck",
4894         .addr           = omap44xx_gpio6_addrs,
4895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4896 };
4897
4898 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4899         {
4900                 .pa_start       = 0x50000000,
4901                 .pa_end         = 0x500003ff,
4902                 .flags          = ADDR_TYPE_RT
4903         },
4904         { }
4905 };
4906
4907 /* l3_main_2 -> gpmc */
4908 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4909         .master         = &omap44xx_l3_main_2_hwmod,
4910         .slave          = &omap44xx_gpmc_hwmod,
4911         .clk            = "l3_div_ck",
4912         .addr           = omap44xx_gpmc_addrs,
4913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4914 };
4915
4916 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4917         {
4918                 .pa_start       = 0x56000000,
4919                 .pa_end         = 0x5600ffff,
4920                 .flags          = ADDR_TYPE_RT
4921         },
4922         { }
4923 };
4924
4925 /* l3_main_2 -> gpu */
4926 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4927         .master         = &omap44xx_l3_main_2_hwmod,
4928         .slave          = &omap44xx_gpu_hwmod,
4929         .clk            = "l3_div_ck",
4930         .addr           = omap44xx_gpu_addrs,
4931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4932 };
4933
4934 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4935         {
4936                 .pa_start       = 0x480b2000,
4937                 .pa_end         = 0x480b201f,
4938                 .flags          = ADDR_TYPE_RT
4939         },
4940         { }
4941 };
4942
4943 /* l4_per -> hdq1w */
4944 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4945         .master         = &omap44xx_l4_per_hwmod,
4946         .slave          = &omap44xx_hdq1w_hwmod,
4947         .clk            = "l4_div_ck",
4948         .addr           = omap44xx_hdq1w_addrs,
4949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4950 };
4951
4952 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4953         {
4954                 .pa_start       = 0x4a058000,
4955                 .pa_end         = 0x4a05bfff,
4956                 .flags          = ADDR_TYPE_RT
4957         },
4958         { }
4959 };
4960
4961 /* l4_cfg -> hsi */
4962 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4963         .master         = &omap44xx_l4_cfg_hwmod,
4964         .slave          = &omap44xx_hsi_hwmod,
4965         .clk            = "l4_div_ck",
4966         .addr           = omap44xx_hsi_addrs,
4967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4968 };
4969
4970 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4971         {
4972                 .pa_start       = 0x48070000,
4973                 .pa_end         = 0x480700ff,
4974                 .flags          = ADDR_TYPE_RT
4975         },
4976         { }
4977 };
4978
4979 /* l4_per -> i2c1 */
4980 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4981         .master         = &omap44xx_l4_per_hwmod,
4982         .slave          = &omap44xx_i2c1_hwmod,
4983         .clk            = "l4_div_ck",
4984         .addr           = omap44xx_i2c1_addrs,
4985         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4986 };
4987
4988 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4989         {
4990                 .pa_start       = 0x48072000,
4991                 .pa_end         = 0x480720ff,
4992                 .flags          = ADDR_TYPE_RT
4993         },
4994         { }
4995 };
4996
4997 /* l4_per -> i2c2 */
4998 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4999         .master         = &omap44xx_l4_per_hwmod,
5000         .slave          = &omap44xx_i2c2_hwmod,
5001         .clk            = "l4_div_ck",
5002         .addr           = omap44xx_i2c2_addrs,
5003         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5004 };
5005
5006 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5007         {
5008                 .pa_start       = 0x48060000,
5009                 .pa_end         = 0x480600ff,
5010                 .flags          = ADDR_TYPE_RT
5011         },
5012         { }
5013 };
5014
5015 /* l4_per -> i2c3 */
5016 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5017         .master         = &omap44xx_l4_per_hwmod,
5018         .slave          = &omap44xx_i2c3_hwmod,
5019         .clk            = "l4_div_ck",
5020         .addr           = omap44xx_i2c3_addrs,
5021         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5022 };
5023
5024 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5025         {
5026                 .pa_start       = 0x48350000,
5027                 .pa_end         = 0x483500ff,
5028                 .flags          = ADDR_TYPE_RT
5029         },
5030         { }
5031 };
5032
5033 /* l4_per -> i2c4 */
5034 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5035         .master         = &omap44xx_l4_per_hwmod,
5036         .slave          = &omap44xx_i2c4_hwmod,
5037         .clk            = "l4_div_ck",
5038         .addr           = omap44xx_i2c4_addrs,
5039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5040 };
5041
5042 /* l3_main_2 -> ipu */
5043 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5044         .master         = &omap44xx_l3_main_2_hwmod,
5045         .slave          = &omap44xx_ipu_hwmod,
5046         .clk            = "l3_div_ck",
5047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5048 };
5049
5050 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5051         {
5052                 .pa_start       = 0x52000000,
5053                 .pa_end         = 0x520000ff,
5054                 .flags          = ADDR_TYPE_RT
5055         },
5056         { }
5057 };
5058
5059 /* l3_main_2 -> iss */
5060 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5061         .master         = &omap44xx_l3_main_2_hwmod,
5062         .slave          = &omap44xx_iss_hwmod,
5063         .clk            = "l3_div_ck",
5064         .addr           = omap44xx_iss_addrs,
5065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5066 };
5067
5068 /* iva -> sl2if */
5069 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5070         .master         = &omap44xx_iva_hwmod,
5071         .slave          = &omap44xx_sl2if_hwmod,
5072         .clk            = "dpll_iva_m5x2_ck",
5073         .user           = OCP_USER_IVA,
5074 };
5075
5076 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5077         {
5078                 .pa_start       = 0x5a000000,
5079                 .pa_end         = 0x5a07ffff,
5080                 .flags          = ADDR_TYPE_RT
5081         },
5082         { }
5083 };
5084
5085 /* l3_main_2 -> iva */
5086 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5087         .master         = &omap44xx_l3_main_2_hwmod,
5088         .slave          = &omap44xx_iva_hwmod,
5089         .clk            = "l3_div_ck",
5090         .addr           = omap44xx_iva_addrs,
5091         .user           = OCP_USER_MPU,
5092 };
5093
5094 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5095         {
5096                 .pa_start       = 0x4a31c000,
5097                 .pa_end         = 0x4a31c07f,
5098                 .flags          = ADDR_TYPE_RT
5099         },
5100         { }
5101 };
5102
5103 /* l4_wkup -> kbd */
5104 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5105         .master         = &omap44xx_l4_wkup_hwmod,
5106         .slave          = &omap44xx_kbd_hwmod,
5107         .clk            = "l4_wkup_clk_mux_ck",
5108         .addr           = omap44xx_kbd_addrs,
5109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5110 };
5111
5112 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5113         {
5114                 .pa_start       = 0x4a0f4000,
5115                 .pa_end         = 0x4a0f41ff,
5116                 .flags          = ADDR_TYPE_RT
5117         },
5118         { }
5119 };
5120
5121 /* l4_cfg -> mailbox */
5122 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5123         .master         = &omap44xx_l4_cfg_hwmod,
5124         .slave          = &omap44xx_mailbox_hwmod,
5125         .clk            = "l4_div_ck",
5126         .addr           = omap44xx_mailbox_addrs,
5127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5128 };
5129
5130 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5131         {
5132                 .pa_start       = 0x40128000,
5133                 .pa_end         = 0x401283ff,
5134                 .flags          = ADDR_TYPE_RT
5135         },
5136         { }
5137 };
5138
5139 /* l4_abe -> mcasp */
5140 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5141         .master         = &omap44xx_l4_abe_hwmod,
5142         .slave          = &omap44xx_mcasp_hwmod,
5143         .clk            = "ocp_abe_iclk",
5144         .addr           = omap44xx_mcasp_addrs,
5145         .user           = OCP_USER_MPU,
5146 };
5147
5148 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5149         {
5150                 .pa_start       = 0x49028000,
5151                 .pa_end         = 0x490283ff,
5152                 .flags          = ADDR_TYPE_RT
5153         },
5154         { }
5155 };
5156
5157 /* l4_abe -> mcasp (dma) */
5158 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5159         .master         = &omap44xx_l4_abe_hwmod,
5160         .slave          = &omap44xx_mcasp_hwmod,
5161         .clk            = "ocp_abe_iclk",
5162         .addr           = omap44xx_mcasp_dma_addrs,
5163         .user           = OCP_USER_SDMA,
5164 };
5165
5166 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5167         {
5168                 .name           = "mpu",
5169                 .pa_start       = 0x40122000,
5170                 .pa_end         = 0x401220ff,
5171                 .flags          = ADDR_TYPE_RT
5172         },
5173         { }
5174 };
5175
5176 /* l4_abe -> mcbsp1 */
5177 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5178         .master         = &omap44xx_l4_abe_hwmod,
5179         .slave          = &omap44xx_mcbsp1_hwmod,
5180         .clk            = "ocp_abe_iclk",
5181         .addr           = omap44xx_mcbsp1_addrs,
5182         .user           = OCP_USER_MPU,
5183 };
5184
5185 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5186         {
5187                 .name           = "dma",
5188                 .pa_start       = 0x49022000,
5189                 .pa_end         = 0x490220ff,
5190                 .flags          = ADDR_TYPE_RT
5191         },
5192         { }
5193 };
5194
5195 /* l4_abe -> mcbsp1 (dma) */
5196 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5197         .master         = &omap44xx_l4_abe_hwmod,
5198         .slave          = &omap44xx_mcbsp1_hwmod,
5199         .clk            = "ocp_abe_iclk",
5200         .addr           = omap44xx_mcbsp1_dma_addrs,
5201         .user           = OCP_USER_SDMA,
5202 };
5203
5204 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5205         {
5206                 .name           = "mpu",
5207                 .pa_start       = 0x40124000,
5208                 .pa_end         = 0x401240ff,
5209                 .flags          = ADDR_TYPE_RT
5210         },
5211         { }
5212 };
5213
5214 /* l4_abe -> mcbsp2 */
5215 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5216         .master         = &omap44xx_l4_abe_hwmod,
5217         .slave          = &omap44xx_mcbsp2_hwmod,
5218         .clk            = "ocp_abe_iclk",
5219         .addr           = omap44xx_mcbsp2_addrs,
5220         .user           = OCP_USER_MPU,
5221 };
5222
5223 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5224         {
5225                 .name           = "dma",
5226                 .pa_start       = 0x49024000,
5227                 .pa_end         = 0x490240ff,
5228                 .flags          = ADDR_TYPE_RT
5229         },
5230         { }
5231 };
5232
5233 /* l4_abe -> mcbsp2 (dma) */
5234 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5235         .master         = &omap44xx_l4_abe_hwmod,
5236         .slave          = &omap44xx_mcbsp2_hwmod,
5237         .clk            = "ocp_abe_iclk",
5238         .addr           = omap44xx_mcbsp2_dma_addrs,
5239         .user           = OCP_USER_SDMA,
5240 };
5241
5242 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5243         {
5244                 .name           = "mpu",
5245                 .pa_start       = 0x40126000,
5246                 .pa_end         = 0x401260ff,
5247                 .flags          = ADDR_TYPE_RT
5248         },
5249         { }
5250 };
5251
5252 /* l4_abe -> mcbsp3 */
5253 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5254         .master         = &omap44xx_l4_abe_hwmod,
5255         .slave          = &omap44xx_mcbsp3_hwmod,
5256         .clk            = "ocp_abe_iclk",
5257         .addr           = omap44xx_mcbsp3_addrs,
5258         .user           = OCP_USER_MPU,
5259 };
5260
5261 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5262         {
5263                 .name           = "dma",
5264                 .pa_start       = 0x49026000,
5265                 .pa_end         = 0x490260ff,
5266                 .flags          = ADDR_TYPE_RT
5267         },
5268         { }
5269 };
5270
5271 /* l4_abe -> mcbsp3 (dma) */
5272 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5273         .master         = &omap44xx_l4_abe_hwmod,
5274         .slave          = &omap44xx_mcbsp3_hwmod,
5275         .clk            = "ocp_abe_iclk",
5276         .addr           = omap44xx_mcbsp3_dma_addrs,
5277         .user           = OCP_USER_SDMA,
5278 };
5279
5280 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5281         {
5282                 .pa_start       = 0x48096000,
5283                 .pa_end         = 0x480960ff,
5284                 .flags          = ADDR_TYPE_RT
5285         },
5286         { }
5287 };
5288
5289 /* l4_per -> mcbsp4 */
5290 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5291         .master         = &omap44xx_l4_per_hwmod,
5292         .slave          = &omap44xx_mcbsp4_hwmod,
5293         .clk            = "l4_div_ck",
5294         .addr           = omap44xx_mcbsp4_addrs,
5295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5296 };
5297
5298 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5299         {
5300                 .name           = "mpu",
5301                 .pa_start       = 0x40132000,
5302                 .pa_end         = 0x4013207f,
5303                 .flags          = ADDR_TYPE_RT
5304         },
5305         { }
5306 };
5307
5308 /* l4_abe -> mcpdm */
5309 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5310         .master         = &omap44xx_l4_abe_hwmod,
5311         .slave          = &omap44xx_mcpdm_hwmod,
5312         .clk            = "ocp_abe_iclk",
5313         .addr           = omap44xx_mcpdm_addrs,
5314         .user           = OCP_USER_MPU,
5315 };
5316
5317 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5318         {
5319                 .name           = "dma",
5320                 .pa_start       = 0x49032000,
5321                 .pa_end         = 0x4903207f,
5322                 .flags          = ADDR_TYPE_RT
5323         },
5324         { }
5325 };
5326
5327 /* l4_abe -> mcpdm (dma) */
5328 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5329         .master         = &omap44xx_l4_abe_hwmod,
5330         .slave          = &omap44xx_mcpdm_hwmod,
5331         .clk            = "ocp_abe_iclk",
5332         .addr           = omap44xx_mcpdm_dma_addrs,
5333         .user           = OCP_USER_SDMA,
5334 };
5335
5336 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5337         {
5338                 .pa_start       = 0x48098000,
5339                 .pa_end         = 0x480981ff,
5340                 .flags          = ADDR_TYPE_RT
5341         },
5342         { }
5343 };
5344
5345 /* l4_per -> mcspi1 */
5346 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5347         .master         = &omap44xx_l4_per_hwmod,
5348         .slave          = &omap44xx_mcspi1_hwmod,
5349         .clk            = "l4_div_ck",
5350         .addr           = omap44xx_mcspi1_addrs,
5351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5352 };
5353
5354 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5355         {
5356                 .pa_start       = 0x4809a000,
5357                 .pa_end         = 0x4809a1ff,
5358                 .flags          = ADDR_TYPE_RT
5359         },
5360         { }
5361 };
5362
5363 /* l4_per -> mcspi2 */
5364 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5365         .master         = &omap44xx_l4_per_hwmod,
5366         .slave          = &omap44xx_mcspi2_hwmod,
5367         .clk            = "l4_div_ck",
5368         .addr           = omap44xx_mcspi2_addrs,
5369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5370 };
5371
5372 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5373         {
5374                 .pa_start       = 0x480b8000,
5375                 .pa_end         = 0x480b81ff,
5376                 .flags          = ADDR_TYPE_RT
5377         },
5378         { }
5379 };
5380
5381 /* l4_per -> mcspi3 */
5382 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5383         .master         = &omap44xx_l4_per_hwmod,
5384         .slave          = &omap44xx_mcspi3_hwmod,
5385         .clk            = "l4_div_ck",
5386         .addr           = omap44xx_mcspi3_addrs,
5387         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5388 };
5389
5390 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5391         {
5392                 .pa_start       = 0x480ba000,
5393                 .pa_end         = 0x480ba1ff,
5394                 .flags          = ADDR_TYPE_RT
5395         },
5396         { }
5397 };
5398
5399 /* l4_per -> mcspi4 */
5400 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5401         .master         = &omap44xx_l4_per_hwmod,
5402         .slave          = &omap44xx_mcspi4_hwmod,
5403         .clk            = "l4_div_ck",
5404         .addr           = omap44xx_mcspi4_addrs,
5405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5406 };
5407
5408 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5409         {
5410                 .pa_start       = 0x4809c000,
5411                 .pa_end         = 0x4809c3ff,
5412                 .flags          = ADDR_TYPE_RT
5413         },
5414         { }
5415 };
5416
5417 /* l4_per -> mmc1 */
5418 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5419         .master         = &omap44xx_l4_per_hwmod,
5420         .slave          = &omap44xx_mmc1_hwmod,
5421         .clk            = "l4_div_ck",
5422         .addr           = omap44xx_mmc1_addrs,
5423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5424 };
5425
5426 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5427         {
5428                 .pa_start       = 0x480b4000,
5429                 .pa_end         = 0x480b43ff,
5430                 .flags          = ADDR_TYPE_RT
5431         },
5432         { }
5433 };
5434
5435 /* l4_per -> mmc2 */
5436 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5437         .master         = &omap44xx_l4_per_hwmod,
5438         .slave          = &omap44xx_mmc2_hwmod,
5439         .clk            = "l4_div_ck",
5440         .addr           = omap44xx_mmc2_addrs,
5441         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5442 };
5443
5444 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5445         {
5446                 .pa_start       = 0x480ad000,
5447                 .pa_end         = 0x480ad3ff,
5448                 .flags          = ADDR_TYPE_RT
5449         },
5450         { }
5451 };
5452
5453 /* l4_per -> mmc3 */
5454 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5455         .master         = &omap44xx_l4_per_hwmod,
5456         .slave          = &omap44xx_mmc3_hwmod,
5457         .clk            = "l4_div_ck",
5458         .addr           = omap44xx_mmc3_addrs,
5459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5460 };
5461
5462 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5463         {
5464                 .pa_start       = 0x480d1000,
5465                 .pa_end         = 0x480d13ff,
5466                 .flags          = ADDR_TYPE_RT
5467         },
5468         { }
5469 };
5470
5471 /* l4_per -> mmc4 */
5472 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5473         .master         = &omap44xx_l4_per_hwmod,
5474         .slave          = &omap44xx_mmc4_hwmod,
5475         .clk            = "l4_div_ck",
5476         .addr           = omap44xx_mmc4_addrs,
5477         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5478 };
5479
5480 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5481         {
5482                 .pa_start       = 0x480d5000,
5483                 .pa_end         = 0x480d53ff,
5484                 .flags          = ADDR_TYPE_RT
5485         },
5486         { }
5487 };
5488
5489 /* l4_per -> mmc5 */
5490 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5491         .master         = &omap44xx_l4_per_hwmod,
5492         .slave          = &omap44xx_mmc5_hwmod,
5493         .clk            = "l4_div_ck",
5494         .addr           = omap44xx_mmc5_addrs,
5495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5496 };
5497
5498 /* l3_main_2 -> ocmc_ram */
5499 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5500         .master         = &omap44xx_l3_main_2_hwmod,
5501         .slave          = &omap44xx_ocmc_ram_hwmod,
5502         .clk            = "l3_div_ck",
5503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5504 };
5505
5506 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5507         {
5508                 .pa_start       = 0x4a0ad000,
5509                 .pa_end         = 0x4a0ad01f,
5510                 .flags          = ADDR_TYPE_RT
5511         },
5512         { }
5513 };
5514
5515 /* l4_cfg -> ocp2scp_usb_phy */
5516 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5517         .master         = &omap44xx_l4_cfg_hwmod,
5518         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5519         .clk            = "l4_div_ck",
5520         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5522 };
5523
5524 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5525         {
5526                 .pa_start       = 0x48243000,
5527                 .pa_end         = 0x48243fff,
5528                 .flags          = ADDR_TYPE_RT
5529         },
5530         { }
5531 };
5532
5533 /* mpu_private -> prcm_mpu */
5534 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5535         .master         = &omap44xx_mpu_private_hwmod,
5536         .slave          = &omap44xx_prcm_mpu_hwmod,
5537         .clk            = "l3_div_ck",
5538         .addr           = omap44xx_prcm_mpu_addrs,
5539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5540 };
5541
5542 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5543         {
5544                 .pa_start       = 0x4a004000,
5545                 .pa_end         = 0x4a004fff,
5546                 .flags          = ADDR_TYPE_RT
5547         },
5548         { }
5549 };
5550
5551 /* l4_wkup -> cm_core_aon */
5552 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5553         .master         = &omap44xx_l4_wkup_hwmod,
5554         .slave          = &omap44xx_cm_core_aon_hwmod,
5555         .clk            = "l4_wkup_clk_mux_ck",
5556         .addr           = omap44xx_cm_core_aon_addrs,
5557         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5558 };
5559
5560 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5561         {
5562                 .pa_start       = 0x4a008000,
5563                 .pa_end         = 0x4a009fff,
5564                 .flags          = ADDR_TYPE_RT
5565         },
5566         { }
5567 };
5568
5569 /* l4_cfg -> cm_core */
5570 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5571         .master         = &omap44xx_l4_cfg_hwmod,
5572         .slave          = &omap44xx_cm_core_hwmod,
5573         .clk            = "l4_div_ck",
5574         .addr           = omap44xx_cm_core_addrs,
5575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5576 };
5577
5578 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5579         {
5580                 .pa_start       = 0x4a306000,
5581                 .pa_end         = 0x4a307fff,
5582                 .flags          = ADDR_TYPE_RT
5583         },
5584         { }
5585 };
5586
5587 /* l4_wkup -> prm */
5588 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5589         .master         = &omap44xx_l4_wkup_hwmod,
5590         .slave          = &omap44xx_prm_hwmod,
5591         .clk            = "l4_wkup_clk_mux_ck",
5592         .addr           = omap44xx_prm_addrs,
5593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5594 };
5595
5596 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5597         {
5598                 .pa_start       = 0x4a30a000,
5599                 .pa_end         = 0x4a30a7ff,
5600                 .flags          = ADDR_TYPE_RT
5601         },
5602         { }
5603 };
5604
5605 /* l4_wkup -> scrm */
5606 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5607         .master         = &omap44xx_l4_wkup_hwmod,
5608         .slave          = &omap44xx_scrm_hwmod,
5609         .clk            = "l4_wkup_clk_mux_ck",
5610         .addr           = omap44xx_scrm_addrs,
5611         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5612 };
5613
5614 /* l3_main_2 -> sl2if */
5615 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5616         .master         = &omap44xx_l3_main_2_hwmod,
5617         .slave          = &omap44xx_sl2if_hwmod,
5618         .clk            = "l3_div_ck",
5619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5620 };
5621
5622 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5623         {
5624                 .pa_start       = 0x4012c000,
5625                 .pa_end         = 0x4012c3ff,
5626                 .flags          = ADDR_TYPE_RT
5627         },
5628         { }
5629 };
5630
5631 /* l4_abe -> slimbus1 */
5632 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5633         .master         = &omap44xx_l4_abe_hwmod,
5634         .slave          = &omap44xx_slimbus1_hwmod,
5635         .clk            = "ocp_abe_iclk",
5636         .addr           = omap44xx_slimbus1_addrs,
5637         .user           = OCP_USER_MPU,
5638 };
5639
5640 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5641         {
5642                 .pa_start       = 0x4902c000,
5643                 .pa_end         = 0x4902c3ff,
5644                 .flags          = ADDR_TYPE_RT
5645         },
5646         { }
5647 };
5648
5649 /* l4_abe -> slimbus1 (dma) */
5650 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5651         .master         = &omap44xx_l4_abe_hwmod,
5652         .slave          = &omap44xx_slimbus1_hwmod,
5653         .clk            = "ocp_abe_iclk",
5654         .addr           = omap44xx_slimbus1_dma_addrs,
5655         .user           = OCP_USER_SDMA,
5656 };
5657
5658 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5659         {
5660                 .pa_start       = 0x48076000,
5661                 .pa_end         = 0x480763ff,
5662                 .flags          = ADDR_TYPE_RT
5663         },
5664         { }
5665 };
5666
5667 /* l4_per -> slimbus2 */
5668 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5669         .master         = &omap44xx_l4_per_hwmod,
5670         .slave          = &omap44xx_slimbus2_hwmod,
5671         .clk            = "l4_div_ck",
5672         .addr           = omap44xx_slimbus2_addrs,
5673         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5674 };
5675
5676 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5677         {
5678                 .pa_start       = 0x4a0dd000,
5679                 .pa_end         = 0x4a0dd03f,
5680                 .flags          = ADDR_TYPE_RT
5681         },
5682         { }
5683 };
5684
5685 /* l4_cfg -> smartreflex_core */
5686 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5687         .master         = &omap44xx_l4_cfg_hwmod,
5688         .slave          = &omap44xx_smartreflex_core_hwmod,
5689         .clk            = "l4_div_ck",
5690         .addr           = omap44xx_smartreflex_core_addrs,
5691         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5692 };
5693
5694 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5695         {
5696                 .pa_start       = 0x4a0db000,
5697                 .pa_end         = 0x4a0db03f,
5698                 .flags          = ADDR_TYPE_RT
5699         },
5700         { }
5701 };
5702
5703 /* l4_cfg -> smartreflex_iva */
5704 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5705         .master         = &omap44xx_l4_cfg_hwmod,
5706         .slave          = &omap44xx_smartreflex_iva_hwmod,
5707         .clk            = "l4_div_ck",
5708         .addr           = omap44xx_smartreflex_iva_addrs,
5709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5710 };
5711
5712 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5713         {
5714                 .pa_start       = 0x4a0d9000,
5715                 .pa_end         = 0x4a0d903f,
5716                 .flags          = ADDR_TYPE_RT
5717         },
5718         { }
5719 };
5720
5721 /* l4_cfg -> smartreflex_mpu */
5722 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5723         .master         = &omap44xx_l4_cfg_hwmod,
5724         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5725         .clk            = "l4_div_ck",
5726         .addr           = omap44xx_smartreflex_mpu_addrs,
5727         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5728 };
5729
5730 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5731         {
5732                 .pa_start       = 0x4a0f6000,
5733                 .pa_end         = 0x4a0f6fff,
5734                 .flags          = ADDR_TYPE_RT
5735         },
5736         { }
5737 };
5738
5739 /* l4_cfg -> spinlock */
5740 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5741         .master         = &omap44xx_l4_cfg_hwmod,
5742         .slave          = &omap44xx_spinlock_hwmod,
5743         .clk            = "l4_div_ck",
5744         .addr           = omap44xx_spinlock_addrs,
5745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5746 };
5747
5748 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5749         {
5750                 .pa_start       = 0x4a318000,
5751                 .pa_end         = 0x4a31807f,
5752                 .flags          = ADDR_TYPE_RT
5753         },
5754         { }
5755 };
5756
5757 /* l4_wkup -> timer1 */
5758 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5759         .master         = &omap44xx_l4_wkup_hwmod,
5760         .slave          = &omap44xx_timer1_hwmod,
5761         .clk            = "l4_wkup_clk_mux_ck",
5762         .addr           = omap44xx_timer1_addrs,
5763         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5764 };
5765
5766 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5767         {
5768                 .pa_start       = 0x48032000,
5769                 .pa_end         = 0x4803207f,
5770                 .flags          = ADDR_TYPE_RT
5771         },
5772         { }
5773 };
5774
5775 /* l4_per -> timer2 */
5776 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5777         .master         = &omap44xx_l4_per_hwmod,
5778         .slave          = &omap44xx_timer2_hwmod,
5779         .clk            = "l4_div_ck",
5780         .addr           = omap44xx_timer2_addrs,
5781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5782 };
5783
5784 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5785         {
5786                 .pa_start       = 0x48034000,
5787                 .pa_end         = 0x4803407f,
5788                 .flags          = ADDR_TYPE_RT
5789         },
5790         { }
5791 };
5792
5793 /* l4_per -> timer3 */
5794 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5795         .master         = &omap44xx_l4_per_hwmod,
5796         .slave          = &omap44xx_timer3_hwmod,
5797         .clk            = "l4_div_ck",
5798         .addr           = omap44xx_timer3_addrs,
5799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5800 };
5801
5802 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5803         {
5804                 .pa_start       = 0x48036000,
5805                 .pa_end         = 0x4803607f,
5806                 .flags          = ADDR_TYPE_RT
5807         },
5808         { }
5809 };
5810
5811 /* l4_per -> timer4 */
5812 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5813         .master         = &omap44xx_l4_per_hwmod,
5814         .slave          = &omap44xx_timer4_hwmod,
5815         .clk            = "l4_div_ck",
5816         .addr           = omap44xx_timer4_addrs,
5817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5818 };
5819
5820 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5821         {
5822                 .pa_start       = 0x40138000,
5823                 .pa_end         = 0x4013807f,
5824                 .flags          = ADDR_TYPE_RT
5825         },
5826         { }
5827 };
5828
5829 /* l4_abe -> timer5 */
5830 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5831         .master         = &omap44xx_l4_abe_hwmod,
5832         .slave          = &omap44xx_timer5_hwmod,
5833         .clk            = "ocp_abe_iclk",
5834         .addr           = omap44xx_timer5_addrs,
5835         .user           = OCP_USER_MPU,
5836 };
5837
5838 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5839         {
5840                 .pa_start       = 0x49038000,
5841                 .pa_end         = 0x4903807f,
5842                 .flags          = ADDR_TYPE_RT
5843         },
5844         { }
5845 };
5846
5847 /* l4_abe -> timer5 (dma) */
5848 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5849         .master         = &omap44xx_l4_abe_hwmod,
5850         .slave          = &omap44xx_timer5_hwmod,
5851         .clk            = "ocp_abe_iclk",
5852         .addr           = omap44xx_timer5_dma_addrs,
5853         .user           = OCP_USER_SDMA,
5854 };
5855
5856 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5857         {
5858                 .pa_start       = 0x4013a000,
5859                 .pa_end         = 0x4013a07f,
5860                 .flags          = ADDR_TYPE_RT
5861         },
5862         { }
5863 };
5864
5865 /* l4_abe -> timer6 */
5866 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5867         .master         = &omap44xx_l4_abe_hwmod,
5868         .slave          = &omap44xx_timer6_hwmod,
5869         .clk            = "ocp_abe_iclk",
5870         .addr           = omap44xx_timer6_addrs,
5871         .user           = OCP_USER_MPU,
5872 };
5873
5874 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5875         {
5876                 .pa_start       = 0x4903a000,
5877                 .pa_end         = 0x4903a07f,
5878                 .flags          = ADDR_TYPE_RT
5879         },
5880         { }
5881 };
5882
5883 /* l4_abe -> timer6 (dma) */
5884 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5885         .master         = &omap44xx_l4_abe_hwmod,
5886         .slave          = &omap44xx_timer6_hwmod,
5887         .clk            = "ocp_abe_iclk",
5888         .addr           = omap44xx_timer6_dma_addrs,
5889         .user           = OCP_USER_SDMA,
5890 };
5891
5892 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5893         {
5894                 .pa_start       = 0x4013c000,
5895                 .pa_end         = 0x4013c07f,
5896                 .flags          = ADDR_TYPE_RT
5897         },
5898         { }
5899 };
5900
5901 /* l4_abe -> timer7 */
5902 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5903         .master         = &omap44xx_l4_abe_hwmod,
5904         .slave          = &omap44xx_timer7_hwmod,
5905         .clk            = "ocp_abe_iclk",
5906         .addr           = omap44xx_timer7_addrs,
5907         .user           = OCP_USER_MPU,
5908 };
5909
5910 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5911         {
5912                 .pa_start       = 0x4903c000,
5913                 .pa_end         = 0x4903c07f,
5914                 .flags          = ADDR_TYPE_RT
5915         },
5916         { }
5917 };
5918
5919 /* l4_abe -> timer7 (dma) */
5920 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5921         .master         = &omap44xx_l4_abe_hwmod,
5922         .slave          = &omap44xx_timer7_hwmod,
5923         .clk            = "ocp_abe_iclk",
5924         .addr           = omap44xx_timer7_dma_addrs,
5925         .user           = OCP_USER_SDMA,
5926 };
5927
5928 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5929         {
5930                 .pa_start       = 0x4013e000,
5931                 .pa_end         = 0x4013e07f,
5932                 .flags          = ADDR_TYPE_RT
5933         },
5934         { }
5935 };
5936
5937 /* l4_abe -> timer8 */
5938 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5939         .master         = &omap44xx_l4_abe_hwmod,
5940         .slave          = &omap44xx_timer8_hwmod,
5941         .clk            = "ocp_abe_iclk",
5942         .addr           = omap44xx_timer8_addrs,
5943         .user           = OCP_USER_MPU,
5944 };
5945
5946 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5947         {
5948                 .pa_start       = 0x4903e000,
5949                 .pa_end         = 0x4903e07f,
5950                 .flags          = ADDR_TYPE_RT
5951         },
5952         { }
5953 };
5954
5955 /* l4_abe -> timer8 (dma) */
5956 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5957         .master         = &omap44xx_l4_abe_hwmod,
5958         .slave          = &omap44xx_timer8_hwmod,
5959         .clk            = "ocp_abe_iclk",
5960         .addr           = omap44xx_timer8_dma_addrs,
5961         .user           = OCP_USER_SDMA,
5962 };
5963
5964 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5965         {
5966                 .pa_start       = 0x4803e000,
5967                 .pa_end         = 0x4803e07f,
5968                 .flags          = ADDR_TYPE_RT
5969         },
5970         { }
5971 };
5972
5973 /* l4_per -> timer9 */
5974 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5975         .master         = &omap44xx_l4_per_hwmod,
5976         .slave          = &omap44xx_timer9_hwmod,
5977         .clk            = "l4_div_ck",
5978         .addr           = omap44xx_timer9_addrs,
5979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5980 };
5981
5982 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5983         {
5984                 .pa_start       = 0x48086000,
5985                 .pa_end         = 0x4808607f,
5986                 .flags          = ADDR_TYPE_RT
5987         },
5988         { }
5989 };
5990
5991 /* l4_per -> timer10 */
5992 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5993         .master         = &omap44xx_l4_per_hwmod,
5994         .slave          = &omap44xx_timer10_hwmod,
5995         .clk            = "l4_div_ck",
5996         .addr           = omap44xx_timer10_addrs,
5997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5998 };
5999
6000 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6001         {
6002                 .pa_start       = 0x48088000,
6003                 .pa_end         = 0x4808807f,
6004                 .flags          = ADDR_TYPE_RT
6005         },
6006         { }
6007 };
6008
6009 /* l4_per -> timer11 */
6010 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6011         .master         = &omap44xx_l4_per_hwmod,
6012         .slave          = &omap44xx_timer11_hwmod,
6013         .clk            = "l4_div_ck",
6014         .addr           = omap44xx_timer11_addrs,
6015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6016 };
6017
6018 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6019         {
6020                 .pa_start       = 0x4806a000,
6021                 .pa_end         = 0x4806a0ff,
6022                 .flags          = ADDR_TYPE_RT
6023         },
6024         { }
6025 };
6026
6027 /* l4_per -> uart1 */
6028 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6029         .master         = &omap44xx_l4_per_hwmod,
6030         .slave          = &omap44xx_uart1_hwmod,
6031         .clk            = "l4_div_ck",
6032         .addr           = omap44xx_uart1_addrs,
6033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6034 };
6035
6036 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6037         {
6038                 .pa_start       = 0x4806c000,
6039                 .pa_end         = 0x4806c0ff,
6040                 .flags          = ADDR_TYPE_RT
6041         },
6042         { }
6043 };
6044
6045 /* l4_per -> uart2 */
6046 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6047         .master         = &omap44xx_l4_per_hwmod,
6048         .slave          = &omap44xx_uart2_hwmod,
6049         .clk            = "l4_div_ck",
6050         .addr           = omap44xx_uart2_addrs,
6051         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6052 };
6053
6054 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6055         {
6056                 .pa_start       = 0x48020000,
6057                 .pa_end         = 0x480200ff,
6058                 .flags          = ADDR_TYPE_RT
6059         },
6060         { }
6061 };
6062
6063 /* l4_per -> uart3 */
6064 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6065         .master         = &omap44xx_l4_per_hwmod,
6066         .slave          = &omap44xx_uart3_hwmod,
6067         .clk            = "l4_div_ck",
6068         .addr           = omap44xx_uart3_addrs,
6069         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6070 };
6071
6072 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6073         {
6074                 .pa_start       = 0x4806e000,
6075                 .pa_end         = 0x4806e0ff,
6076                 .flags          = ADDR_TYPE_RT
6077         },
6078         { }
6079 };
6080
6081 /* l4_per -> uart4 */
6082 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6083         .master         = &omap44xx_l4_per_hwmod,
6084         .slave          = &omap44xx_uart4_hwmod,
6085         .clk            = "l4_div_ck",
6086         .addr           = omap44xx_uart4_addrs,
6087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6088 };
6089
6090 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6091         {
6092                 .pa_start       = 0x4a0a9000,
6093                 .pa_end         = 0x4a0a93ff,
6094                 .flags          = ADDR_TYPE_RT
6095         },
6096         { }
6097 };
6098
6099 /* l4_cfg -> usb_host_fs */
6100 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6101         .master         = &omap44xx_l4_cfg_hwmod,
6102         .slave          = &omap44xx_usb_host_fs_hwmod,
6103         .clk            = "l4_div_ck",
6104         .addr           = omap44xx_usb_host_fs_addrs,
6105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6106 };
6107
6108 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6109         {
6110                 .name           = "uhh",
6111                 .pa_start       = 0x4a064000,
6112                 .pa_end         = 0x4a0647ff,
6113                 .flags          = ADDR_TYPE_RT
6114         },
6115         {
6116                 .name           = "ohci",
6117                 .pa_start       = 0x4a064800,
6118                 .pa_end         = 0x4a064bff,
6119         },
6120         {
6121                 .name           = "ehci",
6122                 .pa_start       = 0x4a064c00,
6123                 .pa_end         = 0x4a064fff,
6124         },
6125         {}
6126 };
6127
6128 /* l4_cfg -> usb_host_hs */
6129 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6130         .master         = &omap44xx_l4_cfg_hwmod,
6131         .slave          = &omap44xx_usb_host_hs_hwmod,
6132         .clk            = "l4_div_ck",
6133         .addr           = omap44xx_usb_host_hs_addrs,
6134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6135 };
6136
6137 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6138         {
6139                 .pa_start       = 0x4a0ab000,
6140                 .pa_end         = 0x4a0ab7ff,
6141                 .flags          = ADDR_TYPE_RT
6142         },
6143         {
6144                 /* XXX: Remove this once control module driver is in place */
6145                 .pa_start       = 0x4a00233c,
6146                 .pa_end         = 0x4a00233f,
6147                 .flags          = ADDR_TYPE_RT
6148         },
6149         { }
6150 };
6151
6152 /* l4_cfg -> usb_otg_hs */
6153 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6154         .master         = &omap44xx_l4_cfg_hwmod,
6155         .slave          = &omap44xx_usb_otg_hs_hwmod,
6156         .clk            = "l4_div_ck",
6157         .addr           = omap44xx_usb_otg_hs_addrs,
6158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6159 };
6160
6161 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6162         {
6163                 .name           = "tll",
6164                 .pa_start       = 0x4a062000,
6165                 .pa_end         = 0x4a063fff,
6166                 .flags          = ADDR_TYPE_RT
6167         },
6168         {}
6169 };
6170
6171 /* l4_cfg -> usb_tll_hs */
6172 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6173         .master         = &omap44xx_l4_cfg_hwmod,
6174         .slave          = &omap44xx_usb_tll_hs_hwmod,
6175         .clk            = "l4_div_ck",
6176         .addr           = omap44xx_usb_tll_hs_addrs,
6177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6178 };
6179
6180 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6181         {
6182                 .pa_start       = 0x4a314000,
6183                 .pa_end         = 0x4a31407f,
6184                 .flags          = ADDR_TYPE_RT
6185         },
6186         { }
6187 };
6188
6189 /* l4_wkup -> wd_timer2 */
6190 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6191         .master         = &omap44xx_l4_wkup_hwmod,
6192         .slave          = &omap44xx_wd_timer2_hwmod,
6193         .clk            = "l4_wkup_clk_mux_ck",
6194         .addr           = omap44xx_wd_timer2_addrs,
6195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6196 };
6197
6198 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6199         {
6200                 .pa_start       = 0x40130000,
6201                 .pa_end         = 0x4013007f,
6202                 .flags          = ADDR_TYPE_RT
6203         },
6204         { }
6205 };
6206
6207 /* l4_abe -> wd_timer3 */
6208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6209         .master         = &omap44xx_l4_abe_hwmod,
6210         .slave          = &omap44xx_wd_timer3_hwmod,
6211         .clk            = "ocp_abe_iclk",
6212         .addr           = omap44xx_wd_timer3_addrs,
6213         .user           = OCP_USER_MPU,
6214 };
6215
6216 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6217         {
6218                 .pa_start       = 0x49030000,
6219                 .pa_end         = 0x4903007f,
6220                 .flags          = ADDR_TYPE_RT
6221         },
6222         { }
6223 };
6224
6225 /* l4_abe -> wd_timer3 (dma) */
6226 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6227         .master         = &omap44xx_l4_abe_hwmod,
6228         .slave          = &omap44xx_wd_timer3_hwmod,
6229         .clk            = "ocp_abe_iclk",
6230         .addr           = omap44xx_wd_timer3_dma_addrs,
6231         .user           = OCP_USER_SDMA,
6232 };
6233
6234 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6235         &omap44xx_c2c__c2c_target_fw,
6236         &omap44xx_l4_cfg__c2c_target_fw,
6237         &omap44xx_l3_main_1__dmm,
6238         &omap44xx_mpu__dmm,
6239         &omap44xx_c2c__emif_fw,
6240         &omap44xx_dmm__emif_fw,
6241         &omap44xx_l4_cfg__emif_fw,
6242         &omap44xx_iva__l3_instr,
6243         &omap44xx_l3_main_3__l3_instr,
6244         &omap44xx_ocp_wp_noc__l3_instr,
6245         &omap44xx_dsp__l3_main_1,
6246         &omap44xx_dss__l3_main_1,
6247         &omap44xx_l3_main_2__l3_main_1,
6248         &omap44xx_l4_cfg__l3_main_1,
6249         &omap44xx_mmc1__l3_main_1,
6250         &omap44xx_mmc2__l3_main_1,
6251         &omap44xx_mpu__l3_main_1,
6252         &omap44xx_c2c_target_fw__l3_main_2,
6253         &omap44xx_debugss__l3_main_2,
6254         &omap44xx_dma_system__l3_main_2,
6255         &omap44xx_fdif__l3_main_2,
6256         &omap44xx_gpu__l3_main_2,
6257         &omap44xx_hsi__l3_main_2,
6258         &omap44xx_ipu__l3_main_2,
6259         &omap44xx_iss__l3_main_2,
6260         &omap44xx_iva__l3_main_2,
6261         &omap44xx_l3_main_1__l3_main_2,
6262         &omap44xx_l4_cfg__l3_main_2,
6263         /* &omap44xx_usb_host_fs__l3_main_2, */
6264         &omap44xx_usb_host_hs__l3_main_2,
6265         &omap44xx_usb_otg_hs__l3_main_2,
6266         &omap44xx_l3_main_1__l3_main_3,
6267         &omap44xx_l3_main_2__l3_main_3,
6268         &omap44xx_l4_cfg__l3_main_3,
6269         /* &omap44xx_aess__l4_abe, */
6270         &omap44xx_dsp__l4_abe,
6271         &omap44xx_l3_main_1__l4_abe,
6272         &omap44xx_mpu__l4_abe,
6273         &omap44xx_l3_main_1__l4_cfg,
6274         &omap44xx_l3_main_2__l4_per,
6275         &omap44xx_l4_cfg__l4_wkup,
6276         &omap44xx_mpu__mpu_private,
6277         &omap44xx_l4_cfg__ocp_wp_noc,
6278         /* &omap44xx_l4_abe__aess, */
6279         /* &omap44xx_l4_abe__aess_dma, */
6280         &omap44xx_l3_main_2__c2c,
6281         &omap44xx_l4_wkup__counter_32k,
6282         &omap44xx_l4_cfg__ctrl_module_core,
6283         &omap44xx_l4_cfg__ctrl_module_pad_core,
6284         &omap44xx_l4_wkup__ctrl_module_wkup,
6285         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6286         &omap44xx_l3_instr__debugss,
6287         &omap44xx_l4_cfg__dma_system,
6288         &omap44xx_l4_abe__dmic,
6289         &omap44xx_l4_abe__dmic_dma,
6290         &omap44xx_dsp__iva,
6291         /* &omap44xx_dsp__sl2if, */
6292         &omap44xx_l4_cfg__dsp,
6293         &omap44xx_l3_main_2__dss,
6294         &omap44xx_l4_per__dss,
6295         &omap44xx_l3_main_2__dss_dispc,
6296         &omap44xx_l4_per__dss_dispc,
6297         &omap44xx_l3_main_2__dss_dsi1,
6298         &omap44xx_l4_per__dss_dsi1,
6299         &omap44xx_l3_main_2__dss_dsi2,
6300         &omap44xx_l4_per__dss_dsi2,
6301         &omap44xx_l3_main_2__dss_hdmi,
6302         &omap44xx_l4_per__dss_hdmi,
6303         &omap44xx_l3_main_2__dss_rfbi,
6304         &omap44xx_l4_per__dss_rfbi,
6305         &omap44xx_l3_main_2__dss_venc,
6306         &omap44xx_l4_per__dss_venc,
6307         &omap44xx_l4_per__elm,
6308         &omap44xx_emif_fw__emif1,
6309         &omap44xx_emif_fw__emif2,
6310         &omap44xx_l4_cfg__fdif,
6311         &omap44xx_l4_wkup__gpio1,
6312         &omap44xx_l4_per__gpio2,
6313         &omap44xx_l4_per__gpio3,
6314         &omap44xx_l4_per__gpio4,
6315         &omap44xx_l4_per__gpio5,
6316         &omap44xx_l4_per__gpio6,
6317         &omap44xx_l3_main_2__gpmc,
6318         &omap44xx_l3_main_2__gpu,
6319         &omap44xx_l4_per__hdq1w,
6320         &omap44xx_l4_cfg__hsi,
6321         &omap44xx_l4_per__i2c1,
6322         &omap44xx_l4_per__i2c2,
6323         &omap44xx_l4_per__i2c3,
6324         &omap44xx_l4_per__i2c4,
6325         &omap44xx_l3_main_2__ipu,
6326         &omap44xx_l3_main_2__iss,
6327         /* &omap44xx_iva__sl2if, */
6328         &omap44xx_l3_main_2__iva,
6329         &omap44xx_l4_wkup__kbd,
6330         &omap44xx_l4_cfg__mailbox,
6331         &omap44xx_l4_abe__mcasp,
6332         &omap44xx_l4_abe__mcasp_dma,
6333         &omap44xx_l4_abe__mcbsp1,
6334         &omap44xx_l4_abe__mcbsp1_dma,
6335         &omap44xx_l4_abe__mcbsp2,
6336         &omap44xx_l4_abe__mcbsp2_dma,
6337         &omap44xx_l4_abe__mcbsp3,
6338         &omap44xx_l4_abe__mcbsp3_dma,
6339         &omap44xx_l4_per__mcbsp4,
6340         &omap44xx_l4_abe__mcpdm,
6341         &omap44xx_l4_abe__mcpdm_dma,
6342         &omap44xx_l4_per__mcspi1,
6343         &omap44xx_l4_per__mcspi2,
6344         &omap44xx_l4_per__mcspi3,
6345         &omap44xx_l4_per__mcspi4,
6346         &omap44xx_l4_per__mmc1,
6347         &omap44xx_l4_per__mmc2,
6348         &omap44xx_l4_per__mmc3,
6349         &omap44xx_l4_per__mmc4,
6350         &omap44xx_l4_per__mmc5,
6351         &omap44xx_l3_main_2__mmu_ipu,
6352         &omap44xx_l4_cfg__mmu_dsp,
6353         &omap44xx_l3_main_2__ocmc_ram,
6354         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6355         &omap44xx_mpu_private__prcm_mpu,
6356         &omap44xx_l4_wkup__cm_core_aon,
6357         &omap44xx_l4_cfg__cm_core,
6358         &omap44xx_l4_wkup__prm,
6359         &omap44xx_l4_wkup__scrm,
6360         /* &omap44xx_l3_main_2__sl2if, */
6361         &omap44xx_l4_abe__slimbus1,
6362         &omap44xx_l4_abe__slimbus1_dma,
6363         &omap44xx_l4_per__slimbus2,
6364         &omap44xx_l4_cfg__smartreflex_core,
6365         &omap44xx_l4_cfg__smartreflex_iva,
6366         &omap44xx_l4_cfg__smartreflex_mpu,
6367         &omap44xx_l4_cfg__spinlock,
6368         &omap44xx_l4_wkup__timer1,
6369         &omap44xx_l4_per__timer2,
6370         &omap44xx_l4_per__timer3,
6371         &omap44xx_l4_per__timer4,
6372         &omap44xx_l4_abe__timer5,
6373         &omap44xx_l4_abe__timer5_dma,
6374         &omap44xx_l4_abe__timer6,
6375         &omap44xx_l4_abe__timer6_dma,
6376         &omap44xx_l4_abe__timer7,
6377         &omap44xx_l4_abe__timer7_dma,
6378         &omap44xx_l4_abe__timer8,
6379         &omap44xx_l4_abe__timer8_dma,
6380         &omap44xx_l4_per__timer9,
6381         &omap44xx_l4_per__timer10,
6382         &omap44xx_l4_per__timer11,
6383         &omap44xx_l4_per__uart1,
6384         &omap44xx_l4_per__uart2,
6385         &omap44xx_l4_per__uart3,
6386         &omap44xx_l4_per__uart4,
6387         /* &omap44xx_l4_cfg__usb_host_fs, */
6388         &omap44xx_l4_cfg__usb_host_hs,
6389         &omap44xx_l4_cfg__usb_otg_hs,
6390         &omap44xx_l4_cfg__usb_tll_hs,
6391         &omap44xx_l4_wkup__wd_timer2,
6392         &omap44xx_l4_abe__wd_timer3,
6393         &omap44xx_l4_abe__wd_timer3_dma,
6394         NULL,
6395 };
6396
6397 int __init omap44xx_hwmod_init(void)
6398 {
6399         omap_hwmod_init();
6400         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6401 }
6402