arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24
  25 #include <plat/omap_hwmod.h>
  26 #include <plat/i2c.h>
  27 #include <plat/dma.h>
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33 #include <plat/iommu.h>
  34
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "wd_timer.h"
  41
  42 /* Base offset for all OMAP4 interrupts external to MPUSS */
  43 #define OMAP44XX_IRQ_GIC_START  32
  44
  45 /* Base offset for all OMAP4 dma requests */
  46 #define OMAP44XX_DMA_REQ_START  1
  47
  48 /*
  49  * IP blocks
  50  */
  51
  52 /*
  53  * 'c2c_target_fw' class
  54  * instance(s): c2c_target_fw
  55  */
  56 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  57         .name   = "c2c_target_fw",
  58 };
  59
  60 /* c2c_target_fw */
  61 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  62         .name           = "c2c_target_fw",
  63         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  64         .clkdm_name     = "d2d_clkdm",
  65         .prcm = {
  66                 .omap4 = {
  67                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  68                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  69                 },
  70         },
  71 };
  72
  73 /*
  74  * 'dmm' class
  75  * instance(s): dmm
  76  */
  77 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  78         .name   = "dmm",
  79 };
  80
  81 /* dmm */
  82 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  83         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  84         { .irq = -1 }
  85 };
  86
  87 static struct omap_hwmod omap44xx_dmm_hwmod = {
  88         .name           = "dmm",
  89         .class          = &omap44xx_dmm_hwmod_class,
  90         .clkdm_name     = "l3_emif_clkdm",
  91         .mpu_irqs       = omap44xx_dmm_irqs,
  92         .prcm = {
  93                 .omap4 = {
  94                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  95                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  96                 },
  97         },
  98 };
  99
 100 /*
 101  * 'emif_fw' class
 102  * instance(s): emif_fw
 103  */
 104 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 105         .name   = "emif_fw",
 106 };
 107
 108 /* emif_fw */
 109 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 110         .name           = "emif_fw",
 111         .class          = &omap44xx_emif_fw_hwmod_class,
 112         .clkdm_name     = "l3_emif_clkdm",
 113         .prcm = {
 114                 .omap4 = {
 115                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 116                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l3' class
 123  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 124  */
 125 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 126         .name   = "l3",
 127 };
 128
 129 /* l3_instr */
 130 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 131         .name           = "l3_instr",
 132         .class          = &omap44xx_l3_hwmod_class,
 133         .clkdm_name     = "l3_instr_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 137                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 138                         .modulemode   = MODULEMODE_HWCTRL,
 139                 },
 140         },
 141 };
 142
 143 /* l3_main_1 */
 144 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 145         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 146         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 147         { .irq = -1 }
 148 };
 149
 150 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 151         .name           = "l3_main_1",
 152         .class          = &omap44xx_l3_hwmod_class,
 153         .clkdm_name     = "l3_1_clkdm",
 154         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 158                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 159                 },
 160         },
 161 };
 162
 163 /* l3_main_2 */
 164 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 165         .name           = "l3_main_2",
 166         .class          = &omap44xx_l3_hwmod_class,
 167         .clkdm_name     = "l3_2_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 171                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /* l3_main_3 */
 177 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 178         .name           = "l3_main_3",
 179         .class          = &omap44xx_l3_hwmod_class,
 180         .clkdm_name     = "l3_instr_clkdm",
 181         .prcm = {
 182                 .omap4 = {
 183                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 184                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 185                         .modulemode   = MODULEMODE_HWCTRL,
 186                 },
 187         },
 188 };
 189
 190 /*
 191  * 'l4' class
 192  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 193  */
 194 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 195         .name   = "l4",
 196 };
 197
 198 /* l4_abe */
 199 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 200         .name           = "l4_abe",
 201         .class          = &omap44xx_l4_hwmod_class,
 202         .clkdm_name     = "abe_clkdm",
 203         .prcm = {
 204                 .omap4 = {
 205                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 206                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 207                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 208                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 209                 },
 210         },
 211 };
 212
 213 /* l4_cfg */
 214 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 215         .name           = "l4_cfg",
 216         .class          = &omap44xx_l4_hwmod_class,
 217         .clkdm_name     = "l4_cfg_clkdm",
 218         .prcm = {
 219                 .omap4 = {
 220                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 221                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 222                 },
 223         },
 224 };
 225
 226 /* l4_per */
 227 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 228         .name           = "l4_per",
 229         .class          = &omap44xx_l4_hwmod_class,
 230         .clkdm_name     = "l4_per_clkdm",
 231         .prcm = {
 232                 .omap4 = {
 233                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 234                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 235                 },
 236         },
 237 };
 238
 239 /* l4_wkup */
 240 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 241         .name           = "l4_wkup",
 242         .class          = &omap44xx_l4_hwmod_class,
 243         .clkdm_name     = "l4_wkup_clkdm",
 244         .prcm = {
 245                 .omap4 = {
 246                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 247                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 248                 },
 249         },
 250 };
 251
 252 /*
 253  * 'mpu_bus' class
 254  * instance(s): mpu_private
 255  */
 256 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 257         .name   = "mpu_bus",
 258 };
 259
 260 /* mpu_private */
 261 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 262         .name           = "mpu_private",
 263         .class          = &omap44xx_mpu_bus_hwmod_class,
 264         .clkdm_name     = "mpuss_clkdm",
 265         .prcm = {
 266                 .omap4 = {
 267                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 268                 },
 269         },
 270 };
 271
 272 /*
 273  * 'ocp_wp_noc' class
 274  * instance(s): ocp_wp_noc
 275  */
 276 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 277         .name   = "ocp_wp_noc",
 278 };
 279
 280 /* ocp_wp_noc */
 281 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 282         .name           = "ocp_wp_noc",
 283         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 284         .clkdm_name     = "l3_instr_clkdm",
 285         .prcm = {
 286                 .omap4 = {
 287                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 288                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 289                         .modulemode   = MODULEMODE_HWCTRL,
 290                 },
 291         },
 292 };
 293
 294 /*
 295  * Modules omap_hwmod structures
 296  *
 297  * The following IPs are excluded for the moment because:
 298  * - They do not need an explicit SW control using omap_hwmod API.
 299  * - They still need to be validated with the driver
 300  *   properly adapted to omap_hwmod / omap_device
 301  *
 302  * usim
 303  */
 304
 305 /*
 306  * 'aess' class
 307  * audio engine sub system
 308  */
 309
 310 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 311         .rev_offs       = 0x0000,
 312         .sysc_offs      = 0x0010,
 313         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 314         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 315                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 316                            MSTANDBY_SMART_WKUP),
 317         .sysc_fields    = &omap_hwmod_sysc_type2,
 318 };
 319
 320 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 321         .name   = "aess",
 322         .sysc   = &omap44xx_aess_sysc,
 323 };
 324
 325 /* aess */
 326 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 327         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 328         { .irq = -1 }
 329 };
 330
 331 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 332         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 333         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 334         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 340         { .dma_req = -1 }
 341 };
 342
 343 static struct omap_hwmod omap44xx_aess_hwmod = {
 344         .name           = "aess",
 345         .class          = &omap44xx_aess_hwmod_class,
 346         .clkdm_name     = "abe_clkdm",
 347         .mpu_irqs       = omap44xx_aess_irqs,
 348         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 349         .main_clk       = "aess_fck",
 350         .prcm = {
 351                 .omap4 = {
 352                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 353                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 354                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 355                         .modulemode   = MODULEMODE_SWCTRL,
 356                 },
 357         },
 358 };
 359
 360 /*
 361  * 'c2c' class
 362  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 363  * soc
 364  */
 365
 366 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 367         .name   = "c2c",
 368 };
 369
 370 /* c2c */
 371 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 372         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 373         { .irq = -1 }
 374 };
 375
 376 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 377         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 378         { .dma_req = -1 }
 379 };
 380
 381 static struct omap_hwmod omap44xx_c2c_hwmod = {
 382         .name           = "c2c",
 383         .class          = &omap44xx_c2c_hwmod_class,
 384         .clkdm_name     = "d2d_clkdm",
 385         .mpu_irqs       = omap44xx_c2c_irqs,
 386         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 387         .prcm = {
 388                 .omap4 = {
 389                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 390                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 391                 },
 392         },
 393 };
 394
 395 /*
 396  * 'counter' class
 397  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 398  */
 399
 400 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 401         .rev_offs       = 0x0000,
 402         .sysc_offs      = 0x0004,
 403         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 404         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 405         .sysc_fields    = &omap_hwmod_sysc_type1,
 406 };
 407
 408 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 409         .name   = "counter",
 410         .sysc   = &omap44xx_counter_sysc,
 411 };
 412
 413 /* counter_32k */
 414 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 415         .name           = "counter_32k",
 416         .class          = &omap44xx_counter_hwmod_class,
 417         .clkdm_name     = "l4_wkup_clkdm",
 418         .flags          = HWMOD_SWSUP_SIDLE,
 419         .main_clk       = "sys_32k_ck",
 420         .prcm = {
 421                 .omap4 = {
 422                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 423                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 424                 },
 425         },
 426 };
 427
 428 /*
 429  * 'ctrl_module' class
 430  * attila core control module + core pad control module + wkup pad control
 431  * module + attila wkup control module
 432  */
 433
 434 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 435         .rev_offs       = 0x0000,
 436         .sysc_offs      = 0x0010,
 437         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 438         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 439                            SIDLE_SMART_WKUP),
 440         .sysc_fields    = &omap_hwmod_sysc_type2,
 441 };
 442
 443 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 444         .name   = "ctrl_module",
 445         .sysc   = &omap44xx_ctrl_module_sysc,
 446 };
 447
 448 /* ctrl_module_core */
 449 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 450         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 451         { .irq = -1 }
 452 };
 453
 454 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 455         .name           = "ctrl_module_core",
 456         .class          = &omap44xx_ctrl_module_hwmod_class,
 457         .clkdm_name     = "l4_cfg_clkdm",
 458         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 459         .prcm = {
 460                 .omap4 = {
 461                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 462                 },
 463         },
 464 };
 465
 466 /* ctrl_module_pad_core */
 467 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 468         .name           = "ctrl_module_pad_core",
 469         .class          = &omap44xx_ctrl_module_hwmod_class,
 470         .clkdm_name     = "l4_cfg_clkdm",
 471         .prcm = {
 472                 .omap4 = {
 473                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 474                 },
 475         },
 476 };
 477
 478 /* ctrl_module_wkup */
 479 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 480         .name           = "ctrl_module_wkup",
 481         .class          = &omap44xx_ctrl_module_hwmod_class,
 482         .clkdm_name     = "l4_wkup_clkdm",
 483         .prcm = {
 484                 .omap4 = {
 485                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 486                 },
 487         },
 488 };
 489
 490 /* ctrl_module_pad_wkup */
 491 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 492         .name           = "ctrl_module_pad_wkup",
 493         .class          = &omap44xx_ctrl_module_hwmod_class,
 494         .clkdm_name     = "l4_wkup_clkdm",
 495         .prcm = {
 496                 .omap4 = {
 497                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 498                 },
 499         },
 500 };
 501
 502 /*
 503  * 'debugss' class
 504  * debug and emulation sub system
 505  */
 506
 507 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 508         .name   = "debugss",
 509 };
 510
 511 /* debugss */
 512 static struct omap_hwmod omap44xx_debugss_hwmod = {
 513         .name           = "debugss",
 514         .class          = &omap44xx_debugss_hwmod_class,
 515         .clkdm_name     = "emu_sys_clkdm",
 516         .main_clk       = "trace_clk_div_ck",
 517         .prcm = {
 518                 .omap4 = {
 519                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 520                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 521                 },
 522         },
 523 };
 524
 525 /*
 526  * 'dma' class
 527  * dma controller for data exchange between memory to memory (i.e. internal or
 528  * external memory) and gp peripherals to memory or memory to gp peripherals
 529  */
 530
 531 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 532         .rev_offs       = 0x0000,
 533         .sysc_offs      = 0x002c,
 534         .syss_offs      = 0x0028,
 535         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 536                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 537                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 538                            SYSS_HAS_RESET_STATUS),
 539         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 540                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 541         .sysc_fields    = &omap_hwmod_sysc_type1,
 542 };
 543
 544 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 545         .name   = "dma",
 546         .sysc   = &omap44xx_dma_sysc,
 547 };
 548
 549 /* dma dev_attr */
 550 static struct omap_dma_dev_attr dma_dev_attr = {
 551         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 552                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 553         .lch_count      = 32,
 554 };
 555
 556 /* dma_system */
 557 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 558         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 559         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 560         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 562         { .irq = -1 }
 563 };
 564
 565 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 566         .name           = "dma_system",
 567         .class          = &omap44xx_dma_hwmod_class,
 568         .clkdm_name     = "l3_dma_clkdm",
 569         .mpu_irqs       = omap44xx_dma_system_irqs,
 570         .main_clk       = "l3_div_ck",
 571         .prcm = {
 572                 .omap4 = {
 573                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 574                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 575                 },
 576         },
 577         .dev_attr       = &dma_dev_attr,
 578 };
 579
 580 /*
 581  * 'dmic' class
 582  * digital microphone controller
 583  */
 584
 585 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 586         .rev_offs       = 0x0000,
 587         .sysc_offs      = 0x0010,
 588         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 589                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 590         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 591                            SIDLE_SMART_WKUP),
 592         .sysc_fields    = &omap_hwmod_sysc_type2,
 593 };
 594
 595 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 596         .name   = "dmic",
 597         .sysc   = &omap44xx_dmic_sysc,
 598 };
 599
 600 /* dmic */
 601 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 602         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 603         { .irq = -1 }
 604 };
 605
 606 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 607         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 608         { .dma_req = -1 }
 609 };
 610
 611 static struct omap_hwmod omap44xx_dmic_hwmod = {
 612         .name           = "dmic",
 613         .class          = &omap44xx_dmic_hwmod_class,
 614         .clkdm_name     = "abe_clkdm",
 615         .mpu_irqs       = omap44xx_dmic_irqs,
 616         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 617         .main_clk       = "dmic_fck",
 618         .prcm = {
 619                 .omap4 = {
 620                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 621                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 622                         .modulemode   = MODULEMODE_SWCTRL,
 623                 },
 624         },
 625 };
 626
 627 /*
 628  * 'dsp' class
 629  * dsp sub-system
 630  */
 631
 632 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 633         .name   = "dsp",
 634 };
 635
 636 /* dsp */
 637 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 638         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 639         { .irq = -1 }
 640 };
 641
 642 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 643         { .name = "dsp", .rst_shift = 0 },
 644 };
 645
 646 static struct omap_hwmod omap44xx_dsp_hwmod = {
 647         .name           = "dsp",
 648         .class          = &omap44xx_dsp_hwmod_class,
 649         .clkdm_name     = "tesla_clkdm",
 650         .mpu_irqs       = omap44xx_dsp_irqs,
 651         .rst_lines      = omap44xx_dsp_resets,
 652         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 653         .main_clk       = "dsp_fck",
 654         .prcm = {
 655                 .omap4 = {
 656                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 657                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 658                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 659                         .modulemode   = MODULEMODE_HWCTRL,
 660                 },
 661         },
 662 };
 663
 664 /*
 665  * 'dss' class
 666  * display sub-system
 667  */
 668
 669 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 670         .rev_offs       = 0x0000,
 671         .syss_offs      = 0x0014,
 672         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 673 };
 674
 675 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 676         .name   = "dss",
 677         .sysc   = &omap44xx_dss_sysc,
 678         .reset  = omap_dss_reset,
 679 };
 680
 681 /* dss */
 682 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 683         { .role = "sys_clk", .clk = "dss_sys_clk" },
 684         { .role = "tv_clk", .clk = "dss_tv_clk" },
 685         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 686 };
 687
 688 static struct omap_hwmod omap44xx_dss_hwmod = {
 689         .name           = "dss_core",
 690         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 691         .class          = &omap44xx_dss_hwmod_class,
 692         .clkdm_name     = "l3_dss_clkdm",
 693         .main_clk       = "dss_dss_clk",
 694         .prcm = {
 695                 .omap4 = {
 696                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 697                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 698                 },
 699         },
 700         .opt_clks       = dss_opt_clks,
 701         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 702 };
 703
 704 /*
 705  * 'dispc' class
 706  * display controller
 707  */
 708
 709 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 710         .rev_offs       = 0x0000,
 711         .sysc_offs      = 0x0010,
 712         .syss_offs      = 0x0014,
 713         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 714                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 715                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 716                            SYSS_HAS_RESET_STATUS),
 717         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 718                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 719         .sysc_fields    = &omap_hwmod_sysc_type1,
 720 };
 721
 722 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 723         .name   = "dispc",
 724         .sysc   = &omap44xx_dispc_sysc,
 725 };
 726
 727 /* dss_dispc */
 728 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 729         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 730         { .irq = -1 }
 731 };
 732
 733 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 734         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 735         { .dma_req = -1 }
 736 };
 737
 738 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 739         .manager_count          = 3,
 740         .has_framedonetv_irq    = 1
 741 };
 742
 743 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 744         .name           = "dss_dispc",
 745         .class          = &omap44xx_dispc_hwmod_class,
 746         .clkdm_name     = "l3_dss_clkdm",
 747         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 748         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 749         .main_clk       = "dss_dss_clk",
 750         .prcm = {
 751                 .omap4 = {
 752                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 753                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 754                 },
 755         },
 756         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 757 };
 758
 759 /*
 760  * 'dsi' class
 761  * display serial interface controller
 762  */
 763
 764 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 765         .rev_offs       = 0x0000,
 766         .sysc_offs      = 0x0010,
 767         .syss_offs      = 0x0014,
 768         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 769                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 770                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 771         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 772         .sysc_fields    = &omap_hwmod_sysc_type1,
 773 };
 774
 775 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 776         .name   = "dsi",
 777         .sysc   = &omap44xx_dsi_sysc,
 778 };
 779
 780 /* dss_dsi1 */
 781 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 782         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 783         { .irq = -1 }
 784 };
 785
 786 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 787         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 788         { .dma_req = -1 }
 789 };
 790
 791 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 792         { .role = "sys_clk", .clk = "dss_sys_clk" },
 793 };
 794
 795 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 796         .name           = "dss_dsi1",
 797         .class          = &omap44xx_dsi_hwmod_class,
 798         .clkdm_name     = "l3_dss_clkdm",
 799         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 800         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 801         .main_clk       = "dss_dss_clk",
 802         .prcm = {
 803                 .omap4 = {
 804                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 805                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 806                 },
 807         },
 808         .opt_clks       = dss_dsi1_opt_clks,
 809         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 810 };
 811
 812 /* dss_dsi2 */
 813 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 814         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 815         { .irq = -1 }
 816 };
 817
 818 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 819         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 820         { .dma_req = -1 }
 821 };
 822
 823 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 824         { .role = "sys_clk", .clk = "dss_sys_clk" },
 825 };
 826
 827 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 828         .name           = "dss_dsi2",
 829         .class          = &omap44xx_dsi_hwmod_class,
 830         .clkdm_name     = "l3_dss_clkdm",
 831         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 832         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 833         .main_clk       = "dss_dss_clk",
 834         .prcm = {
 835                 .omap4 = {
 836                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 837                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 838                 },
 839         },
 840         .opt_clks       = dss_dsi2_opt_clks,
 841         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 842 };
 843
 844 /*
 845  * 'hdmi' class
 846  * hdmi controller
 847  */
 848
 849 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 850         .rev_offs       = 0x0000,
 851         .sysc_offs      = 0x0010,
 852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 853                            SYSC_HAS_SOFTRESET),
 854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 855                            SIDLE_SMART_WKUP),
 856         .sysc_fields    = &omap_hwmod_sysc_type2,
 857 };
 858
 859 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 860         .name   = "hdmi",
 861         .sysc   = &omap44xx_hdmi_sysc,
 862 };
 863
 864 /* dss_hdmi */
 865 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 866         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 867         { .irq = -1 }
 868 };
 869
 870 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 871         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 872         { .dma_req = -1 }
 873 };
 874
 875 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 876         { .role = "sys_clk", .clk = "dss_sys_clk" },
 877 };
 878
 879 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 880         .name           = "dss_hdmi",
 881         .class          = &omap44xx_hdmi_hwmod_class,
 882         .clkdm_name     = "l3_dss_clkdm",
 883         /*
 884          * HDMI audio requires to use no-idle mode. Hence,
 885          * set idle mode by software.
 886          */
 887         .flags          = HWMOD_SWSUP_SIDLE,
 888         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 889         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 890         .main_clk       = "dss_48mhz_clk",
 891         .prcm = {
 892                 .omap4 = {
 893                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 894                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 895                 },
 896         },
 897         .opt_clks       = dss_hdmi_opt_clks,
 898         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 899 };
 900
 901 /*
 902  * 'rfbi' class
 903  * remote frame buffer interface
 904  */
 905
 906 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 907         .rev_offs       = 0x0000,
 908         .sysc_offs      = 0x0010,
 909         .syss_offs      = 0x0014,
 910         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 911                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 912         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 913         .sysc_fields    = &omap_hwmod_sysc_type1,
 914 };
 915
 916 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 917         .name   = "rfbi",
 918         .sysc   = &omap44xx_rfbi_sysc,
 919 };
 920
 921 /* dss_rfbi */
 922 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 923         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 924         { .dma_req = -1 }
 925 };
 926
 927 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 928         { .role = "ick", .clk = "dss_fck" },
 929 };
 930
 931 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 932         .name           = "dss_rfbi",
 933         .class          = &omap44xx_rfbi_hwmod_class,
 934         .clkdm_name     = "l3_dss_clkdm",
 935         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 936         .main_clk       = "dss_dss_clk",
 937         .prcm = {
 938                 .omap4 = {
 939                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 940                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 941                 },
 942         },
 943         .opt_clks       = dss_rfbi_opt_clks,
 944         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 945 };
 946
 947 /*
 948  * 'venc' class
 949  * video encoder
 950  */
 951
 952 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 953         .name   = "venc",
 954 };
 955
 956 /* dss_venc */
 957 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 958         .name           = "dss_venc",
 959         .class          = &omap44xx_venc_hwmod_class,
 960         .clkdm_name     = "l3_dss_clkdm",
 961         .main_clk       = "dss_tv_clk",
 962         .prcm = {
 963                 .omap4 = {
 964                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 965                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 966                 },
 967         },
 968 };
 969
 970 /*
 971  * 'elm' class
 972  * bch error location module
 973  */
 974
 975 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 976         .rev_offs       = 0x0000,
 977         .sysc_offs      = 0x0010,
 978         .syss_offs      = 0x0014,
 979         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 980                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 981                            SYSS_HAS_RESET_STATUS),
 982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 983         .sysc_fields    = &omap_hwmod_sysc_type1,
 984 };
 985
 986 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 987         .name   = "elm",
 988         .sysc   = &omap44xx_elm_sysc,
 989 };
 990
 991 /* elm */
 992 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 993         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 994         { .irq = -1 }
 995 };
 996
 997 static struct omap_hwmod omap44xx_elm_hwmod = {
 998         .name           = "elm",
 999         .class          = &omap44xx_elm_hwmod_class,
1000         .clkdm_name     = "l4_per_clkdm",
1001         .mpu_irqs       = omap44xx_elm_irqs,
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1005                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1006                 },
1007         },
1008 };
1009
1010 /*
1011  * 'emif' class
1012  * external memory interface no1
1013  */
1014
1015 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1016         .rev_offs       = 0x0000,
1017 };
1018
1019 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1020         .name   = "emif",
1021         .sysc   = &omap44xx_emif_sysc,
1022 };
1023
1024 /* emif1 */
1025 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1026         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1027         { .irq = -1 }
1028 };
1029
1030 static struct omap_hwmod omap44xx_emif1_hwmod = {
1031         .name           = "emif1",
1032         .class          = &omap44xx_emif_hwmod_class,
1033         .clkdm_name     = "l3_emif_clkdm",
1034         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1035         .mpu_irqs       = omap44xx_emif1_irqs,
1036         .main_clk       = "ddrphy_ck",
1037         .prcm = {
1038                 .omap4 = {
1039                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1040                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1041                         .modulemode   = MODULEMODE_HWCTRL,
1042                 },
1043         },
1044 };
1045
1046 /* emif2 */
1047 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1048         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1049         { .irq = -1 }
1050 };
1051
1052 static struct omap_hwmod omap44xx_emif2_hwmod = {
1053         .name           = "emif2",
1054         .class          = &omap44xx_emif_hwmod_class,
1055         .clkdm_name     = "l3_emif_clkdm",
1056         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1057         .mpu_irqs       = omap44xx_emif2_irqs,
1058         .main_clk       = "ddrphy_ck",
1059         .prcm = {
1060                 .omap4 = {
1061                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1062                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1063                         .modulemode   = MODULEMODE_HWCTRL,
1064                 },
1065         },
1066 };
1067
1068 /*
1069  * 'fdif' class
1070  * face detection hw accelerator module
1071  */
1072
1073 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1074         .rev_offs       = 0x0000,
1075         .sysc_offs      = 0x0010,
1076         /*
1077          * FDIF needs 100 OCP clk cycles delay after a softreset before
1078          * accessing sysconfig again.
1079          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1080          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1081          *
1082          * TODO: Indicate errata when available.
1083          */
1084         .srst_udelay    = 2,
1085         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1086                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089         .sysc_fields    = &omap_hwmod_sysc_type2,
1090 };
1091
1092 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1093         .name   = "fdif",
1094         .sysc   = &omap44xx_fdif_sysc,
1095 };
1096
1097 /* fdif */
1098 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1099         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1100         { .irq = -1 }
1101 };
1102
1103 static struct omap_hwmod omap44xx_fdif_hwmod = {
1104         .name           = "fdif",
1105         .class          = &omap44xx_fdif_hwmod_class,
1106         .clkdm_name     = "iss_clkdm",
1107         .mpu_irqs       = omap44xx_fdif_irqs,
1108         .main_clk       = "fdif_fck",
1109         .prcm = {
1110                 .omap4 = {
1111                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1112                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1113                         .modulemode   = MODULEMODE_SWCTRL,
1114                 },
1115         },
1116 };
1117
1118 /*
1119  * 'gpio' class
1120  * general purpose io module
1121  */
1122
1123 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1124         .rev_offs       = 0x0000,
1125         .sysc_offs      = 0x0010,
1126         .syss_offs      = 0x0114,
1127         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1128                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1129                            SYSS_HAS_RESET_STATUS),
1130         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1131                            SIDLE_SMART_WKUP),
1132         .sysc_fields    = &omap_hwmod_sysc_type1,
1133 };
1134
1135 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1136         .name   = "gpio",
1137         .sysc   = &omap44xx_gpio_sysc,
1138         .rev    = 2,
1139 };
1140
1141 /* gpio dev_attr */
1142 static struct omap_gpio_dev_attr gpio_dev_attr = {
1143         .bank_width     = 32,
1144         .dbck_flag      = true,
1145 };
1146
1147 /* gpio1 */
1148 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1149         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1150         { .irq = -1 }
1151 };
1152
1153 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1154         { .role = "dbclk", .clk = "gpio1_dbclk" },
1155 };
1156
1157 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1158         .name           = "gpio1",
1159         .class          = &omap44xx_gpio_hwmod_class,
1160         .clkdm_name     = "l4_wkup_clkdm",
1161         .mpu_irqs       = omap44xx_gpio1_irqs,
1162         .main_clk       = "gpio1_ick",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1166                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_HWCTRL,
1168                 },
1169         },
1170         .opt_clks       = gpio1_opt_clks,
1171         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1172         .dev_attr       = &gpio_dev_attr,
1173 };
1174
1175 /* gpio2 */
1176 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1177         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1178         { .irq = -1 }
1179 };
1180
1181 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1182         { .role = "dbclk", .clk = "gpio2_dbclk" },
1183 };
1184
1185 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1186         .name           = "gpio2",
1187         .class          = &omap44xx_gpio_hwmod_class,
1188         .clkdm_name     = "l4_per_clkdm",
1189         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190         .mpu_irqs       = omap44xx_gpio2_irqs,
1191         .main_clk       = "gpio2_ick",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1195                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_HWCTRL,
1197                 },
1198         },
1199         .opt_clks       = gpio2_opt_clks,
1200         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1201         .dev_attr       = &gpio_dev_attr,
1202 };
1203
1204 /* gpio3 */
1205 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1206         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1207         { .irq = -1 }
1208 };
1209
1210 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1211         { .role = "dbclk", .clk = "gpio3_dbclk" },
1212 };
1213
1214 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1215         .name           = "gpio3",
1216         .class          = &omap44xx_gpio_hwmod_class,
1217         .clkdm_name     = "l4_per_clkdm",
1218         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1219         .mpu_irqs       = omap44xx_gpio3_irqs,
1220         .main_clk       = "gpio3_ick",
1221         .prcm = {
1222                 .omap4 = {
1223                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1224                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1225                         .modulemode   = MODULEMODE_HWCTRL,
1226                 },
1227         },
1228         .opt_clks       = gpio3_opt_clks,
1229         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1230         .dev_attr       = &gpio_dev_attr,
1231 };
1232
1233 /* gpio4 */
1234 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1235         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1236         { .irq = -1 }
1237 };
1238
1239 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1240         { .role = "dbclk", .clk = "gpio4_dbclk" },
1241 };
1242
1243 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1244         .name           = "gpio4",
1245         .class          = &omap44xx_gpio_hwmod_class,
1246         .clkdm_name     = "l4_per_clkdm",
1247         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1248         .mpu_irqs       = omap44xx_gpio4_irqs,
1249         .main_clk       = "gpio4_ick",
1250         .prcm = {
1251                 .omap4 = {
1252                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1253                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1254                         .modulemode   = MODULEMODE_HWCTRL,
1255                 },
1256         },
1257         .opt_clks       = gpio4_opt_clks,
1258         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1259         .dev_attr       = &gpio_dev_attr,
1260 };
1261
1262 /* gpio5 */
1263 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1264         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1265         { .irq = -1 }
1266 };
1267
1268 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1269         { .role = "dbclk", .clk = "gpio5_dbclk" },
1270 };
1271
1272 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1273         .name           = "gpio5",
1274         .class          = &omap44xx_gpio_hwmod_class,
1275         .clkdm_name     = "l4_per_clkdm",
1276         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1277         .mpu_irqs       = omap44xx_gpio5_irqs,
1278         .main_clk       = "gpio5_ick",
1279         .prcm = {
1280                 .omap4 = {
1281                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1282                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1283                         .modulemode   = MODULEMODE_HWCTRL,
1284                 },
1285         },
1286         .opt_clks       = gpio5_opt_clks,
1287         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1288         .dev_attr       = &gpio_dev_attr,
1289 };
1290
1291 /* gpio6 */
1292 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1293         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1294         { .irq = -1 }
1295 };
1296
1297 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1298         { .role = "dbclk", .clk = "gpio6_dbclk" },
1299 };
1300
1301 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1302         .name           = "gpio6",
1303         .class          = &omap44xx_gpio_hwmod_class,
1304         .clkdm_name     = "l4_per_clkdm",
1305         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1306         .mpu_irqs       = omap44xx_gpio6_irqs,
1307         .main_clk       = "gpio6_ick",
1308         .prcm = {
1309                 .omap4 = {
1310                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1311                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1312                         .modulemode   = MODULEMODE_HWCTRL,
1313                 },
1314         },
1315         .opt_clks       = gpio6_opt_clks,
1316         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1317         .dev_attr       = &gpio_dev_attr,
1318 };
1319
1320 /*
1321  * 'gpmc' class
1322  * general purpose memory controller
1323  */
1324
1325 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1326         .rev_offs       = 0x0000,
1327         .sysc_offs      = 0x0010,
1328         .syss_offs      = 0x0014,
1329         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1330                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1331         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1332         .sysc_fields    = &omap_hwmod_sysc_type1,
1333 };
1334
1335 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1336         .name   = "gpmc",
1337         .sysc   = &omap44xx_gpmc_sysc,
1338 };
1339
1340 /* gpmc */
1341 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1342         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1343         { .irq = -1 }
1344 };
1345
1346 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1347         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1348         { .dma_req = -1 }
1349 };
1350
1351 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1352         .name           = "gpmc",
1353         .class          = &omap44xx_gpmc_hwmod_class,
1354         .clkdm_name     = "l3_2_clkdm",
1355         /*
1356          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1357          * block.  It is not being added due to any known bugs with
1358          * resetting the GPMC IP block, but rather because any timings
1359          * set by the bootloader are not being correctly programmed by
1360          * the kernel from the board file or DT data.
1361          * HWMOD_INIT_NO_RESET should be removed ASAP.
1362          */
1363         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1364         .mpu_irqs       = omap44xx_gpmc_irqs,
1365         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1366         .prcm = {
1367                 .omap4 = {
1368                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1369                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1370                         .modulemode   = MODULEMODE_HWCTRL,
1371                 },
1372         },
1373 };
1374
1375 /*
1376  * 'gpu' class
1377  * 2d/3d graphics accelerator
1378  */
1379
1380 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1381         .rev_offs       = 0x1fc00,
1382         .sysc_offs      = 0x1fc10,
1383         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1385                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1386                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1387         .sysc_fields    = &omap_hwmod_sysc_type2,
1388 };
1389
1390 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1391         .name   = "gpu",
1392         .sysc   = &omap44xx_gpu_sysc,
1393 };
1394
1395 /* gpu */
1396 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1397         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1398         { .irq = -1 }
1399 };
1400
1401 static struct omap_hwmod omap44xx_gpu_hwmod = {
1402         .name           = "gpu",
1403         .class          = &omap44xx_gpu_hwmod_class,
1404         .clkdm_name     = "l3_gfx_clkdm",
1405         .mpu_irqs       = omap44xx_gpu_irqs,
1406         .main_clk       = "gpu_fck",
1407         .prcm = {
1408                 .omap4 = {
1409                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1410                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1411                         .modulemode   = MODULEMODE_SWCTRL,
1412                 },
1413         },
1414 };
1415
1416 /*
1417  * 'hdq1w' class
1418  * hdq / 1-wire serial interface controller
1419  */
1420
1421 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1422         .rev_offs       = 0x0000,
1423         .sysc_offs      = 0x0014,
1424         .syss_offs      = 0x0018,
1425         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1426                            SYSS_HAS_RESET_STATUS),
1427         .sysc_fields    = &omap_hwmod_sysc_type1,
1428 };
1429
1430 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1431         .name   = "hdq1w",
1432         .sysc   = &omap44xx_hdq1w_sysc,
1433 };
1434
1435 /* hdq1w */
1436 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1437         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1438         { .irq = -1 }
1439 };
1440
1441 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1442         .name           = "hdq1w",
1443         .class          = &omap44xx_hdq1w_hwmod_class,
1444         .clkdm_name     = "l4_per_clkdm",
1445         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1446         .mpu_irqs       = omap44xx_hdq1w_irqs,
1447         .main_clk       = "hdq1w_fck",
1448         .prcm = {
1449                 .omap4 = {
1450                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1451                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1452                         .modulemode   = MODULEMODE_SWCTRL,
1453                 },
1454         },
1455 };
1456
1457 /*
1458  * 'hsi' class
1459  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1460  * serial if)
1461  */
1462
1463 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1464         .rev_offs       = 0x0000,
1465         .sysc_offs      = 0x0010,
1466         .syss_offs      = 0x0014,
1467         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1468                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1469                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1470         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1471                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1472                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1473         .sysc_fields    = &omap_hwmod_sysc_type1,
1474 };
1475
1476 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1477         .name   = "hsi",
1478         .sysc   = &omap44xx_hsi_sysc,
1479 };
1480
1481 /* hsi */
1482 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1483         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1484         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1485         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1486         { .irq = -1 }
1487 };
1488
1489 static struct omap_hwmod omap44xx_hsi_hwmod = {
1490         .name           = "hsi",
1491         .class          = &omap44xx_hsi_hwmod_class,
1492         .clkdm_name     = "l3_init_clkdm",
1493         .mpu_irqs       = omap44xx_hsi_irqs,
1494         .main_clk       = "hsi_fck",
1495         .prcm = {
1496                 .omap4 = {
1497                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1498                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1499                         .modulemode   = MODULEMODE_HWCTRL,
1500                 },
1501         },
1502 };
1503
1504 /*
1505  * 'i2c' class
1506  * multimaster high-speed i2c controller
1507  */
1508
1509 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1510         .sysc_offs      = 0x0010,
1511         .syss_offs      = 0x0090,
1512         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1513                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1514                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1515         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1516                            SIDLE_SMART_WKUP),
1517         .clockact       = CLOCKACT_TEST_ICLK,
1518         .sysc_fields    = &omap_hwmod_sysc_type1,
1519 };
1520
1521 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1522         .name   = "i2c",
1523         .sysc   = &omap44xx_i2c_sysc,
1524         .rev    = OMAP_I2C_IP_VERSION_2,
1525         .reset  = &omap_i2c_reset,
1526 };
1527
1528 static struct omap_i2c_dev_attr i2c_dev_attr = {
1529         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1530                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1531 };
1532
1533 /* i2c1 */
1534 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1535         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1536         { .irq = -1 }
1537 };
1538
1539 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1540         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1541         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1542         { .dma_req = -1 }
1543 };
1544
1545 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1546         .name           = "i2c1",
1547         .class          = &omap44xx_i2c_hwmod_class,
1548         .clkdm_name     = "l4_per_clkdm",
1549         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1550         .mpu_irqs       = omap44xx_i2c1_irqs,
1551         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1552         .main_clk       = "i2c1_fck",
1553         .prcm = {
1554                 .omap4 = {
1555                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1556                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1557                         .modulemode   = MODULEMODE_SWCTRL,
1558                 },
1559         },
1560         .dev_attr       = &i2c_dev_attr,
1561 };
1562
1563 /* i2c2 */
1564 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1565         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1566         { .irq = -1 }
1567 };
1568
1569 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1570         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1571         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1572         { .dma_req = -1 }
1573 };
1574
1575 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1576         .name           = "i2c2",
1577         .class          = &omap44xx_i2c_hwmod_class,
1578         .clkdm_name     = "l4_per_clkdm",
1579         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1580         .mpu_irqs       = omap44xx_i2c2_irqs,
1581         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1582         .main_clk       = "i2c2_fck",
1583         .prcm = {
1584                 .omap4 = {
1585                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1586                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1587                         .modulemode   = MODULEMODE_SWCTRL,
1588                 },
1589         },
1590         .dev_attr       = &i2c_dev_attr,
1591 };
1592
1593 /* i2c3 */
1594 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1595         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1596         { .irq = -1 }
1597 };
1598
1599 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1600         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1601         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1602         { .dma_req = -1 }
1603 };
1604
1605 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1606         .name           = "i2c3",
1607         .class          = &omap44xx_i2c_hwmod_class,
1608         .clkdm_name     = "l4_per_clkdm",
1609         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1610         .mpu_irqs       = omap44xx_i2c3_irqs,
1611         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1612         .main_clk       = "i2c3_fck",
1613         .prcm = {
1614                 .omap4 = {
1615                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1616                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1617                         .modulemode   = MODULEMODE_SWCTRL,
1618                 },
1619         },
1620         .dev_attr       = &i2c_dev_attr,
1621 };
1622
1623 /* i2c4 */
1624 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1625         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1626         { .irq = -1 }
1627 };
1628
1629 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1630         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1631         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1632         { .dma_req = -1 }
1633 };
1634
1635 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1636         .name           = "i2c4",
1637         .class          = &omap44xx_i2c_hwmod_class,
1638         .clkdm_name     = "l4_per_clkdm",
1639         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1640         .mpu_irqs       = omap44xx_i2c4_irqs,
1641         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1642         .main_clk       = "i2c4_fck",
1643         .prcm = {
1644                 .omap4 = {
1645                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1646                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1647                         .modulemode   = MODULEMODE_SWCTRL,
1648                 },
1649         },
1650         .dev_attr       = &i2c_dev_attr,
1651 };
1652
1653 /*
1654  * 'ipu' class
1655  * imaging processor unit
1656  */
1657
1658 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1659         .name   = "ipu",
1660 };
1661
1662 /* ipu */
1663 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1664         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1665         { .irq = -1 }
1666 };
1667
1668 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1669         { .name = "cpu0", .rst_shift = 0 },
1670         { .name = "cpu1", .rst_shift = 1 },
1671 };
1672
1673 static struct omap_hwmod omap44xx_ipu_hwmod = {
1674         .name           = "ipu",
1675         .class          = &omap44xx_ipu_hwmod_class,
1676         .clkdm_name     = "ducati_clkdm",
1677         .mpu_irqs       = omap44xx_ipu_irqs,
1678         .rst_lines      = omap44xx_ipu_resets,
1679         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1680         .main_clk       = "ipu_fck",
1681         .prcm = {
1682                 .omap4 = {
1683                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1684                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1685                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1686                         .modulemode   = MODULEMODE_HWCTRL,
1687                 },
1688         },
1689 };
1690
1691 /*
1692  * 'iss' class
1693  * external images sensor pixel data processor
1694  */
1695
1696 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1697         .rev_offs       = 0x0000,
1698         .sysc_offs      = 0x0010,
1699         /*
1700          * ISS needs 100 OCP clk cycles delay after a softreset before
1701          * accessing sysconfig again.
1702          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1703          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1704          *
1705          * TODO: Indicate errata when available.
1706          */
1707         .srst_udelay    = 2,
1708         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1709                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1710         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1711                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1712                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1713         .sysc_fields    = &omap_hwmod_sysc_type2,
1714 };
1715
1716 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1717         .name   = "iss",
1718         .sysc   = &omap44xx_iss_sysc,
1719 };
1720
1721 /* iss */
1722 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1723         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1724         { .irq = -1 }
1725 };
1726
1727 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1728         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1729         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1730         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1731         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1732         { .dma_req = -1 }
1733 };
1734
1735 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1736         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1737 };
1738
1739 static struct omap_hwmod omap44xx_iss_hwmod = {
1740         .name           = "iss",
1741         .class          = &omap44xx_iss_hwmod_class,
1742         .clkdm_name     = "iss_clkdm",
1743         .mpu_irqs       = omap44xx_iss_irqs,
1744         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1745         .main_clk       = "iss_fck",
1746         .prcm = {
1747                 .omap4 = {
1748                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1749                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1750                         .modulemode   = MODULEMODE_SWCTRL,
1751                 },
1752         },
1753         .opt_clks       = iss_opt_clks,
1754         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1755 };
1756
1757 /*
1758  * 'iva' class
1759  * multi-standard video encoder/decoder hardware accelerator
1760  */
1761
1762 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1763         .name   = "iva",
1764 };
1765
1766 /* iva */
1767 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1768         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1769         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1771         { .irq = -1 }
1772 };
1773
1774 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1775         { .name = "seq0", .rst_shift = 0 },
1776         { .name = "seq1", .rst_shift = 1 },
1777         { .name = "logic", .rst_shift = 2 },
1778 };
1779
1780 static struct omap_hwmod omap44xx_iva_hwmod = {
1781         .name           = "iva",
1782         .class          = &omap44xx_iva_hwmod_class,
1783         .clkdm_name     = "ivahd_clkdm",
1784         .mpu_irqs       = omap44xx_iva_irqs,
1785         .rst_lines      = omap44xx_iva_resets,
1786         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1787         .main_clk       = "iva_fck",
1788         .prcm = {
1789                 .omap4 = {
1790                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1791                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1792                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1793                         .modulemode   = MODULEMODE_HWCTRL,
1794                 },
1795         },
1796 };
1797
1798 /*
1799  * 'kbd' class
1800  * keyboard controller
1801  */
1802
1803 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1804         .rev_offs       = 0x0000,
1805         .sysc_offs      = 0x0010,
1806         .syss_offs      = 0x0014,
1807         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1808                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1809                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1810                            SYSS_HAS_RESET_STATUS),
1811         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1812         .sysc_fields    = &omap_hwmod_sysc_type1,
1813 };
1814
1815 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1816         .name   = "kbd",
1817         .sysc   = &omap44xx_kbd_sysc,
1818 };
1819
1820 /* kbd */
1821 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1822         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1823         { .irq = -1 }
1824 };
1825
1826 static struct omap_hwmod omap44xx_kbd_hwmod = {
1827         .name           = "kbd",
1828         .class          = &omap44xx_kbd_hwmod_class,
1829         .clkdm_name     = "l4_wkup_clkdm",
1830         .mpu_irqs       = omap44xx_kbd_irqs,
1831         .main_clk       = "kbd_fck",
1832         .prcm = {
1833                 .omap4 = {
1834                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1835                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1836                         .modulemode   = MODULEMODE_SWCTRL,
1837                 },
1838         },
1839 };
1840
1841 /*
1842  * 'mailbox' class
1843  * mailbox module allowing communication between the on-chip processors using a
1844  * queued mailbox-interrupt mechanism.
1845  */
1846
1847 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1848         .rev_offs       = 0x0000,
1849         .sysc_offs      = 0x0010,
1850         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1851                            SYSC_HAS_SOFTRESET),
1852         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1853         .sysc_fields    = &omap_hwmod_sysc_type2,
1854 };
1855
1856 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1857         .name   = "mailbox",
1858         .sysc   = &omap44xx_mailbox_sysc,
1859 };
1860
1861 /* mailbox */
1862 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1863         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1864         { .irq = -1 }
1865 };
1866
1867 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1868         .name           = "mailbox",
1869         .class          = &omap44xx_mailbox_hwmod_class,
1870         .clkdm_name     = "l4_cfg_clkdm",
1871         .mpu_irqs       = omap44xx_mailbox_irqs,
1872         .prcm = {
1873                 .omap4 = {
1874                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1875                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1876                 },
1877         },
1878 };
1879
1880 /*
1881  * 'mcasp' class
1882  * multi-channel audio serial port controller
1883  */
1884
1885 /* The IP is not compliant to type1 / type2 scheme */
1886 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1887         .sidle_shift    = 0,
1888 };
1889
1890 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1891         .sysc_offs      = 0x0004,
1892         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1893         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1894                            SIDLE_SMART_WKUP),
1895         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1896 };
1897
1898 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1899         .name   = "mcasp",
1900         .sysc   = &omap44xx_mcasp_sysc,
1901 };
1902
1903 /* mcasp */
1904 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1905         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1906         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1907         { .irq = -1 }
1908 };
1909
1910 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1911         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1912         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1913         { .dma_req = -1 }
1914 };
1915
1916 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1917         .name           = "mcasp",
1918         .class          = &omap44xx_mcasp_hwmod_class,
1919         .clkdm_name     = "abe_clkdm",
1920         .mpu_irqs       = omap44xx_mcasp_irqs,
1921         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1922         .main_clk       = "mcasp_fck",
1923         .prcm = {
1924                 .omap4 = {
1925                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1926                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1927                         .modulemode   = MODULEMODE_SWCTRL,
1928                 },
1929         },
1930 };
1931
1932 /*
1933  * 'mcbsp' class
1934  * multi channel buffered serial port controller
1935  */
1936
1937 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1938         .sysc_offs      = 0x008c,
1939         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1940                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1942         .sysc_fields    = &omap_hwmod_sysc_type1,
1943 };
1944
1945 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1946         .name   = "mcbsp",
1947         .sysc   = &omap44xx_mcbsp_sysc,
1948         .rev    = MCBSP_CONFIG_TYPE4,
1949 };
1950
1951 /* mcbsp1 */
1952 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1953         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1954         { .irq = -1 }
1955 };
1956
1957 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1958         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1959         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1960         { .dma_req = -1 }
1961 };
1962
1963 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1964         { .role = "pad_fck", .clk = "pad_clks_ck" },
1965         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1966 };
1967
1968 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1969         .name           = "mcbsp1",
1970         .class          = &omap44xx_mcbsp_hwmod_class,
1971         .clkdm_name     = "abe_clkdm",
1972         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1973         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1974         .main_clk       = "mcbsp1_fck",
1975         .prcm = {
1976                 .omap4 = {
1977                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1978                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1979                         .modulemode   = MODULEMODE_SWCTRL,
1980                 },
1981         },
1982         .opt_clks       = mcbsp1_opt_clks,
1983         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1984 };
1985
1986 /* mcbsp2 */
1987 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1988         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1989         { .irq = -1 }
1990 };
1991
1992 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1993         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1994         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1995         { .dma_req = -1 }
1996 };
1997
1998 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1999         { .role = "pad_fck", .clk = "pad_clks_ck" },
2000         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2001 };
2002
2003 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2004         .name           = "mcbsp2",
2005         .class          = &omap44xx_mcbsp_hwmod_class,
2006         .clkdm_name     = "abe_clkdm",
2007         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2008         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2009         .main_clk       = "mcbsp2_fck",
2010         .prcm = {
2011                 .omap4 = {
2012                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2013                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2014                         .modulemode   = MODULEMODE_SWCTRL,
2015                 },
2016         },
2017         .opt_clks       = mcbsp2_opt_clks,
2018         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2019 };
2020
2021 /* mcbsp3 */
2022 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2023         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2024         { .irq = -1 }
2025 };
2026
2027 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2028         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2029         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2030         { .dma_req = -1 }
2031 };
2032
2033 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2034         { .role = "pad_fck", .clk = "pad_clks_ck" },
2035         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2036 };
2037
2038 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2039         .name           = "mcbsp3",
2040         .class          = &omap44xx_mcbsp_hwmod_class,
2041         .clkdm_name     = "abe_clkdm",
2042         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2043         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2044         .main_clk       = "mcbsp3_fck",
2045         .prcm = {
2046                 .omap4 = {
2047                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2048                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2049                         .modulemode   = MODULEMODE_SWCTRL,
2050                 },
2051         },
2052         .opt_clks       = mcbsp3_opt_clks,
2053         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2054 };
2055
2056 /* mcbsp4 */
2057 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2058         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2059         { .irq = -1 }
2060 };
2061
2062 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2063         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2064         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2065         { .dma_req = -1 }
2066 };
2067
2068 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2069         { .role = "pad_fck", .clk = "pad_clks_ck" },
2070         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2071 };
2072
2073 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2074         .name           = "mcbsp4",
2075         .class          = &omap44xx_mcbsp_hwmod_class,
2076         .clkdm_name     = "l4_per_clkdm",
2077         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2078         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2079         .main_clk       = "mcbsp4_fck",
2080         .prcm = {
2081                 .omap4 = {
2082                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2083                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2084                         .modulemode   = MODULEMODE_SWCTRL,
2085                 },
2086         },
2087         .opt_clks       = mcbsp4_opt_clks,
2088         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2089 };
2090
2091 /*
2092  * 'mcpdm' class
2093  * multi channel pdm controller (proprietary interface with phoenix power
2094  * ic)
2095  */
2096
2097 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2098         .rev_offs       = 0x0000,
2099         .sysc_offs      = 0x0010,
2100         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2101                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2102         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2103                            SIDLE_SMART_WKUP),
2104         .sysc_fields    = &omap_hwmod_sysc_type2,
2105 };
2106
2107 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2108         .name   = "mcpdm",
2109         .sysc   = &omap44xx_mcpdm_sysc,
2110 };
2111
2112 /* mcpdm */
2113 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2114         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2115         { .irq = -1 }
2116 };
2117
2118 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2119         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2120         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2121         { .dma_req = -1 }
2122 };
2123
2124 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2125         .name           = "mcpdm",
2126         .class          = &omap44xx_mcpdm_hwmod_class,
2127         .clkdm_name     = "abe_clkdm",
2128         /*
2129          * It's suspected that the McPDM requires an off-chip main
2130          * functional clock, controlled via I2C.  This IP block is
2131          * currently reset very early during boot, before I2C is
2132          * available, so it doesn't seem that we have any choice in
2133          * the kernel other than to avoid resetting it.
2134          */
2135         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2136         .mpu_irqs       = omap44xx_mcpdm_irqs,
2137         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2138         .main_clk       = "mcpdm_fck",
2139         .prcm = {
2140                 .omap4 = {
2141                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2142                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2143                         .modulemode   = MODULEMODE_SWCTRL,
2144                 },
2145         },
2146 };
2147
2148 /*
2149  * 'mcspi' class
2150  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2151  * bus
2152  */
2153
2154 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2155         .rev_offs       = 0x0000,
2156         .sysc_offs      = 0x0010,
2157         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2158                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2160                            SIDLE_SMART_WKUP),
2161         .sysc_fields    = &omap_hwmod_sysc_type2,
2162 };
2163
2164 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2165         .name   = "mcspi",
2166         .sysc   = &omap44xx_mcspi_sysc,
2167         .rev    = OMAP4_MCSPI_REV,
2168 };
2169
2170 /* mcspi1 */
2171 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2172         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2173         { .irq = -1 }
2174 };
2175
2176 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2177         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2178         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2179         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2180         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2181         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2182         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2183         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2185         { .dma_req = -1 }
2186 };
2187
2188 /* mcspi1 dev_attr */
2189 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2190         .num_chipselect = 4,
2191 };
2192
2193 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2194         .name           = "mcspi1",
2195         .class          = &omap44xx_mcspi_hwmod_class,
2196         .clkdm_name     = "l4_per_clkdm",
2197         .mpu_irqs       = omap44xx_mcspi1_irqs,
2198         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2199         .main_clk       = "mcspi1_fck",
2200         .prcm = {
2201                 .omap4 = {
2202                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2203                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2204                         .modulemode   = MODULEMODE_SWCTRL,
2205                 },
2206         },
2207         .dev_attr       = &mcspi1_dev_attr,
2208 };
2209
2210 /* mcspi2 */
2211 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2212         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2213         { .irq = -1 }
2214 };
2215
2216 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2217         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2218         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2219         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2220         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2221         { .dma_req = -1 }
2222 };
2223
2224 /* mcspi2 dev_attr */
2225 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2226         .num_chipselect = 2,
2227 };
2228
2229 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2230         .name           = "mcspi2",
2231         .class          = &omap44xx_mcspi_hwmod_class,
2232         .clkdm_name     = "l4_per_clkdm",
2233         .mpu_irqs       = omap44xx_mcspi2_irqs,
2234         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2235         .main_clk       = "mcspi2_fck",
2236         .prcm = {
2237                 .omap4 = {
2238                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2239                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2240                         .modulemode   = MODULEMODE_SWCTRL,
2241                 },
2242         },
2243         .dev_attr       = &mcspi2_dev_attr,
2244 };
2245
2246 /* mcspi3 */
2247 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2248         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2249         { .irq = -1 }
2250 };
2251
2252 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2253         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2254         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2255         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2256         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2257         { .dma_req = -1 }
2258 };
2259
2260 /* mcspi3 dev_attr */
2261 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2262         .num_chipselect = 2,
2263 };
2264
2265 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2266         .name           = "mcspi3",
2267         .class          = &omap44xx_mcspi_hwmod_class,
2268         .clkdm_name     = "l4_per_clkdm",
2269         .mpu_irqs       = omap44xx_mcspi3_irqs,
2270         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2271         .main_clk       = "mcspi3_fck",
2272         .prcm = {
2273                 .omap4 = {
2274                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2275                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2276                         .modulemode   = MODULEMODE_SWCTRL,
2277                 },
2278         },
2279         .dev_attr       = &mcspi3_dev_attr,
2280 };
2281
2282 /* mcspi4 */
2283 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2284         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2285         { .irq = -1 }
2286 };
2287
2288 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2289         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2290         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2291         { .dma_req = -1 }
2292 };
2293
2294 /* mcspi4 dev_attr */
2295 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2296         .num_chipselect = 1,
2297 };
2298
2299 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2300         .name           = "mcspi4",
2301         .class          = &omap44xx_mcspi_hwmod_class,
2302         .clkdm_name     = "l4_per_clkdm",
2303         .mpu_irqs       = omap44xx_mcspi4_irqs,
2304         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2305         .main_clk       = "mcspi4_fck",
2306         .prcm = {
2307                 .omap4 = {
2308                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2309                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2310                         .modulemode   = MODULEMODE_SWCTRL,
2311                 },
2312         },
2313         .dev_attr       = &mcspi4_dev_attr,
2314 };
2315
2316 /*
2317  * 'mmc' class
2318  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2319  */
2320
2321 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2322         .rev_offs       = 0x0000,
2323         .sysc_offs      = 0x0010,
2324         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2325                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2326                            SYSC_HAS_SOFTRESET),
2327         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2328                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2329                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2330         .sysc_fields    = &omap_hwmod_sysc_type2,
2331 };
2332
2333 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2334         .name   = "mmc",
2335         .sysc   = &omap44xx_mmc_sysc,
2336 };
2337
2338 /* mmc1 */
2339 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2340         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2341         { .irq = -1 }
2342 };
2343
2344 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2345         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2346         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2347         { .dma_req = -1 }
2348 };
2349
2350 /* mmc1 dev_attr */
2351 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2352         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2353 };
2354
2355 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2356         .name           = "mmc1",
2357         .class          = &omap44xx_mmc_hwmod_class,
2358         .clkdm_name     = "l3_init_clkdm",
2359         .mpu_irqs       = omap44xx_mmc1_irqs,
2360         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2361         .main_clk       = "mmc1_fck",
2362         .prcm = {
2363                 .omap4 = {
2364                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2365                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2366                         .modulemode   = MODULEMODE_SWCTRL,
2367                 },
2368         },
2369         .dev_attr       = &mmc1_dev_attr,
2370 };
2371
2372 /* mmc2 */
2373 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2374         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2375         { .irq = -1 }
2376 };
2377
2378 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2379         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2380         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2381         { .dma_req = -1 }
2382 };
2383
2384 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2385         .name           = "mmc2",
2386         .class          = &omap44xx_mmc_hwmod_class,
2387         .clkdm_name     = "l3_init_clkdm",
2388         .mpu_irqs       = omap44xx_mmc2_irqs,
2389         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2390         .main_clk       = "mmc2_fck",
2391         .prcm = {
2392                 .omap4 = {
2393                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2394                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2395                         .modulemode   = MODULEMODE_SWCTRL,
2396                 },
2397         },
2398 };
2399
2400 /* mmc3 */
2401 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2402         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2403         { .irq = -1 }
2404 };
2405
2406 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2407         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2408         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2409         { .dma_req = -1 }
2410 };
2411
2412 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2413         .name           = "mmc3",
2414         .class          = &omap44xx_mmc_hwmod_class,
2415         .clkdm_name     = "l4_per_clkdm",
2416         .mpu_irqs       = omap44xx_mmc3_irqs,
2417         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2418         .main_clk       = "mmc3_fck",
2419         .prcm = {
2420                 .omap4 = {
2421                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2422                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2423                         .modulemode   = MODULEMODE_SWCTRL,
2424                 },
2425         },
2426 };
2427
2428 /* mmc4 */
2429 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2430         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2431         { .irq = -1 }
2432 };
2433
2434 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2435         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2436         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2437         { .dma_req = -1 }
2438 };
2439
2440 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2441         .name           = "mmc4",
2442         .class          = &omap44xx_mmc_hwmod_class,
2443         .clkdm_name     = "l4_per_clkdm",
2444         .mpu_irqs       = omap44xx_mmc4_irqs,
2445         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2446         .main_clk       = "mmc4_fck",
2447         .prcm = {
2448                 .omap4 = {
2449                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2450                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2451                         .modulemode   = MODULEMODE_SWCTRL,
2452                 },
2453         },
2454 };
2455
2456 /* mmc5 */
2457 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2458         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2459         { .irq = -1 }
2460 };
2461
2462 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2463         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2464         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2465         { .dma_req = -1 }
2466 };
2467
2468 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2469         .name           = "mmc5",
2470         .class          = &omap44xx_mmc_hwmod_class,
2471         .clkdm_name     = "l4_per_clkdm",
2472         .mpu_irqs       = omap44xx_mmc5_irqs,
2473         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2474         .main_clk       = "mmc5_fck",
2475         .prcm = {
2476                 .omap4 = {
2477                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2478                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2479                         .modulemode   = MODULEMODE_SWCTRL,
2480                 },
2481         },
2482 };
2483
2484 /*
2485  * 'mmu' class
2486  * The memory management unit performs virtual to physical address translation
2487  * for its requestors.
2488  */
2489
2490 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2491         .rev_offs       = 0x000,
2492         .sysc_offs      = 0x010,
2493         .syss_offs      = 0x014,
2494         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2495                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2496         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2497         .sysc_fields    = &omap_hwmod_sysc_type1,
2498 };
2499
2500 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2501         .name = "mmu",
2502         .sysc = &mmu_sysc,
2503 };
2504
2505 /* mmu ipu */
2506
2507 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2508         .da_start       = 0x0,
2509         .da_end         = 0xfffff000,
2510         .nr_tlb_entries = 32,
2511 };
2512
2513 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2514 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2515         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2516         { .irq = -1 }
2517 };
2518
2519 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2520         { .name = "mmu_cache", .rst_shift = 2 },
2521 };
2522
2523 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2524         {
2525                 .pa_start       = 0x55082000,
2526                 .pa_end         = 0x550820ff,
2527                 .flags          = ADDR_TYPE_RT,
2528         },
2529         { }
2530 };
2531
2532 /* l3_main_2 -> mmu_ipu */
2533 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2534         .master         = &omap44xx_l3_main_2_hwmod,
2535         .slave          = &omap44xx_mmu_ipu_hwmod,
2536         .clk            = "l3_div_ck",
2537         .addr           = omap44xx_mmu_ipu_addrs,
2538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2539 };
2540
2541 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2542         .name           = "mmu_ipu",
2543         .class          = &omap44xx_mmu_hwmod_class,
2544         .clkdm_name     = "ducati_clkdm",
2545         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2546         .rst_lines      = omap44xx_mmu_ipu_resets,
2547         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2548         .main_clk       = "ducati_clk_mux_ck",
2549         .prcm = {
2550                 .omap4 = {
2551                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2552                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2553                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2554                         .modulemode   = MODULEMODE_HWCTRL,
2555                 },
2556         },
2557         .dev_attr       = &mmu_ipu_dev_attr,
2558 };
2559
2560 /* mmu dsp */
2561
2562 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2563         .da_start       = 0x0,
2564         .da_end         = 0xfffff000,
2565         .nr_tlb_entries = 32,
2566 };
2567
2568 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2569 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2570         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2571         { .irq = -1 }
2572 };
2573
2574 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2575         { .name = "mmu_cache", .rst_shift = 1 },
2576 };
2577
2578 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2579         {
2580                 .pa_start       = 0x4a066000,
2581                 .pa_end         = 0x4a0660ff,
2582                 .flags          = ADDR_TYPE_RT,
2583         },
2584         { }
2585 };
2586
2587 /* l4_cfg -> dsp */
2588 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2589         .master         = &omap44xx_l4_cfg_hwmod,
2590         .slave          = &omap44xx_mmu_dsp_hwmod,
2591         .clk            = "l4_div_ck",
2592         .addr           = omap44xx_mmu_dsp_addrs,
2593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2594 };
2595
2596 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2597         .name           = "mmu_dsp",
2598         .class          = &omap44xx_mmu_hwmod_class,
2599         .clkdm_name     = "tesla_clkdm",
2600         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2601         .rst_lines      = omap44xx_mmu_dsp_resets,
2602         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2603         .main_clk       = "dpll_iva_m4x2_ck",
2604         .prcm = {
2605                 .omap4 = {
2606                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2607                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2608                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2609                         .modulemode   = MODULEMODE_HWCTRL,
2610                 },
2611         },
2612         .dev_attr       = &mmu_dsp_dev_attr,
2613 };
2614
2615 /*
2616  * 'mpu' class
2617  * mpu sub-system
2618  */
2619
2620 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2621         .name   = "mpu",
2622 };
2623
2624 /* mpu */
2625 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2626         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2627         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2628         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2629         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2630         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2631         { .irq = -1 }
2632 };
2633
2634 static struct omap_hwmod omap44xx_mpu_hwmod = {
2635         .name           = "mpu",
2636         .class          = &omap44xx_mpu_hwmod_class,
2637         .clkdm_name     = "mpuss_clkdm",
2638         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2639         .mpu_irqs       = omap44xx_mpu_irqs,
2640         .main_clk       = "dpll_mpu_m2_ck",
2641         .prcm = {
2642                 .omap4 = {
2643                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2644                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2645                 },
2646         },
2647 };
2648
2649 /*
2650  * 'ocmc_ram' class
2651  * top-level core on-chip ram
2652  */
2653
2654 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2655         .name   = "ocmc_ram",
2656 };
2657
2658 /* ocmc_ram */
2659 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2660         .name           = "ocmc_ram",
2661         .class          = &omap44xx_ocmc_ram_hwmod_class,
2662         .clkdm_name     = "l3_2_clkdm",
2663         .prcm = {
2664                 .omap4 = {
2665                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2666                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2667                 },
2668         },
2669 };
2670
2671 /*
2672  * 'ocp2scp' class
2673  * bridge to transform ocp interface protocol to scp (serial control port)
2674  * protocol
2675  */
2676
2677 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2678         .rev_offs       = 0x0000,
2679         .sysc_offs      = 0x0010,
2680         .syss_offs      = 0x0014,
2681         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2682                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2683         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2684         .sysc_fields    = &omap_hwmod_sysc_type1,
2685 };
2686
2687 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2688         .name   = "ocp2scp",
2689         .sysc   = &omap44xx_ocp2scp_sysc,
2690 };
2691
2692 /* ocp2scp_usb_phy */
2693 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2694         .name           = "ocp2scp_usb_phy",
2695         .class          = &omap44xx_ocp2scp_hwmod_class,
2696         .clkdm_name     = "l3_init_clkdm",
2697         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2698         .prcm = {
2699                 .omap4 = {
2700                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2701                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2702                         .modulemode   = MODULEMODE_HWCTRL,
2703                 },
2704         },
2705 };
2706
2707 /*
2708  * 'prcm' class
2709  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2710  * + clock manager 1 (in always on power domain) + local prm in mpu
2711  */
2712
2713 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2714         .name   = "prcm",
2715 };
2716
2717 /* prcm_mpu */
2718 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2719         .name           = "prcm_mpu",
2720         .class          = &omap44xx_prcm_hwmod_class,
2721         .clkdm_name     = "l4_wkup_clkdm",
2722         .flags          = HWMOD_NO_IDLEST,
2723         .prcm = {
2724                 .omap4 = {
2725                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2726                 },
2727         },
2728 };
2729
2730 /* cm_core_aon */
2731 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2732         .name           = "cm_core_aon",
2733         .class          = &omap44xx_prcm_hwmod_class,
2734         .flags          = HWMOD_NO_IDLEST,
2735         .prcm = {
2736                 .omap4 = {
2737                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2738                 },
2739         },
2740 };
2741
2742 /* cm_core */
2743 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2744         .name           = "cm_core",
2745         .class          = &omap44xx_prcm_hwmod_class,
2746         .flags          = HWMOD_NO_IDLEST,
2747         .prcm = {
2748                 .omap4 = {
2749                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2750                 },
2751         },
2752 };
2753
2754 /* prm */
2755 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2756         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2757         { .irq = -1 }
2758 };
2759
2760 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2761         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2762         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2763 };
2764
2765 static struct omap_hwmod omap44xx_prm_hwmod = {
2766         .name           = "prm",
2767         .class          = &omap44xx_prcm_hwmod_class,
2768         .mpu_irqs       = omap44xx_prm_irqs,
2769         .rst_lines      = omap44xx_prm_resets,
2770         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2771 };
2772
2773 /*
2774  * 'scrm' class
2775  * system clock and reset manager
2776  */
2777
2778 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2779         .name   = "scrm",
2780 };
2781
2782 /* scrm */
2783 static struct omap_hwmod omap44xx_scrm_hwmod = {
2784         .name           = "scrm",
2785         .class          = &omap44xx_scrm_hwmod_class,
2786         .clkdm_name     = "l4_wkup_clkdm",
2787         .prcm = {
2788                 .omap4 = {
2789                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2790                 },
2791         },
2792 };
2793
2794 /*
2795  * 'sl2if' class
2796  * shared level 2 memory interface
2797  */
2798
2799 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2800         .name   = "sl2if",
2801 };
2802
2803 /* sl2if */
2804 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2805         .name           = "sl2if",
2806         .class          = &omap44xx_sl2if_hwmod_class,
2807         .clkdm_name     = "ivahd_clkdm",
2808         .prcm = {
2809                 .omap4 = {
2810                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2811                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2812                         .modulemode   = MODULEMODE_HWCTRL,
2813                 },
2814         },
2815 };
2816
2817 /*
2818  * 'slimbus' class
2819  * bidirectional, multi-drop, multi-channel two-line serial interface between
2820  * the device and external components
2821  */
2822
2823 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2824         .rev_offs       = 0x0000,
2825         .sysc_offs      = 0x0010,
2826         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2827                            SYSC_HAS_SOFTRESET),
2828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2829                            SIDLE_SMART_WKUP),
2830         .sysc_fields    = &omap_hwmod_sysc_type2,
2831 };
2832
2833 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2834         .name   = "slimbus",
2835         .sysc   = &omap44xx_slimbus_sysc,
2836 };
2837
2838 /* slimbus1 */
2839 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2840         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2841         { .irq = -1 }
2842 };
2843
2844 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2845         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2846         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2847         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2848         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2849         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2850         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2851         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2852         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2853         { .dma_req = -1 }
2854 };
2855
2856 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2857         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2858         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2859         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2860         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2861 };
2862
2863 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2864         .name           = "slimbus1",
2865         .class          = &omap44xx_slimbus_hwmod_class,
2866         .clkdm_name     = "abe_clkdm",
2867         .mpu_irqs       = omap44xx_slimbus1_irqs,
2868         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2869         .prcm = {
2870                 .omap4 = {
2871                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2872                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2873                         .modulemode   = MODULEMODE_SWCTRL,
2874                 },
2875         },
2876         .opt_clks       = slimbus1_opt_clks,
2877         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2878 };
2879
2880 /* slimbus2 */
2881 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2882         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2883         { .irq = -1 }
2884 };
2885
2886 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2887         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2888         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2889         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2890         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2891         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2892         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2893         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2894         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2895         { .dma_req = -1 }
2896 };
2897
2898 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2899         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2900         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2901         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2902 };
2903
2904 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2905         .name           = "slimbus2",
2906         .class          = &omap44xx_slimbus_hwmod_class,
2907         .clkdm_name     = "l4_per_clkdm",
2908         .mpu_irqs       = omap44xx_slimbus2_irqs,
2909         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2910         .prcm = {
2911                 .omap4 = {
2912                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2913                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2914                         .modulemode   = MODULEMODE_SWCTRL,
2915                 },
2916         },
2917         .opt_clks       = slimbus2_opt_clks,
2918         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2919 };
2920
2921 /*
2922  * 'smartreflex' class
2923  * smartreflex module (monitor silicon performance and outputs a measure of
2924  * performance error)
2925  */
2926
2927 /* The IP is not compliant to type1 / type2 scheme */
2928 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2929         .sidle_shift    = 24,
2930         .enwkup_shift   = 26,
2931 };
2932
2933 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2934         .sysc_offs      = 0x0038,
2935         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2936         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2937                            SIDLE_SMART_WKUP),
2938         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2939 };
2940
2941 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2942         .name   = "smartreflex",
2943         .sysc   = &omap44xx_smartreflex_sysc,
2944         .rev    = 2,
2945 };
2946
2947 /* smartreflex_core */
2948 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2949         .sensor_voltdm_name   = "core",
2950 };
2951
2952 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2953         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2954         { .irq = -1 }
2955 };
2956
2957 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2958         .name           = "smartreflex_core",
2959         .class          = &omap44xx_smartreflex_hwmod_class,
2960         .clkdm_name     = "l4_ao_clkdm",
2961         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2962
2963         .main_clk       = "smartreflex_core_fck",
2964         .prcm = {
2965                 .omap4 = {
2966                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2967                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2968                         .modulemode   = MODULEMODE_SWCTRL,
2969                 },
2970         },
2971         .dev_attr       = &smartreflex_core_dev_attr,
2972 };
2973
2974 /* smartreflex_iva */
2975 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2976         .sensor_voltdm_name     = "iva",
2977 };
2978
2979 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2980         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2981         { .irq = -1 }
2982 };
2983
2984 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2985         .name           = "smartreflex_iva",
2986         .class          = &omap44xx_smartreflex_hwmod_class,
2987         .clkdm_name     = "l4_ao_clkdm",
2988         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2989         .main_clk       = "smartreflex_iva_fck",
2990         .prcm = {
2991                 .omap4 = {
2992                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2993                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2994                         .modulemode   = MODULEMODE_SWCTRL,
2995                 },
2996         },
2997         .dev_attr       = &smartreflex_iva_dev_attr,
2998 };
2999
3000 /* smartreflex_mpu */
3001 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3002         .sensor_voltdm_name     = "mpu",
3003 };
3004
3005 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3006         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3007         { .irq = -1 }
3008 };
3009
3010 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3011         .name           = "smartreflex_mpu",
3012         .class          = &omap44xx_smartreflex_hwmod_class,
3013         .clkdm_name     = "l4_ao_clkdm",
3014         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3015         .main_clk       = "smartreflex_mpu_fck",
3016         .prcm = {
3017                 .omap4 = {
3018                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3019                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3020                         .modulemode   = MODULEMODE_SWCTRL,
3021                 },
3022         },
3023         .dev_attr       = &smartreflex_mpu_dev_attr,
3024 };
3025
3026 /*
3027  * 'spinlock' class
3028  * spinlock provides hardware assistance for synchronizing the processes
3029  * running on multiple processors
3030  */
3031
3032 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3033         .rev_offs       = 0x0000,
3034         .sysc_offs      = 0x0010,
3035         .syss_offs      = 0x0014,
3036         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3037                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3038                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3039         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3040                            SIDLE_SMART_WKUP),
3041         .sysc_fields    = &omap_hwmod_sysc_type1,
3042 };
3043
3044 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3045         .name   = "spinlock",
3046         .sysc   = &omap44xx_spinlock_sysc,
3047 };
3048
3049 /* spinlock */
3050 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3051         .name           = "spinlock",
3052         .class          = &omap44xx_spinlock_hwmod_class,
3053         .clkdm_name     = "l4_cfg_clkdm",
3054         .prcm = {
3055                 .omap4 = {
3056                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3057                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3058                 },
3059         },
3060 };
3061
3062 /*
3063  * 'timer' class
3064  * general purpose timer module with accurate 1ms tick
3065  * This class contains several variants: ['timer_1ms', 'timer']
3066  */
3067
3068 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3069         .rev_offs       = 0x0000,
3070         .sysc_offs      = 0x0010,
3071         .syss_offs      = 0x0014,
3072         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3073                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3074                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3075                            SYSS_HAS_RESET_STATUS),
3076         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3077         .sysc_fields    = &omap_hwmod_sysc_type1,
3078 };
3079
3080 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3081         .name   = "timer",
3082         .sysc   = &omap44xx_timer_1ms_sysc,
3083 };
3084
3085 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3086         .rev_offs       = 0x0000,
3087         .sysc_offs      = 0x0010,
3088         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3089                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3091                            SIDLE_SMART_WKUP),
3092         .sysc_fields    = &omap_hwmod_sysc_type2,
3093 };
3094
3095 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3096         .name   = "timer",
3097         .sysc   = &omap44xx_timer_sysc,
3098 };
3099
3100 /* always-on timers dev attribute */
3101 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3102         .timer_capability       = OMAP_TIMER_ALWON,
3103 };
3104
3105 /* pwm timers dev attribute */
3106 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3107         .timer_capability       = OMAP_TIMER_HAS_PWM,
3108 };
3109
3110 /* timers with DSP interrupt dev attribute */
3111 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3112         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3113 };
3114
3115 /* pwm timers with DSP interrupt dev attribute */
3116 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3117         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3118 };
3119
3120 /* timer1 */
3121 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3122         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3123         { .irq = -1 }
3124 };
3125
3126 static struct omap_hwmod omap44xx_timer1_hwmod = {
3127         .name           = "timer1",
3128         .class          = &omap44xx_timer_1ms_hwmod_class,
3129         .clkdm_name     = "l4_wkup_clkdm",
3130         .mpu_irqs       = omap44xx_timer1_irqs,
3131         .main_clk       = "timer1_fck",
3132         .prcm = {
3133                 .omap4 = {
3134                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3135                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3136                         .modulemode   = MODULEMODE_SWCTRL,
3137                 },
3138         },
3139         .dev_attr       = &capability_alwon_dev_attr,
3140 };
3141
3142 /* timer2 */
3143 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3144         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3145         { .irq = -1 }
3146 };
3147
3148 static struct omap_hwmod omap44xx_timer2_hwmod = {
3149         .name           = "timer2",
3150         .class          = &omap44xx_timer_1ms_hwmod_class,
3151         .clkdm_name     = "l4_per_clkdm",
3152         .mpu_irqs       = omap44xx_timer2_irqs,
3153         .main_clk       = "timer2_fck",
3154         .prcm = {
3155                 .omap4 = {
3156                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3157                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3158                         .modulemode   = MODULEMODE_SWCTRL,
3159                 },
3160         },
3161 };
3162
3163 /* timer3 */
3164 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3165         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3166         { .irq = -1 }
3167 };
3168
3169 static struct omap_hwmod omap44xx_timer3_hwmod = {
3170         .name           = "timer3",
3171         .class          = &omap44xx_timer_hwmod_class,
3172         .clkdm_name     = "l4_per_clkdm",
3173         .mpu_irqs       = omap44xx_timer3_irqs,
3174         .main_clk       = "timer3_fck",
3175         .prcm = {
3176                 .omap4 = {
3177                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3178                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3179                         .modulemode   = MODULEMODE_SWCTRL,
3180                 },
3181         },
3182 };
3183
3184 /* timer4 */
3185 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3186         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3187         { .irq = -1 }
3188 };
3189
3190 static struct omap_hwmod omap44xx_timer4_hwmod = {
3191         .name           = "timer4",
3192         .class          = &omap44xx_timer_hwmod_class,
3193         .clkdm_name     = "l4_per_clkdm",
3194         .mpu_irqs       = omap44xx_timer4_irqs,
3195         .main_clk       = "timer4_fck",
3196         .prcm = {
3197                 .omap4 = {
3198                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3199                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3200                         .modulemode   = MODULEMODE_SWCTRL,
3201                 },
3202         },
3203 };
3204
3205 /* timer5 */
3206 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3207         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3208         { .irq = -1 }
3209 };
3210
3211 static struct omap_hwmod omap44xx_timer5_hwmod = {
3212         .name           = "timer5",
3213         .class          = &omap44xx_timer_hwmod_class,
3214         .clkdm_name     = "abe_clkdm",
3215         .mpu_irqs       = omap44xx_timer5_irqs,
3216         .main_clk       = "timer5_fck",
3217         .prcm = {
3218                 .omap4 = {
3219                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3220                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3221                         .modulemode   = MODULEMODE_SWCTRL,
3222                 },
3223         },
3224         .dev_attr       = &capability_dsp_dev_attr,
3225 };
3226
3227 /* timer6 */
3228 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3229         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3230         { .irq = -1 }
3231 };
3232
3233 static struct omap_hwmod omap44xx_timer6_hwmod = {
3234         .name           = "timer6",
3235         .class          = &omap44xx_timer_hwmod_class,
3236         .clkdm_name     = "abe_clkdm",
3237         .mpu_irqs       = omap44xx_timer6_irqs,
3238
3239         .main_clk       = "timer6_fck",
3240         .prcm = {
3241                 .omap4 = {
3242                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3243                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3244                         .modulemode   = MODULEMODE_SWCTRL,
3245                 },
3246         },
3247         .dev_attr       = &capability_dsp_dev_attr,
3248 };
3249
3250 /* timer7 */
3251 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3252         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3253         { .irq = -1 }
3254 };
3255
3256 static struct omap_hwmod omap44xx_timer7_hwmod = {
3257         .name           = "timer7",
3258         .class          = &omap44xx_timer_hwmod_class,
3259         .clkdm_name     = "abe_clkdm",
3260         .mpu_irqs       = omap44xx_timer7_irqs,
3261         .main_clk       = "timer7_fck",
3262         .prcm = {
3263                 .omap4 = {
3264                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3265                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3266                         .modulemode   = MODULEMODE_SWCTRL,
3267                 },
3268         },
3269         .dev_attr       = &capability_dsp_dev_attr,
3270 };
3271
3272 /* timer8 */
3273 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3274         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3275         { .irq = -1 }
3276 };
3277
3278 static struct omap_hwmod omap44xx_timer8_hwmod = {
3279         .name           = "timer8",
3280         .class          = &omap44xx_timer_hwmod_class,
3281         .clkdm_name     = "abe_clkdm",
3282         .mpu_irqs       = omap44xx_timer8_irqs,
3283         .main_clk       = "timer8_fck",
3284         .prcm = {
3285                 .omap4 = {
3286                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3287                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3288                         .modulemode   = MODULEMODE_SWCTRL,
3289                 },
3290         },
3291         .dev_attr       = &capability_dsp_pwm_dev_attr,
3292 };
3293
3294 /* timer9 */
3295 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3296         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3297         { .irq = -1 }
3298 };
3299
3300 static struct omap_hwmod omap44xx_timer9_hwmod = {
3301         .name           = "timer9",
3302         .class          = &omap44xx_timer_hwmod_class,
3303         .clkdm_name     = "l4_per_clkdm",
3304         .mpu_irqs       = omap44xx_timer9_irqs,
3305         .main_clk       = "timer9_fck",
3306         .prcm = {
3307                 .omap4 = {
3308                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3309                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3310                         .modulemode   = MODULEMODE_SWCTRL,
3311                 },
3312         },
3313         .dev_attr       = &capability_pwm_dev_attr,
3314 };
3315
3316 /* timer10 */
3317 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3318         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3319         { .irq = -1 }
3320 };
3321
3322 static struct omap_hwmod omap44xx_timer10_hwmod = {
3323         .name           = "timer10",
3324         .class          = &omap44xx_timer_1ms_hwmod_class,
3325         .clkdm_name     = "l4_per_clkdm",
3326         .mpu_irqs       = omap44xx_timer10_irqs,
3327         .main_clk       = "timer10_fck",
3328         .prcm = {
3329                 .omap4 = {
3330                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3331                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3332                         .modulemode   = MODULEMODE_SWCTRL,
3333                 },
3334         },
3335         .dev_attr       = &capability_pwm_dev_attr,
3336 };
3337
3338 /* timer11 */
3339 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3340         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3341         { .irq = -1 }
3342 };
3343
3344 static struct omap_hwmod omap44xx_timer11_hwmod = {
3345         .name           = "timer11",
3346         .class          = &omap44xx_timer_hwmod_class,
3347         .clkdm_name     = "l4_per_clkdm",
3348         .mpu_irqs       = omap44xx_timer11_irqs,
3349         .main_clk       = "timer11_fck",
3350         .prcm = {
3351                 .omap4 = {
3352                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3353                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3354                         .modulemode   = MODULEMODE_SWCTRL,
3355                 },
3356         },
3357         .dev_attr       = &capability_pwm_dev_attr,
3358 };
3359
3360 /*
3361  * 'uart' class
3362  * universal asynchronous receiver/transmitter (uart)
3363  */
3364
3365 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3366         .rev_offs       = 0x0050,
3367         .sysc_offs      = 0x0054,
3368         .syss_offs      = 0x0058,
3369         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3370                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3371                            SYSS_HAS_RESET_STATUS),
3372         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3373                            SIDLE_SMART_WKUP),
3374         .sysc_fields    = &omap_hwmod_sysc_type1,
3375 };
3376
3377 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3378         .name   = "uart",
3379         .sysc   = &omap44xx_uart_sysc,
3380 };
3381
3382 /* uart1 */
3383 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3384         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3385         { .irq = -1 }
3386 };
3387
3388 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3389         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3390         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3391         { .dma_req = -1 }
3392 };
3393
3394 static struct omap_hwmod omap44xx_uart1_hwmod = {
3395         .name           = "uart1",
3396         .class          = &omap44xx_uart_hwmod_class,
3397         .clkdm_name     = "l4_per_clkdm",
3398         .mpu_irqs       = omap44xx_uart1_irqs,
3399         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3400         .main_clk       = "uart1_fck",
3401         .prcm = {
3402                 .omap4 = {
3403                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3404                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3405                         .modulemode   = MODULEMODE_SWCTRL,
3406                 },
3407         },
3408 };
3409
3410 /* uart2 */
3411 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3412         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3413         { .irq = -1 }
3414 };
3415
3416 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3417         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3418         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3419         { .dma_req = -1 }
3420 };
3421
3422 static struct omap_hwmod omap44xx_uart2_hwmod = {
3423         .name           = "uart2",
3424         .class          = &omap44xx_uart_hwmod_class,
3425         .clkdm_name     = "l4_per_clkdm",
3426         .mpu_irqs       = omap44xx_uart2_irqs,
3427         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3428         .main_clk       = "uart2_fck",
3429         .prcm = {
3430                 .omap4 = {
3431                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3432                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3433                         .modulemode   = MODULEMODE_SWCTRL,
3434                 },
3435         },
3436 };
3437
3438 /* uart3 */
3439 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3440         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3441         { .irq = -1 }
3442 };
3443
3444 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3445         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3446         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3447         { .dma_req = -1 }
3448 };
3449
3450 static struct omap_hwmod omap44xx_uart3_hwmod = {
3451         .name           = "uart3",
3452         .class          = &omap44xx_uart_hwmod_class,
3453         .clkdm_name     = "l4_per_clkdm",
3454         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3455         .mpu_irqs       = omap44xx_uart3_irqs,
3456         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3457         .main_clk       = "uart3_fck",
3458         .prcm = {
3459                 .omap4 = {
3460                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3461                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3462                         .modulemode   = MODULEMODE_SWCTRL,
3463                 },
3464         },
3465 };
3466
3467 /* uart4 */
3468 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3469         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3470         { .irq = -1 }
3471 };
3472
3473 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3474         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3475         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3476         { .dma_req = -1 }
3477 };
3478
3479 static struct omap_hwmod omap44xx_uart4_hwmod = {
3480         .name           = "uart4",
3481         .class          = &omap44xx_uart_hwmod_class,
3482         .clkdm_name     = "l4_per_clkdm",
3483         .mpu_irqs       = omap44xx_uart4_irqs,
3484         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3485         .main_clk       = "uart4_fck",
3486         .prcm = {
3487                 .omap4 = {
3488                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3489                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3490                         .modulemode   = MODULEMODE_SWCTRL,
3491                 },
3492         },
3493 };
3494
3495 /*
3496  * 'usb_host_fs' class
3497  * full-speed usb host controller
3498  */
3499
3500 /* The IP is not compliant to type1 / type2 scheme */
3501 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3502         .midle_shift    = 4,
3503         .sidle_shift    = 2,
3504         .srst_shift     = 1,
3505 };
3506
3507 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3508         .rev_offs       = 0x0000,
3509         .sysc_offs      = 0x0210,
3510         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3511                            SYSC_HAS_SOFTRESET),
3512         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3513                            SIDLE_SMART_WKUP),
3514         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3515 };
3516
3517 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3518         .name   = "usb_host_fs",
3519         .sysc   = &omap44xx_usb_host_fs_sysc,
3520 };
3521
3522 /* usb_host_fs */
3523 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3524         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3525         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3526         { .irq = -1 }
3527 };
3528
3529 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3530         .name           = "usb_host_fs",
3531         .class          = &omap44xx_usb_host_fs_hwmod_class,
3532         .clkdm_name     = "l3_init_clkdm",
3533         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3534         .main_clk       = "usb_host_fs_fck",
3535         .prcm = {
3536                 .omap4 = {
3537                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3538                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3539                         .modulemode   = MODULEMODE_SWCTRL,
3540                 },
3541         },
3542 };
3543
3544 /*
3545  * 'usb_host_hs' class
3546  * high-speed multi-port usb host controller
3547  */
3548
3549 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3550         .rev_offs       = 0x0000,
3551         .sysc_offs      = 0x0010,
3552         .syss_offs      = 0x0014,
3553         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3554                            SYSC_HAS_SOFTRESET),
3555         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3556                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3557                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3558         .sysc_fields    = &omap_hwmod_sysc_type2,
3559 };
3560
3561 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3562         .name   = "usb_host_hs",
3563         .sysc   = &omap44xx_usb_host_hs_sysc,
3564 };
3565
3566 /* usb_host_hs */
3567 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3568         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3569         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3570         { .irq = -1 }
3571 };
3572
3573 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3574         .name           = "usb_host_hs",
3575         .class          = &omap44xx_usb_host_hs_hwmod_class,
3576         .clkdm_name     = "l3_init_clkdm",
3577         .main_clk       = "usb_host_hs_fck",
3578         .prcm = {
3579                 .omap4 = {
3580                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3581                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3582                         .modulemode   = MODULEMODE_SWCTRL,
3583                 },
3584         },
3585         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3586
3587         /*
3588          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3589          * id: i660
3590          *
3591          * Description:
3592          * In the following configuration :
3593          * - USBHOST module is set to smart-idle mode
3594          * - PRCM asserts idle_req to the USBHOST module ( This typically
3595          *   happens when the system is going to a low power mode : all ports
3596          *   have been suspended, the master part of the USBHOST module has
3597          *   entered the standby state, and SW has cut the functional clocks)
3598          * - an USBHOST interrupt occurs before the module is able to answer
3599          *   idle_ack, typically a remote wakeup IRQ.
3600          * Then the USB HOST module will enter a deadlock situation where it
3601          * is no more accessible nor functional.
3602          *
3603          * Workaround:
3604          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3605          */
3606
3607         /*
3608          * Errata: USB host EHCI may stall when entering smart-standby mode
3609          * Id: i571
3610          *
3611          * Description:
3612          * When the USBHOST module is set to smart-standby mode, and when it is
3613          * ready to enter the standby state (i.e. all ports are suspended and
3614          * all attached devices are in suspend mode), then it can wrongly assert
3615          * the Mstandby signal too early while there are still some residual OCP
3616          * transactions ongoing. If this condition occurs, the internal state
3617          * machine may go to an undefined state and the USB link may be stuck
3618          * upon the next resume.
3619          *
3620          * Workaround:
3621          * Don't use smart standby; use only force standby,
3622          * hence HWMOD_SWSUP_MSTANDBY
3623          */
3624
3625         /*
3626          * During system boot; If the hwmod framework resets the module
3627          * the module will have smart idle settings; which can lead to deadlock
3628          * (above Errata Id:i660); so, dont reset the module during boot;
3629          * Use HWMOD_INIT_NO_RESET.
3630          */
3631
3632         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3633                           HWMOD_INIT_NO_RESET,
3634 };
3635
3636 /*
3637  * 'usb_otg_hs' class
3638  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3639  */
3640
3641 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3642         .rev_offs       = 0x0400,
3643         .sysc_offs      = 0x0404,
3644         .syss_offs      = 0x0408,
3645         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3646                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3647                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3648         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3649                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3650                            MSTANDBY_SMART),
3651         .sysc_fields    = &omap_hwmod_sysc_type1,
3652 };
3653
3654 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3655         .name   = "usb_otg_hs",
3656         .sysc   = &omap44xx_usb_otg_hs_sysc,
3657 };
3658
3659 /* usb_otg_hs */
3660 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3661         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3662         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3663         { .irq = -1 }
3664 };
3665
3666 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3667         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3668 };
3669
3670 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3671         .name           = "usb_otg_hs",
3672         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3673         .clkdm_name     = "l3_init_clkdm",
3674         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3675         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3676         .main_clk       = "usb_otg_hs_ick",
3677         .prcm = {
3678                 .omap4 = {
3679                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3680                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3681                         .modulemode   = MODULEMODE_HWCTRL,
3682                 },
3683         },
3684         .opt_clks       = usb_otg_hs_opt_clks,
3685         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3686 };
3687
3688 /*
3689  * 'usb_tll_hs' class
3690  * usb_tll_hs module is the adapter on the usb_host_hs ports
3691  */
3692
3693 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3694         .rev_offs       = 0x0000,
3695         .sysc_offs      = 0x0010,
3696         .syss_offs      = 0x0014,
3697         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3698                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3699                            SYSC_HAS_AUTOIDLE),
3700         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3701         .sysc_fields    = &omap_hwmod_sysc_type1,
3702 };
3703
3704 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3705         .name   = "usb_tll_hs",
3706         .sysc   = &omap44xx_usb_tll_hs_sysc,
3707 };
3708
3709 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3710         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3711         { .irq = -1 }
3712 };
3713
3714 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3715         .name           = "usb_tll_hs",
3716         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3717         .clkdm_name     = "l3_init_clkdm",
3718         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3719         .main_clk       = "usb_tll_hs_ick",
3720         .prcm = {
3721                 .omap4 = {
3722                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3723                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3724                         .modulemode   = MODULEMODE_HWCTRL,
3725                 },
3726         },
3727 };
3728
3729 /*
3730  * 'wd_timer' class
3731  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3732  * overflow condition
3733  */
3734
3735 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3736         .rev_offs       = 0x0000,
3737         .sysc_offs      = 0x0010,
3738         .syss_offs      = 0x0014,
3739         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3740                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3741         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3742                            SIDLE_SMART_WKUP),
3743         .sysc_fields    = &omap_hwmod_sysc_type1,
3744 };
3745
3746 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3747         .name           = "wd_timer",
3748         .sysc           = &omap44xx_wd_timer_sysc,
3749         .pre_shutdown   = &omap2_wd_timer_disable,
3750         .reset          = &omap2_wd_timer_reset,
3751 };
3752
3753 /* wd_timer2 */
3754 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3755         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3756         { .irq = -1 }
3757 };
3758
3759 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3760         .name           = "wd_timer2",
3761         .class          = &omap44xx_wd_timer_hwmod_class,
3762         .clkdm_name     = "l4_wkup_clkdm",
3763         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3764         .main_clk       = "wd_timer2_fck",
3765         .prcm = {
3766                 .omap4 = {
3767                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3768                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3769                         .modulemode   = MODULEMODE_SWCTRL,
3770                 },
3771         },
3772 };
3773
3774 /* wd_timer3 */
3775 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3776         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3777         { .irq = -1 }
3778 };
3779
3780 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3781         .name           = "wd_timer3",
3782         .class          = &omap44xx_wd_timer_hwmod_class,
3783         .clkdm_name     = "abe_clkdm",
3784         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3785         .main_clk       = "wd_timer3_fck",
3786         .prcm = {
3787                 .omap4 = {
3788                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3789                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3790                         .modulemode   = MODULEMODE_SWCTRL,
3791                 },
3792         },
3793 };
3794
3795
3796 /*
3797  * interfaces
3798  */
3799
3800 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3801         {
3802                 .pa_start       = 0x4a204000,
3803                 .pa_end         = 0x4a2040ff,
3804                 .flags          = ADDR_TYPE_RT
3805         },
3806         { }
3807 };
3808
3809 /* c2c -> c2c_target_fw */
3810 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3811         .master         = &omap44xx_c2c_hwmod,
3812         .slave          = &omap44xx_c2c_target_fw_hwmod,
3813         .clk            = "div_core_ck",
3814         .addr           = omap44xx_c2c_target_fw_addrs,
3815         .user           = OCP_USER_MPU,
3816 };
3817
3818 /* l4_cfg -> c2c_target_fw */
3819 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3820         .master         = &omap44xx_l4_cfg_hwmod,
3821         .slave          = &omap44xx_c2c_target_fw_hwmod,
3822         .clk            = "l4_div_ck",
3823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3824 };
3825
3826 /* l3_main_1 -> dmm */
3827 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3828         .master         = &omap44xx_l3_main_1_hwmod,
3829         .slave          = &omap44xx_dmm_hwmod,
3830         .clk            = "l3_div_ck",
3831         .user           = OCP_USER_SDMA,
3832 };
3833
3834 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3835         {
3836                 .pa_start       = 0x4e000000,
3837                 .pa_end         = 0x4e0007ff,
3838                 .flags          = ADDR_TYPE_RT
3839         },
3840         { }
3841 };
3842
3843 /* mpu -> dmm */
3844 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3845         .master         = &omap44xx_mpu_hwmod,
3846         .slave          = &omap44xx_dmm_hwmod,
3847         .clk            = "l3_div_ck",
3848         .addr           = omap44xx_dmm_addrs,
3849         .user           = OCP_USER_MPU,
3850 };
3851
3852 /* c2c -> emif_fw */
3853 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3854         .master         = &omap44xx_c2c_hwmod,
3855         .slave          = &omap44xx_emif_fw_hwmod,
3856         .clk            = "div_core_ck",
3857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3859
3860 /* dmm -> emif_fw */
3861 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3862         .master         = &omap44xx_dmm_hwmod,
3863         .slave          = &omap44xx_emif_fw_hwmod,
3864         .clk            = "l3_div_ck",
3865         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3866 };
3867
3868 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3869         {
3870                 .pa_start       = 0x4a20c000,
3871                 .pa_end         = 0x4a20c0ff,
3872                 .flags          = ADDR_TYPE_RT
3873         },
3874         { }
3875 };
3876
3877 /* l4_cfg -> emif_fw */
3878 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3879         .master         = &omap44xx_l4_cfg_hwmod,
3880         .slave          = &omap44xx_emif_fw_hwmod,
3881         .clk            = "l4_div_ck",
3882         .addr           = omap44xx_emif_fw_addrs,
3883         .user           = OCP_USER_MPU,
3884 };
3885
3886 /* iva -> l3_instr */
3887 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3888         .master         = &omap44xx_iva_hwmod,
3889         .slave          = &omap44xx_l3_instr_hwmod,
3890         .clk            = "l3_div_ck",
3891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3892 };
3893
3894 /* l3_main_3 -> l3_instr */
3895 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3896         .master         = &omap44xx_l3_main_3_hwmod,
3897         .slave          = &omap44xx_l3_instr_hwmod,
3898         .clk            = "l3_div_ck",
3899         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3900 };
3901
3902 /* ocp_wp_noc -> l3_instr */
3903 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3904         .master         = &omap44xx_ocp_wp_noc_hwmod,
3905         .slave          = &omap44xx_l3_instr_hwmod,
3906         .clk            = "l3_div_ck",
3907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3908 };
3909
3910 /* dsp -> l3_main_1 */
3911 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3912         .master         = &omap44xx_dsp_hwmod,
3913         .slave          = &omap44xx_l3_main_1_hwmod,
3914         .clk            = "l3_div_ck",
3915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3916 };
3917
3918 /* dss -> l3_main_1 */
3919 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3920         .master         = &omap44xx_dss_hwmod,
3921         .slave          = &omap44xx_l3_main_1_hwmod,
3922         .clk            = "l3_div_ck",
3923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3924 };
3925
3926 /* l3_main_2 -> l3_main_1 */
3927 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3928         .master         = &omap44xx_l3_main_2_hwmod,
3929         .slave          = &omap44xx_l3_main_1_hwmod,
3930         .clk            = "l3_div_ck",
3931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3932 };
3933
3934 /* l4_cfg -> l3_main_1 */
3935 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3936         .master         = &omap44xx_l4_cfg_hwmod,
3937         .slave          = &omap44xx_l3_main_1_hwmod,
3938         .clk            = "l4_div_ck",
3939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3940 };
3941
3942 /* mmc1 -> l3_main_1 */
3943 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3944         .master         = &omap44xx_mmc1_hwmod,
3945         .slave          = &omap44xx_l3_main_1_hwmod,
3946         .clk            = "l3_div_ck",
3947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3948 };
3949
3950 /* mmc2 -> l3_main_1 */
3951 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3952         .master         = &omap44xx_mmc2_hwmod,
3953         .slave          = &omap44xx_l3_main_1_hwmod,
3954         .clk            = "l3_div_ck",
3955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3957
3958 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3959         {
3960                 .pa_start       = 0x44000000,
3961                 .pa_end         = 0x44000fff,
3962                 .flags          = ADDR_TYPE_RT
3963         },
3964         { }
3965 };
3966
3967 /* mpu -> l3_main_1 */
3968 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3969         .master         = &omap44xx_mpu_hwmod,
3970         .slave          = &omap44xx_l3_main_1_hwmod,
3971         .clk            = "l3_div_ck",
3972         .addr           = omap44xx_l3_main_1_addrs,
3973         .user           = OCP_USER_MPU,
3974 };
3975
3976 /* c2c_target_fw -> l3_main_2 */
3977 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3978         .master         = &omap44xx_c2c_target_fw_hwmod,
3979         .slave          = &omap44xx_l3_main_2_hwmod,
3980         .clk            = "l3_div_ck",
3981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3982 };
3983
3984 /* debugss -> l3_main_2 */
3985 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3986         .master         = &omap44xx_debugss_hwmod,
3987         .slave          = &omap44xx_l3_main_2_hwmod,
3988         .clk            = "dbgclk_mux_ck",
3989         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3990 };
3991
3992 /* dma_system -> l3_main_2 */
3993 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3994         .master         = &omap44xx_dma_system_hwmod,
3995         .slave          = &omap44xx_l3_main_2_hwmod,
3996         .clk            = "l3_div_ck",
3997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3998 };
3999
4000 /* fdif -> l3_main_2 */
4001 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4002         .master         = &omap44xx_fdif_hwmod,
4003         .slave          = &omap44xx_l3_main_2_hwmod,
4004         .clk            = "l3_div_ck",
4005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4006 };
4007
4008 /* gpu -> l3_main_2 */
4009 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4010         .master         = &omap44xx_gpu_hwmod,
4011         .slave          = &omap44xx_l3_main_2_hwmod,
4012         .clk            = "l3_div_ck",
4013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4014 };
4015
4016 /* hsi -> l3_main_2 */
4017 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4018         .master         = &omap44xx_hsi_hwmod,
4019         .slave          = &omap44xx_l3_main_2_hwmod,
4020         .clk            = "l3_div_ck",
4021         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4022 };
4023
4024 /* ipu -> l3_main_2 */
4025 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4026         .master         = &omap44xx_ipu_hwmod,
4027         .slave          = &omap44xx_l3_main_2_hwmod,
4028         .clk            = "l3_div_ck",
4029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4030 };
4031
4032 /* iss -> l3_main_2 */
4033 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4034         .master         = &omap44xx_iss_hwmod,
4035         .slave          = &omap44xx_l3_main_2_hwmod,
4036         .clk            = "l3_div_ck",
4037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4038 };
4039
4040 /* iva -> l3_main_2 */
4041 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4042         .master         = &omap44xx_iva_hwmod,
4043         .slave          = &omap44xx_l3_main_2_hwmod,
4044         .clk            = "l3_div_ck",
4045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4046 };
4047
4048 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4049         {
4050                 .pa_start       = 0x44800000,
4051                 .pa_end         = 0x44801fff,
4052                 .flags          = ADDR_TYPE_RT
4053         },
4054         { }
4055 };
4056
4057 /* l3_main_1 -> l3_main_2 */
4058 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4059         .master         = &omap44xx_l3_main_1_hwmod,
4060         .slave          = &omap44xx_l3_main_2_hwmod,
4061         .clk            = "l3_div_ck",
4062         .addr           = omap44xx_l3_main_2_addrs,
4063         .user           = OCP_USER_MPU,
4064 };
4065
4066 /* l4_cfg -> l3_main_2 */
4067 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4068         .master         = &omap44xx_l4_cfg_hwmod,
4069         .slave          = &omap44xx_l3_main_2_hwmod,
4070         .clk            = "l4_div_ck",
4071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4072 };
4073
4074 /* usb_host_fs -> l3_main_2 */
4075 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4076         .master         = &omap44xx_usb_host_fs_hwmod,
4077         .slave          = &omap44xx_l3_main_2_hwmod,
4078         .clk            = "l3_div_ck",
4079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4080 };
4081
4082 /* usb_host_hs -> l3_main_2 */
4083 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4084         .master         = &omap44xx_usb_host_hs_hwmod,
4085         .slave          = &omap44xx_l3_main_2_hwmod,
4086         .clk            = "l3_div_ck",
4087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4088 };
4089
4090 /* usb_otg_hs -> l3_main_2 */
4091 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4092         .master         = &omap44xx_usb_otg_hs_hwmod,
4093         .slave          = &omap44xx_l3_main_2_hwmod,
4094         .clk            = "l3_div_ck",
4095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4096 };
4097
4098 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4099         {
4100                 .pa_start       = 0x45000000,
4101                 .pa_end         = 0x45000fff,
4102                 .flags          = ADDR_TYPE_RT
4103         },
4104         { }
4105 };
4106
4107 /* l3_main_1 -> l3_main_3 */
4108 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4109         .master         = &omap44xx_l3_main_1_hwmod,
4110         .slave          = &omap44xx_l3_main_3_hwmod,
4111         .clk            = "l3_div_ck",
4112         .addr           = omap44xx_l3_main_3_addrs,
4113         .user           = OCP_USER_MPU,
4114 };
4115
4116 /* l3_main_2 -> l3_main_3 */
4117 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4118         .master         = &omap44xx_l3_main_2_hwmod,
4119         .slave          = &omap44xx_l3_main_3_hwmod,
4120         .clk            = "l3_div_ck",
4121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4122 };
4123
4124 /* l4_cfg -> l3_main_3 */
4125 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4126         .master         = &omap44xx_l4_cfg_hwmod,
4127         .slave          = &omap44xx_l3_main_3_hwmod,
4128         .clk            = "l4_div_ck",
4129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4131
4132 /* aess -> l4_abe */
4133 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4134         .master         = &omap44xx_aess_hwmod,
4135         .slave          = &omap44xx_l4_abe_hwmod,
4136         .clk            = "ocp_abe_iclk",
4137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4138 };
4139
4140 /* dsp -> l4_abe */
4141 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4142         .master         = &omap44xx_dsp_hwmod,
4143         .slave          = &omap44xx_l4_abe_hwmod,
4144         .clk            = "ocp_abe_iclk",
4145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4146 };
4147
4148 /* l3_main_1 -> l4_abe */
4149 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4150         .master         = &omap44xx_l3_main_1_hwmod,
4151         .slave          = &omap44xx_l4_abe_hwmod,
4152         .clk            = "l3_div_ck",
4153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4154 };
4155
4156 /* mpu -> l4_abe */
4157 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4158         .master         = &omap44xx_mpu_hwmod,
4159         .slave          = &omap44xx_l4_abe_hwmod,
4160         .clk            = "ocp_abe_iclk",
4161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4162 };
4163
4164 /* l3_main_1 -> l4_cfg */
4165 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4166         .master         = &omap44xx_l3_main_1_hwmod,
4167         .slave          = &omap44xx_l4_cfg_hwmod,
4168         .clk            = "l3_div_ck",
4169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4170 };
4171
4172 /* l3_main_2 -> l4_per */
4173 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4174         .master         = &omap44xx_l3_main_2_hwmod,
4175         .slave          = &omap44xx_l4_per_hwmod,
4176         .clk            = "l3_div_ck",
4177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4179
4180 /* l4_cfg -> l4_wkup */
4181 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4182         .master         = &omap44xx_l4_cfg_hwmod,
4183         .slave          = &omap44xx_l4_wkup_hwmod,
4184         .clk            = "l4_div_ck",
4185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4186 };
4187
4188 /* mpu -> mpu_private */
4189 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4190         .master         = &omap44xx_mpu_hwmod,
4191         .slave          = &omap44xx_mpu_private_hwmod,
4192         .clk            = "l3_div_ck",
4193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4194 };
4195
4196 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4197         {
4198                 .pa_start       = 0x4a102000,
4199                 .pa_end         = 0x4a10207f,
4200                 .flags          = ADDR_TYPE_RT
4201         },
4202         { }
4203 };
4204
4205 /* l4_cfg -> ocp_wp_noc */
4206 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4207         .master         = &omap44xx_l4_cfg_hwmod,
4208         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4209         .clk            = "l4_div_ck",
4210         .addr           = omap44xx_ocp_wp_noc_addrs,
4211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4212 };
4213
4214 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4215         {
4216                 .pa_start       = 0x401f1000,
4217                 .pa_end         = 0x401f13ff,
4218                 .flags          = ADDR_TYPE_RT
4219         },
4220         { }
4221 };
4222
4223 /* l4_abe -> aess */
4224 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4225         .master         = &omap44xx_l4_abe_hwmod,
4226         .slave          = &omap44xx_aess_hwmod,
4227         .clk            = "ocp_abe_iclk",
4228         .addr           = omap44xx_aess_addrs,
4229         .user           = OCP_USER_MPU,
4230 };
4231
4232 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4233         {
4234                 .pa_start       = 0x490f1000,
4235                 .pa_end         = 0x490f13ff,
4236                 .flags          = ADDR_TYPE_RT
4237         },
4238         { }
4239 };
4240
4241 /* l4_abe -> aess (dma) */
4242 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4243         .master         = &omap44xx_l4_abe_hwmod,
4244         .slave          = &omap44xx_aess_hwmod,
4245         .clk            = "ocp_abe_iclk",
4246         .addr           = omap44xx_aess_dma_addrs,
4247         .user           = OCP_USER_SDMA,
4248 };
4249
4250 /* l3_main_2 -> c2c */
4251 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4252         .master         = &omap44xx_l3_main_2_hwmod,
4253         .slave          = &omap44xx_c2c_hwmod,
4254         .clk            = "l3_div_ck",
4255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4256 };
4257
4258 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4259         {
4260                 .pa_start       = 0x4a304000,
4261                 .pa_end         = 0x4a30401f,
4262                 .flags          = ADDR_TYPE_RT
4263         },
4264         { }
4265 };
4266
4267 /* l4_wkup -> counter_32k */
4268 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4269         .master         = &omap44xx_l4_wkup_hwmod,
4270         .slave          = &omap44xx_counter_32k_hwmod,
4271         .clk            = "l4_wkup_clk_mux_ck",
4272         .addr           = omap44xx_counter_32k_addrs,
4273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4274 };
4275
4276 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4277         {
4278                 .pa_start       = 0x4a002000,
4279                 .pa_end         = 0x4a0027ff,
4280                 .flags          = ADDR_TYPE_RT
4281         },
4282         { }
4283 };
4284
4285 /* l4_cfg -> ctrl_module_core */
4286 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4287         .master         = &omap44xx_l4_cfg_hwmod,
4288         .slave          = &omap44xx_ctrl_module_core_hwmod,
4289         .clk            = "l4_div_ck",
4290         .addr           = omap44xx_ctrl_module_core_addrs,
4291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4292 };
4293
4294 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4295         {
4296                 .pa_start       = 0x4a100000,
4297                 .pa_end         = 0x4a1007ff,
4298                 .flags          = ADDR_TYPE_RT
4299         },
4300         { }
4301 };
4302
4303 /* l4_cfg -> ctrl_module_pad_core */
4304 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4305         .master         = &omap44xx_l4_cfg_hwmod,
4306         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4307         .clk            = "l4_div_ck",
4308         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4310 };
4311
4312 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4313         {
4314                 .pa_start       = 0x4a30c000,
4315                 .pa_end         = 0x4a30c7ff,
4316                 .flags          = ADDR_TYPE_RT
4317         },
4318         { }
4319 };
4320
4321 /* l4_wkup -> ctrl_module_wkup */
4322 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4323         .master         = &omap44xx_l4_wkup_hwmod,
4324         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4325         .clk            = "l4_wkup_clk_mux_ck",
4326         .addr           = omap44xx_ctrl_module_wkup_addrs,
4327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4328 };
4329
4330 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4331         {
4332                 .pa_start       = 0x4a31e000,
4333                 .pa_end         = 0x4a31e7ff,
4334                 .flags          = ADDR_TYPE_RT
4335         },
4336         { }
4337 };
4338
4339 /* l4_wkup -> ctrl_module_pad_wkup */
4340 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4341         .master         = &omap44xx_l4_wkup_hwmod,
4342         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4343         .clk            = "l4_wkup_clk_mux_ck",
4344         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4346 };
4347
4348 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4349         {
4350                 .pa_start       = 0x54160000,
4351                 .pa_end         = 0x54167fff,
4352                 .flags          = ADDR_TYPE_RT
4353         },
4354         { }
4355 };
4356
4357 /* l3_instr -> debugss */
4358 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4359         .master         = &omap44xx_l3_instr_hwmod,
4360         .slave          = &omap44xx_debugss_hwmod,
4361         .clk            = "l3_div_ck",
4362         .addr           = omap44xx_debugss_addrs,
4363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4364 };
4365
4366 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4367         {
4368                 .pa_start       = 0x4a056000,
4369                 .pa_end         = 0x4a056fff,
4370                 .flags          = ADDR_TYPE_RT
4371         },
4372         { }
4373 };
4374
4375 /* l4_cfg -> dma_system */
4376 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4377         .master         = &omap44xx_l4_cfg_hwmod,
4378         .slave          = &omap44xx_dma_system_hwmod,
4379         .clk            = "l4_div_ck",
4380         .addr           = omap44xx_dma_system_addrs,
4381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4382 };
4383
4384 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4385         {
4386                 .name           = "mpu",
4387                 .pa_start       = 0x4012e000,
4388                 .pa_end         = 0x4012e07f,
4389                 .flags          = ADDR_TYPE_RT
4390         },
4391         { }
4392 };
4393
4394 /* l4_abe -> dmic */
4395 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4396         .master         = &omap44xx_l4_abe_hwmod,
4397         .slave          = &omap44xx_dmic_hwmod,
4398         .clk            = "ocp_abe_iclk",
4399         .addr           = omap44xx_dmic_addrs,
4400         .user           = OCP_USER_MPU,
4401 };
4402
4403 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4404         {
4405                 .name           = "dma",
4406                 .pa_start       = 0x4902e000,
4407                 .pa_end         = 0x4902e07f,
4408                 .flags          = ADDR_TYPE_RT
4409         },
4410         { }
4411 };
4412
4413 /* l4_abe -> dmic (dma) */
4414 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4415         .master         = &omap44xx_l4_abe_hwmod,
4416         .slave          = &omap44xx_dmic_hwmod,
4417         .clk            = "ocp_abe_iclk",
4418         .addr           = omap44xx_dmic_dma_addrs,
4419         .user           = OCP_USER_SDMA,
4420 };
4421
4422 /* dsp -> iva */
4423 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4424         .master         = &omap44xx_dsp_hwmod,
4425         .slave          = &omap44xx_iva_hwmod,
4426         .clk            = "dpll_iva_m5x2_ck",
4427         .user           = OCP_USER_DSP,
4428 };
4429
4430 /* dsp -> sl2if */
4431 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4432         .master         = &omap44xx_dsp_hwmod,
4433         .slave          = &omap44xx_sl2if_hwmod,
4434         .clk            = "dpll_iva_m5x2_ck",
4435         .user           = OCP_USER_DSP,
4436 };
4437
4438 /* l4_cfg -> dsp */
4439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4440         .master         = &omap44xx_l4_cfg_hwmod,
4441         .slave          = &omap44xx_dsp_hwmod,
4442         .clk            = "l4_div_ck",
4443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4444 };
4445
4446 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4447         {
4448                 .pa_start       = 0x58000000,
4449                 .pa_end         = 0x5800007f,
4450                 .flags          = ADDR_TYPE_RT
4451         },
4452         { }
4453 };
4454
4455 /* l3_main_2 -> dss */
4456 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4457         .master         = &omap44xx_l3_main_2_hwmod,
4458         .slave          = &omap44xx_dss_hwmod,
4459         .clk            = "dss_fck",
4460         .addr           = omap44xx_dss_dma_addrs,
4461         .user           = OCP_USER_SDMA,
4462 };
4463
4464 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4465         {
4466                 .pa_start       = 0x48040000,
4467                 .pa_end         = 0x4804007f,
4468                 .flags          = ADDR_TYPE_RT
4469         },
4470         { }
4471 };
4472
4473 /* l4_per -> dss */
4474 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4475         .master         = &omap44xx_l4_per_hwmod,
4476         .slave          = &omap44xx_dss_hwmod,
4477         .clk            = "l4_div_ck",
4478         .addr           = omap44xx_dss_addrs,
4479         .user           = OCP_USER_MPU,
4480 };
4481
4482 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4483         {
4484                 .pa_start       = 0x58001000,
4485                 .pa_end         = 0x58001fff,
4486                 .flags          = ADDR_TYPE_RT
4487         },
4488         { }
4489 };
4490
4491 /* l3_main_2 -> dss_dispc */
4492 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4493         .master         = &omap44xx_l3_main_2_hwmod,
4494         .slave          = &omap44xx_dss_dispc_hwmod,
4495         .clk            = "dss_fck",
4496         .addr           = omap44xx_dss_dispc_dma_addrs,
4497         .user           = OCP_USER_SDMA,
4498 };
4499
4500 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4501         {
4502                 .pa_start       = 0x48041000,
4503                 .pa_end         = 0x48041fff,
4504                 .flags          = ADDR_TYPE_RT
4505         },
4506         { }
4507 };
4508
4509 /* l4_per -> dss_dispc */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4511         .master         = &omap44xx_l4_per_hwmod,
4512         .slave          = &omap44xx_dss_dispc_hwmod,
4513         .clk            = "l4_div_ck",
4514         .addr           = omap44xx_dss_dispc_addrs,
4515         .user           = OCP_USER_MPU,
4516 };
4517
4518 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4519         {
4520                 .pa_start       = 0x58004000,
4521                 .pa_end         = 0x580041ff,
4522                 .flags          = ADDR_TYPE_RT
4523         },
4524         { }
4525 };
4526
4527 /* l3_main_2 -> dss_dsi1 */
4528 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4529         .master         = &omap44xx_l3_main_2_hwmod,
4530         .slave          = &omap44xx_dss_dsi1_hwmod,
4531         .clk            = "dss_fck",
4532         .addr           = omap44xx_dss_dsi1_dma_addrs,
4533         .user           = OCP_USER_SDMA,
4534 };
4535
4536 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4537         {
4538                 .pa_start       = 0x48044000,
4539                 .pa_end         = 0x480441ff,
4540                 .flags          = ADDR_TYPE_RT
4541         },
4542         { }
4543 };
4544
4545 /* l4_per -> dss_dsi1 */
4546 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4547         .master         = &omap44xx_l4_per_hwmod,
4548         .slave          = &omap44xx_dss_dsi1_hwmod,
4549         .clk            = "l4_div_ck",
4550         .addr           = omap44xx_dss_dsi1_addrs,
4551         .user           = OCP_USER_MPU,
4552 };
4553
4554 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4555         {
4556                 .pa_start       = 0x58005000,
4557                 .pa_end         = 0x580051ff,
4558                 .flags          = ADDR_TYPE_RT
4559         },
4560         { }
4561 };
4562
4563 /* l3_main_2 -> dss_dsi2 */
4564 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4565         .master         = &omap44xx_l3_main_2_hwmod,
4566         .slave          = &omap44xx_dss_dsi2_hwmod,
4567         .clk            = "dss_fck",
4568         .addr           = omap44xx_dss_dsi2_dma_addrs,
4569         .user           = OCP_USER_SDMA,
4570 };
4571
4572 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4573         {
4574                 .pa_start       = 0x48045000,
4575                 .pa_end         = 0x480451ff,
4576                 .flags          = ADDR_TYPE_RT
4577         },
4578         { }
4579 };
4580
4581 /* l4_per -> dss_dsi2 */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4583         .master         = &omap44xx_l4_per_hwmod,
4584         .slave          = &omap44xx_dss_dsi2_hwmod,
4585         .clk            = "l4_div_ck",
4586         .addr           = omap44xx_dss_dsi2_addrs,
4587         .user           = OCP_USER_MPU,
4588 };
4589
4590 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4591         {
4592                 .pa_start       = 0x58006000,
4593                 .pa_end         = 0x58006fff,
4594                 .flags          = ADDR_TYPE_RT
4595         },
4596         { }
4597 };
4598
4599 /* l3_main_2 -> dss_hdmi */
4600 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4601         .master         = &omap44xx_l3_main_2_hwmod,
4602         .slave          = &omap44xx_dss_hdmi_hwmod,
4603         .clk            = "dss_fck",
4604         .addr           = omap44xx_dss_hdmi_dma_addrs,
4605         .user           = OCP_USER_SDMA,
4606 };
4607
4608 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4609         {
4610                 .pa_start       = 0x48046000,
4611                 .pa_end         = 0x48046fff,
4612                 .flags          = ADDR_TYPE_RT
4613         },
4614         { }
4615 };
4616
4617 /* l4_per -> dss_hdmi */
4618 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4619         .master         = &omap44xx_l4_per_hwmod,
4620         .slave          = &omap44xx_dss_hdmi_hwmod,
4621         .clk            = "l4_div_ck",
4622         .addr           = omap44xx_dss_hdmi_addrs,
4623         .user           = OCP_USER_MPU,
4624 };
4625
4626 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4627         {
4628                 .pa_start       = 0x58002000,
4629                 .pa_end         = 0x580020ff,
4630                 .flags          = ADDR_TYPE_RT
4631         },
4632         { }
4633 };
4634
4635 /* l3_main_2 -> dss_rfbi */
4636 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4637         .master         = &omap44xx_l3_main_2_hwmod,
4638         .slave          = &omap44xx_dss_rfbi_hwmod,
4639         .clk            = "dss_fck",
4640         .addr           = omap44xx_dss_rfbi_dma_addrs,
4641         .user           = OCP_USER_SDMA,
4642 };
4643
4644 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4645         {
4646                 .pa_start       = 0x48042000,
4647                 .pa_end         = 0x480420ff,
4648                 .flags          = ADDR_TYPE_RT
4649         },
4650         { }
4651 };
4652
4653 /* l4_per -> dss_rfbi */
4654 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4655         .master         = &omap44xx_l4_per_hwmod,
4656         .slave          = &omap44xx_dss_rfbi_hwmod,
4657         .clk            = "l4_div_ck",
4658         .addr           = omap44xx_dss_rfbi_addrs,
4659         .user           = OCP_USER_MPU,
4660 };
4661
4662 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4663         {
4664                 .pa_start       = 0x58003000,
4665                 .pa_end         = 0x580030ff,
4666                 .flags          = ADDR_TYPE_RT
4667         },
4668         { }
4669 };
4670
4671 /* l3_main_2 -> dss_venc */
4672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4673         .master         = &omap44xx_l3_main_2_hwmod,
4674         .slave          = &omap44xx_dss_venc_hwmod,
4675         .clk            = "dss_fck",
4676         .addr           = omap44xx_dss_venc_dma_addrs,
4677         .user           = OCP_USER_SDMA,
4678 };
4679
4680 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4681         {
4682                 .pa_start       = 0x48043000,
4683                 .pa_end         = 0x480430ff,
4684                 .flags          = ADDR_TYPE_RT
4685         },
4686         { }
4687 };
4688
4689 /* l4_per -> dss_venc */
4690 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4691         .master         = &omap44xx_l4_per_hwmod,
4692         .slave          = &omap44xx_dss_venc_hwmod,
4693         .clk            = "l4_div_ck",
4694         .addr           = omap44xx_dss_venc_addrs,
4695         .user           = OCP_USER_MPU,
4696 };
4697
4698 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4699         {
4700                 .pa_start       = 0x48078000,
4701                 .pa_end         = 0x48078fff,
4702                 .flags          = ADDR_TYPE_RT
4703         },
4704         { }
4705 };
4706
4707 /* l4_per -> elm */
4708 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4709         .master         = &omap44xx_l4_per_hwmod,
4710         .slave          = &omap44xx_elm_hwmod,
4711         .clk            = "l4_div_ck",
4712         .addr           = omap44xx_elm_addrs,
4713         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4714 };
4715
4716 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4717         {
4718                 .pa_start       = 0x4c000000,
4719                 .pa_end         = 0x4c0000ff,
4720                 .flags          = ADDR_TYPE_RT
4721         },
4722         { }
4723 };
4724
4725 /* emif_fw -> emif1 */
4726 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4727         .master         = &omap44xx_emif_fw_hwmod,
4728         .slave          = &omap44xx_emif1_hwmod,
4729         .clk            = "l3_div_ck",
4730         .addr           = omap44xx_emif1_addrs,
4731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4732 };
4733
4734 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4735         {
4736                 .pa_start       = 0x4d000000,
4737                 .pa_end         = 0x4d0000ff,
4738                 .flags          = ADDR_TYPE_RT
4739         },
4740         { }
4741 };
4742
4743 /* emif_fw -> emif2 */
4744 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4745         .master         = &omap44xx_emif_fw_hwmod,
4746         .slave          = &omap44xx_emif2_hwmod,
4747         .clk            = "l3_div_ck",
4748         .addr           = omap44xx_emif2_addrs,
4749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4750 };
4751
4752 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4753         {
4754                 .pa_start       = 0x4a10a000,
4755                 .pa_end         = 0x4a10a1ff,
4756                 .flags          = ADDR_TYPE_RT
4757         },
4758         { }
4759 };
4760
4761 /* l4_cfg -> fdif */
4762 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4763         .master         = &omap44xx_l4_cfg_hwmod,
4764         .slave          = &omap44xx_fdif_hwmod,
4765         .clk            = "l4_div_ck",
4766         .addr           = omap44xx_fdif_addrs,
4767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4768 };
4769
4770 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4771         {
4772                 .pa_start       = 0x4a310000,
4773                 .pa_end         = 0x4a3101ff,
4774                 .flags          = ADDR_TYPE_RT
4775         },
4776         { }
4777 };
4778
4779 /* l4_wkup -> gpio1 */
4780 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4781         .master         = &omap44xx_l4_wkup_hwmod,
4782         .slave          = &omap44xx_gpio1_hwmod,
4783         .clk            = "l4_wkup_clk_mux_ck",
4784         .addr           = omap44xx_gpio1_addrs,
4785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4786 };
4787
4788 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4789         {
4790                 .pa_start       = 0x48055000,
4791                 .pa_end         = 0x480551ff,
4792                 .flags          = ADDR_TYPE_RT
4793         },
4794         { }
4795 };
4796
4797 /* l4_per -> gpio2 */
4798 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4799         .master         = &omap44xx_l4_per_hwmod,
4800         .slave          = &omap44xx_gpio2_hwmod,
4801         .clk            = "l4_div_ck",
4802         .addr           = omap44xx_gpio2_addrs,
4803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4804 };
4805
4806 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4807         {
4808                 .pa_start       = 0x48057000,
4809                 .pa_end         = 0x480571ff,
4810                 .flags          = ADDR_TYPE_RT
4811         },
4812         { }
4813 };
4814
4815 /* l4_per -> gpio3 */
4816 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4817         .master         = &omap44xx_l4_per_hwmod,
4818         .slave          = &omap44xx_gpio3_hwmod,
4819         .clk            = "l4_div_ck",
4820         .addr           = omap44xx_gpio3_addrs,
4821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4822 };
4823
4824 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4825         {
4826                 .pa_start       = 0x48059000,
4827                 .pa_end         = 0x480591ff,
4828                 .flags          = ADDR_TYPE_RT
4829         },
4830         { }
4831 };
4832
4833 /* l4_per -> gpio4 */
4834 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4835         .master         = &omap44xx_l4_per_hwmod,
4836         .slave          = &omap44xx_gpio4_hwmod,
4837         .clk            = "l4_div_ck",
4838         .addr           = omap44xx_gpio4_addrs,
4839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4840 };
4841
4842 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4843         {
4844                 .pa_start       = 0x4805b000,
4845                 .pa_end         = 0x4805b1ff,
4846                 .flags          = ADDR_TYPE_RT
4847         },
4848         { }
4849 };
4850
4851 /* l4_per -> gpio5 */
4852 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4853         .master         = &omap44xx_l4_per_hwmod,
4854         .slave          = &omap44xx_gpio5_hwmod,
4855         .clk            = "l4_div_ck",
4856         .addr           = omap44xx_gpio5_addrs,
4857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4858 };
4859
4860 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4861         {
4862                 .pa_start       = 0x4805d000,
4863                 .pa_end         = 0x4805d1ff,
4864                 .flags          = ADDR_TYPE_RT
4865         },
4866         { }
4867 };
4868
4869 /* l4_per -> gpio6 */
4870 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4871         .master         = &omap44xx_l4_per_hwmod,
4872         .slave          = &omap44xx_gpio6_hwmod,
4873         .clk            = "l4_div_ck",
4874         .addr           = omap44xx_gpio6_addrs,
4875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4876 };
4877
4878 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4879         {
4880                 .pa_start       = 0x50000000,
4881                 .pa_end         = 0x500003ff,
4882                 .flags          = ADDR_TYPE_RT
4883         },
4884         { }
4885 };
4886
4887 /* l3_main_2 -> gpmc */
4888 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4889         .master         = &omap44xx_l3_main_2_hwmod,
4890         .slave          = &omap44xx_gpmc_hwmod,
4891         .clk            = "l3_div_ck",
4892         .addr           = omap44xx_gpmc_addrs,
4893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4894 };
4895
4896 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4897         {
4898                 .pa_start       = 0x56000000,
4899                 .pa_end         = 0x5600ffff,
4900                 .flags          = ADDR_TYPE_RT
4901         },
4902         { }
4903 };
4904
4905 /* l3_main_2 -> gpu */
4906 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4907         .master         = &omap44xx_l3_main_2_hwmod,
4908         .slave          = &omap44xx_gpu_hwmod,
4909         .clk            = "l3_div_ck",
4910         .addr           = omap44xx_gpu_addrs,
4911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4912 };
4913
4914 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4915         {
4916                 .pa_start       = 0x480b2000,
4917                 .pa_end         = 0x480b201f,
4918                 .flags          = ADDR_TYPE_RT
4919         },
4920         { }
4921 };
4922
4923 /* l4_per -> hdq1w */
4924 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4925         .master         = &omap44xx_l4_per_hwmod,
4926         .slave          = &omap44xx_hdq1w_hwmod,
4927         .clk            = "l4_div_ck",
4928         .addr           = omap44xx_hdq1w_addrs,
4929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4930 };
4931
4932 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4933         {
4934                 .pa_start       = 0x4a058000,
4935                 .pa_end         = 0x4a05bfff,
4936                 .flags          = ADDR_TYPE_RT
4937         },
4938         { }
4939 };
4940
4941 /* l4_cfg -> hsi */
4942 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4943         .master         = &omap44xx_l4_cfg_hwmod,
4944         .slave          = &omap44xx_hsi_hwmod,
4945         .clk            = "l4_div_ck",
4946         .addr           = omap44xx_hsi_addrs,
4947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4948 };
4949
4950 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4951         {
4952                 .pa_start       = 0x48070000,
4953                 .pa_end         = 0x480700ff,
4954                 .flags          = ADDR_TYPE_RT
4955         },
4956         { }
4957 };
4958
4959 /* l4_per -> i2c1 */
4960 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4961         .master         = &omap44xx_l4_per_hwmod,
4962         .slave          = &omap44xx_i2c1_hwmod,
4963         .clk            = "l4_div_ck",
4964         .addr           = omap44xx_i2c1_addrs,
4965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4966 };
4967
4968 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4969         {
4970                 .pa_start       = 0x48072000,
4971                 .pa_end         = 0x480720ff,
4972                 .flags          = ADDR_TYPE_RT
4973         },
4974         { }
4975 };
4976
4977 /* l4_per -> i2c2 */
4978 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4979         .master         = &omap44xx_l4_per_hwmod,
4980         .slave          = &omap44xx_i2c2_hwmod,
4981         .clk            = "l4_div_ck",
4982         .addr           = omap44xx_i2c2_addrs,
4983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4984 };
4985
4986 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4987         {
4988                 .pa_start       = 0x48060000,
4989                 .pa_end         = 0x480600ff,
4990                 .flags          = ADDR_TYPE_RT
4991         },
4992         { }
4993 };
4994
4995 /* l4_per -> i2c3 */
4996 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4997         .master         = &omap44xx_l4_per_hwmod,
4998         .slave          = &omap44xx_i2c3_hwmod,
4999         .clk            = "l4_div_ck",
5000         .addr           = omap44xx_i2c3_addrs,
5001         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5002 };
5003
5004 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5005         {
5006                 .pa_start       = 0x48350000,
5007                 .pa_end         = 0x483500ff,
5008                 .flags          = ADDR_TYPE_RT
5009         },
5010         { }
5011 };
5012
5013 /* l4_per -> i2c4 */
5014 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5015         .master         = &omap44xx_l4_per_hwmod,
5016         .slave          = &omap44xx_i2c4_hwmod,
5017         .clk            = "l4_div_ck",
5018         .addr           = omap44xx_i2c4_addrs,
5019         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5020 };
5021
5022 /* l3_main_2 -> ipu */
5023 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5024         .master         = &omap44xx_l3_main_2_hwmod,
5025         .slave          = &omap44xx_ipu_hwmod,
5026         .clk            = "l3_div_ck",
5027         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5028 };
5029
5030 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5031         {
5032                 .pa_start       = 0x52000000,
5033                 .pa_end         = 0x520000ff,
5034                 .flags          = ADDR_TYPE_RT
5035         },
5036         { }
5037 };
5038
5039 /* l3_main_2 -> iss */
5040 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5041         .master         = &omap44xx_l3_main_2_hwmod,
5042         .slave          = &omap44xx_iss_hwmod,
5043         .clk            = "l3_div_ck",
5044         .addr           = omap44xx_iss_addrs,
5045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5046 };
5047
5048 /* iva -> sl2if */
5049 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5050         .master         = &omap44xx_iva_hwmod,
5051         .slave          = &omap44xx_sl2if_hwmod,
5052         .clk            = "dpll_iva_m5x2_ck",
5053         .user           = OCP_USER_IVA,
5054 };
5055
5056 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5057         {
5058                 .pa_start       = 0x5a000000,
5059                 .pa_end         = 0x5a07ffff,
5060                 .flags          = ADDR_TYPE_RT
5061         },
5062         { }
5063 };
5064
5065 /* l3_main_2 -> iva */
5066 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5067         .master         = &omap44xx_l3_main_2_hwmod,
5068         .slave          = &omap44xx_iva_hwmod,
5069         .clk            = "l3_div_ck",
5070         .addr           = omap44xx_iva_addrs,
5071         .user           = OCP_USER_MPU,
5072 };
5073
5074 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5075         {
5076                 .pa_start       = 0x4a31c000,
5077                 .pa_end         = 0x4a31c07f,
5078                 .flags          = ADDR_TYPE_RT
5079         },
5080         { }
5081 };
5082
5083 /* l4_wkup -> kbd */
5084 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5085         .master         = &omap44xx_l4_wkup_hwmod,
5086         .slave          = &omap44xx_kbd_hwmod,
5087         .clk            = "l4_wkup_clk_mux_ck",
5088         .addr           = omap44xx_kbd_addrs,
5089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5090 };
5091
5092 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5093         {
5094                 .pa_start       = 0x4a0f4000,
5095                 .pa_end         = 0x4a0f41ff,
5096                 .flags          = ADDR_TYPE_RT
5097         },
5098         { }
5099 };
5100
5101 /* l4_cfg -> mailbox */
5102 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5103         .master         = &omap44xx_l4_cfg_hwmod,
5104         .slave          = &omap44xx_mailbox_hwmod,
5105         .clk            = "l4_div_ck",
5106         .addr           = omap44xx_mailbox_addrs,
5107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5108 };
5109
5110 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5111         {
5112                 .pa_start       = 0x40128000,
5113                 .pa_end         = 0x401283ff,
5114                 .flags          = ADDR_TYPE_RT
5115         },
5116         { }
5117 };
5118
5119 /* l4_abe -> mcasp */
5120 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5121         .master         = &omap44xx_l4_abe_hwmod,
5122         .slave          = &omap44xx_mcasp_hwmod,
5123         .clk            = "ocp_abe_iclk",
5124         .addr           = omap44xx_mcasp_addrs,
5125         .user           = OCP_USER_MPU,
5126 };
5127
5128 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5129         {
5130                 .pa_start       = 0x49028000,
5131                 .pa_end         = 0x490283ff,
5132                 .flags          = ADDR_TYPE_RT
5133         },
5134         { }
5135 };
5136
5137 /* l4_abe -> mcasp (dma) */
5138 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5139         .master         = &omap44xx_l4_abe_hwmod,
5140         .slave          = &omap44xx_mcasp_hwmod,
5141         .clk            = "ocp_abe_iclk",
5142         .addr           = omap44xx_mcasp_dma_addrs,
5143         .user           = OCP_USER_SDMA,
5144 };
5145
5146 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5147         {
5148                 .name           = "mpu",
5149                 .pa_start       = 0x40122000,
5150                 .pa_end         = 0x401220ff,
5151                 .flags          = ADDR_TYPE_RT
5152         },
5153         { }
5154 };
5155
5156 /* l4_abe -> mcbsp1 */
5157 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5158         .master         = &omap44xx_l4_abe_hwmod,
5159         .slave          = &omap44xx_mcbsp1_hwmod,
5160         .clk            = "ocp_abe_iclk",
5161         .addr           = omap44xx_mcbsp1_addrs,
5162         .user           = OCP_USER_MPU,
5163 };
5164
5165 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5166         {
5167                 .name           = "dma",
5168                 .pa_start       = 0x49022000,
5169                 .pa_end         = 0x490220ff,
5170                 .flags          = ADDR_TYPE_RT
5171         },
5172         { }
5173 };
5174
5175 /* l4_abe -> mcbsp1 (dma) */
5176 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5177         .master         = &omap44xx_l4_abe_hwmod,
5178         .slave          = &omap44xx_mcbsp1_hwmod,
5179         .clk            = "ocp_abe_iclk",
5180         .addr           = omap44xx_mcbsp1_dma_addrs,
5181         .user           = OCP_USER_SDMA,
5182 };
5183
5184 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5185         {
5186                 .name           = "mpu",
5187                 .pa_start       = 0x40124000,
5188                 .pa_end         = 0x401240ff,
5189                 .flags          = ADDR_TYPE_RT
5190         },
5191         { }
5192 };
5193
5194 /* l4_abe -> mcbsp2 */
5195 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5196         .master         = &omap44xx_l4_abe_hwmod,
5197         .slave          = &omap44xx_mcbsp2_hwmod,
5198         .clk            = "ocp_abe_iclk",
5199         .addr           = omap44xx_mcbsp2_addrs,
5200         .user           = OCP_USER_MPU,
5201 };
5202
5203 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5204         {
5205                 .name           = "dma",
5206                 .pa_start       = 0x49024000,
5207                 .pa_end         = 0x490240ff,
5208                 .flags          = ADDR_TYPE_RT
5209         },
5210         { }
5211 };
5212
5213 /* l4_abe -> mcbsp2 (dma) */
5214 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5215         .master         = &omap44xx_l4_abe_hwmod,
5216         .slave          = &omap44xx_mcbsp2_hwmod,
5217         .clk            = "ocp_abe_iclk",
5218         .addr           = omap44xx_mcbsp2_dma_addrs,
5219         .user           = OCP_USER_SDMA,
5220 };
5221
5222 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5223         {
5224                 .name           = "mpu",
5225                 .pa_start       = 0x40126000,
5226                 .pa_end         = 0x401260ff,
5227                 .flags          = ADDR_TYPE_RT
5228         },
5229         { }
5230 };
5231
5232 /* l4_abe -> mcbsp3 */
5233 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5234         .master         = &omap44xx_l4_abe_hwmod,
5235         .slave          = &omap44xx_mcbsp3_hwmod,
5236         .clk            = "ocp_abe_iclk",
5237         .addr           = omap44xx_mcbsp3_addrs,
5238         .user           = OCP_USER_MPU,
5239 };
5240
5241 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5242         {
5243                 .name           = "dma",
5244                 .pa_start       = 0x49026000,
5245                 .pa_end         = 0x490260ff,
5246                 .flags          = ADDR_TYPE_RT
5247         },
5248         { }
5249 };
5250
5251 /* l4_abe -> mcbsp3 (dma) */
5252 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5253         .master         = &omap44xx_l4_abe_hwmod,
5254         .slave          = &omap44xx_mcbsp3_hwmod,
5255         .clk            = "ocp_abe_iclk",
5256         .addr           = omap44xx_mcbsp3_dma_addrs,
5257         .user           = OCP_USER_SDMA,
5258 };
5259
5260 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5261         {
5262                 .pa_start       = 0x48096000,
5263                 .pa_end         = 0x480960ff,
5264                 .flags          = ADDR_TYPE_RT
5265         },
5266         { }
5267 };
5268
5269 /* l4_per -> mcbsp4 */
5270 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5271         .master         = &omap44xx_l4_per_hwmod,
5272         .slave          = &omap44xx_mcbsp4_hwmod,
5273         .clk            = "l4_div_ck",
5274         .addr           = omap44xx_mcbsp4_addrs,
5275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5276 };
5277
5278 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5279         {
5280                 .name           = "mpu",
5281                 .pa_start       = 0x40132000,
5282                 .pa_end         = 0x4013207f,
5283                 .flags          = ADDR_TYPE_RT
5284         },
5285         { }
5286 };
5287
5288 /* l4_abe -> mcpdm */
5289 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5290         .master         = &omap44xx_l4_abe_hwmod,
5291         .slave          = &omap44xx_mcpdm_hwmod,
5292         .clk            = "ocp_abe_iclk",
5293         .addr           = omap44xx_mcpdm_addrs,
5294         .user           = OCP_USER_MPU,
5295 };
5296
5297 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5298         {
5299                 .name           = "dma",
5300                 .pa_start       = 0x49032000,
5301                 .pa_end         = 0x4903207f,
5302                 .flags          = ADDR_TYPE_RT
5303         },
5304         { }
5305 };
5306
5307 /* l4_abe -> mcpdm (dma) */
5308 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5309         .master         = &omap44xx_l4_abe_hwmod,
5310         .slave          = &omap44xx_mcpdm_hwmod,
5311         .clk            = "ocp_abe_iclk",
5312         .addr           = omap44xx_mcpdm_dma_addrs,
5313         .user           = OCP_USER_SDMA,
5314 };
5315
5316 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5317         {
5318                 .pa_start       = 0x48098000,
5319                 .pa_end         = 0x480981ff,
5320                 .flags          = ADDR_TYPE_RT
5321         },
5322         { }
5323 };
5324
5325 /* l4_per -> mcspi1 */
5326 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5327         .master         = &omap44xx_l4_per_hwmod,
5328         .slave          = &omap44xx_mcspi1_hwmod,
5329         .clk            = "l4_div_ck",
5330         .addr           = omap44xx_mcspi1_addrs,
5331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5332 };
5333
5334 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5335         {
5336                 .pa_start       = 0x4809a000,
5337                 .pa_end         = 0x4809a1ff,
5338                 .flags          = ADDR_TYPE_RT
5339         },
5340         { }
5341 };
5342
5343 /* l4_per -> mcspi2 */
5344 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5345         .master         = &omap44xx_l4_per_hwmod,
5346         .slave          = &omap44xx_mcspi2_hwmod,
5347         .clk            = "l4_div_ck",
5348         .addr           = omap44xx_mcspi2_addrs,
5349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5350 };
5351
5352 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5353         {
5354                 .pa_start       = 0x480b8000,
5355                 .pa_end         = 0x480b81ff,
5356                 .flags          = ADDR_TYPE_RT
5357         },
5358         { }
5359 };
5360
5361 /* l4_per -> mcspi3 */
5362 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5363         .master         = &omap44xx_l4_per_hwmod,
5364         .slave          = &omap44xx_mcspi3_hwmod,
5365         .clk            = "l4_div_ck",
5366         .addr           = omap44xx_mcspi3_addrs,
5367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5368 };
5369
5370 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5371         {
5372                 .pa_start       = 0x480ba000,
5373                 .pa_end         = 0x480ba1ff,
5374                 .flags          = ADDR_TYPE_RT
5375         },
5376         { }
5377 };
5378
5379 /* l4_per -> mcspi4 */
5380 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5381         .master         = &omap44xx_l4_per_hwmod,
5382         .slave          = &omap44xx_mcspi4_hwmod,
5383         .clk            = "l4_div_ck",
5384         .addr           = omap44xx_mcspi4_addrs,
5385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5386 };
5387
5388 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5389         {
5390                 .pa_start       = 0x4809c000,
5391                 .pa_end         = 0x4809c3ff,
5392                 .flags          = ADDR_TYPE_RT
5393         },
5394         { }
5395 };
5396
5397 /* l4_per -> mmc1 */
5398 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5399         .master         = &omap44xx_l4_per_hwmod,
5400         .slave          = &omap44xx_mmc1_hwmod,
5401         .clk            = "l4_div_ck",
5402         .addr           = omap44xx_mmc1_addrs,
5403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5404 };
5405
5406 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5407         {
5408                 .pa_start       = 0x480b4000,
5409                 .pa_end         = 0x480b43ff,
5410                 .flags          = ADDR_TYPE_RT
5411         },
5412         { }
5413 };
5414
5415 /* l4_per -> mmc2 */
5416 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5417         .master         = &omap44xx_l4_per_hwmod,
5418         .slave          = &omap44xx_mmc2_hwmod,
5419         .clk            = "l4_div_ck",
5420         .addr           = omap44xx_mmc2_addrs,
5421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5422 };
5423
5424 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5425         {
5426                 .pa_start       = 0x480ad000,
5427                 .pa_end         = 0x480ad3ff,
5428                 .flags          = ADDR_TYPE_RT
5429         },
5430         { }
5431 };
5432
5433 /* l4_per -> mmc3 */
5434 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5435         .master         = &omap44xx_l4_per_hwmod,
5436         .slave          = &omap44xx_mmc3_hwmod,
5437         .clk            = "l4_div_ck",
5438         .addr           = omap44xx_mmc3_addrs,
5439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5440 };
5441
5442 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5443         {
5444                 .pa_start       = 0x480d1000,
5445                 .pa_end         = 0x480d13ff,
5446                 .flags          = ADDR_TYPE_RT
5447         },
5448         { }
5449 };
5450
5451 /* l4_per -> mmc4 */
5452 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5453         .master         = &omap44xx_l4_per_hwmod,
5454         .slave          = &omap44xx_mmc4_hwmod,
5455         .clk            = "l4_div_ck",
5456         .addr           = omap44xx_mmc4_addrs,
5457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5458 };
5459
5460 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5461         {
5462                 .pa_start       = 0x480d5000,
5463                 .pa_end         = 0x480d53ff,
5464                 .flags          = ADDR_TYPE_RT
5465         },
5466         { }
5467 };
5468
5469 /* l4_per -> mmc5 */
5470 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5471         .master         = &omap44xx_l4_per_hwmod,
5472         .slave          = &omap44xx_mmc5_hwmod,
5473         .clk            = "l4_div_ck",
5474         .addr           = omap44xx_mmc5_addrs,
5475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5476 };
5477
5478 /* l3_main_2 -> ocmc_ram */
5479 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5480         .master         = &omap44xx_l3_main_2_hwmod,
5481         .slave          = &omap44xx_ocmc_ram_hwmod,
5482         .clk            = "l3_div_ck",
5483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5484 };
5485
5486 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5487         {
5488                 .pa_start       = 0x4a0ad000,
5489                 .pa_end         = 0x4a0ad01f,
5490                 .flags          = ADDR_TYPE_RT
5491         },
5492         { }
5493 };
5494
5495 /* l4_cfg -> ocp2scp_usb_phy */
5496 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5497         .master         = &omap44xx_l4_cfg_hwmod,
5498         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5499         .clk            = "l4_div_ck",
5500         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5501         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5502 };
5503
5504 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5505         {
5506                 .pa_start       = 0x48243000,
5507                 .pa_end         = 0x48243fff,
5508                 .flags          = ADDR_TYPE_RT
5509         },
5510         { }
5511 };
5512
5513 /* mpu_private -> prcm_mpu */
5514 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5515         .master         = &omap44xx_mpu_private_hwmod,
5516         .slave          = &omap44xx_prcm_mpu_hwmod,
5517         .clk            = "l3_div_ck",
5518         .addr           = omap44xx_prcm_mpu_addrs,
5519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5520 };
5521
5522 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5523         {
5524                 .pa_start       = 0x4a004000,
5525                 .pa_end         = 0x4a004fff,
5526                 .flags          = ADDR_TYPE_RT
5527         },
5528         { }
5529 };
5530
5531 /* l4_wkup -> cm_core_aon */
5532 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5533         .master         = &omap44xx_l4_wkup_hwmod,
5534         .slave          = &omap44xx_cm_core_aon_hwmod,
5535         .clk            = "l4_wkup_clk_mux_ck",
5536         .addr           = omap44xx_cm_core_aon_addrs,
5537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5538 };
5539
5540 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5541         {
5542                 .pa_start       = 0x4a008000,
5543                 .pa_end         = 0x4a009fff,
5544                 .flags          = ADDR_TYPE_RT
5545         },
5546         { }
5547 };
5548
5549 /* l4_cfg -> cm_core */
5550 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5551         .master         = &omap44xx_l4_cfg_hwmod,
5552         .slave          = &omap44xx_cm_core_hwmod,
5553         .clk            = "l4_div_ck",
5554         .addr           = omap44xx_cm_core_addrs,
5555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5556 };
5557
5558 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5559         {
5560                 .pa_start       = 0x4a306000,
5561                 .pa_end         = 0x4a307fff,
5562                 .flags          = ADDR_TYPE_RT
5563         },
5564         { }
5565 };
5566
5567 /* l4_wkup -> prm */
5568 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5569         .master         = &omap44xx_l4_wkup_hwmod,
5570         .slave          = &omap44xx_prm_hwmod,
5571         .clk            = "l4_wkup_clk_mux_ck",
5572         .addr           = omap44xx_prm_addrs,
5573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5574 };
5575
5576 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5577         {
5578                 .pa_start       = 0x4a30a000,
5579                 .pa_end         = 0x4a30a7ff,
5580                 .flags          = ADDR_TYPE_RT
5581         },
5582         { }
5583 };
5584
5585 /* l4_wkup -> scrm */
5586 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5587         .master         = &omap44xx_l4_wkup_hwmod,
5588         .slave          = &omap44xx_scrm_hwmod,
5589         .clk            = "l4_wkup_clk_mux_ck",
5590         .addr           = omap44xx_scrm_addrs,
5591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5592 };
5593
5594 /* l3_main_2 -> sl2if */
5595 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5596         .master         = &omap44xx_l3_main_2_hwmod,
5597         .slave          = &omap44xx_sl2if_hwmod,
5598         .clk            = "l3_div_ck",
5599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5600 };
5601
5602 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5603         {
5604                 .pa_start       = 0x4012c000,
5605                 .pa_end         = 0x4012c3ff,
5606                 .flags          = ADDR_TYPE_RT
5607         },
5608         { }
5609 };
5610
5611 /* l4_abe -> slimbus1 */
5612 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5613         .master         = &omap44xx_l4_abe_hwmod,
5614         .slave          = &omap44xx_slimbus1_hwmod,
5615         .clk            = "ocp_abe_iclk",
5616         .addr           = omap44xx_slimbus1_addrs,
5617         .user           = OCP_USER_MPU,
5618 };
5619
5620 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5621         {
5622                 .pa_start       = 0x4902c000,
5623                 .pa_end         = 0x4902c3ff,
5624                 .flags          = ADDR_TYPE_RT
5625         },
5626         { }
5627 };
5628
5629 /* l4_abe -> slimbus1 (dma) */
5630 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5631         .master         = &omap44xx_l4_abe_hwmod,
5632         .slave          = &omap44xx_slimbus1_hwmod,
5633         .clk            = "ocp_abe_iclk",
5634         .addr           = omap44xx_slimbus1_dma_addrs,
5635         .user           = OCP_USER_SDMA,
5636 };
5637
5638 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5639         {
5640                 .pa_start       = 0x48076000,
5641                 .pa_end         = 0x480763ff,
5642                 .flags          = ADDR_TYPE_RT
5643         },
5644         { }
5645 };
5646
5647 /* l4_per -> slimbus2 */
5648 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5649         .master         = &omap44xx_l4_per_hwmod,
5650         .slave          = &omap44xx_slimbus2_hwmod,
5651         .clk            = "l4_div_ck",
5652         .addr           = omap44xx_slimbus2_addrs,
5653         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5654 };
5655
5656 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5657         {
5658                 .pa_start       = 0x4a0dd000,
5659                 .pa_end         = 0x4a0dd03f,
5660                 .flags          = ADDR_TYPE_RT
5661         },
5662         { }
5663 };
5664
5665 /* l4_cfg -> smartreflex_core */
5666 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5667         .master         = &omap44xx_l4_cfg_hwmod,
5668         .slave          = &omap44xx_smartreflex_core_hwmod,
5669         .clk            = "l4_div_ck",
5670         .addr           = omap44xx_smartreflex_core_addrs,
5671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5672 };
5673
5674 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5675         {
5676                 .pa_start       = 0x4a0db000,
5677                 .pa_end         = 0x4a0db03f,
5678                 .flags          = ADDR_TYPE_RT
5679         },
5680         { }
5681 };
5682
5683 /* l4_cfg -> smartreflex_iva */
5684 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5685         .master         = &omap44xx_l4_cfg_hwmod,
5686         .slave          = &omap44xx_smartreflex_iva_hwmod,
5687         .clk            = "l4_div_ck",
5688         .addr           = omap44xx_smartreflex_iva_addrs,
5689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5690 };
5691
5692 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5693         {
5694                 .pa_start       = 0x4a0d9000,
5695                 .pa_end         = 0x4a0d903f,
5696                 .flags          = ADDR_TYPE_RT
5697         },
5698         { }
5699 };
5700
5701 /* l4_cfg -> smartreflex_mpu */
5702 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5703         .master         = &omap44xx_l4_cfg_hwmod,
5704         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5705         .clk            = "l4_div_ck",
5706         .addr           = omap44xx_smartreflex_mpu_addrs,
5707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5708 };
5709
5710 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5711         {
5712                 .pa_start       = 0x4a0f6000,
5713                 .pa_end         = 0x4a0f6fff,
5714                 .flags          = ADDR_TYPE_RT
5715         },
5716         { }
5717 };
5718
5719 /* l4_cfg -> spinlock */
5720 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5721         .master         = &omap44xx_l4_cfg_hwmod,
5722         .slave          = &omap44xx_spinlock_hwmod,
5723         .clk            = "l4_div_ck",
5724         .addr           = omap44xx_spinlock_addrs,
5725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5726 };
5727
5728 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5729         {
5730                 .pa_start       = 0x4a318000,
5731                 .pa_end         = 0x4a31807f,
5732                 .flags          = ADDR_TYPE_RT
5733         },
5734         { }
5735 };
5736
5737 /* l4_wkup -> timer1 */
5738 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5739         .master         = &omap44xx_l4_wkup_hwmod,
5740         .slave          = &omap44xx_timer1_hwmod,
5741         .clk            = "l4_wkup_clk_mux_ck",
5742         .addr           = omap44xx_timer1_addrs,
5743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5744 };
5745
5746 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5747         {
5748                 .pa_start       = 0x48032000,
5749                 .pa_end         = 0x4803207f,
5750                 .flags          = ADDR_TYPE_RT
5751         },
5752         { }
5753 };
5754
5755 /* l4_per -> timer2 */
5756 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5757         .master         = &omap44xx_l4_per_hwmod,
5758         .slave          = &omap44xx_timer2_hwmod,
5759         .clk            = "l4_div_ck",
5760         .addr           = omap44xx_timer2_addrs,
5761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5762 };
5763
5764 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5765         {
5766                 .pa_start       = 0x48034000,
5767                 .pa_end         = 0x4803407f,
5768                 .flags          = ADDR_TYPE_RT
5769         },
5770         { }
5771 };
5772
5773 /* l4_per -> timer3 */
5774 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5775         .master         = &omap44xx_l4_per_hwmod,
5776         .slave          = &omap44xx_timer3_hwmod,
5777         .clk            = "l4_div_ck",
5778         .addr           = omap44xx_timer3_addrs,
5779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5780 };
5781
5782 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5783         {
5784                 .pa_start       = 0x48036000,
5785                 .pa_end         = 0x4803607f,
5786                 .flags          = ADDR_TYPE_RT
5787         },
5788         { }
5789 };
5790
5791 /* l4_per -> timer4 */
5792 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5793         .master         = &omap44xx_l4_per_hwmod,
5794         .slave          = &omap44xx_timer4_hwmod,
5795         .clk            = "l4_div_ck",
5796         .addr           = omap44xx_timer4_addrs,
5797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5798 };
5799
5800 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5801         {
5802                 .pa_start       = 0x40138000,
5803                 .pa_end         = 0x4013807f,
5804                 .flags          = ADDR_TYPE_RT
5805         },
5806         { }
5807 };
5808
5809 /* l4_abe -> timer5 */
5810 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5811         .master         = &omap44xx_l4_abe_hwmod,
5812         .slave          = &omap44xx_timer5_hwmod,
5813         .clk            = "ocp_abe_iclk",
5814         .addr           = omap44xx_timer5_addrs,
5815         .user           = OCP_USER_MPU,
5816 };
5817
5818 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5819         {
5820                 .pa_start       = 0x49038000,
5821                 .pa_end         = 0x4903807f,
5822                 .flags          = ADDR_TYPE_RT
5823         },
5824         { }
5825 };
5826
5827 /* l4_abe -> timer5 (dma) */
5828 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5829         .master         = &omap44xx_l4_abe_hwmod,
5830         .slave          = &omap44xx_timer5_hwmod,
5831         .clk            = "ocp_abe_iclk",
5832         .addr           = omap44xx_timer5_dma_addrs,
5833         .user           = OCP_USER_SDMA,
5834 };
5835
5836 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5837         {
5838                 .pa_start       = 0x4013a000,
5839                 .pa_end         = 0x4013a07f,
5840                 .flags          = ADDR_TYPE_RT
5841         },
5842         { }
5843 };
5844
5845 /* l4_abe -> timer6 */
5846 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5847         .master         = &omap44xx_l4_abe_hwmod,
5848         .slave          = &omap44xx_timer6_hwmod,
5849         .clk            = "ocp_abe_iclk",
5850         .addr           = omap44xx_timer6_addrs,
5851         .user           = OCP_USER_MPU,
5852 };
5853
5854 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5855         {
5856                 .pa_start       = 0x4903a000,
5857                 .pa_end         = 0x4903a07f,
5858                 .flags          = ADDR_TYPE_RT
5859         },
5860         { }
5861 };
5862
5863 /* l4_abe -> timer6 (dma) */
5864 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5865         .master         = &omap44xx_l4_abe_hwmod,
5866         .slave          = &omap44xx_timer6_hwmod,
5867         .clk            = "ocp_abe_iclk",
5868         .addr           = omap44xx_timer6_dma_addrs,
5869         .user           = OCP_USER_SDMA,
5870 };
5871
5872 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5873         {
5874                 .pa_start       = 0x4013c000,
5875                 .pa_end         = 0x4013c07f,
5876                 .flags          = ADDR_TYPE_RT
5877         },
5878         { }
5879 };
5880
5881 /* l4_abe -> timer7 */
5882 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5883         .master         = &omap44xx_l4_abe_hwmod,
5884         .slave          = &omap44xx_timer7_hwmod,
5885         .clk            = "ocp_abe_iclk",
5886         .addr           = omap44xx_timer7_addrs,
5887         .user           = OCP_USER_MPU,
5888 };
5889
5890 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5891         {
5892                 .pa_start       = 0x4903c000,
5893                 .pa_end         = 0x4903c07f,
5894                 .flags          = ADDR_TYPE_RT
5895         },
5896         { }
5897 };
5898
5899 /* l4_abe -> timer7 (dma) */
5900 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5901         .master         = &omap44xx_l4_abe_hwmod,
5902         .slave          = &omap44xx_timer7_hwmod,
5903         .clk            = "ocp_abe_iclk",
5904         .addr           = omap44xx_timer7_dma_addrs,
5905         .user           = OCP_USER_SDMA,
5906 };
5907
5908 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5909         {
5910                 .pa_start       = 0x4013e000,
5911                 .pa_end         = 0x4013e07f,
5912                 .flags          = ADDR_TYPE_RT
5913         },
5914         { }
5915 };
5916
5917 /* l4_abe -> timer8 */
5918 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5919         .master         = &omap44xx_l4_abe_hwmod,
5920         .slave          = &omap44xx_timer8_hwmod,
5921         .clk            = "ocp_abe_iclk",
5922         .addr           = omap44xx_timer8_addrs,
5923         .user           = OCP_USER_MPU,
5924 };
5925
5926 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5927         {
5928                 .pa_start       = 0x4903e000,
5929                 .pa_end         = 0x4903e07f,
5930                 .flags          = ADDR_TYPE_RT
5931         },
5932         { }
5933 };
5934
5935 /* l4_abe -> timer8 (dma) */
5936 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5937         .master         = &omap44xx_l4_abe_hwmod,
5938         .slave          = &omap44xx_timer8_hwmod,
5939         .clk            = "ocp_abe_iclk",
5940         .addr           = omap44xx_timer8_dma_addrs,
5941         .user           = OCP_USER_SDMA,
5942 };
5943
5944 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5945         {
5946                 .pa_start       = 0x4803e000,
5947                 .pa_end         = 0x4803e07f,
5948                 .flags          = ADDR_TYPE_RT
5949         },
5950         { }
5951 };
5952
5953 /* l4_per -> timer9 */
5954 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5955         .master         = &omap44xx_l4_per_hwmod,
5956         .slave          = &omap44xx_timer9_hwmod,
5957         .clk            = "l4_div_ck",
5958         .addr           = omap44xx_timer9_addrs,
5959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5960 };
5961
5962 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5963         {
5964                 .pa_start       = 0x48086000,
5965                 .pa_end         = 0x4808607f,
5966                 .flags          = ADDR_TYPE_RT
5967         },
5968         { }
5969 };
5970
5971 /* l4_per -> timer10 */
5972 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5973         .master         = &omap44xx_l4_per_hwmod,
5974         .slave          = &omap44xx_timer10_hwmod,
5975         .clk            = "l4_div_ck",
5976         .addr           = omap44xx_timer10_addrs,
5977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5978 };
5979
5980 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5981         {
5982                 .pa_start       = 0x48088000,
5983                 .pa_end         = 0x4808807f,
5984                 .flags          = ADDR_TYPE_RT
5985         },
5986         { }
5987 };
5988
5989 /* l4_per -> timer11 */
5990 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5991         .master         = &omap44xx_l4_per_hwmod,
5992         .slave          = &omap44xx_timer11_hwmod,
5993         .clk            = "l4_div_ck",
5994         .addr           = omap44xx_timer11_addrs,
5995         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5996 };
5997
5998 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5999         {
6000                 .pa_start       = 0x4806a000,
6001                 .pa_end         = 0x4806a0ff,
6002                 .flags          = ADDR_TYPE_RT
6003         },
6004         { }
6005 };
6006
6007 /* l4_per -> uart1 */
6008 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6009         .master         = &omap44xx_l4_per_hwmod,
6010         .slave          = &omap44xx_uart1_hwmod,
6011         .clk            = "l4_div_ck",
6012         .addr           = omap44xx_uart1_addrs,
6013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6014 };
6015
6016 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6017         {
6018                 .pa_start       = 0x4806c000,
6019                 .pa_end         = 0x4806c0ff,
6020                 .flags          = ADDR_TYPE_RT
6021         },
6022         { }
6023 };
6024
6025 /* l4_per -> uart2 */
6026 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6027         .master         = &omap44xx_l4_per_hwmod,
6028         .slave          = &omap44xx_uart2_hwmod,
6029         .clk            = "l4_div_ck",
6030         .addr           = omap44xx_uart2_addrs,
6031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6032 };
6033
6034 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6035         {
6036                 .pa_start       = 0x48020000,
6037                 .pa_end         = 0x480200ff,
6038                 .flags          = ADDR_TYPE_RT
6039         },
6040         { }
6041 };
6042
6043 /* l4_per -> uart3 */
6044 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6045         .master         = &omap44xx_l4_per_hwmod,
6046         .slave          = &omap44xx_uart3_hwmod,
6047         .clk            = "l4_div_ck",
6048         .addr           = omap44xx_uart3_addrs,
6049         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6050 };
6051
6052 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6053         {
6054                 .pa_start       = 0x4806e000,
6055                 .pa_end         = 0x4806e0ff,
6056                 .flags          = ADDR_TYPE_RT
6057         },
6058         { }
6059 };
6060
6061 /* l4_per -> uart4 */
6062 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6063         .master         = &omap44xx_l4_per_hwmod,
6064         .slave          = &omap44xx_uart4_hwmod,
6065         .clk            = "l4_div_ck",
6066         .addr           = omap44xx_uart4_addrs,
6067         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6068 };
6069
6070 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6071         {
6072                 .pa_start       = 0x4a0a9000,
6073                 .pa_end         = 0x4a0a93ff,
6074                 .flags          = ADDR_TYPE_RT
6075         },
6076         { }
6077 };
6078
6079 /* l4_cfg -> usb_host_fs */
6080 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6081         .master         = &omap44xx_l4_cfg_hwmod,
6082         .slave          = &omap44xx_usb_host_fs_hwmod,
6083         .clk            = "l4_div_ck",
6084         .addr           = omap44xx_usb_host_fs_addrs,
6085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6086 };
6087
6088 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6089         {
6090                 .name           = "uhh",
6091                 .pa_start       = 0x4a064000,
6092                 .pa_end         = 0x4a0647ff,
6093                 .flags          = ADDR_TYPE_RT
6094         },
6095         {
6096                 .name           = "ohci",
6097                 .pa_start       = 0x4a064800,
6098                 .pa_end         = 0x4a064bff,
6099         },
6100         {
6101                 .name           = "ehci",
6102                 .pa_start       = 0x4a064c00,
6103                 .pa_end         = 0x4a064fff,
6104         },
6105         {}
6106 };
6107
6108 /* l4_cfg -> usb_host_hs */
6109 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6110         .master         = &omap44xx_l4_cfg_hwmod,
6111         .slave          = &omap44xx_usb_host_hs_hwmod,
6112         .clk            = "l4_div_ck",
6113         .addr           = omap44xx_usb_host_hs_addrs,
6114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6115 };
6116
6117 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6118         {
6119                 .pa_start       = 0x4a0ab000,
6120                 .pa_end         = 0x4a0ab7ff,
6121                 .flags          = ADDR_TYPE_RT
6122         },
6123         {
6124                 /* XXX: Remove this once control module driver is in place */
6125                 .pa_start       = 0x4a00233c,
6126                 .pa_end         = 0x4a00233f,
6127                 .flags          = ADDR_TYPE_RT
6128         },
6129         { }
6130 };
6131
6132 /* l4_cfg -> usb_otg_hs */
6133 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6134         .master         = &omap44xx_l4_cfg_hwmod,
6135         .slave          = &omap44xx_usb_otg_hs_hwmod,
6136         .clk            = "l4_div_ck",
6137         .addr           = omap44xx_usb_otg_hs_addrs,
6138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6139 };
6140
6141 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6142         {
6143                 .name           = "tll",
6144                 .pa_start       = 0x4a062000,
6145                 .pa_end         = 0x4a063fff,
6146                 .flags          = ADDR_TYPE_RT
6147         },
6148         {}
6149 };
6150
6151 /* l4_cfg -> usb_tll_hs */
6152 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6153         .master         = &omap44xx_l4_cfg_hwmod,
6154         .slave          = &omap44xx_usb_tll_hs_hwmod,
6155         .clk            = "l4_div_ck",
6156         .addr           = omap44xx_usb_tll_hs_addrs,
6157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6158 };
6159
6160 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6161         {
6162                 .pa_start       = 0x4a314000,
6163                 .pa_end         = 0x4a31407f,
6164                 .flags          = ADDR_TYPE_RT
6165         },
6166         { }
6167 };
6168
6169 /* l4_wkup -> wd_timer2 */
6170 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6171         .master         = &omap44xx_l4_wkup_hwmod,
6172         .slave          = &omap44xx_wd_timer2_hwmod,
6173         .clk            = "l4_wkup_clk_mux_ck",
6174         .addr           = omap44xx_wd_timer2_addrs,
6175         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6176 };
6177
6178 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6179         {
6180                 .pa_start       = 0x40130000,
6181                 .pa_end         = 0x4013007f,
6182                 .flags          = ADDR_TYPE_RT
6183         },
6184         { }
6185 };
6186
6187 /* l4_abe -> wd_timer3 */
6188 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6189         .master         = &omap44xx_l4_abe_hwmod,
6190         .slave          = &omap44xx_wd_timer3_hwmod,
6191         .clk            = "ocp_abe_iclk",
6192         .addr           = omap44xx_wd_timer3_addrs,
6193         .user           = OCP_USER_MPU,
6194 };
6195
6196 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6197         {
6198                 .pa_start       = 0x49030000,
6199                 .pa_end         = 0x4903007f,
6200                 .flags          = ADDR_TYPE_RT
6201         },
6202         { }
6203 };
6204
6205 /* l4_abe -> wd_timer3 (dma) */
6206 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6207         .master         = &omap44xx_l4_abe_hwmod,
6208         .slave          = &omap44xx_wd_timer3_hwmod,
6209         .clk            = "ocp_abe_iclk",
6210         .addr           = omap44xx_wd_timer3_dma_addrs,
6211         .user           = OCP_USER_SDMA,
6212 };
6213
6214 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6215         &omap44xx_c2c__c2c_target_fw,
6216         &omap44xx_l4_cfg__c2c_target_fw,
6217         &omap44xx_l3_main_1__dmm,
6218         &omap44xx_mpu__dmm,
6219         &omap44xx_c2c__emif_fw,
6220         &omap44xx_dmm__emif_fw,
6221         &omap44xx_l4_cfg__emif_fw,
6222         &omap44xx_iva__l3_instr,
6223         &omap44xx_l3_main_3__l3_instr,
6224         &omap44xx_ocp_wp_noc__l3_instr,
6225         &omap44xx_dsp__l3_main_1,
6226         &omap44xx_dss__l3_main_1,
6227         &omap44xx_l3_main_2__l3_main_1,
6228         &omap44xx_l4_cfg__l3_main_1,
6229         &omap44xx_mmc1__l3_main_1,
6230         &omap44xx_mmc2__l3_main_1,
6231         &omap44xx_mpu__l3_main_1,
6232         &omap44xx_c2c_target_fw__l3_main_2,
6233         &omap44xx_debugss__l3_main_2,
6234         &omap44xx_dma_system__l3_main_2,
6235         &omap44xx_fdif__l3_main_2,
6236         &omap44xx_gpu__l3_main_2,
6237         &omap44xx_hsi__l3_main_2,
6238         &omap44xx_ipu__l3_main_2,
6239         &omap44xx_iss__l3_main_2,
6240         &omap44xx_iva__l3_main_2,
6241         &omap44xx_l3_main_1__l3_main_2,
6242         &omap44xx_l4_cfg__l3_main_2,
6243         /* &omap44xx_usb_host_fs__l3_main_2, */
6244         &omap44xx_usb_host_hs__l3_main_2,
6245         &omap44xx_usb_otg_hs__l3_main_2,
6246         &omap44xx_l3_main_1__l3_main_3,
6247         &omap44xx_l3_main_2__l3_main_3,
6248         &omap44xx_l4_cfg__l3_main_3,
6249         /* &omap44xx_aess__l4_abe, */
6250         &omap44xx_dsp__l4_abe,
6251         &omap44xx_l3_main_1__l4_abe,
6252         &omap44xx_mpu__l4_abe,
6253         &omap44xx_l3_main_1__l4_cfg,
6254         &omap44xx_l3_main_2__l4_per,
6255         &omap44xx_l4_cfg__l4_wkup,
6256         &omap44xx_mpu__mpu_private,
6257         &omap44xx_l4_cfg__ocp_wp_noc,
6258         /* &omap44xx_l4_abe__aess, */
6259         /* &omap44xx_l4_abe__aess_dma, */
6260         &omap44xx_l3_main_2__c2c,
6261         &omap44xx_l4_wkup__counter_32k,
6262         &omap44xx_l4_cfg__ctrl_module_core,
6263         &omap44xx_l4_cfg__ctrl_module_pad_core,
6264         &omap44xx_l4_wkup__ctrl_module_wkup,
6265         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6266         &omap44xx_l3_instr__debugss,
6267         &omap44xx_l4_cfg__dma_system,
6268         &omap44xx_l4_abe__dmic,
6269         &omap44xx_l4_abe__dmic_dma,
6270         &omap44xx_dsp__iva,
6271         /* &omap44xx_dsp__sl2if, */
6272         &omap44xx_l4_cfg__dsp,
6273         &omap44xx_l3_main_2__dss,
6274         &omap44xx_l4_per__dss,
6275         &omap44xx_l3_main_2__dss_dispc,
6276         &omap44xx_l4_per__dss_dispc,
6277         &omap44xx_l3_main_2__dss_dsi1,
6278         &omap44xx_l4_per__dss_dsi1,
6279         &omap44xx_l3_main_2__dss_dsi2,
6280         &omap44xx_l4_per__dss_dsi2,
6281         &omap44xx_l3_main_2__dss_hdmi,
6282         &omap44xx_l4_per__dss_hdmi,
6283         &omap44xx_l3_main_2__dss_rfbi,
6284         &omap44xx_l4_per__dss_rfbi,
6285         &omap44xx_l3_main_2__dss_venc,
6286         &omap44xx_l4_per__dss_venc,
6287         &omap44xx_l4_per__elm,
6288         &omap44xx_emif_fw__emif1,
6289         &omap44xx_emif_fw__emif2,
6290         &omap44xx_l4_cfg__fdif,
6291         &omap44xx_l4_wkup__gpio1,
6292         &omap44xx_l4_per__gpio2,
6293         &omap44xx_l4_per__gpio3,
6294         &omap44xx_l4_per__gpio4,
6295         &omap44xx_l4_per__gpio5,
6296         &omap44xx_l4_per__gpio6,
6297         &omap44xx_l3_main_2__gpmc,
6298         &omap44xx_l3_main_2__gpu,
6299         &omap44xx_l4_per__hdq1w,
6300         &omap44xx_l4_cfg__hsi,
6301         &omap44xx_l4_per__i2c1,
6302         &omap44xx_l4_per__i2c2,
6303         &omap44xx_l4_per__i2c3,
6304         &omap44xx_l4_per__i2c4,
6305         &omap44xx_l3_main_2__ipu,
6306         &omap44xx_l3_main_2__iss,
6307         /* &omap44xx_iva__sl2if, */
6308         &omap44xx_l3_main_2__iva,
6309         &omap44xx_l4_wkup__kbd,
6310         &omap44xx_l4_cfg__mailbox,
6311         &omap44xx_l4_abe__mcasp,
6312         &omap44xx_l4_abe__mcasp_dma,
6313         &omap44xx_l4_abe__mcbsp1,
6314         &omap44xx_l4_abe__mcbsp1_dma,
6315         &omap44xx_l4_abe__mcbsp2,
6316         &omap44xx_l4_abe__mcbsp2_dma,
6317         &omap44xx_l4_abe__mcbsp3,
6318         &omap44xx_l4_abe__mcbsp3_dma,
6319         &omap44xx_l4_per__mcbsp4,
6320         &omap44xx_l4_abe__mcpdm,
6321         &omap44xx_l4_abe__mcpdm_dma,
6322         &omap44xx_l4_per__mcspi1,
6323         &omap44xx_l4_per__mcspi2,
6324         &omap44xx_l4_per__mcspi3,
6325         &omap44xx_l4_per__mcspi4,
6326         &omap44xx_l4_per__mmc1,
6327         &omap44xx_l4_per__mmc2,
6328         &omap44xx_l4_per__mmc3,
6329         &omap44xx_l4_per__mmc4,
6330         &omap44xx_l4_per__mmc5,
6331         &omap44xx_l3_main_2__mmu_ipu,
6332         &omap44xx_l4_cfg__mmu_dsp,
6333         &omap44xx_l3_main_2__ocmc_ram,
6334         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6335         &omap44xx_mpu_private__prcm_mpu,
6336         &omap44xx_l4_wkup__cm_core_aon,
6337         &omap44xx_l4_cfg__cm_core,
6338         &omap44xx_l4_wkup__prm,
6339         &omap44xx_l4_wkup__scrm,
6340         /* &omap44xx_l3_main_2__sl2if, */
6341         &omap44xx_l4_abe__slimbus1,
6342         &omap44xx_l4_abe__slimbus1_dma,
6343         &omap44xx_l4_per__slimbus2,
6344         &omap44xx_l4_cfg__smartreflex_core,
6345         &omap44xx_l4_cfg__smartreflex_iva,
6346         &omap44xx_l4_cfg__smartreflex_mpu,
6347         &omap44xx_l4_cfg__spinlock,
6348         &omap44xx_l4_wkup__timer1,
6349         &omap44xx_l4_per__timer2,
6350         &omap44xx_l4_per__timer3,
6351         &omap44xx_l4_per__timer4,
6352         &omap44xx_l4_abe__timer5,
6353         &omap44xx_l4_abe__timer5_dma,
6354         &omap44xx_l4_abe__timer6,
6355         &omap44xx_l4_abe__timer6_dma,
6356         &omap44xx_l4_abe__timer7,
6357         &omap44xx_l4_abe__timer7_dma,
6358         &omap44xx_l4_abe__timer8,
6359         &omap44xx_l4_abe__timer8_dma,
6360         &omap44xx_l4_per__timer9,
6361         &omap44xx_l4_per__timer10,
6362         &omap44xx_l4_per__timer11,
6363         &omap44xx_l4_per__uart1,
6364         &omap44xx_l4_per__uart2,
6365         &omap44xx_l4_per__uart3,
6366         &omap44xx_l4_per__uart4,
6367         /* &omap44xx_l4_cfg__usb_host_fs, */
6368         &omap44xx_l4_cfg__usb_host_hs,
6369         &omap44xx_l4_cfg__usb_otg_hs,
6370         &omap44xx_l4_cfg__usb_tll_hs,
6371         &omap44xx_l4_wkup__wd_timer2,
6372         &omap44xx_l4_abe__wd_timer3,
6373         &omap44xx_l4_abe__wd_timer3_dma,
6374         NULL,
6375 };
6376
6377 int __init omap44xx_hwmod_init(void)
6378 {
6379         omap_hwmod_init();
6380         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6381 }
6382