arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <plat-omap/dma-omap.h>
  27
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30 #include <plat/dmtimer.h>
  31 #include <plat/iommu.h>
  32
  33 #include "../plat-omap/common.h"
  34
  35 #include "omap_hwmod.h"
  36 #include "omap_hwmod_common_data.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "i2c.h"
  42 #include "mmc.h"
  43 #include "wd_timer.h"
  44
  45 /* Base offset for all OMAP4 interrupts external to MPUSS */
  46 #define OMAP44XX_IRQ_GIC_START  32
  47
  48 /* Base offset for all OMAP4 dma requests */
  49 #define OMAP44XX_DMA_REQ_START  1
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /*
  56  * 'c2c_target_fw' class
  57  * instance(s): c2c_target_fw
  58  */
  59 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  60         .name   = "c2c_target_fw",
  61 };
  62
  63 /* c2c_target_fw */
  64 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  65         .name           = "c2c_target_fw",
  66         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  67         .clkdm_name     = "d2d_clkdm",
  68         .prcm = {
  69                 .omap4 = {
  70                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  71                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  72                 },
  73         },
  74 };
  75
  76 /*
  77  * 'dmm' class
  78  * instance(s): dmm
  79  */
  80 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  81         .name   = "dmm",
  82 };
  83
  84 /* dmm */
  85 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  86         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  87         { .irq = -1 }
  88 };
  89
  90 static struct omap_hwmod omap44xx_dmm_hwmod = {
  91         .name           = "dmm",
  92         .class          = &omap44xx_dmm_hwmod_class,
  93         .clkdm_name     = "l3_emif_clkdm",
  94         .mpu_irqs       = omap44xx_dmm_irqs,
  95         .prcm = {
  96                 .omap4 = {
  97                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  98                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  99                 },
 100         },
 101 };
 102
 103 /*
 104  * 'emif_fw' class
 105  * instance(s): emif_fw
 106  */
 107 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 108         .name   = "emif_fw",
 109 };
 110
 111 /* emif_fw */
 112 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 113         .name           = "emif_fw",
 114         .class          = &omap44xx_emif_fw_hwmod_class,
 115         .clkdm_name     = "l3_emif_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 119                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 120                 },
 121         },
 122 };
 123
 124 /*
 125  * 'l3' class
 126  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 127  */
 128 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 129         .name   = "l3",
 130 };
 131
 132 /* l3_instr */
 133 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 134         .name           = "l3_instr",
 135         .class          = &omap44xx_l3_hwmod_class,
 136         .clkdm_name     = "l3_instr_clkdm",
 137         .prcm = {
 138                 .omap4 = {
 139                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 140                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 141                         .modulemode   = MODULEMODE_HWCTRL,
 142                 },
 143         },
 144 };
 145
 146 /* l3_main_1 */
 147 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 148         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 149         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 150         { .irq = -1 }
 151 };
 152
 153 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 154         .name           = "l3_main_1",
 155         .class          = &omap44xx_l3_hwmod_class,
 156         .clkdm_name     = "l3_1_clkdm",
 157         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 158         .prcm = {
 159                 .omap4 = {
 160                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 161                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 162                 },
 163         },
 164 };
 165
 166 /* l3_main_2 */
 167 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 168         .name           = "l3_main_2",
 169         .class          = &omap44xx_l3_hwmod_class,
 170         .clkdm_name     = "l3_2_clkdm",
 171         .prcm = {
 172                 .omap4 = {
 173                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 174                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 175                 },
 176         },
 177 };
 178
 179 /* l3_main_3 */
 180 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 181         .name           = "l3_main_3",
 182         .class          = &omap44xx_l3_hwmod_class,
 183         .clkdm_name     = "l3_instr_clkdm",
 184         .prcm = {
 185                 .omap4 = {
 186                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 187                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 188                         .modulemode   = MODULEMODE_HWCTRL,
 189                 },
 190         },
 191 };
 192
 193 /*
 194  * 'l4' class
 195  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 196  */
 197 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 198         .name   = "l4",
 199 };
 200
 201 /* l4_abe */
 202 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 203         .name           = "l4_abe",
 204         .class          = &omap44xx_l4_hwmod_class,
 205         .clkdm_name     = "abe_clkdm",
 206         .prcm = {
 207                 .omap4 = {
 208                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 209                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 210                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 211                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 212                 },
 213         },
 214 };
 215
 216 /* l4_cfg */
 217 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 218         .name           = "l4_cfg",
 219         .class          = &omap44xx_l4_hwmod_class,
 220         .clkdm_name     = "l4_cfg_clkdm",
 221         .prcm = {
 222                 .omap4 = {
 223                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 224                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 225                 },
 226         },
 227 };
 228
 229 /* l4_per */
 230 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 231         .name           = "l4_per",
 232         .class          = &omap44xx_l4_hwmod_class,
 233         .clkdm_name     = "l4_per_clkdm",
 234         .prcm = {
 235                 .omap4 = {
 236                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 237                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 238                 },
 239         },
 240 };
 241
 242 /* l4_wkup */
 243 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 244         .name           = "l4_wkup",
 245         .class          = &omap44xx_l4_hwmod_class,
 246         .clkdm_name     = "l4_wkup_clkdm",
 247         .prcm = {
 248                 .omap4 = {
 249                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 250                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 251                 },
 252         },
 253 };
 254
 255 /*
 256  * 'mpu_bus' class
 257  * instance(s): mpu_private
 258  */
 259 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 260         .name   = "mpu_bus",
 261 };
 262
 263 /* mpu_private */
 264 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 265         .name           = "mpu_private",
 266         .class          = &omap44xx_mpu_bus_hwmod_class,
 267         .clkdm_name     = "mpuss_clkdm",
 268         .prcm = {
 269                 .omap4 = {
 270                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 271                 },
 272         },
 273 };
 274
 275 /*
 276  * 'ocp_wp_noc' class
 277  * instance(s): ocp_wp_noc
 278  */
 279 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 280         .name   = "ocp_wp_noc",
 281 };
 282
 283 /* ocp_wp_noc */
 284 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 285         .name           = "ocp_wp_noc",
 286         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 287         .clkdm_name     = "l3_instr_clkdm",
 288         .prcm = {
 289                 .omap4 = {
 290                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 291                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 292                         .modulemode   = MODULEMODE_HWCTRL,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * Modules omap_hwmod structures
 299  *
 300  * The following IPs are excluded for the moment because:
 301  * - They do not need an explicit SW control using omap_hwmod API.
 302  * - They still need to be validated with the driver
 303  *   properly adapted to omap_hwmod / omap_device
 304  *
 305  * usim
 306  */
 307
 308 /*
 309  * 'aess' class
 310  * audio engine sub system
 311  */
 312
 313 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 314         .rev_offs       = 0x0000,
 315         .sysc_offs      = 0x0010,
 316         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 317         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 318                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 319                            MSTANDBY_SMART_WKUP),
 320         .sysc_fields    = &omap_hwmod_sysc_type2,
 321 };
 322
 323 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 324         .name   = "aess",
 325         .sysc   = &omap44xx_aess_sysc,
 326 };
 327
 328 /* aess */
 329 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 330         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 331         { .irq = -1 }
 332 };
 333
 334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 335         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 342         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 343         { .dma_req = -1 }
 344 };
 345
 346 static struct omap_hwmod omap44xx_aess_hwmod = {
 347         .name           = "aess",
 348         .class          = &omap44xx_aess_hwmod_class,
 349         .clkdm_name     = "abe_clkdm",
 350         .mpu_irqs       = omap44xx_aess_irqs,
 351         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 352         .main_clk       = "aess_fck",
 353         .prcm = {
 354                 .omap4 = {
 355                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 356                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 357                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 358                         .modulemode   = MODULEMODE_SWCTRL,
 359                 },
 360         },
 361 };
 362
 363 /*
 364  * 'c2c' class
 365  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 366  * soc
 367  */
 368
 369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 370         .name   = "c2c",
 371 };
 372
 373 /* c2c */
 374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 375         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 376         { .irq = -1 }
 377 };
 378
 379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 380         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 381         { .dma_req = -1 }
 382 };
 383
 384 static struct omap_hwmod omap44xx_c2c_hwmod = {
 385         .name           = "c2c",
 386         .class          = &omap44xx_c2c_hwmod_class,
 387         .clkdm_name     = "d2d_clkdm",
 388         .mpu_irqs       = omap44xx_c2c_irqs,
 389         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 390         .prcm = {
 391                 .omap4 = {
 392                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 393                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 394                 },
 395         },
 396 };
 397
 398 /*
 399  * 'counter' class
 400  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 401  */
 402
 403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 404         .rev_offs       = 0x0000,
 405         .sysc_offs      = 0x0004,
 406         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 408         .sysc_fields    = &omap_hwmod_sysc_type1,
 409 };
 410
 411 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 412         .name   = "counter",
 413         .sysc   = &omap44xx_counter_sysc,
 414 };
 415
 416 /* counter_32k */
 417 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 418         .name           = "counter_32k",
 419         .class          = &omap44xx_counter_hwmod_class,
 420         .clkdm_name     = "l4_wkup_clkdm",
 421         .flags          = HWMOD_SWSUP_SIDLE,
 422         .main_clk       = "sys_32k_ck",
 423         .prcm = {
 424                 .omap4 = {
 425                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 426                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 427                 },
 428         },
 429 };
 430
 431 /*
 432  * 'ctrl_module' class
 433  * attila core control module + core pad control module + wkup pad control
 434  * module + attila wkup control module
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 438         .rev_offs       = 0x0000,
 439         .sysc_offs      = 0x0010,
 440         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                            SIDLE_SMART_WKUP),
 443         .sysc_fields    = &omap_hwmod_sysc_type2,
 444 };
 445
 446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 447         .name   = "ctrl_module",
 448         .sysc   = &omap44xx_ctrl_module_sysc,
 449 };
 450
 451 /* ctrl_module_core */
 452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 453         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 454         { .irq = -1 }
 455 };
 456
 457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 458         .name           = "ctrl_module_core",
 459         .class          = &omap44xx_ctrl_module_hwmod_class,
 460         .clkdm_name     = "l4_cfg_clkdm",
 461         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 462         .prcm = {
 463                 .omap4 = {
 464                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 465                 },
 466         },
 467 };
 468
 469 /* ctrl_module_pad_core */
 470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 471         .name           = "ctrl_module_pad_core",
 472         .class          = &omap44xx_ctrl_module_hwmod_class,
 473         .clkdm_name     = "l4_cfg_clkdm",
 474         .prcm = {
 475                 .omap4 = {
 476                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 477                 },
 478         },
 479 };
 480
 481 /* ctrl_module_wkup */
 482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 483         .name           = "ctrl_module_wkup",
 484         .class          = &omap44xx_ctrl_module_hwmod_class,
 485         .clkdm_name     = "l4_wkup_clkdm",
 486         .prcm = {
 487                 .omap4 = {
 488                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 489                 },
 490         },
 491 };
 492
 493 /* ctrl_module_pad_wkup */
 494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 495         .name           = "ctrl_module_pad_wkup",
 496         .class          = &omap44xx_ctrl_module_hwmod_class,
 497         .clkdm_name     = "l4_wkup_clkdm",
 498         .prcm = {
 499                 .omap4 = {
 500                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 501                 },
 502         },
 503 };
 504
 505 /*
 506  * 'debugss' class
 507  * debug and emulation sub system
 508  */
 509
 510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 511         .name   = "debugss",
 512 };
 513
 514 /* debugss */
 515 static struct omap_hwmod omap44xx_debugss_hwmod = {
 516         .name           = "debugss",
 517         .class          = &omap44xx_debugss_hwmod_class,
 518         .clkdm_name     = "emu_sys_clkdm",
 519         .main_clk       = "trace_clk_div_ck",
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 523                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 524                 },
 525         },
 526 };
 527
 528 /*
 529  * 'dma' class
 530  * dma controller for data exchange between memory to memory (i.e. internal or
 531  * external memory) and gp peripherals to memory or memory to gp peripherals
 532  */
 533
 534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x002c,
 537         .syss_offs      = 0x0028,
 538         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 539                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 540                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 541                            SYSS_HAS_RESET_STATUS),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 543                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 544         .sysc_fields    = &omap_hwmod_sysc_type1,
 545 };
 546
 547 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 548         .name   = "dma",
 549         .sysc   = &omap44xx_dma_sysc,
 550 };
 551
 552 /* dma dev_attr */
 553 static struct omap_dma_dev_attr dma_dev_attr = {
 554         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 555                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 556         .lch_count      = 32,
 557 };
 558
 559 /* dma_system */
 560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 561         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 564         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 565         { .irq = -1 }
 566 };
 567
 568 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 569         .name           = "dma_system",
 570         .class          = &omap44xx_dma_hwmod_class,
 571         .clkdm_name     = "l3_dma_clkdm",
 572         .mpu_irqs       = omap44xx_dma_system_irqs,
 573         .main_clk       = "l3_div_ck",
 574         .prcm = {
 575                 .omap4 = {
 576                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 577                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 578                 },
 579         },
 580         .dev_attr       = &dma_dev_attr,
 581 };
 582
 583 /*
 584  * 'dmic' class
 585  * digital microphone controller
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 594                            SIDLE_SMART_WKUP),
 595         .sysc_fields    = &omap_hwmod_sysc_type2,
 596 };
 597
 598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 599         .name   = "dmic",
 600         .sysc   = &omap44xx_dmic_sysc,
 601 };
 602
 603 /* dmic */
 604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 605         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 606         { .irq = -1 }
 607 };
 608
 609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 610         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 611         { .dma_req = -1 }
 612 };
 613
 614 static struct omap_hwmod omap44xx_dmic_hwmod = {
 615         .name           = "dmic",
 616         .class          = &omap44xx_dmic_hwmod_class,
 617         .clkdm_name     = "abe_clkdm",
 618         .mpu_irqs       = omap44xx_dmic_irqs,
 619         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 620         .main_clk       = "dmic_fck",
 621         .prcm = {
 622                 .omap4 = {
 623                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 624                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 625                         .modulemode   = MODULEMODE_SWCTRL,
 626                 },
 627         },
 628 };
 629
 630 /*
 631  * 'dsp' class
 632  * dsp sub-system
 633  */
 634
 635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 636         .name   = "dsp",
 637 };
 638
 639 /* dsp */
 640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 641         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 642         { .irq = -1 }
 643 };
 644
 645 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 646         { .name = "dsp", .rst_shift = 0 },
 647 };
 648
 649 static struct omap_hwmod omap44xx_dsp_hwmod = {
 650         .name           = "dsp",
 651         .class          = &omap44xx_dsp_hwmod_class,
 652         .clkdm_name     = "tesla_clkdm",
 653         .mpu_irqs       = omap44xx_dsp_irqs,
 654         .rst_lines      = omap44xx_dsp_resets,
 655         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 656         .main_clk       = "dsp_fck",
 657         .prcm = {
 658                 .omap4 = {
 659                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 660                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 661                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 662                         .modulemode   = MODULEMODE_HWCTRL,
 663                 },
 664         },
 665 };
 666
 667 /*
 668  * 'dss' class
 669  * display sub-system
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 673         .rev_offs       = 0x0000,
 674         .syss_offs      = 0x0014,
 675         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 676 };
 677
 678 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 679         .name   = "dss",
 680         .sysc   = &omap44xx_dss_sysc,
 681         .reset  = omap_dss_reset,
 682 };
 683
 684 /* dss */
 685 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 686         { .role = "sys_clk", .clk = "dss_sys_clk" },
 687         { .role = "tv_clk", .clk = "dss_tv_clk" },
 688         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 689 };
 690
 691 static struct omap_hwmod omap44xx_dss_hwmod = {
 692         .name           = "dss_core",
 693         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 694         .class          = &omap44xx_dss_hwmod_class,
 695         .clkdm_name     = "l3_dss_clkdm",
 696         .main_clk       = "dss_dss_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 705 };
 706
 707 /*
 708  * 'dispc' class
 709  * display controller
 710  */
 711
 712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 713         .rev_offs       = 0x0000,
 714         .sysc_offs      = 0x0010,
 715         .syss_offs      = 0x0014,
 716         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 717                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 719                            SYSS_HAS_RESET_STATUS),
 720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 721                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 722         .sysc_fields    = &omap_hwmod_sysc_type1,
 723 };
 724
 725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 726         .name   = "dispc",
 727         .sysc   = &omap44xx_dispc_sysc,
 728 };
 729
 730 /* dss_dispc */
 731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 732         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 733         { .irq = -1 }
 734 };
 735
 736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 737         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 738         { .dma_req = -1 }
 739 };
 740
 741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 742         .manager_count          = 3,
 743         .has_framedonetv_irq    = 1
 744 };
 745
 746 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 747         .name           = "dss_dispc",
 748         .class          = &omap44xx_dispc_hwmod_class,
 749         .clkdm_name     = "l3_dss_clkdm",
 750         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 751         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 752         .main_clk       = "dss_dss_clk",
 753         .prcm = {
 754                 .omap4 = {
 755                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 756                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 757                 },
 758         },
 759         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 760 };
 761
 762 /*
 763  * 'dsi' class
 764  * display serial interface controller
 765  */
 766
 767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 768         .rev_offs       = 0x0000,
 769         .sysc_offs      = 0x0010,
 770         .syss_offs      = 0x0014,
 771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 772                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 773                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 775         .sysc_fields    = &omap_hwmod_sysc_type1,
 776 };
 777
 778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 779         .name   = "dsi",
 780         .sysc   = &omap44xx_dsi_sysc,
 781 };
 782
 783 /* dss_dsi1 */
 784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 785         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 786         { .irq = -1 }
 787 };
 788
 789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 790         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 791         { .dma_req = -1 }
 792 };
 793
 794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 795         { .role = "sys_clk", .clk = "dss_sys_clk" },
 796 };
 797
 798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 799         .name           = "dss_dsi1",
 800         .class          = &omap44xx_dsi_hwmod_class,
 801         .clkdm_name     = "l3_dss_clkdm",
 802         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 803         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 804         .main_clk       = "dss_dss_clk",
 805         .prcm = {
 806                 .omap4 = {
 807                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 808                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 809                 },
 810         },
 811         .opt_clks       = dss_dsi1_opt_clks,
 812         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 813 };
 814
 815 /* dss_dsi2 */
 816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 817         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 818         { .irq = -1 }
 819 };
 820
 821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 822         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 823         { .dma_req = -1 }
 824 };
 825
 826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 827         { .role = "sys_clk", .clk = "dss_sys_clk" },
 828 };
 829
 830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 831         .name           = "dss_dsi2",
 832         .class          = &omap44xx_dsi_hwmod_class,
 833         .clkdm_name     = "l3_dss_clkdm",
 834         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 835         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 836         .main_clk       = "dss_dss_clk",
 837         .prcm = {
 838                 .omap4 = {
 839                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 840                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 841                 },
 842         },
 843         .opt_clks       = dss_dsi2_opt_clks,
 844         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 845 };
 846
 847 /*
 848  * 'hdmi' class
 849  * hdmi controller
 850  */
 851
 852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 853         .rev_offs       = 0x0000,
 854         .sysc_offs      = 0x0010,
 855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 856                            SYSC_HAS_SOFTRESET),
 857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 858                            SIDLE_SMART_WKUP),
 859         .sysc_fields    = &omap_hwmod_sysc_type2,
 860 };
 861
 862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 863         .name   = "hdmi",
 864         .sysc   = &omap44xx_hdmi_sysc,
 865 };
 866
 867 /* dss_hdmi */
 868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 869         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 870         { .irq = -1 }
 871 };
 872
 873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 874         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 875         { .dma_req = -1 }
 876 };
 877
 878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 879         { .role = "sys_clk", .clk = "dss_sys_clk" },
 880 };
 881
 882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 883         .name           = "dss_hdmi",
 884         .class          = &omap44xx_hdmi_hwmod_class,
 885         .clkdm_name     = "l3_dss_clkdm",
 886         /*
 887          * HDMI audio requires to use no-idle mode. Hence,
 888          * set idle mode by software.
 889          */
 890         .flags          = HWMOD_SWSUP_SIDLE,
 891         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 892         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 893         .main_clk       = "dss_48mhz_clk",
 894         .prcm = {
 895                 .omap4 = {
 896                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 897                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 898                 },
 899         },
 900         .opt_clks       = dss_hdmi_opt_clks,
 901         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 902 };
 903
 904 /*
 905  * 'rfbi' class
 906  * remote frame buffer interface
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 910         .rev_offs       = 0x0000,
 911         .sysc_offs      = 0x0010,
 912         .syss_offs      = 0x0014,
 913         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 914                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 916         .sysc_fields    = &omap_hwmod_sysc_type1,
 917 };
 918
 919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 920         .name   = "rfbi",
 921         .sysc   = &omap44xx_rfbi_sysc,
 922 };
 923
 924 /* dss_rfbi */
 925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 926         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 927         { .dma_req = -1 }
 928 };
 929
 930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 931         { .role = "ick", .clk = "dss_fck" },
 932 };
 933
 934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 935         .name           = "dss_rfbi",
 936         .class          = &omap44xx_rfbi_hwmod_class,
 937         .clkdm_name     = "l3_dss_clkdm",
 938         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 939         .main_clk       = "dss_dss_clk",
 940         .prcm = {
 941                 .omap4 = {
 942                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 943                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 944                 },
 945         },
 946         .opt_clks       = dss_rfbi_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 948 };
 949
 950 /*
 951  * 'venc' class
 952  * video encoder
 953  */
 954
 955 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 956         .name   = "venc",
 957 };
 958
 959 /* dss_venc */
 960 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 961         .name           = "dss_venc",
 962         .class          = &omap44xx_venc_hwmod_class,
 963         .clkdm_name     = "l3_dss_clkdm",
 964         .main_clk       = "dss_tv_clk",
 965         .prcm = {
 966                 .omap4 = {
 967                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 968                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 969                 },
 970         },
 971 };
 972
 973 /*
 974  * 'elm' class
 975  * bch error location module
 976  */
 977
 978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 979         .rev_offs       = 0x0000,
 980         .sysc_offs      = 0x0010,
 981         .syss_offs      = 0x0014,
 982         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 983                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 984                            SYSS_HAS_RESET_STATUS),
 985         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 986         .sysc_fields    = &omap_hwmod_sysc_type1,
 987 };
 988
 989 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 990         .name   = "elm",
 991         .sysc   = &omap44xx_elm_sysc,
 992 };
 993
 994 /* elm */
 995 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 996         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 997         { .irq = -1 }
 998 };
 999
1000 static struct omap_hwmod omap44xx_elm_hwmod = {
1001         .name           = "elm",
1002         .class          = &omap44xx_elm_hwmod_class,
1003         .clkdm_name     = "l4_per_clkdm",
1004         .mpu_irqs       = omap44xx_elm_irqs,
1005         .prcm = {
1006                 .omap4 = {
1007                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1008                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1009                 },
1010         },
1011 };
1012
1013 /*
1014  * 'emif' class
1015  * external memory interface no1
1016  */
1017
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1019         .rev_offs       = 0x0000,
1020 };
1021
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1023         .name   = "emif",
1024         .sysc   = &omap44xx_emif_sysc,
1025 };
1026
1027 /* emif1 */
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1029         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030         { .irq = -1 }
1031 };
1032
1033 static struct omap_hwmod omap44xx_emif1_hwmod = {
1034         .name           = "emif1",
1035         .class          = &omap44xx_emif_hwmod_class,
1036         .clkdm_name     = "l3_emif_clkdm",
1037         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1038         .mpu_irqs       = omap44xx_emif1_irqs,
1039         .main_clk       = "ddrphy_ck",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1043                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_HWCTRL,
1045                 },
1046         },
1047 };
1048
1049 /* emif2 */
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1051         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052         { .irq = -1 }
1053 };
1054
1055 static struct omap_hwmod omap44xx_emif2_hwmod = {
1056         .name           = "emif2",
1057         .class          = &omap44xx_emif_hwmod_class,
1058         .clkdm_name     = "l3_emif_clkdm",
1059         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1060         .mpu_irqs       = omap44xx_emif2_irqs,
1061         .main_clk       = "ddrphy_ck",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_HWCTRL,
1067                 },
1068         },
1069 };
1070
1071 /*
1072  * 'fdif' class
1073  * face detection hw accelerator module
1074  */
1075
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1077         .rev_offs       = 0x0000,
1078         .sysc_offs      = 0x0010,
1079         /*
1080          * FDIF needs 100 OCP clk cycles delay after a softreset before
1081          * accessing sysconfig again.
1082          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1084          *
1085          * TODO: Indicate errata when available.
1086          */
1087         .srst_udelay    = 2,
1088         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1089                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1092         .sysc_fields    = &omap_hwmod_sysc_type2,
1093 };
1094
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1096         .name   = "fdif",
1097         .sysc   = &omap44xx_fdif_sysc,
1098 };
1099
1100 /* fdif */
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1102         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod omap44xx_fdif_hwmod = {
1107         .name           = "fdif",
1108         .class          = &omap44xx_fdif_hwmod_class,
1109         .clkdm_name     = "iss_clkdm",
1110         .mpu_irqs       = omap44xx_fdif_irqs,
1111         .main_clk       = "fdif_fck",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1115                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1116                         .modulemode   = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120
1121 /*
1122  * 'gpio' class
1123  * general purpose io module
1124  */
1125
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1127         .rev_offs       = 0x0000,
1128         .sysc_offs      = 0x0010,
1129         .syss_offs      = 0x0114,
1130         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1131                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1132                            SYSS_HAS_RESET_STATUS),
1133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1134                            SIDLE_SMART_WKUP),
1135         .sysc_fields    = &omap_hwmod_sysc_type1,
1136 };
1137
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1139         .name   = "gpio",
1140         .sysc   = &omap44xx_gpio_sysc,
1141         .rev    = 2,
1142 };
1143
1144 /* gpio dev_attr */
1145 static struct omap_gpio_dev_attr gpio_dev_attr = {
1146         .bank_width     = 32,
1147         .dbck_flag      = true,
1148 };
1149
1150 /* gpio1 */
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1152         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153         { .irq = -1 }
1154 };
1155
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1157         { .role = "dbclk", .clk = "gpio1_dbclk" },
1158 };
1159
1160 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161         .name           = "gpio1",
1162         .class          = &omap44xx_gpio_hwmod_class,
1163         .clkdm_name     = "l4_wkup_clkdm",
1164         .mpu_irqs       = omap44xx_gpio1_irqs,
1165         .main_clk       = "gpio1_ick",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1169                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1170                         .modulemode   = MODULEMODE_HWCTRL,
1171                 },
1172         },
1173         .opt_clks       = gpio1_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1175         .dev_attr       = &gpio_dev_attr,
1176 };
1177
1178 /* gpio2 */
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1180         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181         { .irq = -1 }
1182 };
1183
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio2_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1189         .name           = "gpio2",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .mpu_irqs       = omap44xx_gpio2_irqs,
1194         .main_clk       = "gpio2_ick",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1198                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_HWCTRL,
1200                 },
1201         },
1202         .opt_clks       = gpio2_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1204         .dev_attr       = &gpio_dev_attr,
1205 };
1206
1207 /* gpio3 */
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1209         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210         { .irq = -1 }
1211 };
1212
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1214         { .role = "dbclk", .clk = "gpio3_dbclk" },
1215 };
1216
1217 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1218         .name           = "gpio3",
1219         .class          = &omap44xx_gpio_hwmod_class,
1220         .clkdm_name     = "l4_per_clkdm",
1221         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222         .mpu_irqs       = omap44xx_gpio3_irqs,
1223         .main_clk       = "gpio3_ick",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_HWCTRL,
1229                 },
1230         },
1231         .opt_clks       = gpio3_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1233         .dev_attr       = &gpio_dev_attr,
1234 };
1235
1236 /* gpio4 */
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1238         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239         { .irq = -1 }
1240 };
1241
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1243         { .role = "dbclk", .clk = "gpio4_dbclk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1247         .name           = "gpio4",
1248         .class          = &omap44xx_gpio_hwmod_class,
1249         .clkdm_name     = "l4_per_clkdm",
1250         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251         .mpu_irqs       = omap44xx_gpio4_irqs,
1252         .main_clk       = "gpio4_ick",
1253         .prcm = {
1254                 .omap4 = {
1255                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1256                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1257                         .modulemode   = MODULEMODE_HWCTRL,
1258                 },
1259         },
1260         .opt_clks       = gpio4_opt_clks,
1261         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1262         .dev_attr       = &gpio_dev_attr,
1263 };
1264
1265 /* gpio5 */
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1267         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268         { .irq = -1 }
1269 };
1270
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1272         { .role = "dbclk", .clk = "gpio5_dbclk" },
1273 };
1274
1275 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1276         .name           = "gpio5",
1277         .class          = &omap44xx_gpio_hwmod_class,
1278         .clkdm_name     = "l4_per_clkdm",
1279         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280         .mpu_irqs       = omap44xx_gpio5_irqs,
1281         .main_clk       = "gpio5_ick",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_HWCTRL,
1287                 },
1288         },
1289         .opt_clks       = gpio5_opt_clks,
1290         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1291         .dev_attr       = &gpio_dev_attr,
1292 };
1293
1294 /* gpio6 */
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1296         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297         { .irq = -1 }
1298 };
1299
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1301         { .role = "dbclk", .clk = "gpio6_dbclk" },
1302 };
1303
1304 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1305         .name           = "gpio6",
1306         .class          = &omap44xx_gpio_hwmod_class,
1307         .clkdm_name     = "l4_per_clkdm",
1308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309         .mpu_irqs       = omap44xx_gpio6_irqs,
1310         .main_clk       = "gpio6_ick",
1311         .prcm = {
1312                 .omap4 = {
1313                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1314                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1315                         .modulemode   = MODULEMODE_HWCTRL,
1316                 },
1317         },
1318         .opt_clks       = gpio6_opt_clks,
1319         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1320         .dev_attr       = &gpio_dev_attr,
1321 };
1322
1323 /*
1324  * 'gpmc' class
1325  * general purpose memory controller
1326  */
1327
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1329         .rev_offs       = 0x0000,
1330         .sysc_offs      = 0x0010,
1331         .syss_offs      = 0x0014,
1332         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1333                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1335         .sysc_fields    = &omap_hwmod_sysc_type1,
1336 };
1337
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1339         .name   = "gpmc",
1340         .sysc   = &omap44xx_gpmc_sysc,
1341 };
1342
1343 /* gpmc */
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1345         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346         { .irq = -1 }
1347 };
1348
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1350         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351         { .dma_req = -1 }
1352 };
1353
1354 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355         .name           = "gpmc",
1356         .class          = &omap44xx_gpmc_hwmod_class,
1357         .clkdm_name     = "l3_2_clkdm",
1358         /*
1359          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360          * block.  It is not being added due to any known bugs with
1361          * resetting the GPMC IP block, but rather because any timings
1362          * set by the bootloader are not being correctly programmed by
1363          * the kernel from the board file or DT data.
1364          * HWMOD_INIT_NO_RESET should be removed ASAP.
1365          */
1366         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1367         .mpu_irqs       = omap44xx_gpmc_irqs,
1368         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1372                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1373                         .modulemode   = MODULEMODE_HWCTRL,
1374                 },
1375         },
1376 };
1377
1378 /*
1379  * 'gpu' class
1380  * 2d/3d graphics accelerator
1381  */
1382
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1384         .rev_offs       = 0x1fc00,
1385         .sysc_offs      = 0x1fc10,
1386         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1388                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1389                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1390         .sysc_fields    = &omap_hwmod_sysc_type2,
1391 };
1392
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1394         .name   = "gpu",
1395         .sysc   = &omap44xx_gpu_sysc,
1396 };
1397
1398 /* gpu */
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1400         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401         { .irq = -1 }
1402 };
1403
1404 static struct omap_hwmod omap44xx_gpu_hwmod = {
1405         .name           = "gpu",
1406         .class          = &omap44xx_gpu_hwmod_class,
1407         .clkdm_name     = "l3_gfx_clkdm",
1408         .mpu_irqs       = omap44xx_gpu_irqs,
1409         .main_clk       = "gpu_fck",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1414                         .modulemode   = MODULEMODE_SWCTRL,
1415                 },
1416         },
1417 };
1418
1419 /*
1420  * 'hdq1w' class
1421  * hdq / 1-wire serial interface controller
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0014,
1427         .syss_offs      = 0x0018,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1429                            SYSS_HAS_RESET_STATUS),
1430         .sysc_fields    = &omap_hwmod_sysc_type1,
1431 };
1432
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1434         .name   = "hdq1w",
1435         .sysc   = &omap44xx_hdq1w_sysc,
1436 };
1437
1438 /* hdq1w */
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1440         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441         { .irq = -1 }
1442 };
1443
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445         .name           = "hdq1w",
1446         .class          = &omap44xx_hdq1w_hwmod_class,
1447         .clkdm_name     = "l4_per_clkdm",
1448         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1449         .mpu_irqs       = omap44xx_hdq1w_irqs,
1450         .main_clk       = "hdq1w_fck",
1451         .prcm = {
1452                 .omap4 = {
1453                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1454                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1455                         .modulemode   = MODULEMODE_SWCTRL,
1456                 },
1457         },
1458 };
1459
1460 /*
1461  * 'hsi' class
1462  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463  * serial if)
1464  */
1465
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1467         .rev_offs       = 0x0000,
1468         .sysc_offs      = 0x0010,
1469         .syss_offs      = 0x0014,
1470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1471                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1472                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1474                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1475                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1476         .sysc_fields    = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1480         .name   = "hsi",
1481         .sysc   = &omap44xx_hsi_sysc,
1482 };
1483
1484 /* hsi */
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1486         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489         { .irq = -1 }
1490 };
1491
1492 static struct omap_hwmod omap44xx_hsi_hwmod = {
1493         .name           = "hsi",
1494         .class          = &omap44xx_hsi_hwmod_class,
1495         .clkdm_name     = "l3_init_clkdm",
1496         .mpu_irqs       = omap44xx_hsi_irqs,
1497         .main_clk       = "hsi_fck",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1501                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1502                         .modulemode   = MODULEMODE_HWCTRL,
1503                 },
1504         },
1505 };
1506
1507 /*
1508  * 'i2c' class
1509  * multimaster high-speed i2c controller
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1513         .sysc_offs      = 0x0010,
1514         .syss_offs      = 0x0090,
1515         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1516                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1517                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1518         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1519                            SIDLE_SMART_WKUP),
1520         .clockact       = CLOCKACT_TEST_ICLK,
1521         .sysc_fields    = &omap_hwmod_sysc_type1,
1522 };
1523
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1525         .name   = "i2c",
1526         .sysc   = &omap44xx_i2c_sysc,
1527         .rev    = OMAP_I2C_IP_VERSION_2,
1528         .reset  = &omap_i2c_reset,
1529 };
1530
1531 static struct omap_i2c_dev_attr i2c_dev_attr = {
1532         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1533                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1534 };
1535
1536 /* i2c1 */
1537 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1538         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1539         { .irq = -1 }
1540 };
1541
1542 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1543         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1544         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1545         { .dma_req = -1 }
1546 };
1547
1548 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1549         .name           = "i2c1",
1550         .class          = &omap44xx_i2c_hwmod_class,
1551         .clkdm_name     = "l4_per_clkdm",
1552         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1553         .mpu_irqs       = omap44xx_i2c1_irqs,
1554         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1555         .main_clk       = "i2c1_fck",
1556         .prcm = {
1557                 .omap4 = {
1558                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1559                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1560                         .modulemode   = MODULEMODE_SWCTRL,
1561                 },
1562         },
1563         .dev_attr       = &i2c_dev_attr,
1564 };
1565
1566 /* i2c2 */
1567 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1568         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1569         { .irq = -1 }
1570 };
1571
1572 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1573         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1574         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1575         { .dma_req = -1 }
1576 };
1577
1578 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1579         .name           = "i2c2",
1580         .class          = &omap44xx_i2c_hwmod_class,
1581         .clkdm_name     = "l4_per_clkdm",
1582         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1583         .mpu_irqs       = omap44xx_i2c2_irqs,
1584         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1585         .main_clk       = "i2c2_fck",
1586         .prcm = {
1587                 .omap4 = {
1588                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1589                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1590                         .modulemode   = MODULEMODE_SWCTRL,
1591                 },
1592         },
1593         .dev_attr       = &i2c_dev_attr,
1594 };
1595
1596 /* i2c3 */
1597 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1598         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1599         { .irq = -1 }
1600 };
1601
1602 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1603         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1604         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1605         { .dma_req = -1 }
1606 };
1607
1608 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1609         .name           = "i2c3",
1610         .class          = &omap44xx_i2c_hwmod_class,
1611         .clkdm_name     = "l4_per_clkdm",
1612         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1613         .mpu_irqs       = omap44xx_i2c3_irqs,
1614         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1615         .main_clk       = "i2c3_fck",
1616         .prcm = {
1617                 .omap4 = {
1618                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1619                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1620                         .modulemode   = MODULEMODE_SWCTRL,
1621                 },
1622         },
1623         .dev_attr       = &i2c_dev_attr,
1624 };
1625
1626 /* i2c4 */
1627 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1628         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1629         { .irq = -1 }
1630 };
1631
1632 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1633         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1634         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1635         { .dma_req = -1 }
1636 };
1637
1638 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1639         .name           = "i2c4",
1640         .class          = &omap44xx_i2c_hwmod_class,
1641         .clkdm_name     = "l4_per_clkdm",
1642         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1643         .mpu_irqs       = omap44xx_i2c4_irqs,
1644         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1645         .main_clk       = "i2c4_fck",
1646         .prcm = {
1647                 .omap4 = {
1648                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1649                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1650                         .modulemode   = MODULEMODE_SWCTRL,
1651                 },
1652         },
1653         .dev_attr       = &i2c_dev_attr,
1654 };
1655
1656 /*
1657  * 'ipu' class
1658  * imaging processor unit
1659  */
1660
1661 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1662         .name   = "ipu",
1663 };
1664
1665 /* ipu */
1666 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1667         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1668         { .irq = -1 }
1669 };
1670
1671 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1672         { .name = "cpu0", .rst_shift = 0 },
1673         { .name = "cpu1", .rst_shift = 1 },
1674 };
1675
1676 static struct omap_hwmod omap44xx_ipu_hwmod = {
1677         .name           = "ipu",
1678         .class          = &omap44xx_ipu_hwmod_class,
1679         .clkdm_name     = "ducati_clkdm",
1680         .mpu_irqs       = omap44xx_ipu_irqs,
1681         .rst_lines      = omap44xx_ipu_resets,
1682         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1683         .main_clk       = "ipu_fck",
1684         .prcm = {
1685                 .omap4 = {
1686                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1687                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1688                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1689                         .modulemode   = MODULEMODE_HWCTRL,
1690                 },
1691         },
1692 };
1693
1694 /*
1695  * 'iss' class
1696  * external images sensor pixel data processor
1697  */
1698
1699 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1700         .rev_offs       = 0x0000,
1701         .sysc_offs      = 0x0010,
1702         /*
1703          * ISS needs 100 OCP clk cycles delay after a softreset before
1704          * accessing sysconfig again.
1705          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1706          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1707          *
1708          * TODO: Indicate errata when available.
1709          */
1710         .srst_udelay    = 2,
1711         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1712                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1713         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1714                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1715                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1716         .sysc_fields    = &omap_hwmod_sysc_type2,
1717 };
1718
1719 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1720         .name   = "iss",
1721         .sysc   = &omap44xx_iss_sysc,
1722 };
1723
1724 /* iss */
1725 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1726         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1727         { .irq = -1 }
1728 };
1729
1730 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1731         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1732         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1733         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1734         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1735         { .dma_req = -1 }
1736 };
1737
1738 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1739         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1740 };
1741
1742 static struct omap_hwmod omap44xx_iss_hwmod = {
1743         .name           = "iss",
1744         .class          = &omap44xx_iss_hwmod_class,
1745         .clkdm_name     = "iss_clkdm",
1746         .mpu_irqs       = omap44xx_iss_irqs,
1747         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1748         .main_clk       = "iss_fck",
1749         .prcm = {
1750                 .omap4 = {
1751                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1752                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1753                         .modulemode   = MODULEMODE_SWCTRL,
1754                 },
1755         },
1756         .opt_clks       = iss_opt_clks,
1757         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1758 };
1759
1760 /*
1761  * 'iva' class
1762  * multi-standard video encoder/decoder hardware accelerator
1763  */
1764
1765 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1766         .name   = "iva",
1767 };
1768
1769 /* iva */
1770 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1771         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1773         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1774         { .irq = -1 }
1775 };
1776
1777 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1778         { .name = "seq0", .rst_shift = 0 },
1779         { .name = "seq1", .rst_shift = 1 },
1780         { .name = "logic", .rst_shift = 2 },
1781 };
1782
1783 static struct omap_hwmod omap44xx_iva_hwmod = {
1784         .name           = "iva",
1785         .class          = &omap44xx_iva_hwmod_class,
1786         .clkdm_name     = "ivahd_clkdm",
1787         .mpu_irqs       = omap44xx_iva_irqs,
1788         .rst_lines      = omap44xx_iva_resets,
1789         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1790         .main_clk       = "iva_fck",
1791         .prcm = {
1792                 .omap4 = {
1793                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1794                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1795                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1796                         .modulemode   = MODULEMODE_HWCTRL,
1797                 },
1798         },
1799 };
1800
1801 /*
1802  * 'kbd' class
1803  * keyboard controller
1804  */
1805
1806 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1807         .rev_offs       = 0x0000,
1808         .sysc_offs      = 0x0010,
1809         .syss_offs      = 0x0014,
1810         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1811                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1812                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1813                            SYSS_HAS_RESET_STATUS),
1814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1815         .sysc_fields    = &omap_hwmod_sysc_type1,
1816 };
1817
1818 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1819         .name   = "kbd",
1820         .sysc   = &omap44xx_kbd_sysc,
1821 };
1822
1823 /* kbd */
1824 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1825         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1826         { .irq = -1 }
1827 };
1828
1829 static struct omap_hwmod omap44xx_kbd_hwmod = {
1830         .name           = "kbd",
1831         .class          = &omap44xx_kbd_hwmod_class,
1832         .clkdm_name     = "l4_wkup_clkdm",
1833         .mpu_irqs       = omap44xx_kbd_irqs,
1834         .main_clk       = "kbd_fck",
1835         .prcm = {
1836                 .omap4 = {
1837                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1838                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1839                         .modulemode   = MODULEMODE_SWCTRL,
1840                 },
1841         },
1842 };
1843
1844 /*
1845  * 'mailbox' class
1846  * mailbox module allowing communication between the on-chip processors using a
1847  * queued mailbox-interrupt mechanism.
1848  */
1849
1850 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1851         .rev_offs       = 0x0000,
1852         .sysc_offs      = 0x0010,
1853         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1854                            SYSC_HAS_SOFTRESET),
1855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1856         .sysc_fields    = &omap_hwmod_sysc_type2,
1857 };
1858
1859 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1860         .name   = "mailbox",
1861         .sysc   = &omap44xx_mailbox_sysc,
1862 };
1863
1864 /* mailbox */
1865 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1866         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1867         { .irq = -1 }
1868 };
1869
1870 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1871         .name           = "mailbox",
1872         .class          = &omap44xx_mailbox_hwmod_class,
1873         .clkdm_name     = "l4_cfg_clkdm",
1874         .mpu_irqs       = omap44xx_mailbox_irqs,
1875         .prcm = {
1876                 .omap4 = {
1877                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1878                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1879                 },
1880         },
1881 };
1882
1883 /*
1884  * 'mcasp' class
1885  * multi-channel audio serial port controller
1886  */
1887
1888 /* The IP is not compliant to type1 / type2 scheme */
1889 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1890         .sidle_shift    = 0,
1891 };
1892
1893 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1894         .sysc_offs      = 0x0004,
1895         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1896         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1897                            SIDLE_SMART_WKUP),
1898         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1899 };
1900
1901 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1902         .name   = "mcasp",
1903         .sysc   = &omap44xx_mcasp_sysc,
1904 };
1905
1906 /* mcasp */
1907 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1908         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1909         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1910         { .irq = -1 }
1911 };
1912
1913 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1914         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1915         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1916         { .dma_req = -1 }
1917 };
1918
1919 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1920         .name           = "mcasp",
1921         .class          = &omap44xx_mcasp_hwmod_class,
1922         .clkdm_name     = "abe_clkdm",
1923         .mpu_irqs       = omap44xx_mcasp_irqs,
1924         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1925         .main_clk       = "mcasp_fck",
1926         .prcm = {
1927                 .omap4 = {
1928                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1929                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1930                         .modulemode   = MODULEMODE_SWCTRL,
1931                 },
1932         },
1933 };
1934
1935 /*
1936  * 'mcbsp' class
1937  * multi channel buffered serial port controller
1938  */
1939
1940 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1941         .sysc_offs      = 0x008c,
1942         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1943                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1944         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1945         .sysc_fields    = &omap_hwmod_sysc_type1,
1946 };
1947
1948 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1949         .name   = "mcbsp",
1950         .sysc   = &omap44xx_mcbsp_sysc,
1951         .rev    = MCBSP_CONFIG_TYPE4,
1952 };
1953
1954 /* mcbsp1 */
1955 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1956         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1957         { .irq = -1 }
1958 };
1959
1960 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1961         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1962         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1963         { .dma_req = -1 }
1964 };
1965
1966 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1967         { .role = "pad_fck", .clk = "pad_clks_ck" },
1968         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1969 };
1970
1971 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1972         .name           = "mcbsp1",
1973         .class          = &omap44xx_mcbsp_hwmod_class,
1974         .clkdm_name     = "abe_clkdm",
1975         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1976         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1977         .main_clk       = "mcbsp1_fck",
1978         .prcm = {
1979                 .omap4 = {
1980                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1981                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1982                         .modulemode   = MODULEMODE_SWCTRL,
1983                 },
1984         },
1985         .opt_clks       = mcbsp1_opt_clks,
1986         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1987 };
1988
1989 /* mcbsp2 */
1990 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1991         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1992         { .irq = -1 }
1993 };
1994
1995 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1996         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1997         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1998         { .dma_req = -1 }
1999 };
2000
2001 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2002         { .role = "pad_fck", .clk = "pad_clks_ck" },
2003         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2004 };
2005
2006 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2007         .name           = "mcbsp2",
2008         .class          = &omap44xx_mcbsp_hwmod_class,
2009         .clkdm_name     = "abe_clkdm",
2010         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2011         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2012         .main_clk       = "mcbsp2_fck",
2013         .prcm = {
2014                 .omap4 = {
2015                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2016                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2017                         .modulemode   = MODULEMODE_SWCTRL,
2018                 },
2019         },
2020         .opt_clks       = mcbsp2_opt_clks,
2021         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2022 };
2023
2024 /* mcbsp3 */
2025 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2026         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2027         { .irq = -1 }
2028 };
2029
2030 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2031         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2032         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2033         { .dma_req = -1 }
2034 };
2035
2036 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2037         { .role = "pad_fck", .clk = "pad_clks_ck" },
2038         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2039 };
2040
2041 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2042         .name           = "mcbsp3",
2043         .class          = &omap44xx_mcbsp_hwmod_class,
2044         .clkdm_name     = "abe_clkdm",
2045         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2046         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2047         .main_clk       = "mcbsp3_fck",
2048         .prcm = {
2049                 .omap4 = {
2050                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2051                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2052                         .modulemode   = MODULEMODE_SWCTRL,
2053                 },
2054         },
2055         .opt_clks       = mcbsp3_opt_clks,
2056         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2057 };
2058
2059 /* mcbsp4 */
2060 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2061         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2062         { .irq = -1 }
2063 };
2064
2065 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2066         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2067         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2068         { .dma_req = -1 }
2069 };
2070
2071 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2072         { .role = "pad_fck", .clk = "pad_clks_ck" },
2073         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2074 };
2075
2076 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2077         .name           = "mcbsp4",
2078         .class          = &omap44xx_mcbsp_hwmod_class,
2079         .clkdm_name     = "l4_per_clkdm",
2080         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2081         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2082         .main_clk       = "mcbsp4_fck",
2083         .prcm = {
2084                 .omap4 = {
2085                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2086                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2087                         .modulemode   = MODULEMODE_SWCTRL,
2088                 },
2089         },
2090         .opt_clks       = mcbsp4_opt_clks,
2091         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2092 };
2093
2094 /*
2095  * 'mcpdm' class
2096  * multi channel pdm controller (proprietary interface with phoenix power
2097  * ic)
2098  */
2099
2100 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2101         .rev_offs       = 0x0000,
2102         .sysc_offs      = 0x0010,
2103         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2104                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2106                            SIDLE_SMART_WKUP),
2107         .sysc_fields    = &omap_hwmod_sysc_type2,
2108 };
2109
2110 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2111         .name   = "mcpdm",
2112         .sysc   = &omap44xx_mcpdm_sysc,
2113 };
2114
2115 /* mcpdm */
2116 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2117         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2118         { .irq = -1 }
2119 };
2120
2121 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2122         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2123         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2124         { .dma_req = -1 }
2125 };
2126
2127 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2128         .name           = "mcpdm",
2129         .class          = &omap44xx_mcpdm_hwmod_class,
2130         .clkdm_name     = "abe_clkdm",
2131         .mpu_irqs       = omap44xx_mcpdm_irqs,
2132         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2133         .main_clk       = "mcpdm_fck",
2134         .prcm = {
2135                 .omap4 = {
2136                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2137                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2138                         .modulemode   = MODULEMODE_SWCTRL,
2139                 },
2140         },
2141 };
2142
2143 /*
2144  * 'mcspi' class
2145  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2146  * bus
2147  */
2148
2149 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2150         .rev_offs       = 0x0000,
2151         .sysc_offs      = 0x0010,
2152         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2153                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2154         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2155                            SIDLE_SMART_WKUP),
2156         .sysc_fields    = &omap_hwmod_sysc_type2,
2157 };
2158
2159 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2160         .name   = "mcspi",
2161         .sysc   = &omap44xx_mcspi_sysc,
2162         .rev    = OMAP4_MCSPI_REV,
2163 };
2164
2165 /* mcspi1 */
2166 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2167         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2168         { .irq = -1 }
2169 };
2170
2171 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2172         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2173         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2174         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2175         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2176         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2177         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2178         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2179         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2180         { .dma_req = -1 }
2181 };
2182
2183 /* mcspi1 dev_attr */
2184 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2185         .num_chipselect = 4,
2186 };
2187
2188 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2189         .name           = "mcspi1",
2190         .class          = &omap44xx_mcspi_hwmod_class,
2191         .clkdm_name     = "l4_per_clkdm",
2192         .mpu_irqs       = omap44xx_mcspi1_irqs,
2193         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2194         .main_clk       = "mcspi1_fck",
2195         .prcm = {
2196                 .omap4 = {
2197                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2198                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2199                         .modulemode   = MODULEMODE_SWCTRL,
2200                 },
2201         },
2202         .dev_attr       = &mcspi1_dev_attr,
2203 };
2204
2205 /* mcspi2 */
2206 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2207         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2208         { .irq = -1 }
2209 };
2210
2211 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2212         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2213         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2214         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2215         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2216         { .dma_req = -1 }
2217 };
2218
2219 /* mcspi2 dev_attr */
2220 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2221         .num_chipselect = 2,
2222 };
2223
2224 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2225         .name           = "mcspi2",
2226         .class          = &omap44xx_mcspi_hwmod_class,
2227         .clkdm_name     = "l4_per_clkdm",
2228         .mpu_irqs       = omap44xx_mcspi2_irqs,
2229         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2230         .main_clk       = "mcspi2_fck",
2231         .prcm = {
2232                 .omap4 = {
2233                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2234                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2235                         .modulemode   = MODULEMODE_SWCTRL,
2236                 },
2237         },
2238         .dev_attr       = &mcspi2_dev_attr,
2239 };
2240
2241 /* mcspi3 */
2242 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2243         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2244         { .irq = -1 }
2245 };
2246
2247 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2248         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2249         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2250         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2251         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2252         { .dma_req = -1 }
2253 };
2254
2255 /* mcspi3 dev_attr */
2256 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2257         .num_chipselect = 2,
2258 };
2259
2260 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2261         .name           = "mcspi3",
2262         .class          = &omap44xx_mcspi_hwmod_class,
2263         .clkdm_name     = "l4_per_clkdm",
2264         .mpu_irqs       = omap44xx_mcspi3_irqs,
2265         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2266         .main_clk       = "mcspi3_fck",
2267         .prcm = {
2268                 .omap4 = {
2269                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2270                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2271                         .modulemode   = MODULEMODE_SWCTRL,
2272                 },
2273         },
2274         .dev_attr       = &mcspi3_dev_attr,
2275 };
2276
2277 /* mcspi4 */
2278 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2279         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2280         { .irq = -1 }
2281 };
2282
2283 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2284         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2285         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2286         { .dma_req = -1 }
2287 };
2288
2289 /* mcspi4 dev_attr */
2290 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2291         .num_chipselect = 1,
2292 };
2293
2294 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2295         .name           = "mcspi4",
2296         .class          = &omap44xx_mcspi_hwmod_class,
2297         .clkdm_name     = "l4_per_clkdm",
2298         .mpu_irqs       = omap44xx_mcspi4_irqs,
2299         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2300         .main_clk       = "mcspi4_fck",
2301         .prcm = {
2302                 .omap4 = {
2303                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2304                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2305                         .modulemode   = MODULEMODE_SWCTRL,
2306                 },
2307         },
2308         .dev_attr       = &mcspi4_dev_attr,
2309 };
2310
2311 /*
2312  * 'mmc' class
2313  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2314  */
2315
2316 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2317         .rev_offs       = 0x0000,
2318         .sysc_offs      = 0x0010,
2319         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2320                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2321                            SYSC_HAS_SOFTRESET),
2322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2323                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2324                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2325         .sysc_fields    = &omap_hwmod_sysc_type2,
2326 };
2327
2328 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2329         .name   = "mmc",
2330         .sysc   = &omap44xx_mmc_sysc,
2331 };
2332
2333 /* mmc1 */
2334 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2335         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2336         { .irq = -1 }
2337 };
2338
2339 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2340         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2341         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2342         { .dma_req = -1 }
2343 };
2344
2345 /* mmc1 dev_attr */
2346 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2347         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2348 };
2349
2350 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2351         .name           = "mmc1",
2352         .class          = &omap44xx_mmc_hwmod_class,
2353         .clkdm_name     = "l3_init_clkdm",
2354         .mpu_irqs       = omap44xx_mmc1_irqs,
2355         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2356         .main_clk       = "mmc1_fck",
2357         .prcm = {
2358                 .omap4 = {
2359                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2360                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2361                         .modulemode   = MODULEMODE_SWCTRL,
2362                 },
2363         },
2364         .dev_attr       = &mmc1_dev_attr,
2365 };
2366
2367 /* mmc2 */
2368 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2369         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2370         { .irq = -1 }
2371 };
2372
2373 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2374         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2375         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2376         { .dma_req = -1 }
2377 };
2378
2379 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2380         .name           = "mmc2",
2381         .class          = &omap44xx_mmc_hwmod_class,
2382         .clkdm_name     = "l3_init_clkdm",
2383         .mpu_irqs       = omap44xx_mmc2_irqs,
2384         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2385         .main_clk       = "mmc2_fck",
2386         .prcm = {
2387                 .omap4 = {
2388                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2389                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2390                         .modulemode   = MODULEMODE_SWCTRL,
2391                 },
2392         },
2393 };
2394
2395 /* mmc3 */
2396 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2397         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2398         { .irq = -1 }
2399 };
2400
2401 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2402         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2403         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2404         { .dma_req = -1 }
2405 };
2406
2407 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2408         .name           = "mmc3",
2409         .class          = &omap44xx_mmc_hwmod_class,
2410         .clkdm_name     = "l4_per_clkdm",
2411         .mpu_irqs       = omap44xx_mmc3_irqs,
2412         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2413         .main_clk       = "mmc3_fck",
2414         .prcm = {
2415                 .omap4 = {
2416                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2417                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2418                         .modulemode   = MODULEMODE_SWCTRL,
2419                 },
2420         },
2421 };
2422
2423 /* mmc4 */
2424 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2425         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2426         { .irq = -1 }
2427 };
2428
2429 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2430         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2431         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2432         { .dma_req = -1 }
2433 };
2434
2435 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2436         .name           = "mmc4",
2437         .class          = &omap44xx_mmc_hwmod_class,
2438         .clkdm_name     = "l4_per_clkdm",
2439         .mpu_irqs       = omap44xx_mmc4_irqs,
2440         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2441         .main_clk       = "mmc4_fck",
2442         .prcm = {
2443                 .omap4 = {
2444                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2445                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2446                         .modulemode   = MODULEMODE_SWCTRL,
2447                 },
2448         },
2449 };
2450
2451 /* mmc5 */
2452 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2453         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2454         { .irq = -1 }
2455 };
2456
2457 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2458         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2459         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2460         { .dma_req = -1 }
2461 };
2462
2463 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2464         .name           = "mmc5",
2465         .class          = &omap44xx_mmc_hwmod_class,
2466         .clkdm_name     = "l4_per_clkdm",
2467         .mpu_irqs       = omap44xx_mmc5_irqs,
2468         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2469         .main_clk       = "mmc5_fck",
2470         .prcm = {
2471                 .omap4 = {
2472                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2473                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2474                         .modulemode   = MODULEMODE_SWCTRL,
2475                 },
2476         },
2477 };
2478
2479 /*
2480  * 'mmu' class
2481  * The memory management unit performs virtual to physical address translation
2482  * for its requestors.
2483  */
2484
2485 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2486         .rev_offs       = 0x000,
2487         .sysc_offs      = 0x010,
2488         .syss_offs      = 0x014,
2489         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2490                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2491         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2492         .sysc_fields    = &omap_hwmod_sysc_type1,
2493 };
2494
2495 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2496         .name = "mmu",
2497         .sysc = &mmu_sysc,
2498 };
2499
2500 /* mmu ipu */
2501
2502 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2503         .da_start       = 0x0,
2504         .da_end         = 0xfffff000,
2505         .nr_tlb_entries = 32,
2506 };
2507
2508 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2509 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2510         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2511         { .irq = -1 }
2512 };
2513
2514 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2515         { .name = "mmu_cache", .rst_shift = 2 },
2516 };
2517
2518 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2519         {
2520                 .pa_start       = 0x55082000,
2521                 .pa_end         = 0x550820ff,
2522                 .flags          = ADDR_TYPE_RT,
2523         },
2524         { }
2525 };
2526
2527 /* l3_main_2 -> mmu_ipu */
2528 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2529         .master         = &omap44xx_l3_main_2_hwmod,
2530         .slave          = &omap44xx_mmu_ipu_hwmod,
2531         .clk            = "l3_div_ck",
2532         .addr           = omap44xx_mmu_ipu_addrs,
2533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2535
2536 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2537         .name           = "mmu_ipu",
2538         .class          = &omap44xx_mmu_hwmod_class,
2539         .clkdm_name     = "ducati_clkdm",
2540         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2541         .rst_lines      = omap44xx_mmu_ipu_resets,
2542         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2543         .main_clk       = "ducati_clk_mux_ck",
2544         .prcm = {
2545                 .omap4 = {
2546                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2547                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2548                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2549                         .modulemode   = MODULEMODE_HWCTRL,
2550                 },
2551         },
2552         .dev_attr       = &mmu_ipu_dev_attr,
2553 };
2554
2555 /* mmu dsp */
2556
2557 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2558         .da_start       = 0x0,
2559         .da_end         = 0xfffff000,
2560         .nr_tlb_entries = 32,
2561 };
2562
2563 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2564 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2565         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2566         { .irq = -1 }
2567 };
2568
2569 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2570         { .name = "mmu_cache", .rst_shift = 1 },
2571 };
2572
2573 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2574         {
2575                 .pa_start       = 0x4a066000,
2576                 .pa_end         = 0x4a0660ff,
2577                 .flags          = ADDR_TYPE_RT,
2578         },
2579         { }
2580 };
2581
2582 /* l4_cfg -> dsp */
2583 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2584         .master         = &omap44xx_l4_cfg_hwmod,
2585         .slave          = &omap44xx_mmu_dsp_hwmod,
2586         .clk            = "l4_div_ck",
2587         .addr           = omap44xx_mmu_dsp_addrs,
2588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2592         .name           = "mmu_dsp",
2593         .class          = &omap44xx_mmu_hwmod_class,
2594         .clkdm_name     = "tesla_clkdm",
2595         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2596         .rst_lines      = omap44xx_mmu_dsp_resets,
2597         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2598         .main_clk       = "dpll_iva_m4x2_ck",
2599         .prcm = {
2600                 .omap4 = {
2601                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2602                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2603                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2604                         .modulemode   = MODULEMODE_HWCTRL,
2605                 },
2606         },
2607         .dev_attr       = &mmu_dsp_dev_attr,
2608 };
2609
2610 /*
2611  * 'mpu' class
2612  * mpu sub-system
2613  */
2614
2615 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2616         .name   = "mpu",
2617 };
2618
2619 /* mpu */
2620 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2621         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2622         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2623         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2624         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2625         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2626         { .irq = -1 }
2627 };
2628
2629 static struct omap_hwmod omap44xx_mpu_hwmod = {
2630         .name           = "mpu",
2631         .class          = &omap44xx_mpu_hwmod_class,
2632         .clkdm_name     = "mpuss_clkdm",
2633         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2634         .mpu_irqs       = omap44xx_mpu_irqs,
2635         .main_clk       = "dpll_mpu_m2_ck",
2636         .prcm = {
2637                 .omap4 = {
2638                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2639                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2640                 },
2641         },
2642 };
2643
2644 /*
2645  * 'ocmc_ram' class
2646  * top-level core on-chip ram
2647  */
2648
2649 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2650         .name   = "ocmc_ram",
2651 };
2652
2653 /* ocmc_ram */
2654 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2655         .name           = "ocmc_ram",
2656         .class          = &omap44xx_ocmc_ram_hwmod_class,
2657         .clkdm_name     = "l3_2_clkdm",
2658         .prcm = {
2659                 .omap4 = {
2660                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2661                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2662                 },
2663         },
2664 };
2665
2666 /*
2667  * 'ocp2scp' class
2668  * bridge to transform ocp interface protocol to scp (serial control port)
2669  * protocol
2670  */
2671
2672 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2673         .rev_offs       = 0x0000,
2674         .sysc_offs      = 0x0010,
2675         .syss_offs      = 0x0014,
2676         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2677                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2678         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2679         .sysc_fields    = &omap_hwmod_sysc_type1,
2680 };
2681
2682 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2683         .name   = "ocp2scp",
2684         .sysc   = &omap44xx_ocp2scp_sysc,
2685 };
2686
2687 /* ocp2scp_usb_phy */
2688 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2689         .name           = "ocp2scp_usb_phy",
2690         .class          = &omap44xx_ocp2scp_hwmod_class,
2691         .clkdm_name     = "l3_init_clkdm",
2692         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2693         .prcm = {
2694                 .omap4 = {
2695                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2696                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2697                         .modulemode   = MODULEMODE_HWCTRL,
2698                 },
2699         },
2700 };
2701
2702 /*
2703  * 'prcm' class
2704  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2705  * + clock manager 1 (in always on power domain) + local prm in mpu
2706  */
2707
2708 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2709         .name   = "prcm",
2710 };
2711
2712 /* prcm_mpu */
2713 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2714         .name           = "prcm_mpu",
2715         .class          = &omap44xx_prcm_hwmod_class,
2716         .clkdm_name     = "l4_wkup_clkdm",
2717         .flags          = HWMOD_NO_IDLEST,
2718         .prcm = {
2719                 .omap4 = {
2720                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2721                 },
2722         },
2723 };
2724
2725 /* cm_core_aon */
2726 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2727         .name           = "cm_core_aon",
2728         .class          = &omap44xx_prcm_hwmod_class,
2729         .flags          = HWMOD_NO_IDLEST,
2730         .prcm = {
2731                 .omap4 = {
2732                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2733                 },
2734         },
2735 };
2736
2737 /* cm_core */
2738 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2739         .name           = "cm_core",
2740         .class          = &omap44xx_prcm_hwmod_class,
2741         .flags          = HWMOD_NO_IDLEST,
2742         .prcm = {
2743                 .omap4 = {
2744                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2745                 },
2746         },
2747 };
2748
2749 /* prm */
2750 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2751         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2752         { .irq = -1 }
2753 };
2754
2755 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2756         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2757         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2758 };
2759
2760 static struct omap_hwmod omap44xx_prm_hwmod = {
2761         .name           = "prm",
2762         .class          = &omap44xx_prcm_hwmod_class,
2763         .mpu_irqs       = omap44xx_prm_irqs,
2764         .rst_lines      = omap44xx_prm_resets,
2765         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2766 };
2767
2768 /*
2769  * 'scrm' class
2770  * system clock and reset manager
2771  */
2772
2773 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2774         .name   = "scrm",
2775 };
2776
2777 /* scrm */
2778 static struct omap_hwmod omap44xx_scrm_hwmod = {
2779         .name           = "scrm",
2780         .class          = &omap44xx_scrm_hwmod_class,
2781         .clkdm_name     = "l4_wkup_clkdm",
2782         .prcm = {
2783                 .omap4 = {
2784                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2785                 },
2786         },
2787 };
2788
2789 /*
2790  * 'sl2if' class
2791  * shared level 2 memory interface
2792  */
2793
2794 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2795         .name   = "sl2if",
2796 };
2797
2798 /* sl2if */
2799 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2800         .name           = "sl2if",
2801         .class          = &omap44xx_sl2if_hwmod_class,
2802         .clkdm_name     = "ivahd_clkdm",
2803         .prcm = {
2804                 .omap4 = {
2805                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2806                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2807                         .modulemode   = MODULEMODE_HWCTRL,
2808                 },
2809         },
2810 };
2811
2812 /*
2813  * 'slimbus' class
2814  * bidirectional, multi-drop, multi-channel two-line serial interface between
2815  * the device and external components
2816  */
2817
2818 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2819         .rev_offs       = 0x0000,
2820         .sysc_offs      = 0x0010,
2821         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2822                            SYSC_HAS_SOFTRESET),
2823         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2824                            SIDLE_SMART_WKUP),
2825         .sysc_fields    = &omap_hwmod_sysc_type2,
2826 };
2827
2828 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2829         .name   = "slimbus",
2830         .sysc   = &omap44xx_slimbus_sysc,
2831 };
2832
2833 /* slimbus1 */
2834 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2835         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2836         { .irq = -1 }
2837 };
2838
2839 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2840         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2841         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2842         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2843         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2844         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2845         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2846         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2847         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2848         { .dma_req = -1 }
2849 };
2850
2851 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2852         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2853         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2854         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2855         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2856 };
2857
2858 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2859         .name           = "slimbus1",
2860         .class          = &omap44xx_slimbus_hwmod_class,
2861         .clkdm_name     = "abe_clkdm",
2862         .mpu_irqs       = omap44xx_slimbus1_irqs,
2863         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2864         .prcm = {
2865                 .omap4 = {
2866                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2867                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2868                         .modulemode   = MODULEMODE_SWCTRL,
2869                 },
2870         },
2871         .opt_clks       = slimbus1_opt_clks,
2872         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2873 };
2874
2875 /* slimbus2 */
2876 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2877         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2878         { .irq = -1 }
2879 };
2880
2881 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2882         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2883         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2884         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2885         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2886         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2887         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2888         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2889         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2890         { .dma_req = -1 }
2891 };
2892
2893 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2894         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2895         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2896         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2897 };
2898
2899 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2900         .name           = "slimbus2",
2901         .class          = &omap44xx_slimbus_hwmod_class,
2902         .clkdm_name     = "l4_per_clkdm",
2903         .mpu_irqs       = omap44xx_slimbus2_irqs,
2904         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2905         .prcm = {
2906                 .omap4 = {
2907                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2908                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2909                         .modulemode   = MODULEMODE_SWCTRL,
2910                 },
2911         },
2912         .opt_clks       = slimbus2_opt_clks,
2913         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2914 };
2915
2916 /*
2917  * 'smartreflex' class
2918  * smartreflex module (monitor silicon performance and outputs a measure of
2919  * performance error)
2920  */
2921
2922 /* The IP is not compliant to type1 / type2 scheme */
2923 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2924         .sidle_shift    = 24,
2925         .enwkup_shift   = 26,
2926 };
2927
2928 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2929         .sysc_offs      = 0x0038,
2930         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2931         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2932                            SIDLE_SMART_WKUP),
2933         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2934 };
2935
2936 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2937         .name   = "smartreflex",
2938         .sysc   = &omap44xx_smartreflex_sysc,
2939         .rev    = 2,
2940 };
2941
2942 /* smartreflex_core */
2943 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2944         .sensor_voltdm_name   = "core",
2945 };
2946
2947 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2948         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2949         { .irq = -1 }
2950 };
2951
2952 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2953         .name           = "smartreflex_core",
2954         .class          = &omap44xx_smartreflex_hwmod_class,
2955         .clkdm_name     = "l4_ao_clkdm",
2956         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2957
2958         .main_clk       = "smartreflex_core_fck",
2959         .prcm = {
2960                 .omap4 = {
2961                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2962                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2963                         .modulemode   = MODULEMODE_SWCTRL,
2964                 },
2965         },
2966         .dev_attr       = &smartreflex_core_dev_attr,
2967 };
2968
2969 /* smartreflex_iva */
2970 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2971         .sensor_voltdm_name     = "iva",
2972 };
2973
2974 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2975         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2976         { .irq = -1 }
2977 };
2978
2979 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2980         .name           = "smartreflex_iva",
2981         .class          = &omap44xx_smartreflex_hwmod_class,
2982         .clkdm_name     = "l4_ao_clkdm",
2983         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2984         .main_clk       = "smartreflex_iva_fck",
2985         .prcm = {
2986                 .omap4 = {
2987                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2988                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2989                         .modulemode   = MODULEMODE_SWCTRL,
2990                 },
2991         },
2992         .dev_attr       = &smartreflex_iva_dev_attr,
2993 };
2994
2995 /* smartreflex_mpu */
2996 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2997         .sensor_voltdm_name     = "mpu",
2998 };
2999
3000 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3001         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3002         { .irq = -1 }
3003 };
3004
3005 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3006         .name           = "smartreflex_mpu",
3007         .class          = &omap44xx_smartreflex_hwmod_class,
3008         .clkdm_name     = "l4_ao_clkdm",
3009         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3010         .main_clk       = "smartreflex_mpu_fck",
3011         .prcm = {
3012                 .omap4 = {
3013                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3014                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3015                         .modulemode   = MODULEMODE_SWCTRL,
3016                 },
3017         },
3018         .dev_attr       = &smartreflex_mpu_dev_attr,
3019 };
3020
3021 /*
3022  * 'spinlock' class
3023  * spinlock provides hardware assistance for synchronizing the processes
3024  * running on multiple processors
3025  */
3026
3027 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3028         .rev_offs       = 0x0000,
3029         .sysc_offs      = 0x0010,
3030         .syss_offs      = 0x0014,
3031         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3032                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3033                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3034         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3035                            SIDLE_SMART_WKUP),
3036         .sysc_fields    = &omap_hwmod_sysc_type1,
3037 };
3038
3039 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3040         .name   = "spinlock",
3041         .sysc   = &omap44xx_spinlock_sysc,
3042 };
3043
3044 /* spinlock */
3045 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3046         .name           = "spinlock",
3047         .class          = &omap44xx_spinlock_hwmod_class,
3048         .clkdm_name     = "l4_cfg_clkdm",
3049         .prcm = {
3050                 .omap4 = {
3051                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3052                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3053                 },
3054         },
3055 };
3056
3057 /*
3058  * 'timer' class
3059  * general purpose timer module with accurate 1ms tick
3060  * This class contains several variants: ['timer_1ms', 'timer']
3061  */
3062
3063 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3064         .rev_offs       = 0x0000,
3065         .sysc_offs      = 0x0010,
3066         .syss_offs      = 0x0014,
3067         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3068                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3069                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3070                            SYSS_HAS_RESET_STATUS),
3071         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3072         .sysc_fields    = &omap_hwmod_sysc_type1,
3073 };
3074
3075 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3076         .name   = "timer",
3077         .sysc   = &omap44xx_timer_1ms_sysc,
3078 };
3079
3080 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3081         .rev_offs       = 0x0000,
3082         .sysc_offs      = 0x0010,
3083         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3084                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3085         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3086                            SIDLE_SMART_WKUP),
3087         .sysc_fields    = &omap_hwmod_sysc_type2,
3088 };
3089
3090 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3091         .name   = "timer",
3092         .sysc   = &omap44xx_timer_sysc,
3093 };
3094
3095 /* always-on timers dev attribute */
3096 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3097         .timer_capability       = OMAP_TIMER_ALWON,
3098 };
3099
3100 /* pwm timers dev attribute */
3101 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3102         .timer_capability       = OMAP_TIMER_HAS_PWM,
3103 };
3104
3105 /* timers with DSP interrupt dev attribute */
3106 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3107         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3108 };
3109
3110 /* pwm timers with DSP interrupt dev attribute */
3111 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3112         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3113 };
3114
3115 /* timer1 */
3116 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3117         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3118         { .irq = -1 }
3119 };
3120
3121 static struct omap_hwmod omap44xx_timer1_hwmod = {
3122         .name           = "timer1",
3123         .class          = &omap44xx_timer_1ms_hwmod_class,
3124         .clkdm_name     = "l4_wkup_clkdm",
3125         .mpu_irqs       = omap44xx_timer1_irqs,
3126         .main_clk       = "timer1_fck",
3127         .prcm = {
3128                 .omap4 = {
3129                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3130                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3131                         .modulemode   = MODULEMODE_SWCTRL,
3132                 },
3133         },
3134         .dev_attr       = &capability_alwon_dev_attr,
3135 };
3136
3137 /* timer2 */
3138 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3139         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3140         { .irq = -1 }
3141 };
3142
3143 static struct omap_hwmod omap44xx_timer2_hwmod = {
3144         .name           = "timer2",
3145         .class          = &omap44xx_timer_1ms_hwmod_class,
3146         .clkdm_name     = "l4_per_clkdm",
3147         .mpu_irqs       = omap44xx_timer2_irqs,
3148         .main_clk       = "timer2_fck",
3149         .prcm = {
3150                 .omap4 = {
3151                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3152                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3153                         .modulemode   = MODULEMODE_SWCTRL,
3154                 },
3155         },
3156 };
3157
3158 /* timer3 */
3159 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3160         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3161         { .irq = -1 }
3162 };
3163
3164 static struct omap_hwmod omap44xx_timer3_hwmod = {
3165         .name           = "timer3",
3166         .class          = &omap44xx_timer_hwmod_class,
3167         .clkdm_name     = "l4_per_clkdm",
3168         .mpu_irqs       = omap44xx_timer3_irqs,
3169         .main_clk       = "timer3_fck",
3170         .prcm = {
3171                 .omap4 = {
3172                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3173                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3174                         .modulemode   = MODULEMODE_SWCTRL,
3175                 },
3176         },
3177 };
3178
3179 /* timer4 */
3180 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3181         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3182         { .irq = -1 }
3183 };
3184
3185 static struct omap_hwmod omap44xx_timer4_hwmod = {
3186         .name           = "timer4",
3187         .class          = &omap44xx_timer_hwmod_class,
3188         .clkdm_name     = "l4_per_clkdm",
3189         .mpu_irqs       = omap44xx_timer4_irqs,
3190         .main_clk       = "timer4_fck",
3191         .prcm = {
3192                 .omap4 = {
3193                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3194                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3195                         .modulemode   = MODULEMODE_SWCTRL,
3196                 },
3197         },
3198 };
3199
3200 /* timer5 */
3201 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3202         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3203         { .irq = -1 }
3204 };
3205
3206 static struct omap_hwmod omap44xx_timer5_hwmod = {
3207         .name           = "timer5",
3208         .class          = &omap44xx_timer_hwmod_class,
3209         .clkdm_name     = "abe_clkdm",
3210         .mpu_irqs       = omap44xx_timer5_irqs,
3211         .main_clk       = "timer5_fck",
3212         .prcm = {
3213                 .omap4 = {
3214                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3215                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3216                         .modulemode   = MODULEMODE_SWCTRL,
3217                 },
3218         },
3219         .dev_attr       = &capability_dsp_dev_attr,
3220 };
3221
3222 /* timer6 */
3223 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3224         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3225         { .irq = -1 }
3226 };
3227
3228 static struct omap_hwmod omap44xx_timer6_hwmod = {
3229         .name           = "timer6",
3230         .class          = &omap44xx_timer_hwmod_class,
3231         .clkdm_name     = "abe_clkdm",
3232         .mpu_irqs       = omap44xx_timer6_irqs,
3233
3234         .main_clk       = "timer6_fck",
3235         .prcm = {
3236                 .omap4 = {
3237                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3238                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3239                         .modulemode   = MODULEMODE_SWCTRL,
3240                 },
3241         },
3242         .dev_attr       = &capability_dsp_dev_attr,
3243 };
3244
3245 /* timer7 */
3246 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3247         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3248         { .irq = -1 }
3249 };
3250
3251 static struct omap_hwmod omap44xx_timer7_hwmod = {
3252         .name           = "timer7",
3253         .class          = &omap44xx_timer_hwmod_class,
3254         .clkdm_name     = "abe_clkdm",
3255         .mpu_irqs       = omap44xx_timer7_irqs,
3256         .main_clk       = "timer7_fck",
3257         .prcm = {
3258                 .omap4 = {
3259                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3260                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3261                         .modulemode   = MODULEMODE_SWCTRL,
3262                 },
3263         },
3264         .dev_attr       = &capability_dsp_dev_attr,
3265 };
3266
3267 /* timer8 */
3268 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3269         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3270         { .irq = -1 }
3271 };
3272
3273 static struct omap_hwmod omap44xx_timer8_hwmod = {
3274         .name           = "timer8",
3275         .class          = &omap44xx_timer_hwmod_class,
3276         .clkdm_name     = "abe_clkdm",
3277         .mpu_irqs       = omap44xx_timer8_irqs,
3278         .main_clk       = "timer8_fck",
3279         .prcm = {
3280                 .omap4 = {
3281                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3282                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3283                         .modulemode   = MODULEMODE_SWCTRL,
3284                 },
3285         },
3286         .dev_attr       = &capability_dsp_pwm_dev_attr,
3287 };
3288
3289 /* timer9 */
3290 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3291         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3292         { .irq = -1 }
3293 };
3294
3295 static struct omap_hwmod omap44xx_timer9_hwmod = {
3296         .name           = "timer9",
3297         .class          = &omap44xx_timer_hwmod_class,
3298         .clkdm_name     = "l4_per_clkdm",
3299         .mpu_irqs       = omap44xx_timer9_irqs,
3300         .main_clk       = "timer9_fck",
3301         .prcm = {
3302                 .omap4 = {
3303                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3304                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3305                         .modulemode   = MODULEMODE_SWCTRL,
3306                 },
3307         },
3308         .dev_attr       = &capability_pwm_dev_attr,
3309 };
3310
3311 /* timer10 */
3312 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3313         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3314         { .irq = -1 }
3315 };
3316
3317 static struct omap_hwmod omap44xx_timer10_hwmod = {
3318         .name           = "timer10",
3319         .class          = &omap44xx_timer_1ms_hwmod_class,
3320         .clkdm_name     = "l4_per_clkdm",
3321         .mpu_irqs       = omap44xx_timer10_irqs,
3322         .main_clk       = "timer10_fck",
3323         .prcm = {
3324                 .omap4 = {
3325                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3326                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3327                         .modulemode   = MODULEMODE_SWCTRL,
3328                 },
3329         },
3330         .dev_attr       = &capability_pwm_dev_attr,
3331 };
3332
3333 /* timer11 */
3334 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3335         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3336         { .irq = -1 }
3337 };
3338
3339 static struct omap_hwmod omap44xx_timer11_hwmod = {
3340         .name           = "timer11",
3341         .class          = &omap44xx_timer_hwmod_class,
3342         .clkdm_name     = "l4_per_clkdm",
3343         .mpu_irqs       = omap44xx_timer11_irqs,
3344         .main_clk       = "timer11_fck",
3345         .prcm = {
3346                 .omap4 = {
3347                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3348                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3349                         .modulemode   = MODULEMODE_SWCTRL,
3350                 },
3351         },
3352         .dev_attr       = &capability_pwm_dev_attr,
3353 };
3354
3355 /*
3356  * 'uart' class
3357  * universal asynchronous receiver/transmitter (uart)
3358  */
3359
3360 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3361         .rev_offs       = 0x0050,
3362         .sysc_offs      = 0x0054,
3363         .syss_offs      = 0x0058,
3364         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3365                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3366                            SYSS_HAS_RESET_STATUS),
3367         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3368                            SIDLE_SMART_WKUP),
3369         .sysc_fields    = &omap_hwmod_sysc_type1,
3370 };
3371
3372 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3373         .name   = "uart",
3374         .sysc   = &omap44xx_uart_sysc,
3375 };
3376
3377 /* uart1 */
3378 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3379         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3380         { .irq = -1 }
3381 };
3382
3383 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3384         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3385         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3386         { .dma_req = -1 }
3387 };
3388
3389 static struct omap_hwmod omap44xx_uart1_hwmod = {
3390         .name           = "uart1",
3391         .class          = &omap44xx_uart_hwmod_class,
3392         .clkdm_name     = "l4_per_clkdm",
3393         .mpu_irqs       = omap44xx_uart1_irqs,
3394         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3395         .main_clk       = "uart1_fck",
3396         .prcm = {
3397                 .omap4 = {
3398                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3399                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3400                         .modulemode   = MODULEMODE_SWCTRL,
3401                 },
3402         },
3403 };
3404
3405 /* uart2 */
3406 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3407         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3408         { .irq = -1 }
3409 };
3410
3411 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3412         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3413         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3414         { .dma_req = -1 }
3415 };
3416
3417 static struct omap_hwmod omap44xx_uart2_hwmod = {
3418         .name           = "uart2",
3419         .class          = &omap44xx_uart_hwmod_class,
3420         .clkdm_name     = "l4_per_clkdm",
3421         .mpu_irqs       = omap44xx_uart2_irqs,
3422         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3423         .main_clk       = "uart2_fck",
3424         .prcm = {
3425                 .omap4 = {
3426                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3427                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3428                         .modulemode   = MODULEMODE_SWCTRL,
3429                 },
3430         },
3431 };
3432
3433 /* uart3 */
3434 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3435         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3436         { .irq = -1 }
3437 };
3438
3439 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3440         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3441         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3442         { .dma_req = -1 }
3443 };
3444
3445 static struct omap_hwmod omap44xx_uart3_hwmod = {
3446         .name           = "uart3",
3447         .class          = &omap44xx_uart_hwmod_class,
3448         .clkdm_name     = "l4_per_clkdm",
3449         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3450         .mpu_irqs       = omap44xx_uart3_irqs,
3451         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3452         .main_clk       = "uart3_fck",
3453         .prcm = {
3454                 .omap4 = {
3455                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3456                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3457                         .modulemode   = MODULEMODE_SWCTRL,
3458                 },
3459         },
3460 };
3461
3462 /* uart4 */
3463 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3464         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3465         { .irq = -1 }
3466 };
3467
3468 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3469         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3470         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3471         { .dma_req = -1 }
3472 };
3473
3474 static struct omap_hwmod omap44xx_uart4_hwmod = {
3475         .name           = "uart4",
3476         .class          = &omap44xx_uart_hwmod_class,
3477         .clkdm_name     = "l4_per_clkdm",
3478         .mpu_irqs       = omap44xx_uart4_irqs,
3479         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3480         .main_clk       = "uart4_fck",
3481         .prcm = {
3482                 .omap4 = {
3483                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3484                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3485                         .modulemode   = MODULEMODE_SWCTRL,
3486                 },
3487         },
3488 };
3489
3490 /*
3491  * 'usb_host_fs' class
3492  * full-speed usb host controller
3493  */
3494
3495 /* The IP is not compliant to type1 / type2 scheme */
3496 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3497         .midle_shift    = 4,
3498         .sidle_shift    = 2,
3499         .srst_shift     = 1,
3500 };
3501
3502 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3503         .rev_offs       = 0x0000,
3504         .sysc_offs      = 0x0210,
3505         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3506                            SYSC_HAS_SOFTRESET),
3507         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3508                            SIDLE_SMART_WKUP),
3509         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3510 };
3511
3512 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3513         .name   = "usb_host_fs",
3514         .sysc   = &omap44xx_usb_host_fs_sysc,
3515 };
3516
3517 /* usb_host_fs */
3518 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3519         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3520         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3521         { .irq = -1 }
3522 };
3523
3524 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3525         .name           = "usb_host_fs",
3526         .class          = &omap44xx_usb_host_fs_hwmod_class,
3527         .clkdm_name     = "l3_init_clkdm",
3528         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3529         .main_clk       = "usb_host_fs_fck",
3530         .prcm = {
3531                 .omap4 = {
3532                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3533                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3534                         .modulemode   = MODULEMODE_SWCTRL,
3535                 },
3536         },
3537 };
3538
3539 /*
3540  * 'usb_host_hs' class
3541  * high-speed multi-port usb host controller
3542  */
3543
3544 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3545         .rev_offs       = 0x0000,
3546         .sysc_offs      = 0x0010,
3547         .syss_offs      = 0x0014,
3548         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3549                            SYSC_HAS_SOFTRESET),
3550         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3551                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3552                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3553         .sysc_fields    = &omap_hwmod_sysc_type2,
3554 };
3555
3556 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3557         .name   = "usb_host_hs",
3558         .sysc   = &omap44xx_usb_host_hs_sysc,
3559 };
3560
3561 /* usb_host_hs */
3562 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3563         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3564         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3565         { .irq = -1 }
3566 };
3567
3568 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3569         .name           = "usb_host_hs",
3570         .class          = &omap44xx_usb_host_hs_hwmod_class,
3571         .clkdm_name     = "l3_init_clkdm",
3572         .main_clk       = "usb_host_hs_fck",
3573         .prcm = {
3574                 .omap4 = {
3575                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3576                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3577                         .modulemode   = MODULEMODE_SWCTRL,
3578                 },
3579         },
3580         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3581
3582         /*
3583          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3584          * id: i660
3585          *
3586          * Description:
3587          * In the following configuration :
3588          * - USBHOST module is set to smart-idle mode
3589          * - PRCM asserts idle_req to the USBHOST module ( This typically
3590          *   happens when the system is going to a low power mode : all ports
3591          *   have been suspended, the master part of the USBHOST module has
3592          *   entered the standby state, and SW has cut the functional clocks)
3593          * - an USBHOST interrupt occurs before the module is able to answer
3594          *   idle_ack, typically a remote wakeup IRQ.
3595          * Then the USB HOST module will enter a deadlock situation where it
3596          * is no more accessible nor functional.
3597          *
3598          * Workaround:
3599          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3600          */
3601
3602         /*
3603          * Errata: USB host EHCI may stall when entering smart-standby mode
3604          * Id: i571
3605          *
3606          * Description:
3607          * When the USBHOST module is set to smart-standby mode, and when it is
3608          * ready to enter the standby state (i.e. all ports are suspended and
3609          * all attached devices are in suspend mode), then it can wrongly assert
3610          * the Mstandby signal too early while there are still some residual OCP
3611          * transactions ongoing. If this condition occurs, the internal state
3612          * machine may go to an undefined state and the USB link may be stuck
3613          * upon the next resume.
3614          *
3615          * Workaround:
3616          * Don't use smart standby; use only force standby,
3617          * hence HWMOD_SWSUP_MSTANDBY
3618          */
3619
3620         /*
3621          * During system boot; If the hwmod framework resets the module
3622          * the module will have smart idle settings; which can lead to deadlock
3623          * (above Errata Id:i660); so, dont reset the module during boot;
3624          * Use HWMOD_INIT_NO_RESET.
3625          */
3626
3627         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3628                           HWMOD_INIT_NO_RESET,
3629 };
3630
3631 /*
3632  * 'usb_otg_hs' class
3633  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3634  */
3635
3636 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3637         .rev_offs       = 0x0400,
3638         .sysc_offs      = 0x0404,
3639         .syss_offs      = 0x0408,
3640         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3641                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3642                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3643         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3644                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3645                            MSTANDBY_SMART),
3646         .sysc_fields    = &omap_hwmod_sysc_type1,
3647 };
3648
3649 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3650         .name   = "usb_otg_hs",
3651         .sysc   = &omap44xx_usb_otg_hs_sysc,
3652 };
3653
3654 /* usb_otg_hs */
3655 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3656         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3657         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3658         { .irq = -1 }
3659 };
3660
3661 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3662         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3663 };
3664
3665 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3666         .name           = "usb_otg_hs",
3667         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3668         .clkdm_name     = "l3_init_clkdm",
3669         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3670         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3671         .main_clk       = "usb_otg_hs_ick",
3672         .prcm = {
3673                 .omap4 = {
3674                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3675                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3676                         .modulemode   = MODULEMODE_HWCTRL,
3677                 },
3678         },
3679         .opt_clks       = usb_otg_hs_opt_clks,
3680         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3681 };
3682
3683 /*
3684  * 'usb_tll_hs' class
3685  * usb_tll_hs module is the adapter on the usb_host_hs ports
3686  */
3687
3688 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3689         .rev_offs       = 0x0000,
3690         .sysc_offs      = 0x0010,
3691         .syss_offs      = 0x0014,
3692         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3693                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3694                            SYSC_HAS_AUTOIDLE),
3695         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3696         .sysc_fields    = &omap_hwmod_sysc_type1,
3697 };
3698
3699 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3700         .name   = "usb_tll_hs",
3701         .sysc   = &omap44xx_usb_tll_hs_sysc,
3702 };
3703
3704 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3705         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3706         { .irq = -1 }
3707 };
3708
3709 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3710         .name           = "usb_tll_hs",
3711         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3712         .clkdm_name     = "l3_init_clkdm",
3713         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3714         .main_clk       = "usb_tll_hs_ick",
3715         .prcm = {
3716                 .omap4 = {
3717                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3718                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3719                         .modulemode   = MODULEMODE_HWCTRL,
3720                 },
3721         },
3722 };
3723
3724 /*
3725  * 'wd_timer' class
3726  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3727  * overflow condition
3728  */
3729
3730 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3731         .rev_offs       = 0x0000,
3732         .sysc_offs      = 0x0010,
3733         .syss_offs      = 0x0014,
3734         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3735                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3736         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3737                            SIDLE_SMART_WKUP),
3738         .sysc_fields    = &omap_hwmod_sysc_type1,
3739 };
3740
3741 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3742         .name           = "wd_timer",
3743         .sysc           = &omap44xx_wd_timer_sysc,
3744         .pre_shutdown   = &omap2_wd_timer_disable,
3745         .reset          = &omap2_wd_timer_reset,
3746 };
3747
3748 /* wd_timer2 */
3749 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3750         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3751         { .irq = -1 }
3752 };
3753
3754 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3755         .name           = "wd_timer2",
3756         .class          = &omap44xx_wd_timer_hwmod_class,
3757         .clkdm_name     = "l4_wkup_clkdm",
3758         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3759         .main_clk       = "wd_timer2_fck",
3760         .prcm = {
3761                 .omap4 = {
3762                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3763                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3764                         .modulemode   = MODULEMODE_SWCTRL,
3765                 },
3766         },
3767 };
3768
3769 /* wd_timer3 */
3770 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3771         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3772         { .irq = -1 }
3773 };
3774
3775 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3776         .name           = "wd_timer3",
3777         .class          = &omap44xx_wd_timer_hwmod_class,
3778         .clkdm_name     = "abe_clkdm",
3779         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3780         .main_clk       = "wd_timer3_fck",
3781         .prcm = {
3782                 .omap4 = {
3783                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3784                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3785                         .modulemode   = MODULEMODE_SWCTRL,
3786                 },
3787         },
3788 };
3789
3790
3791 /*
3792  * interfaces
3793  */
3794
3795 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3796         {
3797                 .pa_start       = 0x4a204000,
3798                 .pa_end         = 0x4a2040ff,
3799                 .flags          = ADDR_TYPE_RT
3800         },
3801         { }
3802 };
3803
3804 /* c2c -> c2c_target_fw */
3805 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3806         .master         = &omap44xx_c2c_hwmod,
3807         .slave          = &omap44xx_c2c_target_fw_hwmod,
3808         .clk            = "div_core_ck",
3809         .addr           = omap44xx_c2c_target_fw_addrs,
3810         .user           = OCP_USER_MPU,
3811 };
3812
3813 /* l4_cfg -> c2c_target_fw */
3814 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3815         .master         = &omap44xx_l4_cfg_hwmod,
3816         .slave          = &omap44xx_c2c_target_fw_hwmod,
3817         .clk            = "l4_div_ck",
3818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3819 };
3820
3821 /* l3_main_1 -> dmm */
3822 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3823         .master         = &omap44xx_l3_main_1_hwmod,
3824         .slave          = &omap44xx_dmm_hwmod,
3825         .clk            = "l3_div_ck",
3826         .user           = OCP_USER_SDMA,
3827 };
3828
3829 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3830         {
3831                 .pa_start       = 0x4e000000,
3832                 .pa_end         = 0x4e0007ff,
3833                 .flags          = ADDR_TYPE_RT
3834         },
3835         { }
3836 };
3837
3838 /* mpu -> dmm */
3839 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3840         .master         = &omap44xx_mpu_hwmod,
3841         .slave          = &omap44xx_dmm_hwmod,
3842         .clk            = "l3_div_ck",
3843         .addr           = omap44xx_dmm_addrs,
3844         .user           = OCP_USER_MPU,
3845 };
3846
3847 /* c2c -> emif_fw */
3848 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3849         .master         = &omap44xx_c2c_hwmod,
3850         .slave          = &omap44xx_emif_fw_hwmod,
3851         .clk            = "div_core_ck",
3852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3853 };
3854
3855 /* dmm -> emif_fw */
3856 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3857         .master         = &omap44xx_dmm_hwmod,
3858         .slave          = &omap44xx_emif_fw_hwmod,
3859         .clk            = "l3_div_ck",
3860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3861 };
3862
3863 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3864         {
3865                 .pa_start       = 0x4a20c000,
3866                 .pa_end         = 0x4a20c0ff,
3867                 .flags          = ADDR_TYPE_RT
3868         },
3869         { }
3870 };
3871
3872 /* l4_cfg -> emif_fw */
3873 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3874         .master         = &omap44xx_l4_cfg_hwmod,
3875         .slave          = &omap44xx_emif_fw_hwmod,
3876         .clk            = "l4_div_ck",
3877         .addr           = omap44xx_emif_fw_addrs,
3878         .user           = OCP_USER_MPU,
3879 };
3880
3881 /* iva -> l3_instr */
3882 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3883         .master         = &omap44xx_iva_hwmod,
3884         .slave          = &omap44xx_l3_instr_hwmod,
3885         .clk            = "l3_div_ck",
3886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3887 };
3888
3889 /* l3_main_3 -> l3_instr */
3890 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3891         .master         = &omap44xx_l3_main_3_hwmod,
3892         .slave          = &omap44xx_l3_instr_hwmod,
3893         .clk            = "l3_div_ck",
3894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3895 };
3896
3897 /* ocp_wp_noc -> l3_instr */
3898 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3899         .master         = &omap44xx_ocp_wp_noc_hwmod,
3900         .slave          = &omap44xx_l3_instr_hwmod,
3901         .clk            = "l3_div_ck",
3902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3903 };
3904
3905 /* dsp -> l3_main_1 */
3906 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3907         .master         = &omap44xx_dsp_hwmod,
3908         .slave          = &omap44xx_l3_main_1_hwmod,
3909         .clk            = "l3_div_ck",
3910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3911 };
3912
3913 /* dss -> l3_main_1 */
3914 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3915         .master         = &omap44xx_dss_hwmod,
3916         .slave          = &omap44xx_l3_main_1_hwmod,
3917         .clk            = "l3_div_ck",
3918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3919 };
3920
3921 /* l3_main_2 -> l3_main_1 */
3922 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3923         .master         = &omap44xx_l3_main_2_hwmod,
3924         .slave          = &omap44xx_l3_main_1_hwmod,
3925         .clk            = "l3_div_ck",
3926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3927 };
3928
3929 /* l4_cfg -> l3_main_1 */
3930 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3931         .master         = &omap44xx_l4_cfg_hwmod,
3932         .slave          = &omap44xx_l3_main_1_hwmod,
3933         .clk            = "l4_div_ck",
3934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3935 };
3936
3937 /* mmc1 -> l3_main_1 */
3938 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3939         .master         = &omap44xx_mmc1_hwmod,
3940         .slave          = &omap44xx_l3_main_1_hwmod,
3941         .clk            = "l3_div_ck",
3942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3943 };
3944
3945 /* mmc2 -> l3_main_1 */
3946 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3947         .master         = &omap44xx_mmc2_hwmod,
3948         .slave          = &omap44xx_l3_main_1_hwmod,
3949         .clk            = "l3_div_ck",
3950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3951 };
3952
3953 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3954         {
3955                 .pa_start       = 0x44000000,
3956                 .pa_end         = 0x44000fff,
3957                 .flags          = ADDR_TYPE_RT
3958         },
3959         { }
3960 };
3961
3962 /* mpu -> l3_main_1 */
3963 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3964         .master         = &omap44xx_mpu_hwmod,
3965         .slave          = &omap44xx_l3_main_1_hwmod,
3966         .clk            = "l3_div_ck",
3967         .addr           = omap44xx_l3_main_1_addrs,
3968         .user           = OCP_USER_MPU,
3969 };
3970
3971 /* c2c_target_fw -> l3_main_2 */
3972 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3973         .master         = &omap44xx_c2c_target_fw_hwmod,
3974         .slave          = &omap44xx_l3_main_2_hwmod,
3975         .clk            = "l3_div_ck",
3976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3977 };
3978
3979 /* debugss -> l3_main_2 */
3980 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3981         .master         = &omap44xx_debugss_hwmod,
3982         .slave          = &omap44xx_l3_main_2_hwmod,
3983         .clk            = "dbgclk_mux_ck",
3984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3985 };
3986
3987 /* dma_system -> l3_main_2 */
3988 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3989         .master         = &omap44xx_dma_system_hwmod,
3990         .slave          = &omap44xx_l3_main_2_hwmod,
3991         .clk            = "l3_div_ck",
3992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3993 };
3994
3995 /* fdif -> l3_main_2 */
3996 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3997         .master         = &omap44xx_fdif_hwmod,
3998         .slave          = &omap44xx_l3_main_2_hwmod,
3999         .clk            = "l3_div_ck",
4000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4001 };
4002
4003 /* gpu -> l3_main_2 */
4004 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4005         .master         = &omap44xx_gpu_hwmod,
4006         .slave          = &omap44xx_l3_main_2_hwmod,
4007         .clk            = "l3_div_ck",
4008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4009 };
4010
4011 /* hsi -> l3_main_2 */
4012 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4013         .master         = &omap44xx_hsi_hwmod,
4014         .slave          = &omap44xx_l3_main_2_hwmod,
4015         .clk            = "l3_div_ck",
4016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4017 };
4018
4019 /* ipu -> l3_main_2 */
4020 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4021         .master         = &omap44xx_ipu_hwmod,
4022         .slave          = &omap44xx_l3_main_2_hwmod,
4023         .clk            = "l3_div_ck",
4024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4025 };
4026
4027 /* iss -> l3_main_2 */
4028 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4029         .master         = &omap44xx_iss_hwmod,
4030         .slave          = &omap44xx_l3_main_2_hwmod,
4031         .clk            = "l3_div_ck",
4032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4033 };
4034
4035 /* iva -> l3_main_2 */
4036 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4037         .master         = &omap44xx_iva_hwmod,
4038         .slave          = &omap44xx_l3_main_2_hwmod,
4039         .clk            = "l3_div_ck",
4040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4041 };
4042
4043 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4044         {
4045                 .pa_start       = 0x44800000,
4046                 .pa_end         = 0x44801fff,
4047                 .flags          = ADDR_TYPE_RT
4048         },
4049         { }
4050 };
4051
4052 /* l3_main_1 -> l3_main_2 */
4053 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4054         .master         = &omap44xx_l3_main_1_hwmod,
4055         .slave          = &omap44xx_l3_main_2_hwmod,
4056         .clk            = "l3_div_ck",
4057         .addr           = omap44xx_l3_main_2_addrs,
4058         .user           = OCP_USER_MPU,
4059 };
4060
4061 /* l4_cfg -> l3_main_2 */
4062 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4063         .master         = &omap44xx_l4_cfg_hwmod,
4064         .slave          = &omap44xx_l3_main_2_hwmod,
4065         .clk            = "l4_div_ck",
4066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4067 };
4068
4069 /* usb_host_fs -> l3_main_2 */
4070 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4071         .master         = &omap44xx_usb_host_fs_hwmod,
4072         .slave          = &omap44xx_l3_main_2_hwmod,
4073         .clk            = "l3_div_ck",
4074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4075 };
4076
4077 /* usb_host_hs -> l3_main_2 */
4078 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4079         .master         = &omap44xx_usb_host_hs_hwmod,
4080         .slave          = &omap44xx_l3_main_2_hwmod,
4081         .clk            = "l3_div_ck",
4082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4083 };
4084
4085 /* usb_otg_hs -> l3_main_2 */
4086 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4087         .master         = &omap44xx_usb_otg_hs_hwmod,
4088         .slave          = &omap44xx_l3_main_2_hwmod,
4089         .clk            = "l3_div_ck",
4090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4091 };
4092
4093 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4094         {
4095                 .pa_start       = 0x45000000,
4096                 .pa_end         = 0x45000fff,
4097                 .flags          = ADDR_TYPE_RT
4098         },
4099         { }
4100 };
4101
4102 /* l3_main_1 -> l3_main_3 */
4103 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4104         .master         = &omap44xx_l3_main_1_hwmod,
4105         .slave          = &omap44xx_l3_main_3_hwmod,
4106         .clk            = "l3_div_ck",
4107         .addr           = omap44xx_l3_main_3_addrs,
4108         .user           = OCP_USER_MPU,
4109 };
4110
4111 /* l3_main_2 -> l3_main_3 */
4112 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4113         .master         = &omap44xx_l3_main_2_hwmod,
4114         .slave          = &omap44xx_l3_main_3_hwmod,
4115         .clk            = "l3_div_ck",
4116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4117 };
4118
4119 /* l4_cfg -> l3_main_3 */
4120 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4121         .master         = &omap44xx_l4_cfg_hwmod,
4122         .slave          = &omap44xx_l3_main_3_hwmod,
4123         .clk            = "l4_div_ck",
4124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4125 };
4126
4127 /* aess -> l4_abe */
4128 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4129         .master         = &omap44xx_aess_hwmod,
4130         .slave          = &omap44xx_l4_abe_hwmod,
4131         .clk            = "ocp_abe_iclk",
4132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4133 };
4134
4135 /* dsp -> l4_abe */
4136 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4137         .master         = &omap44xx_dsp_hwmod,
4138         .slave          = &omap44xx_l4_abe_hwmod,
4139         .clk            = "ocp_abe_iclk",
4140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4141 };
4142
4143 /* l3_main_1 -> l4_abe */
4144 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4145         .master         = &omap44xx_l3_main_1_hwmod,
4146         .slave          = &omap44xx_l4_abe_hwmod,
4147         .clk            = "l3_div_ck",
4148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4149 };
4150
4151 /* mpu -> l4_abe */
4152 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4153         .master         = &omap44xx_mpu_hwmod,
4154         .slave          = &omap44xx_l4_abe_hwmod,
4155         .clk            = "ocp_abe_iclk",
4156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4157 };
4158
4159 /* l3_main_1 -> l4_cfg */
4160 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4161         .master         = &omap44xx_l3_main_1_hwmod,
4162         .slave          = &omap44xx_l4_cfg_hwmod,
4163         .clk            = "l3_div_ck",
4164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4165 };
4166
4167 /* l3_main_2 -> l4_per */
4168 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4169         .master         = &omap44xx_l3_main_2_hwmod,
4170         .slave          = &omap44xx_l4_per_hwmod,
4171         .clk            = "l3_div_ck",
4172         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4173 };
4174
4175 /* l4_cfg -> l4_wkup */
4176 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4177         .master         = &omap44xx_l4_cfg_hwmod,
4178         .slave          = &omap44xx_l4_wkup_hwmod,
4179         .clk            = "l4_div_ck",
4180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4181 };
4182
4183 /* mpu -> mpu_private */
4184 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4185         .master         = &omap44xx_mpu_hwmod,
4186         .slave          = &omap44xx_mpu_private_hwmod,
4187         .clk            = "l3_div_ck",
4188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4189 };
4190
4191 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4192         {
4193                 .pa_start       = 0x4a102000,
4194                 .pa_end         = 0x4a10207f,
4195                 .flags          = ADDR_TYPE_RT
4196         },
4197         { }
4198 };
4199
4200 /* l4_cfg -> ocp_wp_noc */
4201 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4202         .master         = &omap44xx_l4_cfg_hwmod,
4203         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4204         .clk            = "l4_div_ck",
4205         .addr           = omap44xx_ocp_wp_noc_addrs,
4206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4207 };
4208
4209 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4210         {
4211                 .pa_start       = 0x401f1000,
4212                 .pa_end         = 0x401f13ff,
4213                 .flags          = ADDR_TYPE_RT
4214         },
4215         { }
4216 };
4217
4218 /* l4_abe -> aess */
4219 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4220         .master         = &omap44xx_l4_abe_hwmod,
4221         .slave          = &omap44xx_aess_hwmod,
4222         .clk            = "ocp_abe_iclk",
4223         .addr           = omap44xx_aess_addrs,
4224         .user           = OCP_USER_MPU,
4225 };
4226
4227 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4228         {
4229                 .pa_start       = 0x490f1000,
4230                 .pa_end         = 0x490f13ff,
4231                 .flags          = ADDR_TYPE_RT
4232         },
4233         { }
4234 };
4235
4236 /* l4_abe -> aess (dma) */
4237 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4238         .master         = &omap44xx_l4_abe_hwmod,
4239         .slave          = &omap44xx_aess_hwmod,
4240         .clk            = "ocp_abe_iclk",
4241         .addr           = omap44xx_aess_dma_addrs,
4242         .user           = OCP_USER_SDMA,
4243 };
4244
4245 /* l3_main_2 -> c2c */
4246 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4247         .master         = &omap44xx_l3_main_2_hwmod,
4248         .slave          = &omap44xx_c2c_hwmod,
4249         .clk            = "l3_div_ck",
4250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4251 };
4252
4253 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4254         {
4255                 .pa_start       = 0x4a304000,
4256                 .pa_end         = 0x4a30401f,
4257                 .flags          = ADDR_TYPE_RT
4258         },
4259         { }
4260 };
4261
4262 /* l4_wkup -> counter_32k */
4263 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4264         .master         = &omap44xx_l4_wkup_hwmod,
4265         .slave          = &omap44xx_counter_32k_hwmod,
4266         .clk            = "l4_wkup_clk_mux_ck",
4267         .addr           = omap44xx_counter_32k_addrs,
4268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4269 };
4270
4271 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4272         {
4273                 .pa_start       = 0x4a002000,
4274                 .pa_end         = 0x4a0027ff,
4275                 .flags          = ADDR_TYPE_RT
4276         },
4277         { }
4278 };
4279
4280 /* l4_cfg -> ctrl_module_core */
4281 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4282         .master         = &omap44xx_l4_cfg_hwmod,
4283         .slave          = &omap44xx_ctrl_module_core_hwmod,
4284         .clk            = "l4_div_ck",
4285         .addr           = omap44xx_ctrl_module_core_addrs,
4286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4287 };
4288
4289 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4290         {
4291                 .pa_start       = 0x4a100000,
4292                 .pa_end         = 0x4a1007ff,
4293                 .flags          = ADDR_TYPE_RT
4294         },
4295         { }
4296 };
4297
4298 /* l4_cfg -> ctrl_module_pad_core */
4299 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4300         .master         = &omap44xx_l4_cfg_hwmod,
4301         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4302         .clk            = "l4_div_ck",
4303         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4305 };
4306
4307 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4308         {
4309                 .pa_start       = 0x4a30c000,
4310                 .pa_end         = 0x4a30c7ff,
4311                 .flags          = ADDR_TYPE_RT
4312         },
4313         { }
4314 };
4315
4316 /* l4_wkup -> ctrl_module_wkup */
4317 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4318         .master         = &omap44xx_l4_wkup_hwmod,
4319         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4320         .clk            = "l4_wkup_clk_mux_ck",
4321         .addr           = omap44xx_ctrl_module_wkup_addrs,
4322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4323 };
4324
4325 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4326         {
4327                 .pa_start       = 0x4a31e000,
4328                 .pa_end         = 0x4a31e7ff,
4329                 .flags          = ADDR_TYPE_RT
4330         },
4331         { }
4332 };
4333
4334 /* l4_wkup -> ctrl_module_pad_wkup */
4335 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4336         .master         = &omap44xx_l4_wkup_hwmod,
4337         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4338         .clk            = "l4_wkup_clk_mux_ck",
4339         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4341 };
4342
4343 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4344         {
4345                 .pa_start       = 0x54160000,
4346                 .pa_end         = 0x54167fff,
4347                 .flags          = ADDR_TYPE_RT
4348         },
4349         { }
4350 };
4351
4352 /* l3_instr -> debugss */
4353 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4354         .master         = &omap44xx_l3_instr_hwmod,
4355         .slave          = &omap44xx_debugss_hwmod,
4356         .clk            = "l3_div_ck",
4357         .addr           = omap44xx_debugss_addrs,
4358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4359 };
4360
4361 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4362         {
4363                 .pa_start       = 0x4a056000,
4364                 .pa_end         = 0x4a056fff,
4365                 .flags          = ADDR_TYPE_RT
4366         },
4367         { }
4368 };
4369
4370 /* l4_cfg -> dma_system */
4371 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4372         .master         = &omap44xx_l4_cfg_hwmod,
4373         .slave          = &omap44xx_dma_system_hwmod,
4374         .clk            = "l4_div_ck",
4375         .addr           = omap44xx_dma_system_addrs,
4376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4380         {
4381                 .name           = "mpu",
4382                 .pa_start       = 0x4012e000,
4383                 .pa_end         = 0x4012e07f,
4384                 .flags          = ADDR_TYPE_RT
4385         },
4386         { }
4387 };
4388
4389 /* l4_abe -> dmic */
4390 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4391         .master         = &omap44xx_l4_abe_hwmod,
4392         .slave          = &omap44xx_dmic_hwmod,
4393         .clk            = "ocp_abe_iclk",
4394         .addr           = omap44xx_dmic_addrs,
4395         .user           = OCP_USER_MPU,
4396 };
4397
4398 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4399         {
4400                 .name           = "dma",
4401                 .pa_start       = 0x4902e000,
4402                 .pa_end         = 0x4902e07f,
4403                 .flags          = ADDR_TYPE_RT
4404         },
4405         { }
4406 };
4407
4408 /* l4_abe -> dmic (dma) */
4409 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4410         .master         = &omap44xx_l4_abe_hwmod,
4411         .slave          = &omap44xx_dmic_hwmod,
4412         .clk            = "ocp_abe_iclk",
4413         .addr           = omap44xx_dmic_dma_addrs,
4414         .user           = OCP_USER_SDMA,
4415 };
4416
4417 /* dsp -> iva */
4418 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4419         .master         = &omap44xx_dsp_hwmod,
4420         .slave          = &omap44xx_iva_hwmod,
4421         .clk            = "dpll_iva_m5x2_ck",
4422         .user           = OCP_USER_DSP,
4423 };
4424
4425 /* dsp -> sl2if */
4426 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4427         .master         = &omap44xx_dsp_hwmod,
4428         .slave          = &omap44xx_sl2if_hwmod,
4429         .clk            = "dpll_iva_m5x2_ck",
4430         .user           = OCP_USER_DSP,
4431 };
4432
4433 /* l4_cfg -> dsp */
4434 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4435         .master         = &omap44xx_l4_cfg_hwmod,
4436         .slave          = &omap44xx_dsp_hwmod,
4437         .clk            = "l4_div_ck",
4438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4439 };
4440
4441 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4442         {
4443                 .pa_start       = 0x58000000,
4444                 .pa_end         = 0x5800007f,
4445                 .flags          = ADDR_TYPE_RT
4446         },
4447         { }
4448 };
4449
4450 /* l3_main_2 -> dss */
4451 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4452         .master         = &omap44xx_l3_main_2_hwmod,
4453         .slave          = &omap44xx_dss_hwmod,
4454         .clk            = "dss_fck",
4455         .addr           = omap44xx_dss_dma_addrs,
4456         .user           = OCP_USER_SDMA,
4457 };
4458
4459 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4460         {
4461                 .pa_start       = 0x48040000,
4462                 .pa_end         = 0x4804007f,
4463                 .flags          = ADDR_TYPE_RT
4464         },
4465         { }
4466 };
4467
4468 /* l4_per -> dss */
4469 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4470         .master         = &omap44xx_l4_per_hwmod,
4471         .slave          = &omap44xx_dss_hwmod,
4472         .clk            = "l4_div_ck",
4473         .addr           = omap44xx_dss_addrs,
4474         .user           = OCP_USER_MPU,
4475 };
4476
4477 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4478         {
4479                 .pa_start       = 0x58001000,
4480                 .pa_end         = 0x58001fff,
4481                 .flags          = ADDR_TYPE_RT
4482         },
4483         { }
4484 };
4485
4486 /* l3_main_2 -> dss_dispc */
4487 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4488         .master         = &omap44xx_l3_main_2_hwmod,
4489         .slave          = &omap44xx_dss_dispc_hwmod,
4490         .clk            = "dss_fck",
4491         .addr           = omap44xx_dss_dispc_dma_addrs,
4492         .user           = OCP_USER_SDMA,
4493 };
4494
4495 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4496         {
4497                 .pa_start       = 0x48041000,
4498                 .pa_end         = 0x48041fff,
4499                 .flags          = ADDR_TYPE_RT
4500         },
4501         { }
4502 };
4503
4504 /* l4_per -> dss_dispc */
4505 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4506         .master         = &omap44xx_l4_per_hwmod,
4507         .slave          = &omap44xx_dss_dispc_hwmod,
4508         .clk            = "l4_div_ck",
4509         .addr           = omap44xx_dss_dispc_addrs,
4510         .user           = OCP_USER_MPU,
4511 };
4512
4513 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4514         {
4515                 .pa_start       = 0x58004000,
4516                 .pa_end         = 0x580041ff,
4517                 .flags          = ADDR_TYPE_RT
4518         },
4519         { }
4520 };
4521
4522 /* l3_main_2 -> dss_dsi1 */
4523 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4524         .master         = &omap44xx_l3_main_2_hwmod,
4525         .slave          = &omap44xx_dss_dsi1_hwmod,
4526         .clk            = "dss_fck",
4527         .addr           = omap44xx_dss_dsi1_dma_addrs,
4528         .user           = OCP_USER_SDMA,
4529 };
4530
4531 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4532         {
4533                 .pa_start       = 0x48044000,
4534                 .pa_end         = 0x480441ff,
4535                 .flags          = ADDR_TYPE_RT
4536         },
4537         { }
4538 };
4539
4540 /* l4_per -> dss_dsi1 */
4541 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4542         .master         = &omap44xx_l4_per_hwmod,
4543         .slave          = &omap44xx_dss_dsi1_hwmod,
4544         .clk            = "l4_div_ck",
4545         .addr           = omap44xx_dss_dsi1_addrs,
4546         .user           = OCP_USER_MPU,
4547 };
4548
4549 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4550         {
4551                 .pa_start       = 0x58005000,
4552                 .pa_end         = 0x580051ff,
4553                 .flags          = ADDR_TYPE_RT
4554         },
4555         { }
4556 };
4557
4558 /* l3_main_2 -> dss_dsi2 */
4559 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4560         .master         = &omap44xx_l3_main_2_hwmod,
4561         .slave          = &omap44xx_dss_dsi2_hwmod,
4562         .clk            = "dss_fck",
4563         .addr           = omap44xx_dss_dsi2_dma_addrs,
4564         .user           = OCP_USER_SDMA,
4565 };
4566
4567 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4568         {
4569                 .pa_start       = 0x48045000,
4570                 .pa_end         = 0x480451ff,
4571                 .flags          = ADDR_TYPE_RT
4572         },
4573         { }
4574 };
4575
4576 /* l4_per -> dss_dsi2 */
4577 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4578         .master         = &omap44xx_l4_per_hwmod,
4579         .slave          = &omap44xx_dss_dsi2_hwmod,
4580         .clk            = "l4_div_ck",
4581         .addr           = omap44xx_dss_dsi2_addrs,
4582         .user           = OCP_USER_MPU,
4583 };
4584
4585 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4586         {
4587                 .pa_start       = 0x58006000,
4588                 .pa_end         = 0x58006fff,
4589                 .flags          = ADDR_TYPE_RT
4590         },
4591         { }
4592 };
4593
4594 /* l3_main_2 -> dss_hdmi */
4595 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4596         .master         = &omap44xx_l3_main_2_hwmod,
4597         .slave          = &omap44xx_dss_hdmi_hwmod,
4598         .clk            = "dss_fck",
4599         .addr           = omap44xx_dss_hdmi_dma_addrs,
4600         .user           = OCP_USER_SDMA,
4601 };
4602
4603 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4604         {
4605                 .pa_start       = 0x48046000,
4606                 .pa_end         = 0x48046fff,
4607                 .flags          = ADDR_TYPE_RT
4608         },
4609         { }
4610 };
4611
4612 /* l4_per -> dss_hdmi */
4613 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4614         .master         = &omap44xx_l4_per_hwmod,
4615         .slave          = &omap44xx_dss_hdmi_hwmod,
4616         .clk            = "l4_div_ck",
4617         .addr           = omap44xx_dss_hdmi_addrs,
4618         .user           = OCP_USER_MPU,
4619 };
4620
4621 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4622         {
4623                 .pa_start       = 0x58002000,
4624                 .pa_end         = 0x580020ff,
4625                 .flags          = ADDR_TYPE_RT
4626         },
4627         { }
4628 };
4629
4630 /* l3_main_2 -> dss_rfbi */
4631 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4632         .master         = &omap44xx_l3_main_2_hwmod,
4633         .slave          = &omap44xx_dss_rfbi_hwmod,
4634         .clk            = "dss_fck",
4635         .addr           = omap44xx_dss_rfbi_dma_addrs,
4636         .user           = OCP_USER_SDMA,
4637 };
4638
4639 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4640         {
4641                 .pa_start       = 0x48042000,
4642                 .pa_end         = 0x480420ff,
4643                 .flags          = ADDR_TYPE_RT
4644         },
4645         { }
4646 };
4647
4648 /* l4_per -> dss_rfbi */
4649 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4650         .master         = &omap44xx_l4_per_hwmod,
4651         .slave          = &omap44xx_dss_rfbi_hwmod,
4652         .clk            = "l4_div_ck",
4653         .addr           = omap44xx_dss_rfbi_addrs,
4654         .user           = OCP_USER_MPU,
4655 };
4656
4657 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4658         {
4659                 .pa_start       = 0x58003000,
4660                 .pa_end         = 0x580030ff,
4661                 .flags          = ADDR_TYPE_RT
4662         },
4663         { }
4664 };
4665
4666 /* l3_main_2 -> dss_venc */
4667 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4668         .master         = &omap44xx_l3_main_2_hwmod,
4669         .slave          = &omap44xx_dss_venc_hwmod,
4670         .clk            = "dss_fck",
4671         .addr           = omap44xx_dss_venc_dma_addrs,
4672         .user           = OCP_USER_SDMA,
4673 };
4674
4675 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4676         {
4677                 .pa_start       = 0x48043000,
4678                 .pa_end         = 0x480430ff,
4679                 .flags          = ADDR_TYPE_RT
4680         },
4681         { }
4682 };
4683
4684 /* l4_per -> dss_venc */
4685 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4686         .master         = &omap44xx_l4_per_hwmod,
4687         .slave          = &omap44xx_dss_venc_hwmod,
4688         .clk            = "l4_div_ck",
4689         .addr           = omap44xx_dss_venc_addrs,
4690         .user           = OCP_USER_MPU,
4691 };
4692
4693 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4694         {
4695                 .pa_start       = 0x48078000,
4696                 .pa_end         = 0x48078fff,
4697                 .flags          = ADDR_TYPE_RT
4698         },
4699         { }
4700 };
4701
4702 /* l4_per -> elm */
4703 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4704         .master         = &omap44xx_l4_per_hwmod,
4705         .slave          = &omap44xx_elm_hwmod,
4706         .clk            = "l4_div_ck",
4707         .addr           = omap44xx_elm_addrs,
4708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4709 };
4710
4711 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4712         {
4713                 .pa_start       = 0x4c000000,
4714                 .pa_end         = 0x4c0000ff,
4715                 .flags          = ADDR_TYPE_RT
4716         },
4717         { }
4718 };
4719
4720 /* emif_fw -> emif1 */
4721 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4722         .master         = &omap44xx_emif_fw_hwmod,
4723         .slave          = &omap44xx_emif1_hwmod,
4724         .clk            = "l3_div_ck",
4725         .addr           = omap44xx_emif1_addrs,
4726         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4727 };
4728
4729 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4730         {
4731                 .pa_start       = 0x4d000000,
4732                 .pa_end         = 0x4d0000ff,
4733                 .flags          = ADDR_TYPE_RT
4734         },
4735         { }
4736 };
4737
4738 /* emif_fw -> emif2 */
4739 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4740         .master         = &omap44xx_emif_fw_hwmod,
4741         .slave          = &omap44xx_emif2_hwmod,
4742         .clk            = "l3_div_ck",
4743         .addr           = omap44xx_emif2_addrs,
4744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4745 };
4746
4747 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4748         {
4749                 .pa_start       = 0x4a10a000,
4750                 .pa_end         = 0x4a10a1ff,
4751                 .flags          = ADDR_TYPE_RT
4752         },
4753         { }
4754 };
4755
4756 /* l4_cfg -> fdif */
4757 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4758         .master         = &omap44xx_l4_cfg_hwmod,
4759         .slave          = &omap44xx_fdif_hwmod,
4760         .clk            = "l4_div_ck",
4761         .addr           = omap44xx_fdif_addrs,
4762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4763 };
4764
4765 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4766         {
4767                 .pa_start       = 0x4a310000,
4768                 .pa_end         = 0x4a3101ff,
4769                 .flags          = ADDR_TYPE_RT
4770         },
4771         { }
4772 };
4773
4774 /* l4_wkup -> gpio1 */
4775 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4776         .master         = &omap44xx_l4_wkup_hwmod,
4777         .slave          = &omap44xx_gpio1_hwmod,
4778         .clk            = "l4_wkup_clk_mux_ck",
4779         .addr           = omap44xx_gpio1_addrs,
4780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4781 };
4782
4783 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4784         {
4785                 .pa_start       = 0x48055000,
4786                 .pa_end         = 0x480551ff,
4787                 .flags          = ADDR_TYPE_RT
4788         },
4789         { }
4790 };
4791
4792 /* l4_per -> gpio2 */
4793 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4794         .master         = &omap44xx_l4_per_hwmod,
4795         .slave          = &omap44xx_gpio2_hwmod,
4796         .clk            = "l4_div_ck",
4797         .addr           = omap44xx_gpio2_addrs,
4798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4799 };
4800
4801 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4802         {
4803                 .pa_start       = 0x48057000,
4804                 .pa_end         = 0x480571ff,
4805                 .flags          = ADDR_TYPE_RT
4806         },
4807         { }
4808 };
4809
4810 /* l4_per -> gpio3 */
4811 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4812         .master         = &omap44xx_l4_per_hwmod,
4813         .slave          = &omap44xx_gpio3_hwmod,
4814         .clk            = "l4_div_ck",
4815         .addr           = omap44xx_gpio3_addrs,
4816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4817 };
4818
4819 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4820         {
4821                 .pa_start       = 0x48059000,
4822                 .pa_end         = 0x480591ff,
4823                 .flags          = ADDR_TYPE_RT
4824         },
4825         { }
4826 };
4827
4828 /* l4_per -> gpio4 */
4829 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4830         .master         = &omap44xx_l4_per_hwmod,
4831         .slave          = &omap44xx_gpio4_hwmod,
4832         .clk            = "l4_div_ck",
4833         .addr           = omap44xx_gpio4_addrs,
4834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4835 };
4836
4837 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4838         {
4839                 .pa_start       = 0x4805b000,
4840                 .pa_end         = 0x4805b1ff,
4841                 .flags          = ADDR_TYPE_RT
4842         },
4843         { }
4844 };
4845
4846 /* l4_per -> gpio5 */
4847 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4848         .master         = &omap44xx_l4_per_hwmod,
4849         .slave          = &omap44xx_gpio5_hwmod,
4850         .clk            = "l4_div_ck",
4851         .addr           = omap44xx_gpio5_addrs,
4852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4853 };
4854
4855 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4856         {
4857                 .pa_start       = 0x4805d000,
4858                 .pa_end         = 0x4805d1ff,
4859                 .flags          = ADDR_TYPE_RT
4860         },
4861         { }
4862 };
4863
4864 /* l4_per -> gpio6 */
4865 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4866         .master         = &omap44xx_l4_per_hwmod,
4867         .slave          = &omap44xx_gpio6_hwmod,
4868         .clk            = "l4_div_ck",
4869         .addr           = omap44xx_gpio6_addrs,
4870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4871 };
4872
4873 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4874         {
4875                 .pa_start       = 0x50000000,
4876                 .pa_end         = 0x500003ff,
4877                 .flags          = ADDR_TYPE_RT
4878         },
4879         { }
4880 };
4881
4882 /* l3_main_2 -> gpmc */
4883 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4884         .master         = &omap44xx_l3_main_2_hwmod,
4885         .slave          = &omap44xx_gpmc_hwmod,
4886         .clk            = "l3_div_ck",
4887         .addr           = omap44xx_gpmc_addrs,
4888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4889 };
4890
4891 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4892         {
4893                 .pa_start       = 0x56000000,
4894                 .pa_end         = 0x5600ffff,
4895                 .flags          = ADDR_TYPE_RT
4896         },
4897         { }
4898 };
4899
4900 /* l3_main_2 -> gpu */
4901 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4902         .master         = &omap44xx_l3_main_2_hwmod,
4903         .slave          = &omap44xx_gpu_hwmod,
4904         .clk            = "l3_div_ck",
4905         .addr           = omap44xx_gpu_addrs,
4906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4907 };
4908
4909 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4910         {
4911                 .pa_start       = 0x480b2000,
4912                 .pa_end         = 0x480b201f,
4913                 .flags          = ADDR_TYPE_RT
4914         },
4915         { }
4916 };
4917
4918 /* l4_per -> hdq1w */
4919 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4920         .master         = &omap44xx_l4_per_hwmod,
4921         .slave          = &omap44xx_hdq1w_hwmod,
4922         .clk            = "l4_div_ck",
4923         .addr           = omap44xx_hdq1w_addrs,
4924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4925 };
4926
4927 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4928         {
4929                 .pa_start       = 0x4a058000,
4930                 .pa_end         = 0x4a05bfff,
4931                 .flags          = ADDR_TYPE_RT
4932         },
4933         { }
4934 };
4935
4936 /* l4_cfg -> hsi */
4937 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4938         .master         = &omap44xx_l4_cfg_hwmod,
4939         .slave          = &omap44xx_hsi_hwmod,
4940         .clk            = "l4_div_ck",
4941         .addr           = omap44xx_hsi_addrs,
4942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4943 };
4944
4945 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4946         {
4947                 .pa_start       = 0x48070000,
4948                 .pa_end         = 0x480700ff,
4949                 .flags          = ADDR_TYPE_RT
4950         },
4951         { }
4952 };
4953
4954 /* l4_per -> i2c1 */
4955 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4956         .master         = &omap44xx_l4_per_hwmod,
4957         .slave          = &omap44xx_i2c1_hwmod,
4958         .clk            = "l4_div_ck",
4959         .addr           = omap44xx_i2c1_addrs,
4960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4961 };
4962
4963 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4964         {
4965                 .pa_start       = 0x48072000,
4966                 .pa_end         = 0x480720ff,
4967                 .flags          = ADDR_TYPE_RT
4968         },
4969         { }
4970 };
4971
4972 /* l4_per -> i2c2 */
4973 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4974         .master         = &omap44xx_l4_per_hwmod,
4975         .slave          = &omap44xx_i2c2_hwmod,
4976         .clk            = "l4_div_ck",
4977         .addr           = omap44xx_i2c2_addrs,
4978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4979 };
4980
4981 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4982         {
4983                 .pa_start       = 0x48060000,
4984                 .pa_end         = 0x480600ff,
4985                 .flags          = ADDR_TYPE_RT
4986         },
4987         { }
4988 };
4989
4990 /* l4_per -> i2c3 */
4991 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4992         .master         = &omap44xx_l4_per_hwmod,
4993         .slave          = &omap44xx_i2c3_hwmod,
4994         .clk            = "l4_div_ck",
4995         .addr           = omap44xx_i2c3_addrs,
4996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4997 };
4998
4999 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5000         {
5001                 .pa_start       = 0x48350000,
5002                 .pa_end         = 0x483500ff,
5003                 .flags          = ADDR_TYPE_RT
5004         },
5005         { }
5006 };
5007
5008 /* l4_per -> i2c4 */
5009 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5010         .master         = &omap44xx_l4_per_hwmod,
5011         .slave          = &omap44xx_i2c4_hwmod,
5012         .clk            = "l4_div_ck",
5013         .addr           = omap44xx_i2c4_addrs,
5014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5015 };
5016
5017 /* l3_main_2 -> ipu */
5018 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5019         .master         = &omap44xx_l3_main_2_hwmod,
5020         .slave          = &omap44xx_ipu_hwmod,
5021         .clk            = "l3_div_ck",
5022         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5023 };
5024
5025 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5026         {
5027                 .pa_start       = 0x52000000,
5028                 .pa_end         = 0x520000ff,
5029                 .flags          = ADDR_TYPE_RT
5030         },
5031         { }
5032 };
5033
5034 /* l3_main_2 -> iss */
5035 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5036         .master         = &omap44xx_l3_main_2_hwmod,
5037         .slave          = &omap44xx_iss_hwmod,
5038         .clk            = "l3_div_ck",
5039         .addr           = omap44xx_iss_addrs,
5040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5041 };
5042
5043 /* iva -> sl2if */
5044 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5045         .master         = &omap44xx_iva_hwmod,
5046         .slave          = &omap44xx_sl2if_hwmod,
5047         .clk            = "dpll_iva_m5x2_ck",
5048         .user           = OCP_USER_IVA,
5049 };
5050
5051 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5052         {
5053                 .pa_start       = 0x5a000000,
5054                 .pa_end         = 0x5a07ffff,
5055                 .flags          = ADDR_TYPE_RT
5056         },
5057         { }
5058 };
5059
5060 /* l3_main_2 -> iva */
5061 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5062         .master         = &omap44xx_l3_main_2_hwmod,
5063         .slave          = &omap44xx_iva_hwmod,
5064         .clk            = "l3_div_ck",
5065         .addr           = omap44xx_iva_addrs,
5066         .user           = OCP_USER_MPU,
5067 };
5068
5069 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5070         {
5071                 .pa_start       = 0x4a31c000,
5072                 .pa_end         = 0x4a31c07f,
5073                 .flags          = ADDR_TYPE_RT
5074         },
5075         { }
5076 };
5077
5078 /* l4_wkup -> kbd */
5079 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5080         .master         = &omap44xx_l4_wkup_hwmod,
5081         .slave          = &omap44xx_kbd_hwmod,
5082         .clk            = "l4_wkup_clk_mux_ck",
5083         .addr           = omap44xx_kbd_addrs,
5084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5085 };
5086
5087 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5088         {
5089                 .pa_start       = 0x4a0f4000,
5090                 .pa_end         = 0x4a0f41ff,
5091                 .flags          = ADDR_TYPE_RT
5092         },
5093         { }
5094 };
5095
5096 /* l4_cfg -> mailbox */
5097 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5098         .master         = &omap44xx_l4_cfg_hwmod,
5099         .slave          = &omap44xx_mailbox_hwmod,
5100         .clk            = "l4_div_ck",
5101         .addr           = omap44xx_mailbox_addrs,
5102         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5103 };
5104
5105 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5106         {
5107                 .pa_start       = 0x40128000,
5108                 .pa_end         = 0x401283ff,
5109                 .flags          = ADDR_TYPE_RT
5110         },
5111         { }
5112 };
5113
5114 /* l4_abe -> mcasp */
5115 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5116         .master         = &omap44xx_l4_abe_hwmod,
5117         .slave          = &omap44xx_mcasp_hwmod,
5118         .clk            = "ocp_abe_iclk",
5119         .addr           = omap44xx_mcasp_addrs,
5120         .user           = OCP_USER_MPU,
5121 };
5122
5123 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5124         {
5125                 .pa_start       = 0x49028000,
5126                 .pa_end         = 0x490283ff,
5127                 .flags          = ADDR_TYPE_RT
5128         },
5129         { }
5130 };
5131
5132 /* l4_abe -> mcasp (dma) */
5133 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5134         .master         = &omap44xx_l4_abe_hwmod,
5135         .slave          = &omap44xx_mcasp_hwmod,
5136         .clk            = "ocp_abe_iclk",
5137         .addr           = omap44xx_mcasp_dma_addrs,
5138         .user           = OCP_USER_SDMA,
5139 };
5140
5141 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5142         {
5143                 .name           = "mpu",
5144                 .pa_start       = 0x40122000,
5145                 .pa_end         = 0x401220ff,
5146                 .flags          = ADDR_TYPE_RT
5147         },
5148         { }
5149 };
5150
5151 /* l4_abe -> mcbsp1 */
5152 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5153         .master         = &omap44xx_l4_abe_hwmod,
5154         .slave          = &omap44xx_mcbsp1_hwmod,
5155         .clk            = "ocp_abe_iclk",
5156         .addr           = omap44xx_mcbsp1_addrs,
5157         .user           = OCP_USER_MPU,
5158 };
5159
5160 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5161         {
5162                 .name           = "dma",
5163                 .pa_start       = 0x49022000,
5164                 .pa_end         = 0x490220ff,
5165                 .flags          = ADDR_TYPE_RT
5166         },
5167         { }
5168 };
5169
5170 /* l4_abe -> mcbsp1 (dma) */
5171 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5172         .master         = &omap44xx_l4_abe_hwmod,
5173         .slave          = &omap44xx_mcbsp1_hwmod,
5174         .clk            = "ocp_abe_iclk",
5175         .addr           = omap44xx_mcbsp1_dma_addrs,
5176         .user           = OCP_USER_SDMA,
5177 };
5178
5179 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5180         {
5181                 .name           = "mpu",
5182                 .pa_start       = 0x40124000,
5183                 .pa_end         = 0x401240ff,
5184                 .flags          = ADDR_TYPE_RT
5185         },
5186         { }
5187 };
5188
5189 /* l4_abe -> mcbsp2 */
5190 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5191         .master         = &omap44xx_l4_abe_hwmod,
5192         .slave          = &omap44xx_mcbsp2_hwmod,
5193         .clk            = "ocp_abe_iclk",
5194         .addr           = omap44xx_mcbsp2_addrs,
5195         .user           = OCP_USER_MPU,
5196 };
5197
5198 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5199         {
5200                 .name           = "dma",
5201                 .pa_start       = 0x49024000,
5202                 .pa_end         = 0x490240ff,
5203                 .flags          = ADDR_TYPE_RT
5204         },
5205         { }
5206 };
5207
5208 /* l4_abe -> mcbsp2 (dma) */
5209 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5210         .master         = &omap44xx_l4_abe_hwmod,
5211         .slave          = &omap44xx_mcbsp2_hwmod,
5212         .clk            = "ocp_abe_iclk",
5213         .addr           = omap44xx_mcbsp2_dma_addrs,
5214         .user           = OCP_USER_SDMA,
5215 };
5216
5217 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5218         {
5219                 .name           = "mpu",
5220                 .pa_start       = 0x40126000,
5221                 .pa_end         = 0x401260ff,
5222                 .flags          = ADDR_TYPE_RT
5223         },
5224         { }
5225 };
5226
5227 /* l4_abe -> mcbsp3 */
5228 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5229         .master         = &omap44xx_l4_abe_hwmod,
5230         .slave          = &omap44xx_mcbsp3_hwmod,
5231         .clk            = "ocp_abe_iclk",
5232         .addr           = omap44xx_mcbsp3_addrs,
5233         .user           = OCP_USER_MPU,
5234 };
5235
5236 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5237         {
5238                 .name           = "dma",
5239                 .pa_start       = 0x49026000,
5240                 .pa_end         = 0x490260ff,
5241                 .flags          = ADDR_TYPE_RT
5242         },
5243         { }
5244 };
5245
5246 /* l4_abe -> mcbsp3 (dma) */
5247 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5248         .master         = &omap44xx_l4_abe_hwmod,
5249         .slave          = &omap44xx_mcbsp3_hwmod,
5250         .clk            = "ocp_abe_iclk",
5251         .addr           = omap44xx_mcbsp3_dma_addrs,
5252         .user           = OCP_USER_SDMA,
5253 };
5254
5255 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5256         {
5257                 .pa_start       = 0x48096000,
5258                 .pa_end         = 0x480960ff,
5259                 .flags          = ADDR_TYPE_RT
5260         },
5261         { }
5262 };
5263
5264 /* l4_per -> mcbsp4 */
5265 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5266         .master         = &omap44xx_l4_per_hwmod,
5267         .slave          = &omap44xx_mcbsp4_hwmod,
5268         .clk            = "l4_div_ck",
5269         .addr           = omap44xx_mcbsp4_addrs,
5270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5271 };
5272
5273 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5274         {
5275                 .name           = "mpu",
5276                 .pa_start       = 0x40132000,
5277                 .pa_end         = 0x4013207f,
5278                 .flags          = ADDR_TYPE_RT
5279         },
5280         { }
5281 };
5282
5283 /* l4_abe -> mcpdm */
5284 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5285         .master         = &omap44xx_l4_abe_hwmod,
5286         .slave          = &omap44xx_mcpdm_hwmod,
5287         .clk            = "ocp_abe_iclk",
5288         .addr           = omap44xx_mcpdm_addrs,
5289         .user           = OCP_USER_MPU,
5290 };
5291
5292 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5293         {
5294                 .name           = "dma",
5295                 .pa_start       = 0x49032000,
5296                 .pa_end         = 0x4903207f,
5297                 .flags          = ADDR_TYPE_RT
5298         },
5299         { }
5300 };
5301
5302 /* l4_abe -> mcpdm (dma) */
5303 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5304         .master         = &omap44xx_l4_abe_hwmod,
5305         .slave          = &omap44xx_mcpdm_hwmod,
5306         .clk            = "ocp_abe_iclk",
5307         .addr           = omap44xx_mcpdm_dma_addrs,
5308         .user           = OCP_USER_SDMA,
5309 };
5310
5311 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5312         {
5313                 .pa_start       = 0x48098000,
5314                 .pa_end         = 0x480981ff,
5315                 .flags          = ADDR_TYPE_RT
5316         },
5317         { }
5318 };
5319
5320 /* l4_per -> mcspi1 */
5321 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5322         .master         = &omap44xx_l4_per_hwmod,
5323         .slave          = &omap44xx_mcspi1_hwmod,
5324         .clk            = "l4_div_ck",
5325         .addr           = omap44xx_mcspi1_addrs,
5326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5327 };
5328
5329 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5330         {
5331                 .pa_start       = 0x4809a000,
5332                 .pa_end         = 0x4809a1ff,
5333                 .flags          = ADDR_TYPE_RT
5334         },
5335         { }
5336 };
5337
5338 /* l4_per -> mcspi2 */
5339 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5340         .master         = &omap44xx_l4_per_hwmod,
5341         .slave          = &omap44xx_mcspi2_hwmod,
5342         .clk            = "l4_div_ck",
5343         .addr           = omap44xx_mcspi2_addrs,
5344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5345 };
5346
5347 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5348         {
5349                 .pa_start       = 0x480b8000,
5350                 .pa_end         = 0x480b81ff,
5351                 .flags          = ADDR_TYPE_RT
5352         },
5353         { }
5354 };
5355
5356 /* l4_per -> mcspi3 */
5357 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5358         .master         = &omap44xx_l4_per_hwmod,
5359         .slave          = &omap44xx_mcspi3_hwmod,
5360         .clk            = "l4_div_ck",
5361         .addr           = omap44xx_mcspi3_addrs,
5362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5363 };
5364
5365 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5366         {
5367                 .pa_start       = 0x480ba000,
5368                 .pa_end         = 0x480ba1ff,
5369                 .flags          = ADDR_TYPE_RT
5370         },
5371         { }
5372 };
5373
5374 /* l4_per -> mcspi4 */
5375 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5376         .master         = &omap44xx_l4_per_hwmod,
5377         .slave          = &omap44xx_mcspi4_hwmod,
5378         .clk            = "l4_div_ck",
5379         .addr           = omap44xx_mcspi4_addrs,
5380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5381 };
5382
5383 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5384         {
5385                 .pa_start       = 0x4809c000,
5386                 .pa_end         = 0x4809c3ff,
5387                 .flags          = ADDR_TYPE_RT
5388         },
5389         { }
5390 };
5391
5392 /* l4_per -> mmc1 */
5393 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5394         .master         = &omap44xx_l4_per_hwmod,
5395         .slave          = &omap44xx_mmc1_hwmod,
5396         .clk            = "l4_div_ck",
5397         .addr           = omap44xx_mmc1_addrs,
5398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5399 };
5400
5401 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5402         {
5403                 .pa_start       = 0x480b4000,
5404                 .pa_end         = 0x480b43ff,
5405                 .flags          = ADDR_TYPE_RT
5406         },
5407         { }
5408 };
5409
5410 /* l4_per -> mmc2 */
5411 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5412         .master         = &omap44xx_l4_per_hwmod,
5413         .slave          = &omap44xx_mmc2_hwmod,
5414         .clk            = "l4_div_ck",
5415         .addr           = omap44xx_mmc2_addrs,
5416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5417 };
5418
5419 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5420         {
5421                 .pa_start       = 0x480ad000,
5422                 .pa_end         = 0x480ad3ff,
5423                 .flags          = ADDR_TYPE_RT
5424         },
5425         { }
5426 };
5427
5428 /* l4_per -> mmc3 */
5429 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5430         .master         = &omap44xx_l4_per_hwmod,
5431         .slave          = &omap44xx_mmc3_hwmod,
5432         .clk            = "l4_div_ck",
5433         .addr           = omap44xx_mmc3_addrs,
5434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5435 };
5436
5437 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5438         {
5439                 .pa_start       = 0x480d1000,
5440                 .pa_end         = 0x480d13ff,
5441                 .flags          = ADDR_TYPE_RT
5442         },
5443         { }
5444 };
5445
5446 /* l4_per -> mmc4 */
5447 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5448         .master         = &omap44xx_l4_per_hwmod,
5449         .slave          = &omap44xx_mmc4_hwmod,
5450         .clk            = "l4_div_ck",
5451         .addr           = omap44xx_mmc4_addrs,
5452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5453 };
5454
5455 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5456         {
5457                 .pa_start       = 0x480d5000,
5458                 .pa_end         = 0x480d53ff,
5459                 .flags          = ADDR_TYPE_RT
5460         },
5461         { }
5462 };
5463
5464 /* l4_per -> mmc5 */
5465 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5466         .master         = &omap44xx_l4_per_hwmod,
5467         .slave          = &omap44xx_mmc5_hwmod,
5468         .clk            = "l4_div_ck",
5469         .addr           = omap44xx_mmc5_addrs,
5470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5471 };
5472
5473 /* l3_main_2 -> ocmc_ram */
5474 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5475         .master         = &omap44xx_l3_main_2_hwmod,
5476         .slave          = &omap44xx_ocmc_ram_hwmod,
5477         .clk            = "l3_div_ck",
5478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5479 };
5480
5481 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5482         {
5483                 .pa_start       = 0x4a0ad000,
5484                 .pa_end         = 0x4a0ad01f,
5485                 .flags          = ADDR_TYPE_RT
5486         },
5487         { }
5488 };
5489
5490 /* l4_cfg -> ocp2scp_usb_phy */
5491 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5492         .master         = &omap44xx_l4_cfg_hwmod,
5493         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5494         .clk            = "l4_div_ck",
5495         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5497 };
5498
5499 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5500         {
5501                 .pa_start       = 0x48243000,
5502                 .pa_end         = 0x48243fff,
5503                 .flags          = ADDR_TYPE_RT
5504         },
5505         { }
5506 };
5507
5508 /* mpu_private -> prcm_mpu */
5509 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5510         .master         = &omap44xx_mpu_private_hwmod,
5511         .slave          = &omap44xx_prcm_mpu_hwmod,
5512         .clk            = "l3_div_ck",
5513         .addr           = omap44xx_prcm_mpu_addrs,
5514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5515 };
5516
5517 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5518         {
5519                 .pa_start       = 0x4a004000,
5520                 .pa_end         = 0x4a004fff,
5521                 .flags          = ADDR_TYPE_RT
5522         },
5523         { }
5524 };
5525
5526 /* l4_wkup -> cm_core_aon */
5527 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5528         .master         = &omap44xx_l4_wkup_hwmod,
5529         .slave          = &omap44xx_cm_core_aon_hwmod,
5530         .clk            = "l4_wkup_clk_mux_ck",
5531         .addr           = omap44xx_cm_core_aon_addrs,
5532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5533 };
5534
5535 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5536         {
5537                 .pa_start       = 0x4a008000,
5538                 .pa_end         = 0x4a009fff,
5539                 .flags          = ADDR_TYPE_RT
5540         },
5541         { }
5542 };
5543
5544 /* l4_cfg -> cm_core */
5545 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5546         .master         = &omap44xx_l4_cfg_hwmod,
5547         .slave          = &omap44xx_cm_core_hwmod,
5548         .clk            = "l4_div_ck",
5549         .addr           = omap44xx_cm_core_addrs,
5550         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5551 };
5552
5553 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5554         {
5555                 .pa_start       = 0x4a306000,
5556                 .pa_end         = 0x4a307fff,
5557                 .flags          = ADDR_TYPE_RT
5558         },
5559         { }
5560 };
5561
5562 /* l4_wkup -> prm */
5563 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5564         .master         = &omap44xx_l4_wkup_hwmod,
5565         .slave          = &omap44xx_prm_hwmod,
5566         .clk            = "l4_wkup_clk_mux_ck",
5567         .addr           = omap44xx_prm_addrs,
5568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5569 };
5570
5571 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5572         {
5573                 .pa_start       = 0x4a30a000,
5574                 .pa_end         = 0x4a30a7ff,
5575                 .flags          = ADDR_TYPE_RT
5576         },
5577         { }
5578 };
5579
5580 /* l4_wkup -> scrm */
5581 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5582         .master         = &omap44xx_l4_wkup_hwmod,
5583         .slave          = &omap44xx_scrm_hwmod,
5584         .clk            = "l4_wkup_clk_mux_ck",
5585         .addr           = omap44xx_scrm_addrs,
5586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5587 };
5588
5589 /* l3_main_2 -> sl2if */
5590 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5591         .master         = &omap44xx_l3_main_2_hwmod,
5592         .slave          = &omap44xx_sl2if_hwmod,
5593         .clk            = "l3_div_ck",
5594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5595 };
5596
5597 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5598         {
5599                 .pa_start       = 0x4012c000,
5600                 .pa_end         = 0x4012c3ff,
5601                 .flags          = ADDR_TYPE_RT
5602         },
5603         { }
5604 };
5605
5606 /* l4_abe -> slimbus1 */
5607 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5608         .master         = &omap44xx_l4_abe_hwmod,
5609         .slave          = &omap44xx_slimbus1_hwmod,
5610         .clk            = "ocp_abe_iclk",
5611         .addr           = omap44xx_slimbus1_addrs,
5612         .user           = OCP_USER_MPU,
5613 };
5614
5615 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5616         {
5617                 .pa_start       = 0x4902c000,
5618                 .pa_end         = 0x4902c3ff,
5619                 .flags          = ADDR_TYPE_RT
5620         },
5621         { }
5622 };
5623
5624 /* l4_abe -> slimbus1 (dma) */
5625 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5626         .master         = &omap44xx_l4_abe_hwmod,
5627         .slave          = &omap44xx_slimbus1_hwmod,
5628         .clk            = "ocp_abe_iclk",
5629         .addr           = omap44xx_slimbus1_dma_addrs,
5630         .user           = OCP_USER_SDMA,
5631 };
5632
5633 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5634         {
5635                 .pa_start       = 0x48076000,
5636                 .pa_end         = 0x480763ff,
5637                 .flags          = ADDR_TYPE_RT
5638         },
5639         { }
5640 };
5641
5642 /* l4_per -> slimbus2 */
5643 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5644         .master         = &omap44xx_l4_per_hwmod,
5645         .slave          = &omap44xx_slimbus2_hwmod,
5646         .clk            = "l4_div_ck",
5647         .addr           = omap44xx_slimbus2_addrs,
5648         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5649 };
5650
5651 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5652         {
5653                 .pa_start       = 0x4a0dd000,
5654                 .pa_end         = 0x4a0dd03f,
5655                 .flags          = ADDR_TYPE_RT
5656         },
5657         { }
5658 };
5659
5660 /* l4_cfg -> smartreflex_core */
5661 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5662         .master         = &omap44xx_l4_cfg_hwmod,
5663         .slave          = &omap44xx_smartreflex_core_hwmod,
5664         .clk            = "l4_div_ck",
5665         .addr           = omap44xx_smartreflex_core_addrs,
5666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5667 };
5668
5669 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5670         {
5671                 .pa_start       = 0x4a0db000,
5672                 .pa_end         = 0x4a0db03f,
5673                 .flags          = ADDR_TYPE_RT
5674         },
5675         { }
5676 };
5677
5678 /* l4_cfg -> smartreflex_iva */
5679 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5680         .master         = &omap44xx_l4_cfg_hwmod,
5681         .slave          = &omap44xx_smartreflex_iva_hwmod,
5682         .clk            = "l4_div_ck",
5683         .addr           = omap44xx_smartreflex_iva_addrs,
5684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5685 };
5686
5687 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5688         {
5689                 .pa_start       = 0x4a0d9000,
5690                 .pa_end         = 0x4a0d903f,
5691                 .flags          = ADDR_TYPE_RT
5692         },
5693         { }
5694 };
5695
5696 /* l4_cfg -> smartreflex_mpu */
5697 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5698         .master         = &omap44xx_l4_cfg_hwmod,
5699         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5700         .clk            = "l4_div_ck",
5701         .addr           = omap44xx_smartreflex_mpu_addrs,
5702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5703 };
5704
5705 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5706         {
5707                 .pa_start       = 0x4a0f6000,
5708                 .pa_end         = 0x4a0f6fff,
5709                 .flags          = ADDR_TYPE_RT
5710         },
5711         { }
5712 };
5713
5714 /* l4_cfg -> spinlock */
5715 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5716         .master         = &omap44xx_l4_cfg_hwmod,
5717         .slave          = &omap44xx_spinlock_hwmod,
5718         .clk            = "l4_div_ck",
5719         .addr           = omap44xx_spinlock_addrs,
5720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5721 };
5722
5723 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5724         {
5725                 .pa_start       = 0x4a318000,
5726                 .pa_end         = 0x4a31807f,
5727                 .flags          = ADDR_TYPE_RT
5728         },
5729         { }
5730 };
5731
5732 /* l4_wkup -> timer1 */
5733 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5734         .master         = &omap44xx_l4_wkup_hwmod,
5735         .slave          = &omap44xx_timer1_hwmod,
5736         .clk            = "l4_wkup_clk_mux_ck",
5737         .addr           = omap44xx_timer1_addrs,
5738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5739 };
5740
5741 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5742         {
5743                 .pa_start       = 0x48032000,
5744                 .pa_end         = 0x4803207f,
5745                 .flags          = ADDR_TYPE_RT
5746         },
5747         { }
5748 };
5749
5750 /* l4_per -> timer2 */
5751 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5752         .master         = &omap44xx_l4_per_hwmod,
5753         .slave          = &omap44xx_timer2_hwmod,
5754         .clk            = "l4_div_ck",
5755         .addr           = omap44xx_timer2_addrs,
5756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5757 };
5758
5759 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5760         {
5761                 .pa_start       = 0x48034000,
5762                 .pa_end         = 0x4803407f,
5763                 .flags          = ADDR_TYPE_RT
5764         },
5765         { }
5766 };
5767
5768 /* l4_per -> timer3 */
5769 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5770         .master         = &omap44xx_l4_per_hwmod,
5771         .slave          = &omap44xx_timer3_hwmod,
5772         .clk            = "l4_div_ck",
5773         .addr           = omap44xx_timer3_addrs,
5774         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5775 };
5776
5777 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5778         {
5779                 .pa_start       = 0x48036000,
5780                 .pa_end         = 0x4803607f,
5781                 .flags          = ADDR_TYPE_RT
5782         },
5783         { }
5784 };
5785
5786 /* l4_per -> timer4 */
5787 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5788         .master         = &omap44xx_l4_per_hwmod,
5789         .slave          = &omap44xx_timer4_hwmod,
5790         .clk            = "l4_div_ck",
5791         .addr           = omap44xx_timer4_addrs,
5792         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5793 };
5794
5795 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5796         {
5797                 .pa_start       = 0x40138000,
5798                 .pa_end         = 0x4013807f,
5799                 .flags          = ADDR_TYPE_RT
5800         },
5801         { }
5802 };
5803
5804 /* l4_abe -> timer5 */
5805 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5806         .master         = &omap44xx_l4_abe_hwmod,
5807         .slave          = &omap44xx_timer5_hwmod,
5808         .clk            = "ocp_abe_iclk",
5809         .addr           = omap44xx_timer5_addrs,
5810         .user           = OCP_USER_MPU,
5811 };
5812
5813 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5814         {
5815                 .pa_start       = 0x49038000,
5816                 .pa_end         = 0x4903807f,
5817                 .flags          = ADDR_TYPE_RT
5818         },
5819         { }
5820 };
5821
5822 /* l4_abe -> timer5 (dma) */
5823 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5824         .master         = &omap44xx_l4_abe_hwmod,
5825         .slave          = &omap44xx_timer5_hwmod,
5826         .clk            = "ocp_abe_iclk",
5827         .addr           = omap44xx_timer5_dma_addrs,
5828         .user           = OCP_USER_SDMA,
5829 };
5830
5831 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5832         {
5833                 .pa_start       = 0x4013a000,
5834                 .pa_end         = 0x4013a07f,
5835                 .flags          = ADDR_TYPE_RT
5836         },
5837         { }
5838 };
5839
5840 /* l4_abe -> timer6 */
5841 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5842         .master         = &omap44xx_l4_abe_hwmod,
5843         .slave          = &omap44xx_timer6_hwmod,
5844         .clk            = "ocp_abe_iclk",
5845         .addr           = omap44xx_timer6_addrs,
5846         .user           = OCP_USER_MPU,
5847 };
5848
5849 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5850         {
5851                 .pa_start       = 0x4903a000,
5852                 .pa_end         = 0x4903a07f,
5853                 .flags          = ADDR_TYPE_RT
5854         },
5855         { }
5856 };
5857
5858 /* l4_abe -> timer6 (dma) */
5859 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5860         .master         = &omap44xx_l4_abe_hwmod,
5861         .slave          = &omap44xx_timer6_hwmod,
5862         .clk            = "ocp_abe_iclk",
5863         .addr           = omap44xx_timer6_dma_addrs,
5864         .user           = OCP_USER_SDMA,
5865 };
5866
5867 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5868         {
5869                 .pa_start       = 0x4013c000,
5870                 .pa_end         = 0x4013c07f,
5871                 .flags          = ADDR_TYPE_RT
5872         },
5873         { }
5874 };
5875
5876 /* l4_abe -> timer7 */
5877 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5878         .master         = &omap44xx_l4_abe_hwmod,
5879         .slave          = &omap44xx_timer7_hwmod,
5880         .clk            = "ocp_abe_iclk",
5881         .addr           = omap44xx_timer7_addrs,
5882         .user           = OCP_USER_MPU,
5883 };
5884
5885 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5886         {
5887                 .pa_start       = 0x4903c000,
5888                 .pa_end         = 0x4903c07f,
5889                 .flags          = ADDR_TYPE_RT
5890         },
5891         { }
5892 };
5893
5894 /* l4_abe -> timer7 (dma) */
5895 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5896         .master         = &omap44xx_l4_abe_hwmod,
5897         .slave          = &omap44xx_timer7_hwmod,
5898         .clk            = "ocp_abe_iclk",
5899         .addr           = omap44xx_timer7_dma_addrs,
5900         .user           = OCP_USER_SDMA,
5901 };
5902
5903 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5904         {
5905                 .pa_start       = 0x4013e000,
5906                 .pa_end         = 0x4013e07f,
5907                 .flags          = ADDR_TYPE_RT
5908         },
5909         { }
5910 };
5911
5912 /* l4_abe -> timer8 */
5913 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5914         .master         = &omap44xx_l4_abe_hwmod,
5915         .slave          = &omap44xx_timer8_hwmod,
5916         .clk            = "ocp_abe_iclk",
5917         .addr           = omap44xx_timer8_addrs,
5918         .user           = OCP_USER_MPU,
5919 };
5920
5921 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5922         {
5923                 .pa_start       = 0x4903e000,
5924                 .pa_end         = 0x4903e07f,
5925                 .flags          = ADDR_TYPE_RT
5926         },
5927         { }
5928 };
5929
5930 /* l4_abe -> timer8 (dma) */
5931 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5932         .master         = &omap44xx_l4_abe_hwmod,
5933         .slave          = &omap44xx_timer8_hwmod,
5934         .clk            = "ocp_abe_iclk",
5935         .addr           = omap44xx_timer8_dma_addrs,
5936         .user           = OCP_USER_SDMA,
5937 };
5938
5939 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5940         {
5941                 .pa_start       = 0x4803e000,
5942                 .pa_end         = 0x4803e07f,
5943                 .flags          = ADDR_TYPE_RT
5944         },
5945         { }
5946 };
5947
5948 /* l4_per -> timer9 */
5949 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5950         .master         = &omap44xx_l4_per_hwmod,
5951         .slave          = &omap44xx_timer9_hwmod,
5952         .clk            = "l4_div_ck",
5953         .addr           = omap44xx_timer9_addrs,
5954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5955 };
5956
5957 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5958         {
5959                 .pa_start       = 0x48086000,
5960                 .pa_end         = 0x4808607f,
5961                 .flags          = ADDR_TYPE_RT
5962         },
5963         { }
5964 };
5965
5966 /* l4_per -> timer10 */
5967 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5968         .master         = &omap44xx_l4_per_hwmod,
5969         .slave          = &omap44xx_timer10_hwmod,
5970         .clk            = "l4_div_ck",
5971         .addr           = omap44xx_timer10_addrs,
5972         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5973 };
5974
5975 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5976         {
5977                 .pa_start       = 0x48088000,
5978                 .pa_end         = 0x4808807f,
5979                 .flags          = ADDR_TYPE_RT
5980         },
5981         { }
5982 };
5983
5984 /* l4_per -> timer11 */
5985 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5986         .master         = &omap44xx_l4_per_hwmod,
5987         .slave          = &omap44xx_timer11_hwmod,
5988         .clk            = "l4_div_ck",
5989         .addr           = omap44xx_timer11_addrs,
5990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5991 };
5992
5993 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5994         {
5995                 .pa_start       = 0x4806a000,
5996                 .pa_end         = 0x4806a0ff,
5997                 .flags          = ADDR_TYPE_RT
5998         },
5999         { }
6000 };
6001
6002 /* l4_per -> uart1 */
6003 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6004         .master         = &omap44xx_l4_per_hwmod,
6005         .slave          = &omap44xx_uart1_hwmod,
6006         .clk            = "l4_div_ck",
6007         .addr           = omap44xx_uart1_addrs,
6008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6009 };
6010
6011 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6012         {
6013                 .pa_start       = 0x4806c000,
6014                 .pa_end         = 0x4806c0ff,
6015                 .flags          = ADDR_TYPE_RT
6016         },
6017         { }
6018 };
6019
6020 /* l4_per -> uart2 */
6021 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6022         .master         = &omap44xx_l4_per_hwmod,
6023         .slave          = &omap44xx_uart2_hwmod,
6024         .clk            = "l4_div_ck",
6025         .addr           = omap44xx_uart2_addrs,
6026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6027 };
6028
6029 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6030         {
6031                 .pa_start       = 0x48020000,
6032                 .pa_end         = 0x480200ff,
6033                 .flags          = ADDR_TYPE_RT
6034         },
6035         { }
6036 };
6037
6038 /* l4_per -> uart3 */
6039 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6040         .master         = &omap44xx_l4_per_hwmod,
6041         .slave          = &omap44xx_uart3_hwmod,
6042         .clk            = "l4_div_ck",
6043         .addr           = omap44xx_uart3_addrs,
6044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6045 };
6046
6047 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6048         {
6049                 .pa_start       = 0x4806e000,
6050                 .pa_end         = 0x4806e0ff,
6051                 .flags          = ADDR_TYPE_RT
6052         },
6053         { }
6054 };
6055
6056 /* l4_per -> uart4 */
6057 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6058         .master         = &omap44xx_l4_per_hwmod,
6059         .slave          = &omap44xx_uart4_hwmod,
6060         .clk            = "l4_div_ck",
6061         .addr           = omap44xx_uart4_addrs,
6062         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6063 };
6064
6065 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6066         {
6067                 .pa_start       = 0x4a0a9000,
6068                 .pa_end         = 0x4a0a93ff,
6069                 .flags          = ADDR_TYPE_RT
6070         },
6071         { }
6072 };
6073
6074 /* l4_cfg -> usb_host_fs */
6075 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6076         .master         = &omap44xx_l4_cfg_hwmod,
6077         .slave          = &omap44xx_usb_host_fs_hwmod,
6078         .clk            = "l4_div_ck",
6079         .addr           = omap44xx_usb_host_fs_addrs,
6080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6081 };
6082
6083 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6084         {
6085                 .name           = "uhh",
6086                 .pa_start       = 0x4a064000,
6087                 .pa_end         = 0x4a0647ff,
6088                 .flags          = ADDR_TYPE_RT
6089         },
6090         {
6091                 .name           = "ohci",
6092                 .pa_start       = 0x4a064800,
6093                 .pa_end         = 0x4a064bff,
6094         },
6095         {
6096                 .name           = "ehci",
6097                 .pa_start       = 0x4a064c00,
6098                 .pa_end         = 0x4a064fff,
6099         },
6100         {}
6101 };
6102
6103 /* l4_cfg -> usb_host_hs */
6104 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6105         .master         = &omap44xx_l4_cfg_hwmod,
6106         .slave          = &omap44xx_usb_host_hs_hwmod,
6107         .clk            = "l4_div_ck",
6108         .addr           = omap44xx_usb_host_hs_addrs,
6109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6110 };
6111
6112 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6113         {
6114                 .pa_start       = 0x4a0ab000,
6115                 .pa_end         = 0x4a0ab7ff,
6116                 .flags          = ADDR_TYPE_RT
6117         },
6118         {
6119                 /* XXX: Remove this once control module driver is in place */
6120                 .pa_start       = 0x4a00233c,
6121                 .pa_end         = 0x4a00233f,
6122                 .flags          = ADDR_TYPE_RT
6123         },
6124         { }
6125 };
6126
6127 /* l4_cfg -> usb_otg_hs */
6128 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6129         .master         = &omap44xx_l4_cfg_hwmod,
6130         .slave          = &omap44xx_usb_otg_hs_hwmod,
6131         .clk            = "l4_div_ck",
6132         .addr           = omap44xx_usb_otg_hs_addrs,
6133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6134 };
6135
6136 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6137         {
6138                 .name           = "tll",
6139                 .pa_start       = 0x4a062000,
6140                 .pa_end         = 0x4a063fff,
6141                 .flags          = ADDR_TYPE_RT
6142         },
6143         {}
6144 };
6145
6146 /* l4_cfg -> usb_tll_hs */
6147 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6148         .master         = &omap44xx_l4_cfg_hwmod,
6149         .slave          = &omap44xx_usb_tll_hs_hwmod,
6150         .clk            = "l4_div_ck",
6151         .addr           = omap44xx_usb_tll_hs_addrs,
6152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6153 };
6154
6155 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6156         {
6157                 .pa_start       = 0x4a314000,
6158                 .pa_end         = 0x4a31407f,
6159                 .flags          = ADDR_TYPE_RT
6160         },
6161         { }
6162 };
6163
6164 /* l4_wkup -> wd_timer2 */
6165 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6166         .master         = &omap44xx_l4_wkup_hwmod,
6167         .slave          = &omap44xx_wd_timer2_hwmod,
6168         .clk            = "l4_wkup_clk_mux_ck",
6169         .addr           = omap44xx_wd_timer2_addrs,
6170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6171 };
6172
6173 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6174         {
6175                 .pa_start       = 0x40130000,
6176                 .pa_end         = 0x4013007f,
6177                 .flags          = ADDR_TYPE_RT
6178         },
6179         { }
6180 };
6181
6182 /* l4_abe -> wd_timer3 */
6183 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6184         .master         = &omap44xx_l4_abe_hwmod,
6185         .slave          = &omap44xx_wd_timer3_hwmod,
6186         .clk            = "ocp_abe_iclk",
6187         .addr           = omap44xx_wd_timer3_addrs,
6188         .user           = OCP_USER_MPU,
6189 };
6190
6191 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6192         {
6193                 .pa_start       = 0x49030000,
6194                 .pa_end         = 0x4903007f,
6195                 .flags          = ADDR_TYPE_RT
6196         },
6197         { }
6198 };
6199
6200 /* l4_abe -> wd_timer3 (dma) */
6201 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6202         .master         = &omap44xx_l4_abe_hwmod,
6203         .slave          = &omap44xx_wd_timer3_hwmod,
6204         .clk            = "ocp_abe_iclk",
6205         .addr           = omap44xx_wd_timer3_dma_addrs,
6206         .user           = OCP_USER_SDMA,
6207 };
6208
6209 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6210         &omap44xx_c2c__c2c_target_fw,
6211         &omap44xx_l4_cfg__c2c_target_fw,
6212         &omap44xx_l3_main_1__dmm,
6213         &omap44xx_mpu__dmm,
6214         &omap44xx_c2c__emif_fw,
6215         &omap44xx_dmm__emif_fw,
6216         &omap44xx_l4_cfg__emif_fw,
6217         &omap44xx_iva__l3_instr,
6218         &omap44xx_l3_main_3__l3_instr,
6219         &omap44xx_ocp_wp_noc__l3_instr,
6220         &omap44xx_dsp__l3_main_1,
6221         &omap44xx_dss__l3_main_1,
6222         &omap44xx_l3_main_2__l3_main_1,
6223         &omap44xx_l4_cfg__l3_main_1,
6224         &omap44xx_mmc1__l3_main_1,
6225         &omap44xx_mmc2__l3_main_1,
6226         &omap44xx_mpu__l3_main_1,
6227         &omap44xx_c2c_target_fw__l3_main_2,
6228         &omap44xx_debugss__l3_main_2,
6229         &omap44xx_dma_system__l3_main_2,
6230         &omap44xx_fdif__l3_main_2,
6231         &omap44xx_gpu__l3_main_2,
6232         &omap44xx_hsi__l3_main_2,
6233         &omap44xx_ipu__l3_main_2,
6234         &omap44xx_iss__l3_main_2,
6235         &omap44xx_iva__l3_main_2,
6236         &omap44xx_l3_main_1__l3_main_2,
6237         &omap44xx_l4_cfg__l3_main_2,
6238         /* &omap44xx_usb_host_fs__l3_main_2, */
6239         &omap44xx_usb_host_hs__l3_main_2,
6240         &omap44xx_usb_otg_hs__l3_main_2,
6241         &omap44xx_l3_main_1__l3_main_3,
6242         &omap44xx_l3_main_2__l3_main_3,
6243         &omap44xx_l4_cfg__l3_main_3,
6244         /* &omap44xx_aess__l4_abe, */
6245         &omap44xx_dsp__l4_abe,
6246         &omap44xx_l3_main_1__l4_abe,
6247         &omap44xx_mpu__l4_abe,
6248         &omap44xx_l3_main_1__l4_cfg,
6249         &omap44xx_l3_main_2__l4_per,
6250         &omap44xx_l4_cfg__l4_wkup,
6251         &omap44xx_mpu__mpu_private,
6252         &omap44xx_l4_cfg__ocp_wp_noc,
6253         /* &omap44xx_l4_abe__aess, */
6254         /* &omap44xx_l4_abe__aess_dma, */
6255         &omap44xx_l3_main_2__c2c,
6256         &omap44xx_l4_wkup__counter_32k,
6257         &omap44xx_l4_cfg__ctrl_module_core,
6258         &omap44xx_l4_cfg__ctrl_module_pad_core,
6259         &omap44xx_l4_wkup__ctrl_module_wkup,
6260         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6261         &omap44xx_l3_instr__debugss,
6262         &omap44xx_l4_cfg__dma_system,
6263         &omap44xx_l4_abe__dmic,
6264         &omap44xx_l4_abe__dmic_dma,
6265         &omap44xx_dsp__iva,
6266         /* &omap44xx_dsp__sl2if, */
6267         &omap44xx_l4_cfg__dsp,
6268         &omap44xx_l3_main_2__dss,
6269         &omap44xx_l4_per__dss,
6270         &omap44xx_l3_main_2__dss_dispc,
6271         &omap44xx_l4_per__dss_dispc,
6272         &omap44xx_l3_main_2__dss_dsi1,
6273         &omap44xx_l4_per__dss_dsi1,
6274         &omap44xx_l3_main_2__dss_dsi2,
6275         &omap44xx_l4_per__dss_dsi2,
6276         &omap44xx_l3_main_2__dss_hdmi,
6277         &omap44xx_l4_per__dss_hdmi,
6278         &omap44xx_l3_main_2__dss_rfbi,
6279         &omap44xx_l4_per__dss_rfbi,
6280         &omap44xx_l3_main_2__dss_venc,
6281         &omap44xx_l4_per__dss_venc,
6282         &omap44xx_l4_per__elm,
6283         &omap44xx_emif_fw__emif1,
6284         &omap44xx_emif_fw__emif2,
6285         &omap44xx_l4_cfg__fdif,
6286         &omap44xx_l4_wkup__gpio1,
6287         &omap44xx_l4_per__gpio2,
6288         &omap44xx_l4_per__gpio3,
6289         &omap44xx_l4_per__gpio4,
6290         &omap44xx_l4_per__gpio5,
6291         &omap44xx_l4_per__gpio6,
6292         &omap44xx_l3_main_2__gpmc,
6293         &omap44xx_l3_main_2__gpu,
6294         &omap44xx_l4_per__hdq1w,
6295         &omap44xx_l4_cfg__hsi,
6296         &omap44xx_l4_per__i2c1,
6297         &omap44xx_l4_per__i2c2,
6298         &omap44xx_l4_per__i2c3,
6299         &omap44xx_l4_per__i2c4,
6300         &omap44xx_l3_main_2__ipu,
6301         &omap44xx_l3_main_2__iss,
6302         /* &omap44xx_iva__sl2if, */
6303         &omap44xx_l3_main_2__iva,
6304         &omap44xx_l4_wkup__kbd,
6305         &omap44xx_l4_cfg__mailbox,
6306         &omap44xx_l4_abe__mcasp,
6307         &omap44xx_l4_abe__mcasp_dma,
6308         &omap44xx_l4_abe__mcbsp1,
6309         &omap44xx_l4_abe__mcbsp1_dma,
6310         &omap44xx_l4_abe__mcbsp2,
6311         &omap44xx_l4_abe__mcbsp2_dma,
6312         &omap44xx_l4_abe__mcbsp3,
6313         &omap44xx_l4_abe__mcbsp3_dma,
6314         &omap44xx_l4_per__mcbsp4,
6315         &omap44xx_l4_abe__mcpdm,
6316         &omap44xx_l4_abe__mcpdm_dma,
6317         &omap44xx_l4_per__mcspi1,
6318         &omap44xx_l4_per__mcspi2,
6319         &omap44xx_l4_per__mcspi3,
6320         &omap44xx_l4_per__mcspi4,
6321         &omap44xx_l4_per__mmc1,
6322         &omap44xx_l4_per__mmc2,
6323         &omap44xx_l4_per__mmc3,
6324         &omap44xx_l4_per__mmc4,
6325         &omap44xx_l4_per__mmc5,
6326         &omap44xx_l3_main_2__mmu_ipu,
6327         &omap44xx_l4_cfg__mmu_dsp,
6328         &omap44xx_l3_main_2__ocmc_ram,
6329         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6330         &omap44xx_mpu_private__prcm_mpu,
6331         &omap44xx_l4_wkup__cm_core_aon,
6332         &omap44xx_l4_cfg__cm_core,
6333         &omap44xx_l4_wkup__prm,
6334         &omap44xx_l4_wkup__scrm,
6335         /* &omap44xx_l3_main_2__sl2if, */
6336         &omap44xx_l4_abe__slimbus1,
6337         &omap44xx_l4_abe__slimbus1_dma,
6338         &omap44xx_l4_per__slimbus2,
6339         &omap44xx_l4_cfg__smartreflex_core,
6340         &omap44xx_l4_cfg__smartreflex_iva,
6341         &omap44xx_l4_cfg__smartreflex_mpu,
6342         &omap44xx_l4_cfg__spinlock,
6343         &omap44xx_l4_wkup__timer1,
6344         &omap44xx_l4_per__timer2,
6345         &omap44xx_l4_per__timer3,
6346         &omap44xx_l4_per__timer4,
6347         &omap44xx_l4_abe__timer5,
6348         &omap44xx_l4_abe__timer5_dma,
6349         &omap44xx_l4_abe__timer6,
6350         &omap44xx_l4_abe__timer6_dma,
6351         &omap44xx_l4_abe__timer7,
6352         &omap44xx_l4_abe__timer7_dma,
6353         &omap44xx_l4_abe__timer8,
6354         &omap44xx_l4_abe__timer8_dma,
6355         &omap44xx_l4_per__timer9,
6356         &omap44xx_l4_per__timer10,
6357         &omap44xx_l4_per__timer11,
6358         &omap44xx_l4_per__uart1,
6359         &omap44xx_l4_per__uart2,
6360         &omap44xx_l4_per__uart3,
6361         &omap44xx_l4_per__uart4,
6362         /* &omap44xx_l4_cfg__usb_host_fs, */
6363         &omap44xx_l4_cfg__usb_host_hs,
6364         &omap44xx_l4_cfg__usb_otg_hs,
6365         &omap44xx_l4_cfg__usb_tll_hs,
6366         &omap44xx_l4_wkup__wd_timer2,
6367         &omap44xx_l4_abe__wd_timer3,
6368         &omap44xx_l4_abe__wd_timer3_dma,
6369         NULL,
6370 };
6371
6372 int __init omap44xx_hwmod_init(void)
6373 {
6374         omap_hwmod_init();
6375         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6376 }
6377