arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <plat-omap/dma-omap.h>
  27
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30 #include <plat/dmtimer.h>
  31 #include <plat/iommu.h>
  32
  33 #include "omap_hwmod.h"
  34 #include "omap_hwmod_common_data.h"
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "i2c.h"
  40 #include "mmc.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 208                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 209                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 210                 },
 211         },
 212 };
 213
 214 /* l4_cfg */
 215 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 216         .name           = "l4_cfg",
 217         .class          = &omap44xx_l4_hwmod_class,
 218         .clkdm_name     = "l4_cfg_clkdm",
 219         .prcm = {
 220                 .omap4 = {
 221                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 222                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 223                 },
 224         },
 225 };
 226
 227 /* l4_per */
 228 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 229         .name           = "l4_per",
 230         .class          = &omap44xx_l4_hwmod_class,
 231         .clkdm_name     = "l4_per_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 236                 },
 237         },
 238 };
 239
 240 /* l4_wkup */
 241 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 242         .name           = "l4_wkup",
 243         .class          = &omap44xx_l4_hwmod_class,
 244         .clkdm_name     = "l4_wkup_clkdm",
 245         .prcm = {
 246                 .omap4 = {
 247                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 248                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 249                 },
 250         },
 251 };
 252
 253 /*
 254  * 'mpu_bus' class
 255  * instance(s): mpu_private
 256  */
 257 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 258         .name   = "mpu_bus",
 259 };
 260
 261 /* mpu_private */
 262 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 263         .name           = "mpu_private",
 264         .class          = &omap44xx_mpu_bus_hwmod_class,
 265         .clkdm_name     = "mpuss_clkdm",
 266         .prcm = {
 267                 .omap4 = {
 268                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 269                 },
 270         },
 271 };
 272
 273 /*
 274  * 'ocp_wp_noc' class
 275  * instance(s): ocp_wp_noc
 276  */
 277 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 278         .name   = "ocp_wp_noc",
 279 };
 280
 281 /* ocp_wp_noc */
 282 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 283         .name           = "ocp_wp_noc",
 284         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 285         .clkdm_name     = "l3_instr_clkdm",
 286         .prcm = {
 287                 .omap4 = {
 288                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 289                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 290                         .modulemode   = MODULEMODE_HWCTRL,
 291                 },
 292         },
 293 };
 294
 295 /*
 296  * Modules omap_hwmod structures
 297  *
 298  * The following IPs are excluded for the moment because:
 299  * - They do not need an explicit SW control using omap_hwmod API.
 300  * - They still need to be validated with the driver
 301  *   properly adapted to omap_hwmod / omap_device
 302  *
 303  * usim
 304  */
 305
 306 /*
 307  * 'aess' class
 308  * audio engine sub system
 309  */
 310
 311 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 312         .rev_offs       = 0x0000,
 313         .sysc_offs      = 0x0010,
 314         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 315         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 316                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 317                            MSTANDBY_SMART_WKUP),
 318         .sysc_fields    = &omap_hwmod_sysc_type2,
 319 };
 320
 321 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 322         .name   = "aess",
 323         .sysc   = &omap44xx_aess_sysc,
 324 };
 325
 326 /* aess */
 327 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 328         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 329         { .irq = -1 }
 330 };
 331
 332 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 333         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 334         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 341         { .dma_req = -1 }
 342 };
 343
 344 static struct omap_hwmod omap44xx_aess_hwmod = {
 345         .name           = "aess",
 346         .class          = &omap44xx_aess_hwmod_class,
 347         .clkdm_name     = "abe_clkdm",
 348         .mpu_irqs       = omap44xx_aess_irqs,
 349         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 350         .main_clk       = "aess_fck",
 351         .prcm = {
 352                 .omap4 = {
 353                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 354                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 355                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 356                         .modulemode   = MODULEMODE_SWCTRL,
 357                 },
 358         },
 359 };
 360
 361 /*
 362  * 'c2c' class
 363  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 364  * soc
 365  */
 366
 367 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 368         .name   = "c2c",
 369 };
 370
 371 /* c2c */
 372 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 373         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 374         { .irq = -1 }
 375 };
 376
 377 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 378         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 379         { .dma_req = -1 }
 380 };
 381
 382 static struct omap_hwmod omap44xx_c2c_hwmod = {
 383         .name           = "c2c",
 384         .class          = &omap44xx_c2c_hwmod_class,
 385         .clkdm_name     = "d2d_clkdm",
 386         .mpu_irqs       = omap44xx_c2c_irqs,
 387         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 388         .prcm = {
 389                 .omap4 = {
 390                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 391                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 392                 },
 393         },
 394 };
 395
 396 /*
 397  * 'counter' class
 398  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 399  */
 400
 401 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 402         .rev_offs       = 0x0000,
 403         .sysc_offs      = 0x0004,
 404         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 405         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 406         .sysc_fields    = &omap_hwmod_sysc_type1,
 407 };
 408
 409 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 410         .name   = "counter",
 411         .sysc   = &omap44xx_counter_sysc,
 412 };
 413
 414 /* counter_32k */
 415 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 416         .name           = "counter_32k",
 417         .class          = &omap44xx_counter_hwmod_class,
 418         .clkdm_name     = "l4_wkup_clkdm",
 419         .flags          = HWMOD_SWSUP_SIDLE,
 420         .main_clk       = "sys_32k_ck",
 421         .prcm = {
 422                 .omap4 = {
 423                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 424                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 425                 },
 426         },
 427 };
 428
 429 /*
 430  * 'ctrl_module' class
 431  * attila core control module + core pad control module + wkup pad control
 432  * module + attila wkup control module
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 439         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 440                            SIDLE_SMART_WKUP),
 441         .sysc_fields    = &omap_hwmod_sysc_type2,
 442 };
 443
 444 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 445         .name   = "ctrl_module",
 446         .sysc   = &omap44xx_ctrl_module_sysc,
 447 };
 448
 449 /* ctrl_module_core */
 450 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 451         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 452         { .irq = -1 }
 453 };
 454
 455 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 456         .name           = "ctrl_module_core",
 457         .class          = &omap44xx_ctrl_module_hwmod_class,
 458         .clkdm_name     = "l4_cfg_clkdm",
 459         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 460         .prcm = {
 461                 .omap4 = {
 462                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 463                 },
 464         },
 465 };
 466
 467 /* ctrl_module_pad_core */
 468 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 469         .name           = "ctrl_module_pad_core",
 470         .class          = &omap44xx_ctrl_module_hwmod_class,
 471         .clkdm_name     = "l4_cfg_clkdm",
 472         .prcm = {
 473                 .omap4 = {
 474                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 475                 },
 476         },
 477 };
 478
 479 /* ctrl_module_wkup */
 480 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 481         .name           = "ctrl_module_wkup",
 482         .class          = &omap44xx_ctrl_module_hwmod_class,
 483         .clkdm_name     = "l4_wkup_clkdm",
 484         .prcm = {
 485                 .omap4 = {
 486                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 487                 },
 488         },
 489 };
 490
 491 /* ctrl_module_pad_wkup */
 492 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 493         .name           = "ctrl_module_pad_wkup",
 494         .class          = &omap44xx_ctrl_module_hwmod_class,
 495         .clkdm_name     = "l4_wkup_clkdm",
 496         .prcm = {
 497                 .omap4 = {
 498                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 499                 },
 500         },
 501 };
 502
 503 /*
 504  * 'debugss' class
 505  * debug and emulation sub system
 506  */
 507
 508 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 509         .name   = "debugss",
 510 };
 511
 512 /* debugss */
 513 static struct omap_hwmod omap44xx_debugss_hwmod = {
 514         .name           = "debugss",
 515         .class          = &omap44xx_debugss_hwmod_class,
 516         .clkdm_name     = "emu_sys_clkdm",
 517         .main_clk       = "trace_clk_div_ck",
 518         .prcm = {
 519                 .omap4 = {
 520                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 521                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 522                 },
 523         },
 524 };
 525
 526 /*
 527  * 'dma' class
 528  * dma controller for data exchange between memory to memory (i.e. internal or
 529  * external memory) and gp peripherals to memory or memory to gp peripherals
 530  */
 531
 532 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 533         .rev_offs       = 0x0000,
 534         .sysc_offs      = 0x002c,
 535         .syss_offs      = 0x0028,
 536         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 537                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 538                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 539                            SYSS_HAS_RESET_STATUS),
 540         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 541                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 546         .name   = "dma",
 547         .sysc   = &omap44xx_dma_sysc,
 548 };
 549
 550 /* dma dev_attr */
 551 static struct omap_dma_dev_attr dma_dev_attr = {
 552         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 553                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 554         .lch_count      = 32,
 555 };
 556
 557 /* dma_system */
 558 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 559         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 560         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 563         { .irq = -1 }
 564 };
 565
 566 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 567         .name           = "dma_system",
 568         .class          = &omap44xx_dma_hwmod_class,
 569         .clkdm_name     = "l3_dma_clkdm",
 570         .mpu_irqs       = omap44xx_dma_system_irqs,
 571         .main_clk       = "l3_div_ck",
 572         .prcm = {
 573                 .omap4 = {
 574                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 575                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 576                 },
 577         },
 578         .dev_attr       = &dma_dev_attr,
 579 };
 580
 581 /*
 582  * 'dmic' class
 583  * digital microphone controller
 584  */
 585
 586 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 587         .rev_offs       = 0x0000,
 588         .sysc_offs      = 0x0010,
 589         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 590                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 591         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 592                            SIDLE_SMART_WKUP),
 593         .sysc_fields    = &omap_hwmod_sysc_type2,
 594 };
 595
 596 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 597         .name   = "dmic",
 598         .sysc   = &omap44xx_dmic_sysc,
 599 };
 600
 601 /* dmic */
 602 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 603         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 604         { .irq = -1 }
 605 };
 606
 607 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 608         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 609         { .dma_req = -1 }
 610 };
 611
 612 static struct omap_hwmod omap44xx_dmic_hwmod = {
 613         .name           = "dmic",
 614         .class          = &omap44xx_dmic_hwmod_class,
 615         .clkdm_name     = "abe_clkdm",
 616         .mpu_irqs       = omap44xx_dmic_irqs,
 617         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 618         .main_clk       = "dmic_fck",
 619         .prcm = {
 620                 .omap4 = {
 621                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 622                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 623                         .modulemode   = MODULEMODE_SWCTRL,
 624                 },
 625         },
 626 };
 627
 628 /*
 629  * 'dsp' class
 630  * dsp sub-system
 631  */
 632
 633 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 634         .name   = "dsp",
 635 };
 636
 637 /* dsp */
 638 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 639         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 640         { .irq = -1 }
 641 };
 642
 643 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 644         { .name = "dsp", .rst_shift = 0 },
 645 };
 646
 647 static struct omap_hwmod omap44xx_dsp_hwmod = {
 648         .name           = "dsp",
 649         .class          = &omap44xx_dsp_hwmod_class,
 650         .clkdm_name     = "tesla_clkdm",
 651         .mpu_irqs       = omap44xx_dsp_irqs,
 652         .rst_lines      = omap44xx_dsp_resets,
 653         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 654         .main_clk       = "dsp_fck",
 655         .prcm = {
 656                 .omap4 = {
 657                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 658                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 659                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 660                         .modulemode   = MODULEMODE_HWCTRL,
 661                 },
 662         },
 663 };
 664
 665 /*
 666  * 'dss' class
 667  * display sub-system
 668  */
 669
 670 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 671         .rev_offs       = 0x0000,
 672         .syss_offs      = 0x0014,
 673         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 674 };
 675
 676 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 677         .name   = "dss",
 678         .sysc   = &omap44xx_dss_sysc,
 679         .reset  = omap_dss_reset,
 680 };
 681
 682 /* dss */
 683 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 684         { .role = "sys_clk", .clk = "dss_sys_clk" },
 685         { .role = "tv_clk", .clk = "dss_tv_clk" },
 686         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 687 };
 688
 689 static struct omap_hwmod omap44xx_dss_hwmod = {
 690         .name           = "dss_core",
 691         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 692         .class          = &omap44xx_dss_hwmod_class,
 693         .clkdm_name     = "l3_dss_clkdm",
 694         .main_clk       = "dss_dss_clk",
 695         .prcm = {
 696                 .omap4 = {
 697                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 698                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 699                 },
 700         },
 701         .opt_clks       = dss_opt_clks,
 702         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 703 };
 704
 705 /*
 706  * 'dispc' class
 707  * display controller
 708  */
 709
 710 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 711         .rev_offs       = 0x0000,
 712         .sysc_offs      = 0x0010,
 713         .syss_offs      = 0x0014,
 714         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 715                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 716                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 717                            SYSS_HAS_RESET_STATUS),
 718         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 719                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 724         .name   = "dispc",
 725         .sysc   = &omap44xx_dispc_sysc,
 726 };
 727
 728 /* dss_dispc */
 729 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 730         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 731         { .irq = -1 }
 732 };
 733
 734 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 735         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 736         { .dma_req = -1 }
 737 };
 738
 739 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 740         .manager_count          = 3,
 741         .has_framedonetv_irq    = 1
 742 };
 743
 744 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 745         .name           = "dss_dispc",
 746         .class          = &omap44xx_dispc_hwmod_class,
 747         .clkdm_name     = "l3_dss_clkdm",
 748         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 749         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 750         .main_clk       = "dss_dss_clk",
 751         .prcm = {
 752                 .omap4 = {
 753                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 754                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 755                 },
 756         },
 757         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 758 };
 759
 760 /*
 761  * 'dsi' class
 762  * display serial interface controller
 763  */
 764
 765 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 766         .rev_offs       = 0x0000,
 767         .sysc_offs      = 0x0010,
 768         .syss_offs      = 0x0014,
 769         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 770                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 771                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 773         .sysc_fields    = &omap_hwmod_sysc_type1,
 774 };
 775
 776 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 777         .name   = "dsi",
 778         .sysc   = &omap44xx_dsi_sysc,
 779 };
 780
 781 /* dss_dsi1 */
 782 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 783         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 784         { .irq = -1 }
 785 };
 786
 787 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 788         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 789         { .dma_req = -1 }
 790 };
 791
 792 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 793         { .role = "sys_clk", .clk = "dss_sys_clk" },
 794 };
 795
 796 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 797         .name           = "dss_dsi1",
 798         .class          = &omap44xx_dsi_hwmod_class,
 799         .clkdm_name     = "l3_dss_clkdm",
 800         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 801         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 802         .main_clk       = "dss_dss_clk",
 803         .prcm = {
 804                 .omap4 = {
 805                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 806                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 807                 },
 808         },
 809         .opt_clks       = dss_dsi1_opt_clks,
 810         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 811 };
 812
 813 /* dss_dsi2 */
 814 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 815         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 816         { .irq = -1 }
 817 };
 818
 819 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 820         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 821         { .dma_req = -1 }
 822 };
 823
 824 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 825         { .role = "sys_clk", .clk = "dss_sys_clk" },
 826 };
 827
 828 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 829         .name           = "dss_dsi2",
 830         .class          = &omap44xx_dsi_hwmod_class,
 831         .clkdm_name     = "l3_dss_clkdm",
 832         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 833         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 834         .main_clk       = "dss_dss_clk",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 838                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 839                 },
 840         },
 841         .opt_clks       = dss_dsi2_opt_clks,
 842         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 843 };
 844
 845 /*
 846  * 'hdmi' class
 847  * hdmi controller
 848  */
 849
 850 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 851         .rev_offs       = 0x0000,
 852         .sysc_offs      = 0x0010,
 853         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 854                            SYSC_HAS_SOFTRESET),
 855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 856                            SIDLE_SMART_WKUP),
 857         .sysc_fields    = &omap_hwmod_sysc_type2,
 858 };
 859
 860 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 861         .name   = "hdmi",
 862         .sysc   = &omap44xx_hdmi_sysc,
 863 };
 864
 865 /* dss_hdmi */
 866 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 867         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 868         { .irq = -1 }
 869 };
 870
 871 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 872         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 873         { .dma_req = -1 }
 874 };
 875
 876 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 877         { .role = "sys_clk", .clk = "dss_sys_clk" },
 878 };
 879
 880 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 881         .name           = "dss_hdmi",
 882         .class          = &omap44xx_hdmi_hwmod_class,
 883         .clkdm_name     = "l3_dss_clkdm",
 884         /*
 885          * HDMI audio requires to use no-idle mode. Hence,
 886          * set idle mode by software.
 887          */
 888         .flags          = HWMOD_SWSUP_SIDLE,
 889         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 890         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 891         .main_clk       = "dss_48mhz_clk",
 892         .prcm = {
 893                 .omap4 = {
 894                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 895                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 896                 },
 897         },
 898         .opt_clks       = dss_hdmi_opt_clks,
 899         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 900 };
 901
 902 /*
 903  * 'rfbi' class
 904  * remote frame buffer interface
 905  */
 906
 907 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 908         .rev_offs       = 0x0000,
 909         .sysc_offs      = 0x0010,
 910         .syss_offs      = 0x0014,
 911         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 912                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 914         .sysc_fields    = &omap_hwmod_sysc_type1,
 915 };
 916
 917 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 918         .name   = "rfbi",
 919         .sysc   = &omap44xx_rfbi_sysc,
 920 };
 921
 922 /* dss_rfbi */
 923 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 924         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 925         { .dma_req = -1 }
 926 };
 927
 928 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 929         { .role = "ick", .clk = "dss_fck" },
 930 };
 931
 932 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 933         .name           = "dss_rfbi",
 934         .class          = &omap44xx_rfbi_hwmod_class,
 935         .clkdm_name     = "l3_dss_clkdm",
 936         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 937         .main_clk       = "dss_dss_clk",
 938         .prcm = {
 939                 .omap4 = {
 940                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 941                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 942                 },
 943         },
 944         .opt_clks       = dss_rfbi_opt_clks,
 945         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 946 };
 947
 948 /*
 949  * 'venc' class
 950  * video encoder
 951  */
 952
 953 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 954         .name   = "venc",
 955 };
 956
 957 /* dss_venc */
 958 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 959         .name           = "dss_venc",
 960         .class          = &omap44xx_venc_hwmod_class,
 961         .clkdm_name     = "l3_dss_clkdm",
 962         .main_clk       = "dss_tv_clk",
 963         .prcm = {
 964                 .omap4 = {
 965                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 966                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 967                 },
 968         },
 969 };
 970
 971 /*
 972  * 'elm' class
 973  * bch error location module
 974  */
 975
 976 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 977         .rev_offs       = 0x0000,
 978         .sysc_offs      = 0x0010,
 979         .syss_offs      = 0x0014,
 980         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 981                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 982                            SYSS_HAS_RESET_STATUS),
 983         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 984         .sysc_fields    = &omap_hwmod_sysc_type1,
 985 };
 986
 987 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 988         .name   = "elm",
 989         .sysc   = &omap44xx_elm_sysc,
 990 };
 991
 992 /* elm */
 993 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 994         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 995         { .irq = -1 }
 996 };
 997
 998 static struct omap_hwmod omap44xx_elm_hwmod = {
 999         .name           = "elm",
1000         .class          = &omap44xx_elm_hwmod_class,
1001         .clkdm_name     = "l4_per_clkdm",
1002         .mpu_irqs       = omap44xx_elm_irqs,
1003         .prcm = {
1004                 .omap4 = {
1005                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1006                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1007                 },
1008         },
1009 };
1010
1011 /*
1012  * 'emif' class
1013  * external memory interface no1
1014  */
1015
1016 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1017         .rev_offs       = 0x0000,
1018 };
1019
1020 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1021         .name   = "emif",
1022         .sysc   = &omap44xx_emif_sysc,
1023 };
1024
1025 /* emif1 */
1026 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1027         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1028         { .irq = -1 }
1029 };
1030
1031 static struct omap_hwmod omap44xx_emif1_hwmod = {
1032         .name           = "emif1",
1033         .class          = &omap44xx_emif_hwmod_class,
1034         .clkdm_name     = "l3_emif_clkdm",
1035         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1036         .mpu_irqs       = omap44xx_emif1_irqs,
1037         .main_clk       = "ddrphy_ck",
1038         .prcm = {
1039                 .omap4 = {
1040                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1041                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1042                         .modulemode   = MODULEMODE_HWCTRL,
1043                 },
1044         },
1045 };
1046
1047 /* emif2 */
1048 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1049         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1050         { .irq = -1 }
1051 };
1052
1053 static struct omap_hwmod omap44xx_emif2_hwmod = {
1054         .name           = "emif2",
1055         .class          = &omap44xx_emif_hwmod_class,
1056         .clkdm_name     = "l3_emif_clkdm",
1057         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1058         .mpu_irqs       = omap44xx_emif2_irqs,
1059         .main_clk       = "ddrphy_ck",
1060         .prcm = {
1061                 .omap4 = {
1062                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1063                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1064                         .modulemode   = MODULEMODE_HWCTRL,
1065                 },
1066         },
1067 };
1068
1069 /*
1070  * 'fdif' class
1071  * face detection hw accelerator module
1072  */
1073
1074 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1075         .rev_offs       = 0x0000,
1076         .sysc_offs      = 0x0010,
1077         /*
1078          * FDIF needs 100 OCP clk cycles delay after a softreset before
1079          * accessing sysconfig again.
1080          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1081          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1082          *
1083          * TODO: Indicate errata when available.
1084          */
1085         .srst_udelay    = 2,
1086         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1087                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1088         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1090         .sysc_fields    = &omap_hwmod_sysc_type2,
1091 };
1092
1093 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1094         .name   = "fdif",
1095         .sysc   = &omap44xx_fdif_sysc,
1096 };
1097
1098 /* fdif */
1099 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1100         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1101         { .irq = -1 }
1102 };
1103
1104 static struct omap_hwmod omap44xx_fdif_hwmod = {
1105         .name           = "fdif",
1106         .class          = &omap44xx_fdif_hwmod_class,
1107         .clkdm_name     = "iss_clkdm",
1108         .mpu_irqs       = omap44xx_fdif_irqs,
1109         .main_clk       = "fdif_fck",
1110         .prcm = {
1111                 .omap4 = {
1112                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1113                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1114                         .modulemode   = MODULEMODE_SWCTRL,
1115                 },
1116         },
1117 };
1118
1119 /*
1120  * 'gpio' class
1121  * general purpose io module
1122  */
1123
1124 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1125         .rev_offs       = 0x0000,
1126         .sysc_offs      = 0x0010,
1127         .syss_offs      = 0x0114,
1128         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1129                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1130                            SYSS_HAS_RESET_STATUS),
1131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1132                            SIDLE_SMART_WKUP),
1133         .sysc_fields    = &omap_hwmod_sysc_type1,
1134 };
1135
1136 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1137         .name   = "gpio",
1138         .sysc   = &omap44xx_gpio_sysc,
1139         .rev    = 2,
1140 };
1141
1142 /* gpio dev_attr */
1143 static struct omap_gpio_dev_attr gpio_dev_attr = {
1144         .bank_width     = 32,
1145         .dbck_flag      = true,
1146 };
1147
1148 /* gpio1 */
1149 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1150         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1151         { .irq = -1 }
1152 };
1153
1154 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1155         { .role = "dbclk", .clk = "gpio1_dbclk" },
1156 };
1157
1158 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1159         .name           = "gpio1",
1160         .class          = &omap44xx_gpio_hwmod_class,
1161         .clkdm_name     = "l4_wkup_clkdm",
1162         .mpu_irqs       = omap44xx_gpio1_irqs,
1163         .main_clk       = "gpio1_ick",
1164         .prcm = {
1165                 .omap4 = {
1166                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1167                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1168                         .modulemode   = MODULEMODE_HWCTRL,
1169                 },
1170         },
1171         .opt_clks       = gpio1_opt_clks,
1172         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1173         .dev_attr       = &gpio_dev_attr,
1174 };
1175
1176 /* gpio2 */
1177 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1178         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1179         { .irq = -1 }
1180 };
1181
1182 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1183         { .role = "dbclk", .clk = "gpio2_dbclk" },
1184 };
1185
1186 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1187         .name           = "gpio2",
1188         .class          = &omap44xx_gpio_hwmod_class,
1189         .clkdm_name     = "l4_per_clkdm",
1190         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1191         .mpu_irqs       = omap44xx_gpio2_irqs,
1192         .main_clk       = "gpio2_ick",
1193         .prcm = {
1194                 .omap4 = {
1195                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1196                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1197                         .modulemode   = MODULEMODE_HWCTRL,
1198                 },
1199         },
1200         .opt_clks       = gpio2_opt_clks,
1201         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1202         .dev_attr       = &gpio_dev_attr,
1203 };
1204
1205 /* gpio3 */
1206 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1207         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1208         { .irq = -1 }
1209 };
1210
1211 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1212         { .role = "dbclk", .clk = "gpio3_dbclk" },
1213 };
1214
1215 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1216         .name           = "gpio3",
1217         .class          = &omap44xx_gpio_hwmod_class,
1218         .clkdm_name     = "l4_per_clkdm",
1219         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1220         .mpu_irqs       = omap44xx_gpio3_irqs,
1221         .main_clk       = "gpio3_ick",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1225                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1226                         .modulemode   = MODULEMODE_HWCTRL,
1227                 },
1228         },
1229         .opt_clks       = gpio3_opt_clks,
1230         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1231         .dev_attr       = &gpio_dev_attr,
1232 };
1233
1234 /* gpio4 */
1235 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1236         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1237         { .irq = -1 }
1238 };
1239
1240 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1241         { .role = "dbclk", .clk = "gpio4_dbclk" },
1242 };
1243
1244 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1245         .name           = "gpio4",
1246         .class          = &omap44xx_gpio_hwmod_class,
1247         .clkdm_name     = "l4_per_clkdm",
1248         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249         .mpu_irqs       = omap44xx_gpio4_irqs,
1250         .main_clk       = "gpio4_ick",
1251         .prcm = {
1252                 .omap4 = {
1253                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1254                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1255                         .modulemode   = MODULEMODE_HWCTRL,
1256                 },
1257         },
1258         .opt_clks       = gpio4_opt_clks,
1259         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1260         .dev_attr       = &gpio_dev_attr,
1261 };
1262
1263 /* gpio5 */
1264 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1265         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1266         { .irq = -1 }
1267 };
1268
1269 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1270         { .role = "dbclk", .clk = "gpio5_dbclk" },
1271 };
1272
1273 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1274         .name           = "gpio5",
1275         .class          = &omap44xx_gpio_hwmod_class,
1276         .clkdm_name     = "l4_per_clkdm",
1277         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1278         .mpu_irqs       = omap44xx_gpio5_irqs,
1279         .main_clk       = "gpio5_ick",
1280         .prcm = {
1281                 .omap4 = {
1282                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1283                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1284                         .modulemode   = MODULEMODE_HWCTRL,
1285                 },
1286         },
1287         .opt_clks       = gpio5_opt_clks,
1288         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1289         .dev_attr       = &gpio_dev_attr,
1290 };
1291
1292 /* gpio6 */
1293 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1294         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1295         { .irq = -1 }
1296 };
1297
1298 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1299         { .role = "dbclk", .clk = "gpio6_dbclk" },
1300 };
1301
1302 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1303         .name           = "gpio6",
1304         .class          = &omap44xx_gpio_hwmod_class,
1305         .clkdm_name     = "l4_per_clkdm",
1306         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1307         .mpu_irqs       = omap44xx_gpio6_irqs,
1308         .main_clk       = "gpio6_ick",
1309         .prcm = {
1310                 .omap4 = {
1311                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1312                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1313                         .modulemode   = MODULEMODE_HWCTRL,
1314                 },
1315         },
1316         .opt_clks       = gpio6_opt_clks,
1317         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1318         .dev_attr       = &gpio_dev_attr,
1319 };
1320
1321 /*
1322  * 'gpmc' class
1323  * general purpose memory controller
1324  */
1325
1326 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1327         .rev_offs       = 0x0000,
1328         .sysc_offs      = 0x0010,
1329         .syss_offs      = 0x0014,
1330         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1331                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1332         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1333         .sysc_fields    = &omap_hwmod_sysc_type1,
1334 };
1335
1336 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1337         .name   = "gpmc",
1338         .sysc   = &omap44xx_gpmc_sysc,
1339 };
1340
1341 /* gpmc */
1342 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1343         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1344         { .irq = -1 }
1345 };
1346
1347 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1348         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1349         { .dma_req = -1 }
1350 };
1351
1352 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1353         .name           = "gpmc",
1354         .class          = &omap44xx_gpmc_hwmod_class,
1355         .clkdm_name     = "l3_2_clkdm",
1356         /*
1357          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1358          * block.  It is not being added due to any known bugs with
1359          * resetting the GPMC IP block, but rather because any timings
1360          * set by the bootloader are not being correctly programmed by
1361          * the kernel from the board file or DT data.
1362          * HWMOD_INIT_NO_RESET should be removed ASAP.
1363          */
1364         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1365         .mpu_irqs       = omap44xx_gpmc_irqs,
1366         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1367         .prcm = {
1368                 .omap4 = {
1369                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1370                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1371                         .modulemode   = MODULEMODE_HWCTRL,
1372                 },
1373         },
1374 };
1375
1376 /*
1377  * 'gpu' class
1378  * 2d/3d graphics accelerator
1379  */
1380
1381 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1382         .rev_offs       = 0x1fc00,
1383         .sysc_offs      = 0x1fc10,
1384         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1386                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1387                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1388         .sysc_fields    = &omap_hwmod_sysc_type2,
1389 };
1390
1391 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1392         .name   = "gpu",
1393         .sysc   = &omap44xx_gpu_sysc,
1394 };
1395
1396 /* gpu */
1397 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1398         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1399         { .irq = -1 }
1400 };
1401
1402 static struct omap_hwmod omap44xx_gpu_hwmod = {
1403         .name           = "gpu",
1404         .class          = &omap44xx_gpu_hwmod_class,
1405         .clkdm_name     = "l3_gfx_clkdm",
1406         .mpu_irqs       = omap44xx_gpu_irqs,
1407         .main_clk       = "gpu_fck",
1408         .prcm = {
1409                 .omap4 = {
1410                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1411                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1412                         .modulemode   = MODULEMODE_SWCTRL,
1413                 },
1414         },
1415 };
1416
1417 /*
1418  * 'hdq1w' class
1419  * hdq / 1-wire serial interface controller
1420  */
1421
1422 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1423         .rev_offs       = 0x0000,
1424         .sysc_offs      = 0x0014,
1425         .syss_offs      = 0x0018,
1426         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1427                            SYSS_HAS_RESET_STATUS),
1428         .sysc_fields    = &omap_hwmod_sysc_type1,
1429 };
1430
1431 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1432         .name   = "hdq1w",
1433         .sysc   = &omap44xx_hdq1w_sysc,
1434 };
1435
1436 /* hdq1w */
1437 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1438         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1439         { .irq = -1 }
1440 };
1441
1442 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1443         .name           = "hdq1w",
1444         .class          = &omap44xx_hdq1w_hwmod_class,
1445         .clkdm_name     = "l4_per_clkdm",
1446         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1447         .mpu_irqs       = omap44xx_hdq1w_irqs,
1448         .main_clk       = "hdq1w_fck",
1449         .prcm = {
1450                 .omap4 = {
1451                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1452                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1453                         .modulemode   = MODULEMODE_SWCTRL,
1454                 },
1455         },
1456 };
1457
1458 /*
1459  * 'hsi' class
1460  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1461  * serial if)
1462  */
1463
1464 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1465         .rev_offs       = 0x0000,
1466         .sysc_offs      = 0x0010,
1467         .syss_offs      = 0x0014,
1468         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1469                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1470                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1471         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1472                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1473                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1474         .sysc_fields    = &omap_hwmod_sysc_type1,
1475 };
1476
1477 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1478         .name   = "hsi",
1479         .sysc   = &omap44xx_hsi_sysc,
1480 };
1481
1482 /* hsi */
1483 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1484         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1485         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1487         { .irq = -1 }
1488 };
1489
1490 static struct omap_hwmod omap44xx_hsi_hwmod = {
1491         .name           = "hsi",
1492         .class          = &omap44xx_hsi_hwmod_class,
1493         .clkdm_name     = "l3_init_clkdm",
1494         .mpu_irqs       = omap44xx_hsi_irqs,
1495         .main_clk       = "hsi_fck",
1496         .prcm = {
1497                 .omap4 = {
1498                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1499                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1500                         .modulemode   = MODULEMODE_HWCTRL,
1501                 },
1502         },
1503 };
1504
1505 /*
1506  * 'i2c' class
1507  * multimaster high-speed i2c controller
1508  */
1509
1510 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1511         .sysc_offs      = 0x0010,
1512         .syss_offs      = 0x0090,
1513         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1514                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1515                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1516         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1517                            SIDLE_SMART_WKUP),
1518         .clockact       = CLOCKACT_TEST_ICLK,
1519         .sysc_fields    = &omap_hwmod_sysc_type1,
1520 };
1521
1522 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1523         .name   = "i2c",
1524         .sysc   = &omap44xx_i2c_sysc,
1525         .rev    = OMAP_I2C_IP_VERSION_2,
1526         .reset  = &omap_i2c_reset,
1527 };
1528
1529 static struct omap_i2c_dev_attr i2c_dev_attr = {
1530         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1531                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1532 };
1533
1534 /* i2c1 */
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1537         { .irq = -1 }
1538 };
1539
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1543         { .dma_req = -1 }
1544 };
1545
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1547         .name           = "i2c1",
1548         .class          = &omap44xx_i2c_hwmod_class,
1549         .clkdm_name     = "l4_per_clkdm",
1550         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551         .mpu_irqs       = omap44xx_i2c1_irqs,
1552         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1553         .main_clk       = "i2c1_fck",
1554         .prcm = {
1555                 .omap4 = {
1556                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558                         .modulemode   = MODULEMODE_SWCTRL,
1559                 },
1560         },
1561         .dev_attr       = &i2c_dev_attr,
1562 };
1563
1564 /* i2c2 */
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1567         { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1573         { .dma_req = -1 }
1574 };
1575
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1577         .name           = "i2c2",
1578         .class          = &omap44xx_i2c_hwmod_class,
1579         .clkdm_name     = "l4_per_clkdm",
1580         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581         .mpu_irqs       = omap44xx_i2c2_irqs,
1582         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1583         .main_clk       = "i2c2_fck",
1584         .prcm = {
1585                 .omap4 = {
1586                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588                         .modulemode   = MODULEMODE_SWCTRL,
1589                 },
1590         },
1591         .dev_attr       = &i2c_dev_attr,
1592 };
1593
1594 /* i2c3 */
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1597         { .irq = -1 }
1598 };
1599
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1603         { .dma_req = -1 }
1604 };
1605
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1607         .name           = "i2c3",
1608         .class          = &omap44xx_i2c_hwmod_class,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611         .mpu_irqs       = omap44xx_i2c3_irqs,
1612         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1613         .main_clk       = "i2c3_fck",
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618                         .modulemode   = MODULEMODE_SWCTRL,
1619                 },
1620         },
1621         .dev_attr       = &i2c_dev_attr,
1622 };
1623
1624 /* i2c4 */
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1627         { .irq = -1 }
1628 };
1629
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1633         { .dma_req = -1 }
1634 };
1635
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1637         .name           = "i2c4",
1638         .class          = &omap44xx_i2c_hwmod_class,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641         .mpu_irqs       = omap44xx_i2c4_irqs,
1642         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1643         .main_clk       = "i2c4_fck",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_SWCTRL,
1649                 },
1650         },
1651         .dev_attr       = &i2c_dev_attr,
1652 };
1653
1654 /*
1655  * 'ipu' class
1656  * imaging processor unit
1657  */
1658
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1660         .name   = "ipu",
1661 };
1662
1663 /* ipu */
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1666         { .irq = -1 }
1667 };
1668
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670         { .name = "cpu0", .rst_shift = 0 },
1671         { .name = "cpu1", .rst_shift = 1 },
1672 };
1673
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1675         .name           = "ipu",
1676         .class          = &omap44xx_ipu_hwmod_class,
1677         .clkdm_name     = "ducati_clkdm",
1678         .mpu_irqs       = omap44xx_ipu_irqs,
1679         .rst_lines      = omap44xx_ipu_resets,
1680         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1681         .main_clk       = "ipu_fck",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_HWCTRL,
1688                 },
1689         },
1690 };
1691
1692 /*
1693  * 'iss' class
1694  * external images sensor pixel data processor
1695  */
1696
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         /*
1701          * ISS needs 100 OCP clk cycles delay after a softreset before
1702          * accessing sysconfig again.
1703          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1705          *
1706          * TODO: Indicate errata when available.
1707          */
1708         .srst_udelay    = 2,
1709         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714         .sysc_fields    = &omap_hwmod_sysc_type2,
1715 };
1716
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1718         .name   = "iss",
1719         .sysc   = &omap44xx_iss_sysc,
1720 };
1721
1722 /* iss */
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1725         { .irq = -1 }
1726 };
1727
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1733         { .dma_req = -1 }
1734 };
1735
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1738 };
1739
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1741         .name           = "iss",
1742         .class          = &omap44xx_iss_hwmod_class,
1743         .clkdm_name     = "iss_clkdm",
1744         .mpu_irqs       = omap44xx_iss_irqs,
1745         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1746         .main_clk       = "iss_fck",
1747         .prcm = {
1748                 .omap4 = {
1749                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751                         .modulemode   = MODULEMODE_SWCTRL,
1752                 },
1753         },
1754         .opt_clks       = iss_opt_clks,
1755         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1756 };
1757
1758 /*
1759  * 'iva' class
1760  * multi-standard video encoder/decoder hardware accelerator
1761  */
1762
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1764         .name   = "iva",
1765 };
1766
1767 /* iva */
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776         { .name = "seq0", .rst_shift = 0 },
1777         { .name = "seq1", .rst_shift = 1 },
1778         { .name = "logic", .rst_shift = 2 },
1779 };
1780
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1782         .name           = "iva",
1783         .class          = &omap44xx_iva_hwmod_class,
1784         .clkdm_name     = "ivahd_clkdm",
1785         .mpu_irqs       = omap44xx_iva_irqs,
1786         .rst_lines      = omap44xx_iva_resets,
1787         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1788         .main_clk       = "iva_fck",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794                         .modulemode   = MODULEMODE_HWCTRL,
1795                 },
1796         },
1797 };
1798
1799 /*
1800  * 'kbd' class
1801  * keyboard controller
1802  */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0014,
1808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811                            SYSS_HAS_RESET_STATUS),
1812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813         .sysc_fields    = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1817         .name   = "kbd",
1818         .sysc   = &omap44xx_kbd_sysc,
1819 };
1820
1821 /* kbd */
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1828         .name           = "kbd",
1829         .class          = &omap44xx_kbd_hwmod_class,
1830         .clkdm_name     = "l4_wkup_clkdm",
1831         .mpu_irqs       = omap44xx_kbd_irqs,
1832         .main_clk       = "kbd_fck",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mailbox' class
1844  * mailbox module allowing communication between the on-chip processors using a
1845  * queued mailbox-interrupt mechanism.
1846  */
1847
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1849         .rev_offs       = 0x0000,
1850         .sysc_offs      = 0x0010,
1851         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852                            SYSC_HAS_SOFTRESET),
1853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854         .sysc_fields    = &omap_hwmod_sysc_type2,
1855 };
1856
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1858         .name   = "mailbox",
1859         .sysc   = &omap44xx_mailbox_sysc,
1860 };
1861
1862 /* mailbox */
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1865         { .irq = -1 }
1866 };
1867
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1869         .name           = "mailbox",
1870         .class          = &omap44xx_mailbox_hwmod_class,
1871         .clkdm_name     = "l4_cfg_clkdm",
1872         .mpu_irqs       = omap44xx_mailbox_irqs,
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'mcasp' class
1883  * multi-channel audio serial port controller
1884  */
1885
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1888         .sidle_shift    = 0,
1889 };
1890
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892         .sysc_offs      = 0x0004,
1893         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1895                            SIDLE_SMART_WKUP),
1896         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1897 };
1898
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1900         .name   = "mcasp",
1901         .sysc   = &omap44xx_mcasp_sysc,
1902 };
1903
1904 /* mcasp */
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1908         { .irq = -1 }
1909 };
1910
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1914         { .dma_req = -1 }
1915 };
1916
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1918         .name           = "mcasp",
1919         .class          = &omap44xx_mcasp_hwmod_class,
1920         .clkdm_name     = "abe_clkdm",
1921         .mpu_irqs       = omap44xx_mcasp_irqs,
1922         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1923         .main_clk       = "mcasp_fck",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931 };
1932
1933 /*
1934  * 'mcbsp' class
1935  * multi channel buffered serial port controller
1936  */
1937
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939         .sysc_offs      = 0x008c,
1940         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943         .sysc_fields    = &omap_hwmod_sysc_type1,
1944 };
1945
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1947         .name   = "mcbsp",
1948         .sysc   = &omap44xx_mcbsp_sysc,
1949         .rev    = MCBSP_CONFIG_TYPE4,
1950 };
1951
1952 /* mcbsp1 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1970         .name           = "mcbsp1",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1975         .main_clk       = "mcbsp1_fck",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp1_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1985 };
1986
1987 /* mcbsp2 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2005         .name           = "mcbsp2",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2010         .main_clk       = "mcbsp2_fck",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp2_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2020 };
2021
2022 /* mcbsp3 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2040         .name           = "mcbsp3",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "abe_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2045         .main_clk       = "mcbsp3_fck",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp3_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2055 };
2056
2057 /* mcbsp4 */
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2060         { .irq = -1 }
2061 };
2062
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2066         { .dma_req = -1 }
2067 };
2068
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070         { .role = "pad_fck", .clk = "pad_clks_ck" },
2071         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2072 };
2073
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2075         .name           = "mcbsp4",
2076         .class          = &omap44xx_mcbsp_hwmod_class,
2077         .clkdm_name     = "l4_per_clkdm",
2078         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2079         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2080         .main_clk       = "mcbsp4_fck",
2081         .prcm = {
2082                 .omap4 = {
2083                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085                         .modulemode   = MODULEMODE_SWCTRL,
2086                 },
2087         },
2088         .opt_clks       = mcbsp4_opt_clks,
2089         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2090 };
2091
2092 /*
2093  * 'mcpdm' class
2094  * multi channel pdm controller (proprietary interface with phoenix power
2095  * ic)
2096  */
2097
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2099         .rev_offs       = 0x0000,
2100         .sysc_offs      = 0x0010,
2101         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2104                            SIDLE_SMART_WKUP),
2105         .sysc_fields    = &omap_hwmod_sysc_type2,
2106 };
2107
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2109         .name   = "mcpdm",
2110         .sysc   = &omap44xx_mcpdm_sysc,
2111 };
2112
2113 /* mcpdm */
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2116         { .irq = -1 }
2117 };
2118
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2122         { .dma_req = -1 }
2123 };
2124
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2126         .name           = "mcpdm",
2127         .class          = &omap44xx_mcpdm_hwmod_class,
2128         .clkdm_name     = "abe_clkdm",
2129         .mpu_irqs       = omap44xx_mcpdm_irqs,
2130         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2131         .main_clk       = "mcpdm_fck",
2132         .prcm = {
2133                 .omap4 = {
2134                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2135                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2136                         .modulemode   = MODULEMODE_SWCTRL,
2137                 },
2138         },
2139 };
2140
2141 /*
2142  * 'mcspi' class
2143  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2144  * bus
2145  */
2146
2147 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2148         .rev_offs       = 0x0000,
2149         .sysc_offs      = 0x0010,
2150         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2151                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2153                            SIDLE_SMART_WKUP),
2154         .sysc_fields    = &omap_hwmod_sysc_type2,
2155 };
2156
2157 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2158         .name   = "mcspi",
2159         .sysc   = &omap44xx_mcspi_sysc,
2160         .rev    = OMAP4_MCSPI_REV,
2161 };
2162
2163 /* mcspi1 */
2164 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2165         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2166         { .irq = -1 }
2167 };
2168
2169 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2170         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2171         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2172         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2173         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2174         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2175         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2176         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2177         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2178         { .dma_req = -1 }
2179 };
2180
2181 /* mcspi1 dev_attr */
2182 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2183         .num_chipselect = 4,
2184 };
2185
2186 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2187         .name           = "mcspi1",
2188         .class          = &omap44xx_mcspi_hwmod_class,
2189         .clkdm_name     = "l4_per_clkdm",
2190         .mpu_irqs       = omap44xx_mcspi1_irqs,
2191         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2192         .main_clk       = "mcspi1_fck",
2193         .prcm = {
2194                 .omap4 = {
2195                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2196                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2197                         .modulemode   = MODULEMODE_SWCTRL,
2198                 },
2199         },
2200         .dev_attr       = &mcspi1_dev_attr,
2201 };
2202
2203 /* mcspi2 */
2204 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2205         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2206         { .irq = -1 }
2207 };
2208
2209 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2210         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2211         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2212         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2213         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2214         { .dma_req = -1 }
2215 };
2216
2217 /* mcspi2 dev_attr */
2218 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2219         .num_chipselect = 2,
2220 };
2221
2222 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2223         .name           = "mcspi2",
2224         .class          = &omap44xx_mcspi_hwmod_class,
2225         .clkdm_name     = "l4_per_clkdm",
2226         .mpu_irqs       = omap44xx_mcspi2_irqs,
2227         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2228         .main_clk       = "mcspi2_fck",
2229         .prcm = {
2230                 .omap4 = {
2231                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2232                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2233                         .modulemode   = MODULEMODE_SWCTRL,
2234                 },
2235         },
2236         .dev_attr       = &mcspi2_dev_attr,
2237 };
2238
2239 /* mcspi3 */
2240 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2241         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2242         { .irq = -1 }
2243 };
2244
2245 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2246         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2247         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2248         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2249         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2250         { .dma_req = -1 }
2251 };
2252
2253 /* mcspi3 dev_attr */
2254 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2255         .num_chipselect = 2,
2256 };
2257
2258 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2259         .name           = "mcspi3",
2260         .class          = &omap44xx_mcspi_hwmod_class,
2261         .clkdm_name     = "l4_per_clkdm",
2262         .mpu_irqs       = omap44xx_mcspi3_irqs,
2263         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2264         .main_clk       = "mcspi3_fck",
2265         .prcm = {
2266                 .omap4 = {
2267                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2268                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2269                         .modulemode   = MODULEMODE_SWCTRL,
2270                 },
2271         },
2272         .dev_attr       = &mcspi3_dev_attr,
2273 };
2274
2275 /* mcspi4 */
2276 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2277         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2278         { .irq = -1 }
2279 };
2280
2281 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2282         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2283         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2284         { .dma_req = -1 }
2285 };
2286
2287 /* mcspi4 dev_attr */
2288 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2289         .num_chipselect = 1,
2290 };
2291
2292 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2293         .name           = "mcspi4",
2294         .class          = &omap44xx_mcspi_hwmod_class,
2295         .clkdm_name     = "l4_per_clkdm",
2296         .mpu_irqs       = omap44xx_mcspi4_irqs,
2297         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2298         .main_clk       = "mcspi4_fck",
2299         .prcm = {
2300                 .omap4 = {
2301                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2302                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2303                         .modulemode   = MODULEMODE_SWCTRL,
2304                 },
2305         },
2306         .dev_attr       = &mcspi4_dev_attr,
2307 };
2308
2309 /*
2310  * 'mmc' class
2311  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2312  */
2313
2314 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2315         .rev_offs       = 0x0000,
2316         .sysc_offs      = 0x0010,
2317         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2318                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2319                            SYSC_HAS_SOFTRESET),
2320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2321                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2322                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2323         .sysc_fields    = &omap_hwmod_sysc_type2,
2324 };
2325
2326 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2327         .name   = "mmc",
2328         .sysc   = &omap44xx_mmc_sysc,
2329 };
2330
2331 /* mmc1 */
2332 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2333         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2334         { .irq = -1 }
2335 };
2336
2337 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2338         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2339         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2340         { .dma_req = -1 }
2341 };
2342
2343 /* mmc1 dev_attr */
2344 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2345         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2346 };
2347
2348 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2349         .name           = "mmc1",
2350         .class          = &omap44xx_mmc_hwmod_class,
2351         .clkdm_name     = "l3_init_clkdm",
2352         .mpu_irqs       = omap44xx_mmc1_irqs,
2353         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2354         .main_clk       = "mmc1_fck",
2355         .prcm = {
2356                 .omap4 = {
2357                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2358                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2359                         .modulemode   = MODULEMODE_SWCTRL,
2360                 },
2361         },
2362         .dev_attr       = &mmc1_dev_attr,
2363 };
2364
2365 /* mmc2 */
2366 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2367         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2368         { .irq = -1 }
2369 };
2370
2371 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2372         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2373         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2374         { .dma_req = -1 }
2375 };
2376
2377 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2378         .name           = "mmc2",
2379         .class          = &omap44xx_mmc_hwmod_class,
2380         .clkdm_name     = "l3_init_clkdm",
2381         .mpu_irqs       = omap44xx_mmc2_irqs,
2382         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2383         .main_clk       = "mmc2_fck",
2384         .prcm = {
2385                 .omap4 = {
2386                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2387                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2388                         .modulemode   = MODULEMODE_SWCTRL,
2389                 },
2390         },
2391 };
2392
2393 /* mmc3 */
2394 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2395         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2396         { .irq = -1 }
2397 };
2398
2399 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2400         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2401         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2402         { .dma_req = -1 }
2403 };
2404
2405 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2406         .name           = "mmc3",
2407         .class          = &omap44xx_mmc_hwmod_class,
2408         .clkdm_name     = "l4_per_clkdm",
2409         .mpu_irqs       = omap44xx_mmc3_irqs,
2410         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2411         .main_clk       = "mmc3_fck",
2412         .prcm = {
2413                 .omap4 = {
2414                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2415                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2416                         .modulemode   = MODULEMODE_SWCTRL,
2417                 },
2418         },
2419 };
2420
2421 /* mmc4 */
2422 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2423         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2424         { .irq = -1 }
2425 };
2426
2427 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2428         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2429         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2430         { .dma_req = -1 }
2431 };
2432
2433 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2434         .name           = "mmc4",
2435         .class          = &omap44xx_mmc_hwmod_class,
2436         .clkdm_name     = "l4_per_clkdm",
2437         .mpu_irqs       = omap44xx_mmc4_irqs,
2438         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2439         .main_clk       = "mmc4_fck",
2440         .prcm = {
2441                 .omap4 = {
2442                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2443                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2444                         .modulemode   = MODULEMODE_SWCTRL,
2445                 },
2446         },
2447 };
2448
2449 /* mmc5 */
2450 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2451         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2452         { .irq = -1 }
2453 };
2454
2455 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2456         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2457         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2458         { .dma_req = -1 }
2459 };
2460
2461 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2462         .name           = "mmc5",
2463         .class          = &omap44xx_mmc_hwmod_class,
2464         .clkdm_name     = "l4_per_clkdm",
2465         .mpu_irqs       = omap44xx_mmc5_irqs,
2466         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2467         .main_clk       = "mmc5_fck",
2468         .prcm = {
2469                 .omap4 = {
2470                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2471                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2472                         .modulemode   = MODULEMODE_SWCTRL,
2473                 },
2474         },
2475 };
2476
2477 /*
2478  * 'mmu' class
2479  * The memory management unit performs virtual to physical address translation
2480  * for its requestors.
2481  */
2482
2483 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2484         .rev_offs       = 0x000,
2485         .sysc_offs      = 0x010,
2486         .syss_offs      = 0x014,
2487         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2488                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2490         .sysc_fields    = &omap_hwmod_sysc_type1,
2491 };
2492
2493 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2494         .name = "mmu",
2495         .sysc = &mmu_sysc,
2496 };
2497
2498 /* mmu ipu */
2499
2500 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2501         .da_start       = 0x0,
2502         .da_end         = 0xfffff000,
2503         .nr_tlb_entries = 32,
2504 };
2505
2506 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2507 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2508         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2509         { .irq = -1 }
2510 };
2511
2512 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2513         { .name = "mmu_cache", .rst_shift = 2 },
2514 };
2515
2516 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2517         {
2518                 .pa_start       = 0x55082000,
2519                 .pa_end         = 0x550820ff,
2520                 .flags          = ADDR_TYPE_RT,
2521         },
2522         { }
2523 };
2524
2525 /* l3_main_2 -> mmu_ipu */
2526 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2527         .master         = &omap44xx_l3_main_2_hwmod,
2528         .slave          = &omap44xx_mmu_ipu_hwmod,
2529         .clk            = "l3_div_ck",
2530         .addr           = omap44xx_mmu_ipu_addrs,
2531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2532 };
2533
2534 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2535         .name           = "mmu_ipu",
2536         .class          = &omap44xx_mmu_hwmod_class,
2537         .clkdm_name     = "ducati_clkdm",
2538         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2539         .rst_lines      = omap44xx_mmu_ipu_resets,
2540         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2541         .main_clk       = "ducati_clk_mux_ck",
2542         .prcm = {
2543                 .omap4 = {
2544                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2545                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2546                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2547                         .modulemode   = MODULEMODE_HWCTRL,
2548                 },
2549         },
2550         .dev_attr       = &mmu_ipu_dev_attr,
2551 };
2552
2553 /* mmu dsp */
2554
2555 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2556         .da_start       = 0x0,
2557         .da_end         = 0xfffff000,
2558         .nr_tlb_entries = 32,
2559 };
2560
2561 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2562 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2563         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2564         { .irq = -1 }
2565 };
2566
2567 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2568         { .name = "mmu_cache", .rst_shift = 1 },
2569 };
2570
2571 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2572         {
2573                 .pa_start       = 0x4a066000,
2574                 .pa_end         = 0x4a0660ff,
2575                 .flags          = ADDR_TYPE_RT,
2576         },
2577         { }
2578 };
2579
2580 /* l4_cfg -> dsp */
2581 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2582         .master         = &omap44xx_l4_cfg_hwmod,
2583         .slave          = &omap44xx_mmu_dsp_hwmod,
2584         .clk            = "l4_div_ck",
2585         .addr           = omap44xx_mmu_dsp_addrs,
2586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588
2589 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2590         .name           = "mmu_dsp",
2591         .class          = &omap44xx_mmu_hwmod_class,
2592         .clkdm_name     = "tesla_clkdm",
2593         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2594         .rst_lines      = omap44xx_mmu_dsp_resets,
2595         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2596         .main_clk       = "dpll_iva_m4x2_ck",
2597         .prcm = {
2598                 .omap4 = {
2599                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2600                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2601                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2602                         .modulemode   = MODULEMODE_HWCTRL,
2603                 },
2604         },
2605         .dev_attr       = &mmu_dsp_dev_attr,
2606 };
2607
2608 /*
2609  * 'mpu' class
2610  * mpu sub-system
2611  */
2612
2613 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2614         .name   = "mpu",
2615 };
2616
2617 /* mpu */
2618 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2619         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2620         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2621         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2622         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2623         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2624         { .irq = -1 }
2625 };
2626
2627 static struct omap_hwmod omap44xx_mpu_hwmod = {
2628         .name           = "mpu",
2629         .class          = &omap44xx_mpu_hwmod_class,
2630         .clkdm_name     = "mpuss_clkdm",
2631         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2632         .mpu_irqs       = omap44xx_mpu_irqs,
2633         .main_clk       = "dpll_mpu_m2_ck",
2634         .prcm = {
2635                 .omap4 = {
2636                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2637                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2638                 },
2639         },
2640 };
2641
2642 /*
2643  * 'ocmc_ram' class
2644  * top-level core on-chip ram
2645  */
2646
2647 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2648         .name   = "ocmc_ram",
2649 };
2650
2651 /* ocmc_ram */
2652 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2653         .name           = "ocmc_ram",
2654         .class          = &omap44xx_ocmc_ram_hwmod_class,
2655         .clkdm_name     = "l3_2_clkdm",
2656         .prcm = {
2657                 .omap4 = {
2658                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2659                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2660                 },
2661         },
2662 };
2663
2664 /*
2665  * 'ocp2scp' class
2666  * bridge to transform ocp interface protocol to scp (serial control port)
2667  * protocol
2668  */
2669
2670 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2671         .rev_offs       = 0x0000,
2672         .sysc_offs      = 0x0010,
2673         .syss_offs      = 0x0014,
2674         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2675                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2676         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2677         .sysc_fields    = &omap_hwmod_sysc_type1,
2678 };
2679
2680 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2681         .name   = "ocp2scp",
2682         .sysc   = &omap44xx_ocp2scp_sysc,
2683 };
2684
2685 /* ocp2scp_usb_phy */
2686 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2687         .name           = "ocp2scp_usb_phy",
2688         .class          = &omap44xx_ocp2scp_hwmod_class,
2689         .clkdm_name     = "l3_init_clkdm",
2690         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2691         .prcm = {
2692                 .omap4 = {
2693                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2694                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2695                         .modulemode   = MODULEMODE_HWCTRL,
2696                 },
2697         },
2698 };
2699
2700 /*
2701  * 'prcm' class
2702  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2703  * + clock manager 1 (in always on power domain) + local prm in mpu
2704  */
2705
2706 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2707         .name   = "prcm",
2708 };
2709
2710 /* prcm_mpu */
2711 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2712         .name           = "prcm_mpu",
2713         .class          = &omap44xx_prcm_hwmod_class,
2714         .clkdm_name     = "l4_wkup_clkdm",
2715         .flags          = HWMOD_NO_IDLEST,
2716         .prcm = {
2717                 .omap4 = {
2718                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2719                 },
2720         },
2721 };
2722
2723 /* cm_core_aon */
2724 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2725         .name           = "cm_core_aon",
2726         .class          = &omap44xx_prcm_hwmod_class,
2727         .flags          = HWMOD_NO_IDLEST,
2728         .prcm = {
2729                 .omap4 = {
2730                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2731                 },
2732         },
2733 };
2734
2735 /* cm_core */
2736 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2737         .name           = "cm_core",
2738         .class          = &omap44xx_prcm_hwmod_class,
2739         .flags          = HWMOD_NO_IDLEST,
2740         .prcm = {
2741                 .omap4 = {
2742                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2743                 },
2744         },
2745 };
2746
2747 /* prm */
2748 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2749         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2750         { .irq = -1 }
2751 };
2752
2753 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2754         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2755         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2756 };
2757
2758 static struct omap_hwmod omap44xx_prm_hwmod = {
2759         .name           = "prm",
2760         .class          = &omap44xx_prcm_hwmod_class,
2761         .mpu_irqs       = omap44xx_prm_irqs,
2762         .rst_lines      = omap44xx_prm_resets,
2763         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2764 };
2765
2766 /*
2767  * 'scrm' class
2768  * system clock and reset manager
2769  */
2770
2771 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2772         .name   = "scrm",
2773 };
2774
2775 /* scrm */
2776 static struct omap_hwmod omap44xx_scrm_hwmod = {
2777         .name           = "scrm",
2778         .class          = &omap44xx_scrm_hwmod_class,
2779         .clkdm_name     = "l4_wkup_clkdm",
2780         .prcm = {
2781                 .omap4 = {
2782                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2783                 },
2784         },
2785 };
2786
2787 /*
2788  * 'sl2if' class
2789  * shared level 2 memory interface
2790  */
2791
2792 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2793         .name   = "sl2if",
2794 };
2795
2796 /* sl2if */
2797 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2798         .name           = "sl2if",
2799         .class          = &omap44xx_sl2if_hwmod_class,
2800         .clkdm_name     = "ivahd_clkdm",
2801         .prcm = {
2802                 .omap4 = {
2803                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2804                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2805                         .modulemode   = MODULEMODE_HWCTRL,
2806                 },
2807         },
2808 };
2809
2810 /*
2811  * 'slimbus' class
2812  * bidirectional, multi-drop, multi-channel two-line serial interface between
2813  * the device and external components
2814  */
2815
2816 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2817         .rev_offs       = 0x0000,
2818         .sysc_offs      = 0x0010,
2819         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2820                            SYSC_HAS_SOFTRESET),
2821         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2822                            SIDLE_SMART_WKUP),
2823         .sysc_fields    = &omap_hwmod_sysc_type2,
2824 };
2825
2826 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2827         .name   = "slimbus",
2828         .sysc   = &omap44xx_slimbus_sysc,
2829 };
2830
2831 /* slimbus1 */
2832 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2833         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2834         { .irq = -1 }
2835 };
2836
2837 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2838         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2839         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2840         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2841         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2842         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2843         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2844         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2845         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2846         { .dma_req = -1 }
2847 };
2848
2849 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2850         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2851         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2852         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2853         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2854 };
2855
2856 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2857         .name           = "slimbus1",
2858         .class          = &omap44xx_slimbus_hwmod_class,
2859         .clkdm_name     = "abe_clkdm",
2860         .mpu_irqs       = omap44xx_slimbus1_irqs,
2861         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2862         .prcm = {
2863                 .omap4 = {
2864                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2865                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2866                         .modulemode   = MODULEMODE_SWCTRL,
2867                 },
2868         },
2869         .opt_clks       = slimbus1_opt_clks,
2870         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2871 };
2872
2873 /* slimbus2 */
2874 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2875         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2876         { .irq = -1 }
2877 };
2878
2879 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2880         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2881         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2882         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2883         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2884         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2885         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2886         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2887         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2888         { .dma_req = -1 }
2889 };
2890
2891 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2892         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2893         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2894         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2895 };
2896
2897 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2898         .name           = "slimbus2",
2899         .class          = &omap44xx_slimbus_hwmod_class,
2900         .clkdm_name     = "l4_per_clkdm",
2901         .mpu_irqs       = omap44xx_slimbus2_irqs,
2902         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2903         .prcm = {
2904                 .omap4 = {
2905                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2906                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2907                         .modulemode   = MODULEMODE_SWCTRL,
2908                 },
2909         },
2910         .opt_clks       = slimbus2_opt_clks,
2911         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2912 };
2913
2914 /*
2915  * 'smartreflex' class
2916  * smartreflex module (monitor silicon performance and outputs a measure of
2917  * performance error)
2918  */
2919
2920 /* The IP is not compliant to type1 / type2 scheme */
2921 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2922         .sidle_shift    = 24,
2923         .enwkup_shift   = 26,
2924 };
2925
2926 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2927         .sysc_offs      = 0x0038,
2928         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2929         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2930                            SIDLE_SMART_WKUP),
2931         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2932 };
2933
2934 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2935         .name   = "smartreflex",
2936         .sysc   = &omap44xx_smartreflex_sysc,
2937         .rev    = 2,
2938 };
2939
2940 /* smartreflex_core */
2941 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2942         .sensor_voltdm_name   = "core",
2943 };
2944
2945 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2946         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2947         { .irq = -1 }
2948 };
2949
2950 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2951         .name           = "smartreflex_core",
2952         .class          = &omap44xx_smartreflex_hwmod_class,
2953         .clkdm_name     = "l4_ao_clkdm",
2954         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2955
2956         .main_clk       = "smartreflex_core_fck",
2957         .prcm = {
2958                 .omap4 = {
2959                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2960                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2961                         .modulemode   = MODULEMODE_SWCTRL,
2962                 },
2963         },
2964         .dev_attr       = &smartreflex_core_dev_attr,
2965 };
2966
2967 /* smartreflex_iva */
2968 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2969         .sensor_voltdm_name     = "iva",
2970 };
2971
2972 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2973         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2974         { .irq = -1 }
2975 };
2976
2977 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2978         .name           = "smartreflex_iva",
2979         .class          = &omap44xx_smartreflex_hwmod_class,
2980         .clkdm_name     = "l4_ao_clkdm",
2981         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2982         .main_clk       = "smartreflex_iva_fck",
2983         .prcm = {
2984                 .omap4 = {
2985                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2986                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2987                         .modulemode   = MODULEMODE_SWCTRL,
2988                 },
2989         },
2990         .dev_attr       = &smartreflex_iva_dev_attr,
2991 };
2992
2993 /* smartreflex_mpu */
2994 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2995         .sensor_voltdm_name     = "mpu",
2996 };
2997
2998 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2999         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3000         { .irq = -1 }
3001 };
3002
3003 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3004         .name           = "smartreflex_mpu",
3005         .class          = &omap44xx_smartreflex_hwmod_class,
3006         .clkdm_name     = "l4_ao_clkdm",
3007         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3008         .main_clk       = "smartreflex_mpu_fck",
3009         .prcm = {
3010                 .omap4 = {
3011                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3012                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3013                         .modulemode   = MODULEMODE_SWCTRL,
3014                 },
3015         },
3016         .dev_attr       = &smartreflex_mpu_dev_attr,
3017 };
3018
3019 /*
3020  * 'spinlock' class
3021  * spinlock provides hardware assistance for synchronizing the processes
3022  * running on multiple processors
3023  */
3024
3025 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3026         .rev_offs       = 0x0000,
3027         .sysc_offs      = 0x0010,
3028         .syss_offs      = 0x0014,
3029         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3030                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3031                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3032         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3033                            SIDLE_SMART_WKUP),
3034         .sysc_fields    = &omap_hwmod_sysc_type1,
3035 };
3036
3037 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3038         .name   = "spinlock",
3039         .sysc   = &omap44xx_spinlock_sysc,
3040 };
3041
3042 /* spinlock */
3043 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3044         .name           = "spinlock",
3045         .class          = &omap44xx_spinlock_hwmod_class,
3046         .clkdm_name     = "l4_cfg_clkdm",
3047         .prcm = {
3048                 .omap4 = {
3049                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3050                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3051                 },
3052         },
3053 };
3054
3055 /*
3056  * 'timer' class
3057  * general purpose timer module with accurate 1ms tick
3058  * This class contains several variants: ['timer_1ms', 'timer']
3059  */
3060
3061 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3062         .rev_offs       = 0x0000,
3063         .sysc_offs      = 0x0010,
3064         .syss_offs      = 0x0014,
3065         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3066                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3067                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3068                            SYSS_HAS_RESET_STATUS),
3069         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3070         .clockact       = CLOCKACT_TEST_ICLK,
3071         .sysc_fields    = &omap_hwmod_sysc_type1,
3072 };
3073
3074 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3075         .name   = "timer",
3076         .sysc   = &omap44xx_timer_1ms_sysc,
3077 };
3078
3079 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3080         .rev_offs       = 0x0000,
3081         .sysc_offs      = 0x0010,
3082         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3083                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3084         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3085                            SIDLE_SMART_WKUP),
3086         .sysc_fields    = &omap_hwmod_sysc_type2,
3087 };
3088
3089 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3090         .name   = "timer",
3091         .sysc   = &omap44xx_timer_sysc,
3092 };
3093
3094 /* always-on timers dev attribute */
3095 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3096         .timer_capability       = OMAP_TIMER_ALWON,
3097 };
3098
3099 /* pwm timers dev attribute */
3100 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3101         .timer_capability       = OMAP_TIMER_HAS_PWM,
3102 };
3103
3104 /* timers with DSP interrupt dev attribute */
3105 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3106         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3107 };
3108
3109 /* pwm timers with DSP interrupt dev attribute */
3110 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3111         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3112 };
3113
3114 /* timer1 */
3115 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3116         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3117         { .irq = -1 }
3118 };
3119
3120 static struct omap_hwmod omap44xx_timer1_hwmod = {
3121         .name           = "timer1",
3122         .class          = &omap44xx_timer_1ms_hwmod_class,
3123         .clkdm_name     = "l4_wkup_clkdm",
3124         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3125         .mpu_irqs       = omap44xx_timer1_irqs,
3126         .main_clk       = "timer1_fck",
3127         .prcm = {
3128                 .omap4 = {
3129                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3130                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3131                         .modulemode   = MODULEMODE_SWCTRL,
3132                 },
3133         },
3134         .dev_attr       = &capability_alwon_dev_attr,
3135 };
3136
3137 /* timer2 */
3138 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3139         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3140         { .irq = -1 }
3141 };
3142
3143 static struct omap_hwmod omap44xx_timer2_hwmod = {
3144         .name           = "timer2",
3145         .class          = &omap44xx_timer_1ms_hwmod_class,
3146         .clkdm_name     = "l4_per_clkdm",
3147         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3148         .mpu_irqs       = omap44xx_timer2_irqs,
3149         .main_clk       = "timer2_fck",
3150         .prcm = {
3151                 .omap4 = {
3152                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3153                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3154                         .modulemode   = MODULEMODE_SWCTRL,
3155                 },
3156         },
3157 };
3158
3159 /* timer3 */
3160 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3161         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3162         { .irq = -1 }
3163 };
3164
3165 static struct omap_hwmod omap44xx_timer3_hwmod = {
3166         .name           = "timer3",
3167         .class          = &omap44xx_timer_hwmod_class,
3168         .clkdm_name     = "l4_per_clkdm",
3169         .mpu_irqs       = omap44xx_timer3_irqs,
3170         .main_clk       = "timer3_fck",
3171         .prcm = {
3172                 .omap4 = {
3173                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3174                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3175                         .modulemode   = MODULEMODE_SWCTRL,
3176                 },
3177         },
3178 };
3179
3180 /* timer4 */
3181 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3182         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3183         { .irq = -1 }
3184 };
3185
3186 static struct omap_hwmod omap44xx_timer4_hwmod = {
3187         .name           = "timer4",
3188         .class          = &omap44xx_timer_hwmod_class,
3189         .clkdm_name     = "l4_per_clkdm",
3190         .mpu_irqs       = omap44xx_timer4_irqs,
3191         .main_clk       = "timer4_fck",
3192         .prcm = {
3193                 .omap4 = {
3194                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3195                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3196                         .modulemode   = MODULEMODE_SWCTRL,
3197                 },
3198         },
3199 };
3200
3201 /* timer5 */
3202 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3203         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3204         { .irq = -1 }
3205 };
3206
3207 static struct omap_hwmod omap44xx_timer5_hwmod = {
3208         .name           = "timer5",
3209         .class          = &omap44xx_timer_hwmod_class,
3210         .clkdm_name     = "abe_clkdm",
3211         .mpu_irqs       = omap44xx_timer5_irqs,
3212         .main_clk       = "timer5_fck",
3213         .prcm = {
3214                 .omap4 = {
3215                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3216                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3217                         .modulemode   = MODULEMODE_SWCTRL,
3218                 },
3219         },
3220         .dev_attr       = &capability_dsp_dev_attr,
3221 };
3222
3223 /* timer6 */
3224 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3225         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3226         { .irq = -1 }
3227 };
3228
3229 static struct omap_hwmod omap44xx_timer6_hwmod = {
3230         .name           = "timer6",
3231         .class          = &omap44xx_timer_hwmod_class,
3232         .clkdm_name     = "abe_clkdm",
3233         .mpu_irqs       = omap44xx_timer6_irqs,
3234
3235         .main_clk       = "timer6_fck",
3236         .prcm = {
3237                 .omap4 = {
3238                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3239                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3240                         .modulemode   = MODULEMODE_SWCTRL,
3241                 },
3242         },
3243         .dev_attr       = &capability_dsp_dev_attr,
3244 };
3245
3246 /* timer7 */
3247 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3248         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3249         { .irq = -1 }
3250 };
3251
3252 static struct omap_hwmod omap44xx_timer7_hwmod = {
3253         .name           = "timer7",
3254         .class          = &omap44xx_timer_hwmod_class,
3255         .clkdm_name     = "abe_clkdm",
3256         .mpu_irqs       = omap44xx_timer7_irqs,
3257         .main_clk       = "timer7_fck",
3258         .prcm = {
3259                 .omap4 = {
3260                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3261                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3262                         .modulemode   = MODULEMODE_SWCTRL,
3263                 },
3264         },
3265         .dev_attr       = &capability_dsp_dev_attr,
3266 };
3267
3268 /* timer8 */
3269 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3270         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3271         { .irq = -1 }
3272 };
3273
3274 static struct omap_hwmod omap44xx_timer8_hwmod = {
3275         .name           = "timer8",
3276         .class          = &omap44xx_timer_hwmod_class,
3277         .clkdm_name     = "abe_clkdm",
3278         .mpu_irqs       = omap44xx_timer8_irqs,
3279         .main_clk       = "timer8_fck",
3280         .prcm = {
3281                 .omap4 = {
3282                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3283                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3284                         .modulemode   = MODULEMODE_SWCTRL,
3285                 },
3286         },
3287         .dev_attr       = &capability_dsp_pwm_dev_attr,
3288 };
3289
3290 /* timer9 */
3291 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3292         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3293         { .irq = -1 }
3294 };
3295
3296 static struct omap_hwmod omap44xx_timer9_hwmod = {
3297         .name           = "timer9",
3298         .class          = &omap44xx_timer_hwmod_class,
3299         .clkdm_name     = "l4_per_clkdm",
3300         .mpu_irqs       = omap44xx_timer9_irqs,
3301         .main_clk       = "timer9_fck",
3302         .prcm = {
3303                 .omap4 = {
3304                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3305                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3306                         .modulemode   = MODULEMODE_SWCTRL,
3307                 },
3308         },
3309         .dev_attr       = &capability_pwm_dev_attr,
3310 };
3311
3312 /* timer10 */
3313 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3314         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3315         { .irq = -1 }
3316 };
3317
3318 static struct omap_hwmod omap44xx_timer10_hwmod = {
3319         .name           = "timer10",
3320         .class          = &omap44xx_timer_1ms_hwmod_class,
3321         .clkdm_name     = "l4_per_clkdm",
3322         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3323         .mpu_irqs       = omap44xx_timer10_irqs,
3324         .main_clk       = "timer10_fck",
3325         .prcm = {
3326                 .omap4 = {
3327                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3328                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3329                         .modulemode   = MODULEMODE_SWCTRL,
3330                 },
3331         },
3332         .dev_attr       = &capability_pwm_dev_attr,
3333 };
3334
3335 /* timer11 */
3336 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3337         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3338         { .irq = -1 }
3339 };
3340
3341 static struct omap_hwmod omap44xx_timer11_hwmod = {
3342         .name           = "timer11",
3343         .class          = &omap44xx_timer_hwmod_class,
3344         .clkdm_name     = "l4_per_clkdm",
3345         .mpu_irqs       = omap44xx_timer11_irqs,
3346         .main_clk       = "timer11_fck",
3347         .prcm = {
3348                 .omap4 = {
3349                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3350                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3351                         .modulemode   = MODULEMODE_SWCTRL,
3352                 },
3353         },
3354         .dev_attr       = &capability_pwm_dev_attr,
3355 };
3356
3357 /*
3358  * 'uart' class
3359  * universal asynchronous receiver/transmitter (uart)
3360  */
3361
3362 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3363         .rev_offs       = 0x0050,
3364         .sysc_offs      = 0x0054,
3365         .syss_offs      = 0x0058,
3366         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3367                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3368                            SYSS_HAS_RESET_STATUS),
3369         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3370                            SIDLE_SMART_WKUP),
3371         .sysc_fields    = &omap_hwmod_sysc_type1,
3372 };
3373
3374 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3375         .name   = "uart",
3376         .sysc   = &omap44xx_uart_sysc,
3377 };
3378
3379 /* uart1 */
3380 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3381         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3382         { .irq = -1 }
3383 };
3384
3385 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3386         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3387         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3388         { .dma_req = -1 }
3389 };
3390
3391 static struct omap_hwmod omap44xx_uart1_hwmod = {
3392         .name           = "uart1",
3393         .class          = &omap44xx_uart_hwmod_class,
3394         .clkdm_name     = "l4_per_clkdm",
3395         .mpu_irqs       = omap44xx_uart1_irqs,
3396         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3397         .main_clk       = "uart1_fck",
3398         .prcm = {
3399                 .omap4 = {
3400                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3401                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3402                         .modulemode   = MODULEMODE_SWCTRL,
3403                 },
3404         },
3405 };
3406
3407 /* uart2 */
3408 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3409         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3410         { .irq = -1 }
3411 };
3412
3413 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3414         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3415         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3416         { .dma_req = -1 }
3417 };
3418
3419 static struct omap_hwmod omap44xx_uart2_hwmod = {
3420         .name           = "uart2",
3421         .class          = &omap44xx_uart_hwmod_class,
3422         .clkdm_name     = "l4_per_clkdm",
3423         .mpu_irqs       = omap44xx_uart2_irqs,
3424         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3425         .main_clk       = "uart2_fck",
3426         .prcm = {
3427                 .omap4 = {
3428                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3429                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3430                         .modulemode   = MODULEMODE_SWCTRL,
3431                 },
3432         },
3433 };
3434
3435 /* uart3 */
3436 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3437         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3438         { .irq = -1 }
3439 };
3440
3441 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3442         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3443         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3444         { .dma_req = -1 }
3445 };
3446
3447 static struct omap_hwmod omap44xx_uart3_hwmod = {
3448         .name           = "uart3",
3449         .class          = &omap44xx_uart_hwmod_class,
3450         .clkdm_name     = "l4_per_clkdm",
3451         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3452         .mpu_irqs       = omap44xx_uart3_irqs,
3453         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3454         .main_clk       = "uart3_fck",
3455         .prcm = {
3456                 .omap4 = {
3457                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3458                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3459                         .modulemode   = MODULEMODE_SWCTRL,
3460                 },
3461         },
3462 };
3463
3464 /* uart4 */
3465 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3466         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3467         { .irq = -1 }
3468 };
3469
3470 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3471         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3472         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3473         { .dma_req = -1 }
3474 };
3475
3476 static struct omap_hwmod omap44xx_uart4_hwmod = {
3477         .name           = "uart4",
3478         .class          = &omap44xx_uart_hwmod_class,
3479         .clkdm_name     = "l4_per_clkdm",
3480         .mpu_irqs       = omap44xx_uart4_irqs,
3481         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3482         .main_clk       = "uart4_fck",
3483         .prcm = {
3484                 .omap4 = {
3485                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3486                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3487                         .modulemode   = MODULEMODE_SWCTRL,
3488                 },
3489         },
3490 };
3491
3492 /*
3493  * 'usb_host_fs' class
3494  * full-speed usb host controller
3495  */
3496
3497 /* The IP is not compliant to type1 / type2 scheme */
3498 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3499         .midle_shift    = 4,
3500         .sidle_shift    = 2,
3501         .srst_shift     = 1,
3502 };
3503
3504 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3505         .rev_offs       = 0x0000,
3506         .sysc_offs      = 0x0210,
3507         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3508                            SYSC_HAS_SOFTRESET),
3509         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3510                            SIDLE_SMART_WKUP),
3511         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3512 };
3513
3514 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3515         .name   = "usb_host_fs",
3516         .sysc   = &omap44xx_usb_host_fs_sysc,
3517 };
3518
3519 /* usb_host_fs */
3520 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3521         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3522         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3523         { .irq = -1 }
3524 };
3525
3526 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3527         .name           = "usb_host_fs",
3528         .class          = &omap44xx_usb_host_fs_hwmod_class,
3529         .clkdm_name     = "l3_init_clkdm",
3530         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3531         .main_clk       = "usb_host_fs_fck",
3532         .prcm = {
3533                 .omap4 = {
3534                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3535                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3536                         .modulemode   = MODULEMODE_SWCTRL,
3537                 },
3538         },
3539 };
3540
3541 /*
3542  * 'usb_host_hs' class
3543  * high-speed multi-port usb host controller
3544  */
3545
3546 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3547         .rev_offs       = 0x0000,
3548         .sysc_offs      = 0x0010,
3549         .syss_offs      = 0x0014,
3550         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3551                            SYSC_HAS_SOFTRESET),
3552         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3553                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3554                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3555         .sysc_fields    = &omap_hwmod_sysc_type2,
3556 };
3557
3558 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3559         .name   = "usb_host_hs",
3560         .sysc   = &omap44xx_usb_host_hs_sysc,
3561 };
3562
3563 /* usb_host_hs */
3564 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3565         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3566         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3567         { .irq = -1 }
3568 };
3569
3570 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3571         .name           = "usb_host_hs",
3572         .class          = &omap44xx_usb_host_hs_hwmod_class,
3573         .clkdm_name     = "l3_init_clkdm",
3574         .main_clk       = "usb_host_hs_fck",
3575         .prcm = {
3576                 .omap4 = {
3577                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3578                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3579                         .modulemode   = MODULEMODE_SWCTRL,
3580                 },
3581         },
3582         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3583
3584         /*
3585          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3586          * id: i660
3587          *
3588          * Description:
3589          * In the following configuration :
3590          * - USBHOST module is set to smart-idle mode
3591          * - PRCM asserts idle_req to the USBHOST module ( This typically
3592          *   happens when the system is going to a low power mode : all ports
3593          *   have been suspended, the master part of the USBHOST module has
3594          *   entered the standby state, and SW has cut the functional clocks)
3595          * - an USBHOST interrupt occurs before the module is able to answer
3596          *   idle_ack, typically a remote wakeup IRQ.
3597          * Then the USB HOST module will enter a deadlock situation where it
3598          * is no more accessible nor functional.
3599          *
3600          * Workaround:
3601          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3602          */
3603
3604         /*
3605          * Errata: USB host EHCI may stall when entering smart-standby mode
3606          * Id: i571
3607          *
3608          * Description:
3609          * When the USBHOST module is set to smart-standby mode, and when it is
3610          * ready to enter the standby state (i.e. all ports are suspended and
3611          * all attached devices are in suspend mode), then it can wrongly assert
3612          * the Mstandby signal too early while there are still some residual OCP
3613          * transactions ongoing. If this condition occurs, the internal state
3614          * machine may go to an undefined state and the USB link may be stuck
3615          * upon the next resume.
3616          *
3617          * Workaround:
3618          * Don't use smart standby; use only force standby,
3619          * hence HWMOD_SWSUP_MSTANDBY
3620          */
3621
3622         /*
3623          * During system boot; If the hwmod framework resets the module
3624          * the module will have smart idle settings; which can lead to deadlock
3625          * (above Errata Id:i660); so, dont reset the module during boot;
3626          * Use HWMOD_INIT_NO_RESET.
3627          */
3628
3629         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3630                           HWMOD_INIT_NO_RESET,
3631 };
3632
3633 /*
3634  * 'usb_otg_hs' class
3635  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3636  */
3637
3638 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3639         .rev_offs       = 0x0400,
3640         .sysc_offs      = 0x0404,
3641         .syss_offs      = 0x0408,
3642         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3643                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3644                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3645         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3646                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3647                            MSTANDBY_SMART),
3648         .sysc_fields    = &omap_hwmod_sysc_type1,
3649 };
3650
3651 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3652         .name   = "usb_otg_hs",
3653         .sysc   = &omap44xx_usb_otg_hs_sysc,
3654 };
3655
3656 /* usb_otg_hs */
3657 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3658         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3659         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3660         { .irq = -1 }
3661 };
3662
3663 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3664         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3665 };
3666
3667 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3668         .name           = "usb_otg_hs",
3669         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3670         .clkdm_name     = "l3_init_clkdm",
3671         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3672         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3673         .main_clk       = "usb_otg_hs_ick",
3674         .prcm = {
3675                 .omap4 = {
3676                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3677                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3678                         .modulemode   = MODULEMODE_HWCTRL,
3679                 },
3680         },
3681         .opt_clks       = usb_otg_hs_opt_clks,
3682         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3683 };
3684
3685 /*
3686  * 'usb_tll_hs' class
3687  * usb_tll_hs module is the adapter on the usb_host_hs ports
3688  */
3689
3690 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3691         .rev_offs       = 0x0000,
3692         .sysc_offs      = 0x0010,
3693         .syss_offs      = 0x0014,
3694         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3695                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3696                            SYSC_HAS_AUTOIDLE),
3697         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3698         .sysc_fields    = &omap_hwmod_sysc_type1,
3699 };
3700
3701 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3702         .name   = "usb_tll_hs",
3703         .sysc   = &omap44xx_usb_tll_hs_sysc,
3704 };
3705
3706 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3707         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3708         { .irq = -1 }
3709 };
3710
3711 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3712         .name           = "usb_tll_hs",
3713         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3714         .clkdm_name     = "l3_init_clkdm",
3715         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3716         .main_clk       = "usb_tll_hs_ick",
3717         .prcm = {
3718                 .omap4 = {
3719                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3720                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3721                         .modulemode   = MODULEMODE_HWCTRL,
3722                 },
3723         },
3724 };
3725
3726 /*
3727  * 'wd_timer' class
3728  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3729  * overflow condition
3730  */
3731
3732 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3733         .rev_offs       = 0x0000,
3734         .sysc_offs      = 0x0010,
3735         .syss_offs      = 0x0014,
3736         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3737                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3738         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3739                            SIDLE_SMART_WKUP),
3740         .sysc_fields    = &omap_hwmod_sysc_type1,
3741 };
3742
3743 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3744         .name           = "wd_timer",
3745         .sysc           = &omap44xx_wd_timer_sysc,
3746         .pre_shutdown   = &omap2_wd_timer_disable,
3747         .reset          = &omap2_wd_timer_reset,
3748 };
3749
3750 /* wd_timer2 */
3751 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3752         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3753         { .irq = -1 }
3754 };
3755
3756 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3757         .name           = "wd_timer2",
3758         .class          = &omap44xx_wd_timer_hwmod_class,
3759         .clkdm_name     = "l4_wkup_clkdm",
3760         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3761         .main_clk       = "wd_timer2_fck",
3762         .prcm = {
3763                 .omap4 = {
3764                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3765                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3766                         .modulemode   = MODULEMODE_SWCTRL,
3767                 },
3768         },
3769 };
3770
3771 /* wd_timer3 */
3772 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3773         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3774         { .irq = -1 }
3775 };
3776
3777 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3778         .name           = "wd_timer3",
3779         .class          = &omap44xx_wd_timer_hwmod_class,
3780         .clkdm_name     = "abe_clkdm",
3781         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3782         .main_clk       = "wd_timer3_fck",
3783         .prcm = {
3784                 .omap4 = {
3785                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3786                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3787                         .modulemode   = MODULEMODE_SWCTRL,
3788                 },
3789         },
3790 };
3791
3792
3793 /*
3794  * interfaces
3795  */
3796
3797 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3798         {
3799                 .pa_start       = 0x4a204000,
3800                 .pa_end         = 0x4a2040ff,
3801                 .flags          = ADDR_TYPE_RT
3802         },
3803         { }
3804 };
3805
3806 /* c2c -> c2c_target_fw */
3807 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3808         .master         = &omap44xx_c2c_hwmod,
3809         .slave          = &omap44xx_c2c_target_fw_hwmod,
3810         .clk            = "div_core_ck",
3811         .addr           = omap44xx_c2c_target_fw_addrs,
3812         .user           = OCP_USER_MPU,
3813 };
3814
3815 /* l4_cfg -> c2c_target_fw */
3816 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3817         .master         = &omap44xx_l4_cfg_hwmod,
3818         .slave          = &omap44xx_c2c_target_fw_hwmod,
3819         .clk            = "l4_div_ck",
3820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3821 };
3822
3823 /* l3_main_1 -> dmm */
3824 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3825         .master         = &omap44xx_l3_main_1_hwmod,
3826         .slave          = &omap44xx_dmm_hwmod,
3827         .clk            = "l3_div_ck",
3828         .user           = OCP_USER_SDMA,
3829 };
3830
3831 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3832         {
3833                 .pa_start       = 0x4e000000,
3834                 .pa_end         = 0x4e0007ff,
3835                 .flags          = ADDR_TYPE_RT
3836         },
3837         { }
3838 };
3839
3840 /* mpu -> dmm */
3841 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3842         .master         = &omap44xx_mpu_hwmod,
3843         .slave          = &omap44xx_dmm_hwmod,
3844         .clk            = "l3_div_ck",
3845         .addr           = omap44xx_dmm_addrs,
3846         .user           = OCP_USER_MPU,
3847 };
3848
3849 /* c2c -> emif_fw */
3850 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3851         .master         = &omap44xx_c2c_hwmod,
3852         .slave          = &omap44xx_emif_fw_hwmod,
3853         .clk            = "div_core_ck",
3854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3855 };
3856
3857 /* dmm -> emif_fw */
3858 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3859         .master         = &omap44xx_dmm_hwmod,
3860         .slave          = &omap44xx_emif_fw_hwmod,
3861         .clk            = "l3_div_ck",
3862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3863 };
3864
3865 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3866         {
3867                 .pa_start       = 0x4a20c000,
3868                 .pa_end         = 0x4a20c0ff,
3869                 .flags          = ADDR_TYPE_RT
3870         },
3871         { }
3872 };
3873
3874 /* l4_cfg -> emif_fw */
3875 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3876         .master         = &omap44xx_l4_cfg_hwmod,
3877         .slave          = &omap44xx_emif_fw_hwmod,
3878         .clk            = "l4_div_ck",
3879         .addr           = omap44xx_emif_fw_addrs,
3880         .user           = OCP_USER_MPU,
3881 };
3882
3883 /* iva -> l3_instr */
3884 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3885         .master         = &omap44xx_iva_hwmod,
3886         .slave          = &omap44xx_l3_instr_hwmod,
3887         .clk            = "l3_div_ck",
3888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3889 };
3890
3891 /* l3_main_3 -> l3_instr */
3892 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3893         .master         = &omap44xx_l3_main_3_hwmod,
3894         .slave          = &omap44xx_l3_instr_hwmod,
3895         .clk            = "l3_div_ck",
3896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3897 };
3898
3899 /* ocp_wp_noc -> l3_instr */
3900 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3901         .master         = &omap44xx_ocp_wp_noc_hwmod,
3902         .slave          = &omap44xx_l3_instr_hwmod,
3903         .clk            = "l3_div_ck",
3904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3905 };
3906
3907 /* dsp -> l3_main_1 */
3908 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3909         .master         = &omap44xx_dsp_hwmod,
3910         .slave          = &omap44xx_l3_main_1_hwmod,
3911         .clk            = "l3_div_ck",
3912         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3913 };
3914
3915 /* dss -> l3_main_1 */
3916 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3917         .master         = &omap44xx_dss_hwmod,
3918         .slave          = &omap44xx_l3_main_1_hwmod,
3919         .clk            = "l3_div_ck",
3920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3921 };
3922
3923 /* l3_main_2 -> l3_main_1 */
3924 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3925         .master         = &omap44xx_l3_main_2_hwmod,
3926         .slave          = &omap44xx_l3_main_1_hwmod,
3927         .clk            = "l3_div_ck",
3928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3929 };
3930
3931 /* l4_cfg -> l3_main_1 */
3932 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3933         .master         = &omap44xx_l4_cfg_hwmod,
3934         .slave          = &omap44xx_l3_main_1_hwmod,
3935         .clk            = "l4_div_ck",
3936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3937 };
3938
3939 /* mmc1 -> l3_main_1 */
3940 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3941         .master         = &omap44xx_mmc1_hwmod,
3942         .slave          = &omap44xx_l3_main_1_hwmod,
3943         .clk            = "l3_div_ck",
3944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3945 };
3946
3947 /* mmc2 -> l3_main_1 */
3948 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3949         .master         = &omap44xx_mmc2_hwmod,
3950         .slave          = &omap44xx_l3_main_1_hwmod,
3951         .clk            = "l3_div_ck",
3952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3953 };
3954
3955 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3956         {
3957                 .pa_start       = 0x44000000,
3958                 .pa_end         = 0x44000fff,
3959                 .flags          = ADDR_TYPE_RT
3960         },
3961         { }
3962 };
3963
3964 /* mpu -> l3_main_1 */
3965 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3966         .master         = &omap44xx_mpu_hwmod,
3967         .slave          = &omap44xx_l3_main_1_hwmod,
3968         .clk            = "l3_div_ck",
3969         .addr           = omap44xx_l3_main_1_addrs,
3970         .user           = OCP_USER_MPU,
3971 };
3972
3973 /* c2c_target_fw -> l3_main_2 */
3974 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3975         .master         = &omap44xx_c2c_target_fw_hwmod,
3976         .slave          = &omap44xx_l3_main_2_hwmod,
3977         .clk            = "l3_div_ck",
3978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3979 };
3980
3981 /* debugss -> l3_main_2 */
3982 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3983         .master         = &omap44xx_debugss_hwmod,
3984         .slave          = &omap44xx_l3_main_2_hwmod,
3985         .clk            = "dbgclk_mux_ck",
3986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3987 };
3988
3989 /* dma_system -> l3_main_2 */
3990 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3991         .master         = &omap44xx_dma_system_hwmod,
3992         .slave          = &omap44xx_l3_main_2_hwmod,
3993         .clk            = "l3_div_ck",
3994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3995 };
3996
3997 /* fdif -> l3_main_2 */
3998 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3999         .master         = &omap44xx_fdif_hwmod,
4000         .slave          = &omap44xx_l3_main_2_hwmod,
4001         .clk            = "l3_div_ck",
4002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4003 };
4004
4005 /* gpu -> l3_main_2 */
4006 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4007         .master         = &omap44xx_gpu_hwmod,
4008         .slave          = &omap44xx_l3_main_2_hwmod,
4009         .clk            = "l3_div_ck",
4010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4011 };
4012
4013 /* hsi -> l3_main_2 */
4014 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4015         .master         = &omap44xx_hsi_hwmod,
4016         .slave          = &omap44xx_l3_main_2_hwmod,
4017         .clk            = "l3_div_ck",
4018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4019 };
4020
4021 /* ipu -> l3_main_2 */
4022 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4023         .master         = &omap44xx_ipu_hwmod,
4024         .slave          = &omap44xx_l3_main_2_hwmod,
4025         .clk            = "l3_div_ck",
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 /* iss -> l3_main_2 */
4030 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4031         .master         = &omap44xx_iss_hwmod,
4032         .slave          = &omap44xx_l3_main_2_hwmod,
4033         .clk            = "l3_div_ck",
4034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4035 };
4036
4037 /* iva -> l3_main_2 */
4038 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4039         .master         = &omap44xx_iva_hwmod,
4040         .slave          = &omap44xx_l3_main_2_hwmod,
4041         .clk            = "l3_div_ck",
4042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4043 };
4044
4045 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4046         {
4047                 .pa_start       = 0x44800000,
4048                 .pa_end         = 0x44801fff,
4049                 .flags          = ADDR_TYPE_RT
4050         },
4051         { }
4052 };
4053
4054 /* l3_main_1 -> l3_main_2 */
4055 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4056         .master         = &omap44xx_l3_main_1_hwmod,
4057         .slave          = &omap44xx_l3_main_2_hwmod,
4058         .clk            = "l3_div_ck",
4059         .addr           = omap44xx_l3_main_2_addrs,
4060         .user           = OCP_USER_MPU,
4061 };
4062
4063 /* l4_cfg -> l3_main_2 */
4064 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4065         .master         = &omap44xx_l4_cfg_hwmod,
4066         .slave          = &omap44xx_l3_main_2_hwmod,
4067         .clk            = "l4_div_ck",
4068         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4069 };
4070
4071 /* usb_host_fs -> l3_main_2 */
4072 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4073         .master         = &omap44xx_usb_host_fs_hwmod,
4074         .slave          = &omap44xx_l3_main_2_hwmod,
4075         .clk            = "l3_div_ck",
4076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4077 };
4078
4079 /* usb_host_hs -> l3_main_2 */
4080 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4081         .master         = &omap44xx_usb_host_hs_hwmod,
4082         .slave          = &omap44xx_l3_main_2_hwmod,
4083         .clk            = "l3_div_ck",
4084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4085 };
4086
4087 /* usb_otg_hs -> l3_main_2 */
4088 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4089         .master         = &omap44xx_usb_otg_hs_hwmod,
4090         .slave          = &omap44xx_l3_main_2_hwmod,
4091         .clk            = "l3_div_ck",
4092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4093 };
4094
4095 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4096         {
4097                 .pa_start       = 0x45000000,
4098                 .pa_end         = 0x45000fff,
4099                 .flags          = ADDR_TYPE_RT
4100         },
4101         { }
4102 };
4103
4104 /* l3_main_1 -> l3_main_3 */
4105 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4106         .master         = &omap44xx_l3_main_1_hwmod,
4107         .slave          = &omap44xx_l3_main_3_hwmod,
4108         .clk            = "l3_div_ck",
4109         .addr           = omap44xx_l3_main_3_addrs,
4110         .user           = OCP_USER_MPU,
4111 };
4112
4113 /* l3_main_2 -> l3_main_3 */
4114 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4115         .master         = &omap44xx_l3_main_2_hwmod,
4116         .slave          = &omap44xx_l3_main_3_hwmod,
4117         .clk            = "l3_div_ck",
4118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4119 };
4120
4121 /* l4_cfg -> l3_main_3 */
4122 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4123         .master         = &omap44xx_l4_cfg_hwmod,
4124         .slave          = &omap44xx_l3_main_3_hwmod,
4125         .clk            = "l4_div_ck",
4126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4127 };
4128
4129 /* aess -> l4_abe */
4130 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4131         .master         = &omap44xx_aess_hwmod,
4132         .slave          = &omap44xx_l4_abe_hwmod,
4133         .clk            = "ocp_abe_iclk",
4134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4135 };
4136
4137 /* dsp -> l4_abe */
4138 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4139         .master         = &omap44xx_dsp_hwmod,
4140         .slave          = &omap44xx_l4_abe_hwmod,
4141         .clk            = "ocp_abe_iclk",
4142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4143 };
4144
4145 /* l3_main_1 -> l4_abe */
4146 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4147         .master         = &omap44xx_l3_main_1_hwmod,
4148         .slave          = &omap44xx_l4_abe_hwmod,
4149         .clk            = "l3_div_ck",
4150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4151 };
4152
4153 /* mpu -> l4_abe */
4154 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4155         .master         = &omap44xx_mpu_hwmod,
4156         .slave          = &omap44xx_l4_abe_hwmod,
4157         .clk            = "ocp_abe_iclk",
4158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4159 };
4160
4161 /* l3_main_1 -> l4_cfg */
4162 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4163         .master         = &omap44xx_l3_main_1_hwmod,
4164         .slave          = &omap44xx_l4_cfg_hwmod,
4165         .clk            = "l3_div_ck",
4166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4167 };
4168
4169 /* l3_main_2 -> l4_per */
4170 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4171         .master         = &omap44xx_l3_main_2_hwmod,
4172         .slave          = &omap44xx_l4_per_hwmod,
4173         .clk            = "l3_div_ck",
4174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4175 };
4176
4177 /* l4_cfg -> l4_wkup */
4178 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4179         .master         = &omap44xx_l4_cfg_hwmod,
4180         .slave          = &omap44xx_l4_wkup_hwmod,
4181         .clk            = "l4_div_ck",
4182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4183 };
4184
4185 /* mpu -> mpu_private */
4186 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4187         .master         = &omap44xx_mpu_hwmod,
4188         .slave          = &omap44xx_mpu_private_hwmod,
4189         .clk            = "l3_div_ck",
4190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4191 };
4192
4193 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4194         {
4195                 .pa_start       = 0x4a102000,
4196                 .pa_end         = 0x4a10207f,
4197                 .flags          = ADDR_TYPE_RT
4198         },
4199         { }
4200 };
4201
4202 /* l4_cfg -> ocp_wp_noc */
4203 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4204         .master         = &omap44xx_l4_cfg_hwmod,
4205         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4206         .clk            = "l4_div_ck",
4207         .addr           = omap44xx_ocp_wp_noc_addrs,
4208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4209 };
4210
4211 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4212         {
4213                 .pa_start       = 0x401f1000,
4214                 .pa_end         = 0x401f13ff,
4215                 .flags          = ADDR_TYPE_RT
4216         },
4217         { }
4218 };
4219
4220 /* l4_abe -> aess */
4221 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4222         .master         = &omap44xx_l4_abe_hwmod,
4223         .slave          = &omap44xx_aess_hwmod,
4224         .clk            = "ocp_abe_iclk",
4225         .addr           = omap44xx_aess_addrs,
4226         .user           = OCP_USER_MPU,
4227 };
4228
4229 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4230         {
4231                 .pa_start       = 0x490f1000,
4232                 .pa_end         = 0x490f13ff,
4233                 .flags          = ADDR_TYPE_RT
4234         },
4235         { }
4236 };
4237
4238 /* l4_abe -> aess (dma) */
4239 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4240         .master         = &omap44xx_l4_abe_hwmod,
4241         .slave          = &omap44xx_aess_hwmod,
4242         .clk            = "ocp_abe_iclk",
4243         .addr           = omap44xx_aess_dma_addrs,
4244         .user           = OCP_USER_SDMA,
4245 };
4246
4247 /* l3_main_2 -> c2c */
4248 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4249         .master         = &omap44xx_l3_main_2_hwmod,
4250         .slave          = &omap44xx_c2c_hwmod,
4251         .clk            = "l3_div_ck",
4252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4253 };
4254
4255 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4256         {
4257                 .pa_start       = 0x4a304000,
4258                 .pa_end         = 0x4a30401f,
4259                 .flags          = ADDR_TYPE_RT
4260         },
4261         { }
4262 };
4263
4264 /* l4_wkup -> counter_32k */
4265 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4266         .master         = &omap44xx_l4_wkup_hwmod,
4267         .slave          = &omap44xx_counter_32k_hwmod,
4268         .clk            = "l4_wkup_clk_mux_ck",
4269         .addr           = omap44xx_counter_32k_addrs,
4270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4271 };
4272
4273 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4274         {
4275                 .pa_start       = 0x4a002000,
4276                 .pa_end         = 0x4a0027ff,
4277                 .flags          = ADDR_TYPE_RT
4278         },
4279         { }
4280 };
4281
4282 /* l4_cfg -> ctrl_module_core */
4283 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4284         .master         = &omap44xx_l4_cfg_hwmod,
4285         .slave          = &omap44xx_ctrl_module_core_hwmod,
4286         .clk            = "l4_div_ck",
4287         .addr           = omap44xx_ctrl_module_core_addrs,
4288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4289 };
4290
4291 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4292         {
4293                 .pa_start       = 0x4a100000,
4294                 .pa_end         = 0x4a1007ff,
4295                 .flags          = ADDR_TYPE_RT
4296         },
4297         { }
4298 };
4299
4300 /* l4_cfg -> ctrl_module_pad_core */
4301 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4302         .master         = &omap44xx_l4_cfg_hwmod,
4303         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4304         .clk            = "l4_div_ck",
4305         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4307 };
4308
4309 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4310         {
4311                 .pa_start       = 0x4a30c000,
4312                 .pa_end         = 0x4a30c7ff,
4313                 .flags          = ADDR_TYPE_RT
4314         },
4315         { }
4316 };
4317
4318 /* l4_wkup -> ctrl_module_wkup */
4319 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4320         .master         = &omap44xx_l4_wkup_hwmod,
4321         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4322         .clk            = "l4_wkup_clk_mux_ck",
4323         .addr           = omap44xx_ctrl_module_wkup_addrs,
4324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4325 };
4326
4327 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4328         {
4329                 .pa_start       = 0x4a31e000,
4330                 .pa_end         = 0x4a31e7ff,
4331                 .flags          = ADDR_TYPE_RT
4332         },
4333         { }
4334 };
4335
4336 /* l4_wkup -> ctrl_module_pad_wkup */
4337 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4338         .master         = &omap44xx_l4_wkup_hwmod,
4339         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4340         .clk            = "l4_wkup_clk_mux_ck",
4341         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4343 };
4344
4345 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4346         {
4347                 .pa_start       = 0x54160000,
4348                 .pa_end         = 0x54167fff,
4349                 .flags          = ADDR_TYPE_RT
4350         },
4351         { }
4352 };
4353
4354 /* l3_instr -> debugss */
4355 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4356         .master         = &omap44xx_l3_instr_hwmod,
4357         .slave          = &omap44xx_debugss_hwmod,
4358         .clk            = "l3_div_ck",
4359         .addr           = omap44xx_debugss_addrs,
4360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4361 };
4362
4363 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4364         {
4365                 .pa_start       = 0x4a056000,
4366                 .pa_end         = 0x4a056fff,
4367                 .flags          = ADDR_TYPE_RT
4368         },
4369         { }
4370 };
4371
4372 /* l4_cfg -> dma_system */
4373 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4374         .master         = &omap44xx_l4_cfg_hwmod,
4375         .slave          = &omap44xx_dma_system_hwmod,
4376         .clk            = "l4_div_ck",
4377         .addr           = omap44xx_dma_system_addrs,
4378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4379 };
4380
4381 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4382         {
4383                 .name           = "mpu",
4384                 .pa_start       = 0x4012e000,
4385                 .pa_end         = 0x4012e07f,
4386                 .flags          = ADDR_TYPE_RT
4387         },
4388         { }
4389 };
4390
4391 /* l4_abe -> dmic */
4392 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4393         .master         = &omap44xx_l4_abe_hwmod,
4394         .slave          = &omap44xx_dmic_hwmod,
4395         .clk            = "ocp_abe_iclk",
4396         .addr           = omap44xx_dmic_addrs,
4397         .user           = OCP_USER_MPU,
4398 };
4399
4400 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4401         {
4402                 .name           = "dma",
4403                 .pa_start       = 0x4902e000,
4404                 .pa_end         = 0x4902e07f,
4405                 .flags          = ADDR_TYPE_RT
4406         },
4407         { }
4408 };
4409
4410 /* l4_abe -> dmic (dma) */
4411 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4412         .master         = &omap44xx_l4_abe_hwmod,
4413         .slave          = &omap44xx_dmic_hwmod,
4414         .clk            = "ocp_abe_iclk",
4415         .addr           = omap44xx_dmic_dma_addrs,
4416         .user           = OCP_USER_SDMA,
4417 };
4418
4419 /* dsp -> iva */
4420 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4421         .master         = &omap44xx_dsp_hwmod,
4422         .slave          = &omap44xx_iva_hwmod,
4423         .clk            = "dpll_iva_m5x2_ck",
4424         .user           = OCP_USER_DSP,
4425 };
4426
4427 /* dsp -> sl2if */
4428 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4429         .master         = &omap44xx_dsp_hwmod,
4430         .slave          = &omap44xx_sl2if_hwmod,
4431         .clk            = "dpll_iva_m5x2_ck",
4432         .user           = OCP_USER_DSP,
4433 };
4434
4435 /* l4_cfg -> dsp */
4436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4437         .master         = &omap44xx_l4_cfg_hwmod,
4438         .slave          = &omap44xx_dsp_hwmod,
4439         .clk            = "l4_div_ck",
4440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4441 };
4442
4443 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4444         {
4445                 .pa_start       = 0x58000000,
4446                 .pa_end         = 0x5800007f,
4447                 .flags          = ADDR_TYPE_RT
4448         },
4449         { }
4450 };
4451
4452 /* l3_main_2 -> dss */
4453 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4454         .master         = &omap44xx_l3_main_2_hwmod,
4455         .slave          = &omap44xx_dss_hwmod,
4456         .clk            = "dss_fck",
4457         .addr           = omap44xx_dss_dma_addrs,
4458         .user           = OCP_USER_SDMA,
4459 };
4460
4461 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4462         {
4463                 .pa_start       = 0x48040000,
4464                 .pa_end         = 0x4804007f,
4465                 .flags          = ADDR_TYPE_RT
4466         },
4467         { }
4468 };
4469
4470 /* l4_per -> dss */
4471 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4472         .master         = &omap44xx_l4_per_hwmod,
4473         .slave          = &omap44xx_dss_hwmod,
4474         .clk            = "l4_div_ck",
4475         .addr           = omap44xx_dss_addrs,
4476         .user           = OCP_USER_MPU,
4477 };
4478
4479 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4480         {
4481                 .pa_start       = 0x58001000,
4482                 .pa_end         = 0x58001fff,
4483                 .flags          = ADDR_TYPE_RT
4484         },
4485         { }
4486 };
4487
4488 /* l3_main_2 -> dss_dispc */
4489 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4490         .master         = &omap44xx_l3_main_2_hwmod,
4491         .slave          = &omap44xx_dss_dispc_hwmod,
4492         .clk            = "dss_fck",
4493         .addr           = omap44xx_dss_dispc_dma_addrs,
4494         .user           = OCP_USER_SDMA,
4495 };
4496
4497 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4498         {
4499                 .pa_start       = 0x48041000,
4500                 .pa_end         = 0x48041fff,
4501                 .flags          = ADDR_TYPE_RT
4502         },
4503         { }
4504 };
4505
4506 /* l4_per -> dss_dispc */
4507 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4508         .master         = &omap44xx_l4_per_hwmod,
4509         .slave          = &omap44xx_dss_dispc_hwmod,
4510         .clk            = "l4_div_ck",
4511         .addr           = omap44xx_dss_dispc_addrs,
4512         .user           = OCP_USER_MPU,
4513 };
4514
4515 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4516         {
4517                 .pa_start       = 0x58004000,
4518                 .pa_end         = 0x580041ff,
4519                 .flags          = ADDR_TYPE_RT
4520         },
4521         { }
4522 };
4523
4524 /* l3_main_2 -> dss_dsi1 */
4525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4526         .master         = &omap44xx_l3_main_2_hwmod,
4527         .slave          = &omap44xx_dss_dsi1_hwmod,
4528         .clk            = "dss_fck",
4529         .addr           = omap44xx_dss_dsi1_dma_addrs,
4530         .user           = OCP_USER_SDMA,
4531 };
4532
4533 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4534         {
4535                 .pa_start       = 0x48044000,
4536                 .pa_end         = 0x480441ff,
4537                 .flags          = ADDR_TYPE_RT
4538         },
4539         { }
4540 };
4541
4542 /* l4_per -> dss_dsi1 */
4543 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4544         .master         = &omap44xx_l4_per_hwmod,
4545         .slave          = &omap44xx_dss_dsi1_hwmod,
4546         .clk            = "l4_div_ck",
4547         .addr           = omap44xx_dss_dsi1_addrs,
4548         .user           = OCP_USER_MPU,
4549 };
4550
4551 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4552         {
4553                 .pa_start       = 0x58005000,
4554                 .pa_end         = 0x580051ff,
4555                 .flags          = ADDR_TYPE_RT
4556         },
4557         { }
4558 };
4559
4560 /* l3_main_2 -> dss_dsi2 */
4561 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4562         .master         = &omap44xx_l3_main_2_hwmod,
4563         .slave          = &omap44xx_dss_dsi2_hwmod,
4564         .clk            = "dss_fck",
4565         .addr           = omap44xx_dss_dsi2_dma_addrs,
4566         .user           = OCP_USER_SDMA,
4567 };
4568
4569 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4570         {
4571                 .pa_start       = 0x48045000,
4572                 .pa_end         = 0x480451ff,
4573                 .flags          = ADDR_TYPE_RT
4574         },
4575         { }
4576 };
4577
4578 /* l4_per -> dss_dsi2 */
4579 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4580         .master         = &omap44xx_l4_per_hwmod,
4581         .slave          = &omap44xx_dss_dsi2_hwmod,
4582         .clk            = "l4_div_ck",
4583         .addr           = omap44xx_dss_dsi2_addrs,
4584         .user           = OCP_USER_MPU,
4585 };
4586
4587 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4588         {
4589                 .pa_start       = 0x58006000,
4590                 .pa_end         = 0x58006fff,
4591                 .flags          = ADDR_TYPE_RT
4592         },
4593         { }
4594 };
4595
4596 /* l3_main_2 -> dss_hdmi */
4597 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4598         .master         = &omap44xx_l3_main_2_hwmod,
4599         .slave          = &omap44xx_dss_hdmi_hwmod,
4600         .clk            = "dss_fck",
4601         .addr           = omap44xx_dss_hdmi_dma_addrs,
4602         .user           = OCP_USER_SDMA,
4603 };
4604
4605 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4606         {
4607                 .pa_start       = 0x48046000,
4608                 .pa_end         = 0x48046fff,
4609                 .flags          = ADDR_TYPE_RT
4610         },
4611         { }
4612 };
4613
4614 /* l4_per -> dss_hdmi */
4615 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4616         .master         = &omap44xx_l4_per_hwmod,
4617         .slave          = &omap44xx_dss_hdmi_hwmod,
4618         .clk            = "l4_div_ck",
4619         .addr           = omap44xx_dss_hdmi_addrs,
4620         .user           = OCP_USER_MPU,
4621 };
4622
4623 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4624         {
4625                 .pa_start       = 0x58002000,
4626                 .pa_end         = 0x580020ff,
4627                 .flags          = ADDR_TYPE_RT
4628         },
4629         { }
4630 };
4631
4632 /* l3_main_2 -> dss_rfbi */
4633 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4634         .master         = &omap44xx_l3_main_2_hwmod,
4635         .slave          = &omap44xx_dss_rfbi_hwmod,
4636         .clk            = "dss_fck",
4637         .addr           = omap44xx_dss_rfbi_dma_addrs,
4638         .user           = OCP_USER_SDMA,
4639 };
4640
4641 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4642         {
4643                 .pa_start       = 0x48042000,
4644                 .pa_end         = 0x480420ff,
4645                 .flags          = ADDR_TYPE_RT
4646         },
4647         { }
4648 };
4649
4650 /* l4_per -> dss_rfbi */
4651 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4652         .master         = &omap44xx_l4_per_hwmod,
4653         .slave          = &omap44xx_dss_rfbi_hwmod,
4654         .clk            = "l4_div_ck",
4655         .addr           = omap44xx_dss_rfbi_addrs,
4656         .user           = OCP_USER_MPU,
4657 };
4658
4659 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4660         {
4661                 .pa_start       = 0x58003000,
4662                 .pa_end         = 0x580030ff,
4663                 .flags          = ADDR_TYPE_RT
4664         },
4665         { }
4666 };
4667
4668 /* l3_main_2 -> dss_venc */
4669 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4670         .master         = &omap44xx_l3_main_2_hwmod,
4671         .slave          = &omap44xx_dss_venc_hwmod,
4672         .clk            = "dss_fck",
4673         .addr           = omap44xx_dss_venc_dma_addrs,
4674         .user           = OCP_USER_SDMA,
4675 };
4676
4677 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4678         {
4679                 .pa_start       = 0x48043000,
4680                 .pa_end         = 0x480430ff,
4681                 .flags          = ADDR_TYPE_RT
4682         },
4683         { }
4684 };
4685
4686 /* l4_per -> dss_venc */
4687 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4688         .master         = &omap44xx_l4_per_hwmod,
4689         .slave          = &omap44xx_dss_venc_hwmod,
4690         .clk            = "l4_div_ck",
4691         .addr           = omap44xx_dss_venc_addrs,
4692         .user           = OCP_USER_MPU,
4693 };
4694
4695 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4696         {
4697                 .pa_start       = 0x48078000,
4698                 .pa_end         = 0x48078fff,
4699                 .flags          = ADDR_TYPE_RT
4700         },
4701         { }
4702 };
4703
4704 /* l4_per -> elm */
4705 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4706         .master         = &omap44xx_l4_per_hwmod,
4707         .slave          = &omap44xx_elm_hwmod,
4708         .clk            = "l4_div_ck",
4709         .addr           = omap44xx_elm_addrs,
4710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4711 };
4712
4713 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4714         {
4715                 .pa_start       = 0x4c000000,
4716                 .pa_end         = 0x4c0000ff,
4717                 .flags          = ADDR_TYPE_RT
4718         },
4719         { }
4720 };
4721
4722 /* emif_fw -> emif1 */
4723 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4724         .master         = &omap44xx_emif_fw_hwmod,
4725         .slave          = &omap44xx_emif1_hwmod,
4726         .clk            = "l3_div_ck",
4727         .addr           = omap44xx_emif1_addrs,
4728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4729 };
4730
4731 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4732         {
4733                 .pa_start       = 0x4d000000,
4734                 .pa_end         = 0x4d0000ff,
4735                 .flags          = ADDR_TYPE_RT
4736         },
4737         { }
4738 };
4739
4740 /* emif_fw -> emif2 */
4741 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4742         .master         = &omap44xx_emif_fw_hwmod,
4743         .slave          = &omap44xx_emif2_hwmod,
4744         .clk            = "l3_div_ck",
4745         .addr           = omap44xx_emif2_addrs,
4746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4747 };
4748
4749 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4750         {
4751                 .pa_start       = 0x4a10a000,
4752                 .pa_end         = 0x4a10a1ff,
4753                 .flags          = ADDR_TYPE_RT
4754         },
4755         { }
4756 };
4757
4758 /* l4_cfg -> fdif */
4759 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4760         .master         = &omap44xx_l4_cfg_hwmod,
4761         .slave          = &omap44xx_fdif_hwmod,
4762         .clk            = "l4_div_ck",
4763         .addr           = omap44xx_fdif_addrs,
4764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4765 };
4766
4767 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4768         {
4769                 .pa_start       = 0x4a310000,
4770                 .pa_end         = 0x4a3101ff,
4771                 .flags          = ADDR_TYPE_RT
4772         },
4773         { }
4774 };
4775
4776 /* l4_wkup -> gpio1 */
4777 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4778         .master         = &omap44xx_l4_wkup_hwmod,
4779         .slave          = &omap44xx_gpio1_hwmod,
4780         .clk            = "l4_wkup_clk_mux_ck",
4781         .addr           = omap44xx_gpio1_addrs,
4782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4783 };
4784
4785 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4786         {
4787                 .pa_start       = 0x48055000,
4788                 .pa_end         = 0x480551ff,
4789                 .flags          = ADDR_TYPE_RT
4790         },
4791         { }
4792 };
4793
4794 /* l4_per -> gpio2 */
4795 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4796         .master         = &omap44xx_l4_per_hwmod,
4797         .slave          = &omap44xx_gpio2_hwmod,
4798         .clk            = "l4_div_ck",
4799         .addr           = omap44xx_gpio2_addrs,
4800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4801 };
4802
4803 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4804         {
4805                 .pa_start       = 0x48057000,
4806                 .pa_end         = 0x480571ff,
4807                 .flags          = ADDR_TYPE_RT
4808         },
4809         { }
4810 };
4811
4812 /* l4_per -> gpio3 */
4813 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4814         .master         = &omap44xx_l4_per_hwmod,
4815         .slave          = &omap44xx_gpio3_hwmod,
4816         .clk            = "l4_div_ck",
4817         .addr           = omap44xx_gpio3_addrs,
4818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4819 };
4820
4821 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4822         {
4823                 .pa_start       = 0x48059000,
4824                 .pa_end         = 0x480591ff,
4825                 .flags          = ADDR_TYPE_RT
4826         },
4827         { }
4828 };
4829
4830 /* l4_per -> gpio4 */
4831 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4832         .master         = &omap44xx_l4_per_hwmod,
4833         .slave          = &omap44xx_gpio4_hwmod,
4834         .clk            = "l4_div_ck",
4835         .addr           = omap44xx_gpio4_addrs,
4836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4837 };
4838
4839 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4840         {
4841                 .pa_start       = 0x4805b000,
4842                 .pa_end         = 0x4805b1ff,
4843                 .flags          = ADDR_TYPE_RT
4844         },
4845         { }
4846 };
4847
4848 /* l4_per -> gpio5 */
4849 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4850         .master         = &omap44xx_l4_per_hwmod,
4851         .slave          = &omap44xx_gpio5_hwmod,
4852         .clk            = "l4_div_ck",
4853         .addr           = omap44xx_gpio5_addrs,
4854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4855 };
4856
4857 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4858         {
4859                 .pa_start       = 0x4805d000,
4860                 .pa_end         = 0x4805d1ff,
4861                 .flags          = ADDR_TYPE_RT
4862         },
4863         { }
4864 };
4865
4866 /* l4_per -> gpio6 */
4867 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4868         .master         = &omap44xx_l4_per_hwmod,
4869         .slave          = &omap44xx_gpio6_hwmod,
4870         .clk            = "l4_div_ck",
4871         .addr           = omap44xx_gpio6_addrs,
4872         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4873 };
4874
4875 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4876         {
4877                 .pa_start       = 0x50000000,
4878                 .pa_end         = 0x500003ff,
4879                 .flags          = ADDR_TYPE_RT
4880         },
4881         { }
4882 };
4883
4884 /* l3_main_2 -> gpmc */
4885 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4886         .master         = &omap44xx_l3_main_2_hwmod,
4887         .slave          = &omap44xx_gpmc_hwmod,
4888         .clk            = "l3_div_ck",
4889         .addr           = omap44xx_gpmc_addrs,
4890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4891 };
4892
4893 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4894         {
4895                 .pa_start       = 0x56000000,
4896                 .pa_end         = 0x5600ffff,
4897                 .flags          = ADDR_TYPE_RT
4898         },
4899         { }
4900 };
4901
4902 /* l3_main_2 -> gpu */
4903 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4904         .master         = &omap44xx_l3_main_2_hwmod,
4905         .slave          = &omap44xx_gpu_hwmod,
4906         .clk            = "l3_div_ck",
4907         .addr           = omap44xx_gpu_addrs,
4908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4909 };
4910
4911 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4912         {
4913                 .pa_start       = 0x480b2000,
4914                 .pa_end         = 0x480b201f,
4915                 .flags          = ADDR_TYPE_RT
4916         },
4917         { }
4918 };
4919
4920 /* l4_per -> hdq1w */
4921 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4922         .master         = &omap44xx_l4_per_hwmod,
4923         .slave          = &omap44xx_hdq1w_hwmod,
4924         .clk            = "l4_div_ck",
4925         .addr           = omap44xx_hdq1w_addrs,
4926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4927 };
4928
4929 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4930         {
4931                 .pa_start       = 0x4a058000,
4932                 .pa_end         = 0x4a05bfff,
4933                 .flags          = ADDR_TYPE_RT
4934         },
4935         { }
4936 };
4937
4938 /* l4_cfg -> hsi */
4939 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4940         .master         = &omap44xx_l4_cfg_hwmod,
4941         .slave          = &omap44xx_hsi_hwmod,
4942         .clk            = "l4_div_ck",
4943         .addr           = omap44xx_hsi_addrs,
4944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4945 };
4946
4947 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4948         {
4949                 .pa_start       = 0x48070000,
4950                 .pa_end         = 0x480700ff,
4951                 .flags          = ADDR_TYPE_RT
4952         },
4953         { }
4954 };
4955
4956 /* l4_per -> i2c1 */
4957 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4958         .master         = &omap44xx_l4_per_hwmod,
4959         .slave          = &omap44xx_i2c1_hwmod,
4960         .clk            = "l4_div_ck",
4961         .addr           = omap44xx_i2c1_addrs,
4962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4963 };
4964
4965 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4966         {
4967                 .pa_start       = 0x48072000,
4968                 .pa_end         = 0x480720ff,
4969                 .flags          = ADDR_TYPE_RT
4970         },
4971         { }
4972 };
4973
4974 /* l4_per -> i2c2 */
4975 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4976         .master         = &omap44xx_l4_per_hwmod,
4977         .slave          = &omap44xx_i2c2_hwmod,
4978         .clk            = "l4_div_ck",
4979         .addr           = omap44xx_i2c2_addrs,
4980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4981 };
4982
4983 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4984         {
4985                 .pa_start       = 0x48060000,
4986                 .pa_end         = 0x480600ff,
4987                 .flags          = ADDR_TYPE_RT
4988         },
4989         { }
4990 };
4991
4992 /* l4_per -> i2c3 */
4993 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4994         .master         = &omap44xx_l4_per_hwmod,
4995         .slave          = &omap44xx_i2c3_hwmod,
4996         .clk            = "l4_div_ck",
4997         .addr           = omap44xx_i2c3_addrs,
4998         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4999 };
5000
5001 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5002         {
5003                 .pa_start       = 0x48350000,
5004                 .pa_end         = 0x483500ff,
5005                 .flags          = ADDR_TYPE_RT
5006         },
5007         { }
5008 };
5009
5010 /* l4_per -> i2c4 */
5011 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5012         .master         = &omap44xx_l4_per_hwmod,
5013         .slave          = &omap44xx_i2c4_hwmod,
5014         .clk            = "l4_div_ck",
5015         .addr           = omap44xx_i2c4_addrs,
5016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5017 };
5018
5019 /* l3_main_2 -> ipu */
5020 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5021         .master         = &omap44xx_l3_main_2_hwmod,
5022         .slave          = &omap44xx_ipu_hwmod,
5023         .clk            = "l3_div_ck",
5024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5025 };
5026
5027 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5028         {
5029                 .pa_start       = 0x52000000,
5030                 .pa_end         = 0x520000ff,
5031                 .flags          = ADDR_TYPE_RT
5032         },
5033         { }
5034 };
5035
5036 /* l3_main_2 -> iss */
5037 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5038         .master         = &omap44xx_l3_main_2_hwmod,
5039         .slave          = &omap44xx_iss_hwmod,
5040         .clk            = "l3_div_ck",
5041         .addr           = omap44xx_iss_addrs,
5042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5043 };
5044
5045 /* iva -> sl2if */
5046 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5047         .master         = &omap44xx_iva_hwmod,
5048         .slave          = &omap44xx_sl2if_hwmod,
5049         .clk            = "dpll_iva_m5x2_ck",
5050         .user           = OCP_USER_IVA,
5051 };
5052
5053 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5054         {
5055                 .pa_start       = 0x5a000000,
5056                 .pa_end         = 0x5a07ffff,
5057                 .flags          = ADDR_TYPE_RT
5058         },
5059         { }
5060 };
5061
5062 /* l3_main_2 -> iva */
5063 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5064         .master         = &omap44xx_l3_main_2_hwmod,
5065         .slave          = &omap44xx_iva_hwmod,
5066         .clk            = "l3_div_ck",
5067         .addr           = omap44xx_iva_addrs,
5068         .user           = OCP_USER_MPU,
5069 };
5070
5071 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5072         {
5073                 .pa_start       = 0x4a31c000,
5074                 .pa_end         = 0x4a31c07f,
5075                 .flags          = ADDR_TYPE_RT
5076         },
5077         { }
5078 };
5079
5080 /* l4_wkup -> kbd */
5081 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5082         .master         = &omap44xx_l4_wkup_hwmod,
5083         .slave          = &omap44xx_kbd_hwmod,
5084         .clk            = "l4_wkup_clk_mux_ck",
5085         .addr           = omap44xx_kbd_addrs,
5086         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5087 };
5088
5089 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5090         {
5091                 .pa_start       = 0x4a0f4000,
5092                 .pa_end         = 0x4a0f41ff,
5093                 .flags          = ADDR_TYPE_RT
5094         },
5095         { }
5096 };
5097
5098 /* l4_cfg -> mailbox */
5099 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5100         .master         = &omap44xx_l4_cfg_hwmod,
5101         .slave          = &omap44xx_mailbox_hwmod,
5102         .clk            = "l4_div_ck",
5103         .addr           = omap44xx_mailbox_addrs,
5104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5105 };
5106
5107 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5108         {
5109                 .pa_start       = 0x40128000,
5110                 .pa_end         = 0x401283ff,
5111                 .flags          = ADDR_TYPE_RT
5112         },
5113         { }
5114 };
5115
5116 /* l4_abe -> mcasp */
5117 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5118         .master         = &omap44xx_l4_abe_hwmod,
5119         .slave          = &omap44xx_mcasp_hwmod,
5120         .clk            = "ocp_abe_iclk",
5121         .addr           = omap44xx_mcasp_addrs,
5122         .user           = OCP_USER_MPU,
5123 };
5124
5125 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5126         {
5127                 .pa_start       = 0x49028000,
5128                 .pa_end         = 0x490283ff,
5129                 .flags          = ADDR_TYPE_RT
5130         },
5131         { }
5132 };
5133
5134 /* l4_abe -> mcasp (dma) */
5135 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5136         .master         = &omap44xx_l4_abe_hwmod,
5137         .slave          = &omap44xx_mcasp_hwmod,
5138         .clk            = "ocp_abe_iclk",
5139         .addr           = omap44xx_mcasp_dma_addrs,
5140         .user           = OCP_USER_SDMA,
5141 };
5142
5143 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5144         {
5145                 .name           = "mpu",
5146                 .pa_start       = 0x40122000,
5147                 .pa_end         = 0x401220ff,
5148                 .flags          = ADDR_TYPE_RT
5149         },
5150         { }
5151 };
5152
5153 /* l4_abe -> mcbsp1 */
5154 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5155         .master         = &omap44xx_l4_abe_hwmod,
5156         .slave          = &omap44xx_mcbsp1_hwmod,
5157         .clk            = "ocp_abe_iclk",
5158         .addr           = omap44xx_mcbsp1_addrs,
5159         .user           = OCP_USER_MPU,
5160 };
5161
5162 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5163         {
5164                 .name           = "dma",
5165                 .pa_start       = 0x49022000,
5166                 .pa_end         = 0x490220ff,
5167                 .flags          = ADDR_TYPE_RT
5168         },
5169         { }
5170 };
5171
5172 /* l4_abe -> mcbsp1 (dma) */
5173 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5174         .master         = &omap44xx_l4_abe_hwmod,
5175         .slave          = &omap44xx_mcbsp1_hwmod,
5176         .clk            = "ocp_abe_iclk",
5177         .addr           = omap44xx_mcbsp1_dma_addrs,
5178         .user           = OCP_USER_SDMA,
5179 };
5180
5181 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5182         {
5183                 .name           = "mpu",
5184                 .pa_start       = 0x40124000,
5185                 .pa_end         = 0x401240ff,
5186                 .flags          = ADDR_TYPE_RT
5187         },
5188         { }
5189 };
5190
5191 /* l4_abe -> mcbsp2 */
5192 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5193         .master         = &omap44xx_l4_abe_hwmod,
5194         .slave          = &omap44xx_mcbsp2_hwmod,
5195         .clk            = "ocp_abe_iclk",
5196         .addr           = omap44xx_mcbsp2_addrs,
5197         .user           = OCP_USER_MPU,
5198 };
5199
5200 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5201         {
5202                 .name           = "dma",
5203                 .pa_start       = 0x49024000,
5204                 .pa_end         = 0x490240ff,
5205                 .flags          = ADDR_TYPE_RT
5206         },
5207         { }
5208 };
5209
5210 /* l4_abe -> mcbsp2 (dma) */
5211 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5212         .master         = &omap44xx_l4_abe_hwmod,
5213         .slave          = &omap44xx_mcbsp2_hwmod,
5214         .clk            = "ocp_abe_iclk",
5215         .addr           = omap44xx_mcbsp2_dma_addrs,
5216         .user           = OCP_USER_SDMA,
5217 };
5218
5219 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5220         {
5221                 .name           = "mpu",
5222                 .pa_start       = 0x40126000,
5223                 .pa_end         = 0x401260ff,
5224                 .flags          = ADDR_TYPE_RT
5225         },
5226         { }
5227 };
5228
5229 /* l4_abe -> mcbsp3 */
5230 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5231         .master         = &omap44xx_l4_abe_hwmod,
5232         .slave          = &omap44xx_mcbsp3_hwmod,
5233         .clk            = "ocp_abe_iclk",
5234         .addr           = omap44xx_mcbsp3_addrs,
5235         .user           = OCP_USER_MPU,
5236 };
5237
5238 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5239         {
5240                 .name           = "dma",
5241                 .pa_start       = 0x49026000,
5242                 .pa_end         = 0x490260ff,
5243                 .flags          = ADDR_TYPE_RT
5244         },
5245         { }
5246 };
5247
5248 /* l4_abe -> mcbsp3 (dma) */
5249 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5250         .master         = &omap44xx_l4_abe_hwmod,
5251         .slave          = &omap44xx_mcbsp3_hwmod,
5252         .clk            = "ocp_abe_iclk",
5253         .addr           = omap44xx_mcbsp3_dma_addrs,
5254         .user           = OCP_USER_SDMA,
5255 };
5256
5257 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5258         {
5259                 .pa_start       = 0x48096000,
5260                 .pa_end         = 0x480960ff,
5261                 .flags          = ADDR_TYPE_RT
5262         },
5263         { }
5264 };
5265
5266 /* l4_per -> mcbsp4 */
5267 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5268         .master         = &omap44xx_l4_per_hwmod,
5269         .slave          = &omap44xx_mcbsp4_hwmod,
5270         .clk            = "l4_div_ck",
5271         .addr           = omap44xx_mcbsp4_addrs,
5272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5273 };
5274
5275 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5276         {
5277                 .name           = "mpu",
5278                 .pa_start       = 0x40132000,
5279                 .pa_end         = 0x4013207f,
5280                 .flags          = ADDR_TYPE_RT
5281         },
5282         { }
5283 };
5284
5285 /* l4_abe -> mcpdm */
5286 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5287         .master         = &omap44xx_l4_abe_hwmod,
5288         .slave          = &omap44xx_mcpdm_hwmod,
5289         .clk            = "ocp_abe_iclk",
5290         .addr           = omap44xx_mcpdm_addrs,
5291         .user           = OCP_USER_MPU,
5292 };
5293
5294 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5295         {
5296                 .name           = "dma",
5297                 .pa_start       = 0x49032000,
5298                 .pa_end         = 0x4903207f,
5299                 .flags          = ADDR_TYPE_RT
5300         },
5301         { }
5302 };
5303
5304 /* l4_abe -> mcpdm (dma) */
5305 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5306         .master         = &omap44xx_l4_abe_hwmod,
5307         .slave          = &omap44xx_mcpdm_hwmod,
5308         .clk            = "ocp_abe_iclk",
5309         .addr           = omap44xx_mcpdm_dma_addrs,
5310         .user           = OCP_USER_SDMA,
5311 };
5312
5313 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5314         {
5315                 .pa_start       = 0x48098000,
5316                 .pa_end         = 0x480981ff,
5317                 .flags          = ADDR_TYPE_RT
5318         },
5319         { }
5320 };
5321
5322 /* l4_per -> mcspi1 */
5323 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5324         .master         = &omap44xx_l4_per_hwmod,
5325         .slave          = &omap44xx_mcspi1_hwmod,
5326         .clk            = "l4_div_ck",
5327         .addr           = omap44xx_mcspi1_addrs,
5328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5329 };
5330
5331 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5332         {
5333                 .pa_start       = 0x4809a000,
5334                 .pa_end         = 0x4809a1ff,
5335                 .flags          = ADDR_TYPE_RT
5336         },
5337         { }
5338 };
5339
5340 /* l4_per -> mcspi2 */
5341 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5342         .master         = &omap44xx_l4_per_hwmod,
5343         .slave          = &omap44xx_mcspi2_hwmod,
5344         .clk            = "l4_div_ck",
5345         .addr           = omap44xx_mcspi2_addrs,
5346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5347 };
5348
5349 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5350         {
5351                 .pa_start       = 0x480b8000,
5352                 .pa_end         = 0x480b81ff,
5353                 .flags          = ADDR_TYPE_RT
5354         },
5355         { }
5356 };
5357
5358 /* l4_per -> mcspi3 */
5359 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5360         .master         = &omap44xx_l4_per_hwmod,
5361         .slave          = &omap44xx_mcspi3_hwmod,
5362         .clk            = "l4_div_ck",
5363         .addr           = omap44xx_mcspi3_addrs,
5364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5365 };
5366
5367 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5368         {
5369                 .pa_start       = 0x480ba000,
5370                 .pa_end         = 0x480ba1ff,
5371                 .flags          = ADDR_TYPE_RT
5372         },
5373         { }
5374 };
5375
5376 /* l4_per -> mcspi4 */
5377 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5378         .master         = &omap44xx_l4_per_hwmod,
5379         .slave          = &omap44xx_mcspi4_hwmod,
5380         .clk            = "l4_div_ck",
5381         .addr           = omap44xx_mcspi4_addrs,
5382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5383 };
5384
5385 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5386         {
5387                 .pa_start       = 0x4809c000,
5388                 .pa_end         = 0x4809c3ff,
5389                 .flags          = ADDR_TYPE_RT
5390         },
5391         { }
5392 };
5393
5394 /* l4_per -> mmc1 */
5395 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5396         .master         = &omap44xx_l4_per_hwmod,
5397         .slave          = &omap44xx_mmc1_hwmod,
5398         .clk            = "l4_div_ck",
5399         .addr           = omap44xx_mmc1_addrs,
5400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5401 };
5402
5403 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5404         {
5405                 .pa_start       = 0x480b4000,
5406                 .pa_end         = 0x480b43ff,
5407                 .flags          = ADDR_TYPE_RT
5408         },
5409         { }
5410 };
5411
5412 /* l4_per -> mmc2 */
5413 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5414         .master         = &omap44xx_l4_per_hwmod,
5415         .slave          = &omap44xx_mmc2_hwmod,
5416         .clk            = "l4_div_ck",
5417         .addr           = omap44xx_mmc2_addrs,
5418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5419 };
5420
5421 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5422         {
5423                 .pa_start       = 0x480ad000,
5424                 .pa_end         = 0x480ad3ff,
5425                 .flags          = ADDR_TYPE_RT
5426         },
5427         { }
5428 };
5429
5430 /* l4_per -> mmc3 */
5431 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5432         .master         = &omap44xx_l4_per_hwmod,
5433         .slave          = &omap44xx_mmc3_hwmod,
5434         .clk            = "l4_div_ck",
5435         .addr           = omap44xx_mmc3_addrs,
5436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5437 };
5438
5439 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5440         {
5441                 .pa_start       = 0x480d1000,
5442                 .pa_end         = 0x480d13ff,
5443                 .flags          = ADDR_TYPE_RT
5444         },
5445         { }
5446 };
5447
5448 /* l4_per -> mmc4 */
5449 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5450         .master         = &omap44xx_l4_per_hwmod,
5451         .slave          = &omap44xx_mmc4_hwmod,
5452         .clk            = "l4_div_ck",
5453         .addr           = omap44xx_mmc4_addrs,
5454         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5455 };
5456
5457 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5458         {
5459                 .pa_start       = 0x480d5000,
5460                 .pa_end         = 0x480d53ff,
5461                 .flags          = ADDR_TYPE_RT
5462         },
5463         { }
5464 };
5465
5466 /* l4_per -> mmc5 */
5467 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5468         .master         = &omap44xx_l4_per_hwmod,
5469         .slave          = &omap44xx_mmc5_hwmod,
5470         .clk            = "l4_div_ck",
5471         .addr           = omap44xx_mmc5_addrs,
5472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5473 };
5474
5475 /* l3_main_2 -> ocmc_ram */
5476 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5477         .master         = &omap44xx_l3_main_2_hwmod,
5478         .slave          = &omap44xx_ocmc_ram_hwmod,
5479         .clk            = "l3_div_ck",
5480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5481 };
5482
5483 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5484         {
5485                 .pa_start       = 0x4a0ad000,
5486                 .pa_end         = 0x4a0ad01f,
5487                 .flags          = ADDR_TYPE_RT
5488         },
5489         { }
5490 };
5491
5492 /* l4_cfg -> ocp2scp_usb_phy */
5493 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5494         .master         = &omap44xx_l4_cfg_hwmod,
5495         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5496         .clk            = "l4_div_ck",
5497         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5499 };
5500
5501 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5502         {
5503                 .pa_start       = 0x48243000,
5504                 .pa_end         = 0x48243fff,
5505                 .flags          = ADDR_TYPE_RT
5506         },
5507         { }
5508 };
5509
5510 /* mpu_private -> prcm_mpu */
5511 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5512         .master         = &omap44xx_mpu_private_hwmod,
5513         .slave          = &omap44xx_prcm_mpu_hwmod,
5514         .clk            = "l3_div_ck",
5515         .addr           = omap44xx_prcm_mpu_addrs,
5516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5517 };
5518
5519 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5520         {
5521                 .pa_start       = 0x4a004000,
5522                 .pa_end         = 0x4a004fff,
5523                 .flags          = ADDR_TYPE_RT
5524         },
5525         { }
5526 };
5527
5528 /* l4_wkup -> cm_core_aon */
5529 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5530         .master         = &omap44xx_l4_wkup_hwmod,
5531         .slave          = &omap44xx_cm_core_aon_hwmod,
5532         .clk            = "l4_wkup_clk_mux_ck",
5533         .addr           = omap44xx_cm_core_aon_addrs,
5534         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5535 };
5536
5537 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5538         {
5539                 .pa_start       = 0x4a008000,
5540                 .pa_end         = 0x4a009fff,
5541                 .flags          = ADDR_TYPE_RT
5542         },
5543         { }
5544 };
5545
5546 /* l4_cfg -> cm_core */
5547 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5548         .master         = &omap44xx_l4_cfg_hwmod,
5549         .slave          = &omap44xx_cm_core_hwmod,
5550         .clk            = "l4_div_ck",
5551         .addr           = omap44xx_cm_core_addrs,
5552         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5553 };
5554
5555 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5556         {
5557                 .pa_start       = 0x4a306000,
5558                 .pa_end         = 0x4a307fff,
5559                 .flags          = ADDR_TYPE_RT
5560         },
5561         { }
5562 };
5563
5564 /* l4_wkup -> prm */
5565 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5566         .master         = &omap44xx_l4_wkup_hwmod,
5567         .slave          = &omap44xx_prm_hwmod,
5568         .clk            = "l4_wkup_clk_mux_ck",
5569         .addr           = omap44xx_prm_addrs,
5570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5571 };
5572
5573 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5574         {
5575                 .pa_start       = 0x4a30a000,
5576                 .pa_end         = 0x4a30a7ff,
5577                 .flags          = ADDR_TYPE_RT
5578         },
5579         { }
5580 };
5581
5582 /* l4_wkup -> scrm */
5583 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5584         .master         = &omap44xx_l4_wkup_hwmod,
5585         .slave          = &omap44xx_scrm_hwmod,
5586         .clk            = "l4_wkup_clk_mux_ck",
5587         .addr           = omap44xx_scrm_addrs,
5588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5589 };
5590
5591 /* l3_main_2 -> sl2if */
5592 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5593         .master         = &omap44xx_l3_main_2_hwmod,
5594         .slave          = &omap44xx_sl2if_hwmod,
5595         .clk            = "l3_div_ck",
5596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5597 };
5598
5599 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5600         {
5601                 .pa_start       = 0x4012c000,
5602                 .pa_end         = 0x4012c3ff,
5603                 .flags          = ADDR_TYPE_RT
5604         },
5605         { }
5606 };
5607
5608 /* l4_abe -> slimbus1 */
5609 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5610         .master         = &omap44xx_l4_abe_hwmod,
5611         .slave          = &omap44xx_slimbus1_hwmod,
5612         .clk            = "ocp_abe_iclk",
5613         .addr           = omap44xx_slimbus1_addrs,
5614         .user           = OCP_USER_MPU,
5615 };
5616
5617 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5618         {
5619                 .pa_start       = 0x4902c000,
5620                 .pa_end         = 0x4902c3ff,
5621                 .flags          = ADDR_TYPE_RT
5622         },
5623         { }
5624 };
5625
5626 /* l4_abe -> slimbus1 (dma) */
5627 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5628         .master         = &omap44xx_l4_abe_hwmod,
5629         .slave          = &omap44xx_slimbus1_hwmod,
5630         .clk            = "ocp_abe_iclk",
5631         .addr           = omap44xx_slimbus1_dma_addrs,
5632         .user           = OCP_USER_SDMA,
5633 };
5634
5635 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5636         {
5637                 .pa_start       = 0x48076000,
5638                 .pa_end         = 0x480763ff,
5639                 .flags          = ADDR_TYPE_RT
5640         },
5641         { }
5642 };
5643
5644 /* l4_per -> slimbus2 */
5645 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5646         .master         = &omap44xx_l4_per_hwmod,
5647         .slave          = &omap44xx_slimbus2_hwmod,
5648         .clk            = "l4_div_ck",
5649         .addr           = omap44xx_slimbus2_addrs,
5650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5651 };
5652
5653 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5654         {
5655                 .pa_start       = 0x4a0dd000,
5656                 .pa_end         = 0x4a0dd03f,
5657                 .flags          = ADDR_TYPE_RT
5658         },
5659         { }
5660 };
5661
5662 /* l4_cfg -> smartreflex_core */
5663 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5664         .master         = &omap44xx_l4_cfg_hwmod,
5665         .slave          = &omap44xx_smartreflex_core_hwmod,
5666         .clk            = "l4_div_ck",
5667         .addr           = omap44xx_smartreflex_core_addrs,
5668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5669 };
5670
5671 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5672         {
5673                 .pa_start       = 0x4a0db000,
5674                 .pa_end         = 0x4a0db03f,
5675                 .flags          = ADDR_TYPE_RT
5676         },
5677         { }
5678 };
5679
5680 /* l4_cfg -> smartreflex_iva */
5681 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5682         .master         = &omap44xx_l4_cfg_hwmod,
5683         .slave          = &omap44xx_smartreflex_iva_hwmod,
5684         .clk            = "l4_div_ck",
5685         .addr           = omap44xx_smartreflex_iva_addrs,
5686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5687 };
5688
5689 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5690         {
5691                 .pa_start       = 0x4a0d9000,
5692                 .pa_end         = 0x4a0d903f,
5693                 .flags          = ADDR_TYPE_RT
5694         },
5695         { }
5696 };
5697
5698 /* l4_cfg -> smartreflex_mpu */
5699 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5700         .master         = &omap44xx_l4_cfg_hwmod,
5701         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5702         .clk            = "l4_div_ck",
5703         .addr           = omap44xx_smartreflex_mpu_addrs,
5704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5705 };
5706
5707 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5708         {
5709                 .pa_start       = 0x4a0f6000,
5710                 .pa_end         = 0x4a0f6fff,
5711                 .flags          = ADDR_TYPE_RT
5712         },
5713         { }
5714 };
5715
5716 /* l4_cfg -> spinlock */
5717 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5718         .master         = &omap44xx_l4_cfg_hwmod,
5719         .slave          = &omap44xx_spinlock_hwmod,
5720         .clk            = "l4_div_ck",
5721         .addr           = omap44xx_spinlock_addrs,
5722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5723 };
5724
5725 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5726         {
5727                 .pa_start       = 0x4a318000,
5728                 .pa_end         = 0x4a31807f,
5729                 .flags          = ADDR_TYPE_RT
5730         },
5731         { }
5732 };
5733
5734 /* l4_wkup -> timer1 */
5735 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5736         .master         = &omap44xx_l4_wkup_hwmod,
5737         .slave          = &omap44xx_timer1_hwmod,
5738         .clk            = "l4_wkup_clk_mux_ck",
5739         .addr           = omap44xx_timer1_addrs,
5740         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5741 };
5742
5743 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5744         {
5745                 .pa_start       = 0x48032000,
5746                 .pa_end         = 0x4803207f,
5747                 .flags          = ADDR_TYPE_RT
5748         },
5749         { }
5750 };
5751
5752 /* l4_per -> timer2 */
5753 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5754         .master         = &omap44xx_l4_per_hwmod,
5755         .slave          = &omap44xx_timer2_hwmod,
5756         .clk            = "l4_div_ck",
5757         .addr           = omap44xx_timer2_addrs,
5758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5759 };
5760
5761 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5762         {
5763                 .pa_start       = 0x48034000,
5764                 .pa_end         = 0x4803407f,
5765                 .flags          = ADDR_TYPE_RT
5766         },
5767         { }
5768 };
5769
5770 /* l4_per -> timer3 */
5771 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5772         .master         = &omap44xx_l4_per_hwmod,
5773         .slave          = &omap44xx_timer3_hwmod,
5774         .clk            = "l4_div_ck",
5775         .addr           = omap44xx_timer3_addrs,
5776         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5777 };
5778
5779 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5780         {
5781                 .pa_start       = 0x48036000,
5782                 .pa_end         = 0x4803607f,
5783                 .flags          = ADDR_TYPE_RT
5784         },
5785         { }
5786 };
5787
5788 /* l4_per -> timer4 */
5789 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5790         .master         = &omap44xx_l4_per_hwmod,
5791         .slave          = &omap44xx_timer4_hwmod,
5792         .clk            = "l4_div_ck",
5793         .addr           = omap44xx_timer4_addrs,
5794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5795 };
5796
5797 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5798         {
5799                 .pa_start       = 0x40138000,
5800                 .pa_end         = 0x4013807f,
5801                 .flags          = ADDR_TYPE_RT
5802         },
5803         { }
5804 };
5805
5806 /* l4_abe -> timer5 */
5807 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5808         .master         = &omap44xx_l4_abe_hwmod,
5809         .slave          = &omap44xx_timer5_hwmod,
5810         .clk            = "ocp_abe_iclk",
5811         .addr           = omap44xx_timer5_addrs,
5812         .user           = OCP_USER_MPU,
5813 };
5814
5815 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5816         {
5817                 .pa_start       = 0x49038000,
5818                 .pa_end         = 0x4903807f,
5819                 .flags          = ADDR_TYPE_RT
5820         },
5821         { }
5822 };
5823
5824 /* l4_abe -> timer5 (dma) */
5825 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5826         .master         = &omap44xx_l4_abe_hwmod,
5827         .slave          = &omap44xx_timer5_hwmod,
5828         .clk            = "ocp_abe_iclk",
5829         .addr           = omap44xx_timer5_dma_addrs,
5830         .user           = OCP_USER_SDMA,
5831 };
5832
5833 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5834         {
5835                 .pa_start       = 0x4013a000,
5836                 .pa_end         = 0x4013a07f,
5837                 .flags          = ADDR_TYPE_RT
5838         },
5839         { }
5840 };
5841
5842 /* l4_abe -> timer6 */
5843 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5844         .master         = &omap44xx_l4_abe_hwmod,
5845         .slave          = &omap44xx_timer6_hwmod,
5846         .clk            = "ocp_abe_iclk",
5847         .addr           = omap44xx_timer6_addrs,
5848         .user           = OCP_USER_MPU,
5849 };
5850
5851 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5852         {
5853                 .pa_start       = 0x4903a000,
5854                 .pa_end         = 0x4903a07f,
5855                 .flags          = ADDR_TYPE_RT
5856         },
5857         { }
5858 };
5859
5860 /* l4_abe -> timer6 (dma) */
5861 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5862         .master         = &omap44xx_l4_abe_hwmod,
5863         .slave          = &omap44xx_timer6_hwmod,
5864         .clk            = "ocp_abe_iclk",
5865         .addr           = omap44xx_timer6_dma_addrs,
5866         .user           = OCP_USER_SDMA,
5867 };
5868
5869 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5870         {
5871                 .pa_start       = 0x4013c000,
5872                 .pa_end         = 0x4013c07f,
5873                 .flags          = ADDR_TYPE_RT
5874         },
5875         { }
5876 };
5877
5878 /* l4_abe -> timer7 */
5879 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5880         .master         = &omap44xx_l4_abe_hwmod,
5881         .slave          = &omap44xx_timer7_hwmod,
5882         .clk            = "ocp_abe_iclk",
5883         .addr           = omap44xx_timer7_addrs,
5884         .user           = OCP_USER_MPU,
5885 };
5886
5887 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5888         {
5889                 .pa_start       = 0x4903c000,
5890                 .pa_end         = 0x4903c07f,
5891                 .flags          = ADDR_TYPE_RT
5892         },
5893         { }
5894 };
5895
5896 /* l4_abe -> timer7 (dma) */
5897 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5898         .master         = &omap44xx_l4_abe_hwmod,
5899         .slave          = &omap44xx_timer7_hwmod,
5900         .clk            = "ocp_abe_iclk",
5901         .addr           = omap44xx_timer7_dma_addrs,
5902         .user           = OCP_USER_SDMA,
5903 };
5904
5905 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5906         {
5907                 .pa_start       = 0x4013e000,
5908                 .pa_end         = 0x4013e07f,
5909                 .flags          = ADDR_TYPE_RT
5910         },
5911         { }
5912 };
5913
5914 /* l4_abe -> timer8 */
5915 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5916         .master         = &omap44xx_l4_abe_hwmod,
5917         .slave          = &omap44xx_timer8_hwmod,
5918         .clk            = "ocp_abe_iclk",
5919         .addr           = omap44xx_timer8_addrs,
5920         .user           = OCP_USER_MPU,
5921 };
5922
5923 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5924         {
5925                 .pa_start       = 0x4903e000,
5926                 .pa_end         = 0x4903e07f,
5927                 .flags          = ADDR_TYPE_RT
5928         },
5929         { }
5930 };
5931
5932 /* l4_abe -> timer8 (dma) */
5933 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5934         .master         = &omap44xx_l4_abe_hwmod,
5935         .slave          = &omap44xx_timer8_hwmod,
5936         .clk            = "ocp_abe_iclk",
5937         .addr           = omap44xx_timer8_dma_addrs,
5938         .user           = OCP_USER_SDMA,
5939 };
5940
5941 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5942         {
5943                 .pa_start       = 0x4803e000,
5944                 .pa_end         = 0x4803e07f,
5945                 .flags          = ADDR_TYPE_RT
5946         },
5947         { }
5948 };
5949
5950 /* l4_per -> timer9 */
5951 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5952         .master         = &omap44xx_l4_per_hwmod,
5953         .slave          = &omap44xx_timer9_hwmod,
5954         .clk            = "l4_div_ck",
5955         .addr           = omap44xx_timer9_addrs,
5956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5957 };
5958
5959 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5960         {
5961                 .pa_start       = 0x48086000,
5962                 .pa_end         = 0x4808607f,
5963                 .flags          = ADDR_TYPE_RT
5964         },
5965         { }
5966 };
5967
5968 /* l4_per -> timer10 */
5969 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5970         .master         = &omap44xx_l4_per_hwmod,
5971         .slave          = &omap44xx_timer10_hwmod,
5972         .clk            = "l4_div_ck",
5973         .addr           = omap44xx_timer10_addrs,
5974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5975 };
5976
5977 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5978         {
5979                 .pa_start       = 0x48088000,
5980                 .pa_end         = 0x4808807f,
5981                 .flags          = ADDR_TYPE_RT
5982         },
5983         { }
5984 };
5985
5986 /* l4_per -> timer11 */
5987 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5988         .master         = &omap44xx_l4_per_hwmod,
5989         .slave          = &omap44xx_timer11_hwmod,
5990         .clk            = "l4_div_ck",
5991         .addr           = omap44xx_timer11_addrs,
5992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5993 };
5994
5995 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5996         {
5997                 .pa_start       = 0x4806a000,
5998                 .pa_end         = 0x4806a0ff,
5999                 .flags          = ADDR_TYPE_RT
6000         },
6001         { }
6002 };
6003
6004 /* l4_per -> uart1 */
6005 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6006         .master         = &omap44xx_l4_per_hwmod,
6007         .slave          = &omap44xx_uart1_hwmod,
6008         .clk            = "l4_div_ck",
6009         .addr           = omap44xx_uart1_addrs,
6010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6011 };
6012
6013 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6014         {
6015                 .pa_start       = 0x4806c000,
6016                 .pa_end         = 0x4806c0ff,
6017                 .flags          = ADDR_TYPE_RT
6018         },
6019         { }
6020 };
6021
6022 /* l4_per -> uart2 */
6023 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6024         .master         = &omap44xx_l4_per_hwmod,
6025         .slave          = &omap44xx_uart2_hwmod,
6026         .clk            = "l4_div_ck",
6027         .addr           = omap44xx_uart2_addrs,
6028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6029 };
6030
6031 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6032         {
6033                 .pa_start       = 0x48020000,
6034                 .pa_end         = 0x480200ff,
6035                 .flags          = ADDR_TYPE_RT
6036         },
6037         { }
6038 };
6039
6040 /* l4_per -> uart3 */
6041 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6042         .master         = &omap44xx_l4_per_hwmod,
6043         .slave          = &omap44xx_uart3_hwmod,
6044         .clk            = "l4_div_ck",
6045         .addr           = omap44xx_uart3_addrs,
6046         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6047 };
6048
6049 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6050         {
6051                 .pa_start       = 0x4806e000,
6052                 .pa_end         = 0x4806e0ff,
6053                 .flags          = ADDR_TYPE_RT
6054         },
6055         { }
6056 };
6057
6058 /* l4_per -> uart4 */
6059 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6060         .master         = &omap44xx_l4_per_hwmod,
6061         .slave          = &omap44xx_uart4_hwmod,
6062         .clk            = "l4_div_ck",
6063         .addr           = omap44xx_uart4_addrs,
6064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6065 };
6066
6067 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6068         {
6069                 .pa_start       = 0x4a0a9000,
6070                 .pa_end         = 0x4a0a93ff,
6071                 .flags          = ADDR_TYPE_RT
6072         },
6073         { }
6074 };
6075
6076 /* l4_cfg -> usb_host_fs */
6077 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6078         .master         = &omap44xx_l4_cfg_hwmod,
6079         .slave          = &omap44xx_usb_host_fs_hwmod,
6080         .clk            = "l4_div_ck",
6081         .addr           = omap44xx_usb_host_fs_addrs,
6082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6083 };
6084
6085 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6086         {
6087                 .name           = "uhh",
6088                 .pa_start       = 0x4a064000,
6089                 .pa_end         = 0x4a0647ff,
6090                 .flags          = ADDR_TYPE_RT
6091         },
6092         {
6093                 .name           = "ohci",
6094                 .pa_start       = 0x4a064800,
6095                 .pa_end         = 0x4a064bff,
6096         },
6097         {
6098                 .name           = "ehci",
6099                 .pa_start       = 0x4a064c00,
6100                 .pa_end         = 0x4a064fff,
6101         },
6102         {}
6103 };
6104
6105 /* l4_cfg -> usb_host_hs */
6106 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6107         .master         = &omap44xx_l4_cfg_hwmod,
6108         .slave          = &omap44xx_usb_host_hs_hwmod,
6109         .clk            = "l4_div_ck",
6110         .addr           = omap44xx_usb_host_hs_addrs,
6111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6112 };
6113
6114 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6115         {
6116                 .pa_start       = 0x4a0ab000,
6117                 .pa_end         = 0x4a0ab7ff,
6118                 .flags          = ADDR_TYPE_RT
6119         },
6120         {
6121                 /* XXX: Remove this once control module driver is in place */
6122                 .pa_start       = 0x4a00233c,
6123                 .pa_end         = 0x4a00233f,
6124                 .flags          = ADDR_TYPE_RT
6125         },
6126         { }
6127 };
6128
6129 /* l4_cfg -> usb_otg_hs */
6130 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6131         .master         = &omap44xx_l4_cfg_hwmod,
6132         .slave          = &omap44xx_usb_otg_hs_hwmod,
6133         .clk            = "l4_div_ck",
6134         .addr           = omap44xx_usb_otg_hs_addrs,
6135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6136 };
6137
6138 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6139         {
6140                 .name           = "tll",
6141                 .pa_start       = 0x4a062000,
6142                 .pa_end         = 0x4a063fff,
6143                 .flags          = ADDR_TYPE_RT
6144         },
6145         {}
6146 };
6147
6148 /* l4_cfg -> usb_tll_hs */
6149 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6150         .master         = &omap44xx_l4_cfg_hwmod,
6151         .slave          = &omap44xx_usb_tll_hs_hwmod,
6152         .clk            = "l4_div_ck",
6153         .addr           = omap44xx_usb_tll_hs_addrs,
6154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6155 };
6156
6157 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6158         {
6159                 .pa_start       = 0x4a314000,
6160                 .pa_end         = 0x4a31407f,
6161                 .flags          = ADDR_TYPE_RT
6162         },
6163         { }
6164 };
6165
6166 /* l4_wkup -> wd_timer2 */
6167 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6168         .master         = &omap44xx_l4_wkup_hwmod,
6169         .slave          = &omap44xx_wd_timer2_hwmod,
6170         .clk            = "l4_wkup_clk_mux_ck",
6171         .addr           = omap44xx_wd_timer2_addrs,
6172         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6173 };
6174
6175 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6176         {
6177                 .pa_start       = 0x40130000,
6178                 .pa_end         = 0x4013007f,
6179                 .flags          = ADDR_TYPE_RT
6180         },
6181         { }
6182 };
6183
6184 /* l4_abe -> wd_timer3 */
6185 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6186         .master         = &omap44xx_l4_abe_hwmod,
6187         .slave          = &omap44xx_wd_timer3_hwmod,
6188         .clk            = "ocp_abe_iclk",
6189         .addr           = omap44xx_wd_timer3_addrs,
6190         .user           = OCP_USER_MPU,
6191 };
6192
6193 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6194         {
6195                 .pa_start       = 0x49030000,
6196                 .pa_end         = 0x4903007f,
6197                 .flags          = ADDR_TYPE_RT
6198         },
6199         { }
6200 };
6201
6202 /* l4_abe -> wd_timer3 (dma) */
6203 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6204         .master         = &omap44xx_l4_abe_hwmod,
6205         .slave          = &omap44xx_wd_timer3_hwmod,
6206         .clk            = "ocp_abe_iclk",
6207         .addr           = omap44xx_wd_timer3_dma_addrs,
6208         .user           = OCP_USER_SDMA,
6209 };
6210
6211 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6212         &omap44xx_c2c__c2c_target_fw,
6213         &omap44xx_l4_cfg__c2c_target_fw,
6214         &omap44xx_l3_main_1__dmm,
6215         &omap44xx_mpu__dmm,
6216         &omap44xx_c2c__emif_fw,
6217         &omap44xx_dmm__emif_fw,
6218         &omap44xx_l4_cfg__emif_fw,
6219         &omap44xx_iva__l3_instr,
6220         &omap44xx_l3_main_3__l3_instr,
6221         &omap44xx_ocp_wp_noc__l3_instr,
6222         &omap44xx_dsp__l3_main_1,
6223         &omap44xx_dss__l3_main_1,
6224         &omap44xx_l3_main_2__l3_main_1,
6225         &omap44xx_l4_cfg__l3_main_1,
6226         &omap44xx_mmc1__l3_main_1,
6227         &omap44xx_mmc2__l3_main_1,
6228         &omap44xx_mpu__l3_main_1,
6229         &omap44xx_c2c_target_fw__l3_main_2,
6230         &omap44xx_debugss__l3_main_2,
6231         &omap44xx_dma_system__l3_main_2,
6232         &omap44xx_fdif__l3_main_2,
6233         &omap44xx_gpu__l3_main_2,
6234         &omap44xx_hsi__l3_main_2,
6235         &omap44xx_ipu__l3_main_2,
6236         &omap44xx_iss__l3_main_2,
6237         &omap44xx_iva__l3_main_2,
6238         &omap44xx_l3_main_1__l3_main_2,
6239         &omap44xx_l4_cfg__l3_main_2,
6240         /* &omap44xx_usb_host_fs__l3_main_2, */
6241         &omap44xx_usb_host_hs__l3_main_2,
6242         &omap44xx_usb_otg_hs__l3_main_2,
6243         &omap44xx_l3_main_1__l3_main_3,
6244         &omap44xx_l3_main_2__l3_main_3,
6245         &omap44xx_l4_cfg__l3_main_3,
6246         /* &omap44xx_aess__l4_abe, */
6247         &omap44xx_dsp__l4_abe,
6248         &omap44xx_l3_main_1__l4_abe,
6249         &omap44xx_mpu__l4_abe,
6250         &omap44xx_l3_main_1__l4_cfg,
6251         &omap44xx_l3_main_2__l4_per,
6252         &omap44xx_l4_cfg__l4_wkup,
6253         &omap44xx_mpu__mpu_private,
6254         &omap44xx_l4_cfg__ocp_wp_noc,
6255         /* &omap44xx_l4_abe__aess, */
6256         /* &omap44xx_l4_abe__aess_dma, */
6257         &omap44xx_l3_main_2__c2c,
6258         &omap44xx_l4_wkup__counter_32k,
6259         &omap44xx_l4_cfg__ctrl_module_core,
6260         &omap44xx_l4_cfg__ctrl_module_pad_core,
6261         &omap44xx_l4_wkup__ctrl_module_wkup,
6262         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6263         &omap44xx_l3_instr__debugss,
6264         &omap44xx_l4_cfg__dma_system,
6265         &omap44xx_l4_abe__dmic,
6266         &omap44xx_l4_abe__dmic_dma,
6267         &omap44xx_dsp__iva,
6268         /* &omap44xx_dsp__sl2if, */
6269         &omap44xx_l4_cfg__dsp,
6270         &omap44xx_l3_main_2__dss,
6271         &omap44xx_l4_per__dss,
6272         &omap44xx_l3_main_2__dss_dispc,
6273         &omap44xx_l4_per__dss_dispc,
6274         &omap44xx_l3_main_2__dss_dsi1,
6275         &omap44xx_l4_per__dss_dsi1,
6276         &omap44xx_l3_main_2__dss_dsi2,
6277         &omap44xx_l4_per__dss_dsi2,
6278         &omap44xx_l3_main_2__dss_hdmi,
6279         &omap44xx_l4_per__dss_hdmi,
6280         &omap44xx_l3_main_2__dss_rfbi,
6281         &omap44xx_l4_per__dss_rfbi,
6282         &omap44xx_l3_main_2__dss_venc,
6283         &omap44xx_l4_per__dss_venc,
6284         &omap44xx_l4_per__elm,
6285         &omap44xx_emif_fw__emif1,
6286         &omap44xx_emif_fw__emif2,
6287         &omap44xx_l4_cfg__fdif,
6288         &omap44xx_l4_wkup__gpio1,
6289         &omap44xx_l4_per__gpio2,
6290         &omap44xx_l4_per__gpio3,
6291         &omap44xx_l4_per__gpio4,
6292         &omap44xx_l4_per__gpio5,
6293         &omap44xx_l4_per__gpio6,
6294         &omap44xx_l3_main_2__gpmc,
6295         &omap44xx_l3_main_2__gpu,
6296         &omap44xx_l4_per__hdq1w,
6297         &omap44xx_l4_cfg__hsi,
6298         &omap44xx_l4_per__i2c1,
6299         &omap44xx_l4_per__i2c2,
6300         &omap44xx_l4_per__i2c3,
6301         &omap44xx_l4_per__i2c4,
6302         &omap44xx_l3_main_2__ipu,
6303         &omap44xx_l3_main_2__iss,
6304         /* &omap44xx_iva__sl2if, */
6305         &omap44xx_l3_main_2__iva,
6306         &omap44xx_l4_wkup__kbd,
6307         &omap44xx_l4_cfg__mailbox,
6308         &omap44xx_l4_abe__mcasp,
6309         &omap44xx_l4_abe__mcasp_dma,
6310         &omap44xx_l4_abe__mcbsp1,
6311         &omap44xx_l4_abe__mcbsp1_dma,
6312         &omap44xx_l4_abe__mcbsp2,
6313         &omap44xx_l4_abe__mcbsp2_dma,
6314         &omap44xx_l4_abe__mcbsp3,
6315         &omap44xx_l4_abe__mcbsp3_dma,
6316         &omap44xx_l4_per__mcbsp4,
6317         &omap44xx_l4_abe__mcpdm,
6318         &omap44xx_l4_abe__mcpdm_dma,
6319         &omap44xx_l4_per__mcspi1,
6320         &omap44xx_l4_per__mcspi2,
6321         &omap44xx_l4_per__mcspi3,
6322         &omap44xx_l4_per__mcspi4,
6323         &omap44xx_l4_per__mmc1,
6324         &omap44xx_l4_per__mmc2,
6325         &omap44xx_l4_per__mmc3,
6326         &omap44xx_l4_per__mmc4,
6327         &omap44xx_l4_per__mmc5,
6328         &omap44xx_l3_main_2__mmu_ipu,
6329         &omap44xx_l4_cfg__mmu_dsp,
6330         &omap44xx_l3_main_2__ocmc_ram,
6331         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6332         &omap44xx_mpu_private__prcm_mpu,
6333         &omap44xx_l4_wkup__cm_core_aon,
6334         &omap44xx_l4_cfg__cm_core,
6335         &omap44xx_l4_wkup__prm,
6336         &omap44xx_l4_wkup__scrm,
6337         /* &omap44xx_l3_main_2__sl2if, */
6338         &omap44xx_l4_abe__slimbus1,
6339         &omap44xx_l4_abe__slimbus1_dma,
6340         &omap44xx_l4_per__slimbus2,
6341         &omap44xx_l4_cfg__smartreflex_core,
6342         &omap44xx_l4_cfg__smartreflex_iva,
6343         &omap44xx_l4_cfg__smartreflex_mpu,
6344         &omap44xx_l4_cfg__spinlock,
6345         &omap44xx_l4_wkup__timer1,
6346         &omap44xx_l4_per__timer2,
6347         &omap44xx_l4_per__timer3,
6348         &omap44xx_l4_per__timer4,
6349         &omap44xx_l4_abe__timer5,
6350         &omap44xx_l4_abe__timer5_dma,
6351         &omap44xx_l4_abe__timer6,
6352         &omap44xx_l4_abe__timer6_dma,
6353         &omap44xx_l4_abe__timer7,
6354         &omap44xx_l4_abe__timer7_dma,
6355         &omap44xx_l4_abe__timer8,
6356         &omap44xx_l4_abe__timer8_dma,
6357         &omap44xx_l4_per__timer9,
6358         &omap44xx_l4_per__timer10,
6359         &omap44xx_l4_per__timer11,
6360         &omap44xx_l4_per__uart1,
6361         &omap44xx_l4_per__uart2,
6362         &omap44xx_l4_per__uart3,
6363         &omap44xx_l4_per__uart4,
6364         /* &omap44xx_l4_cfg__usb_host_fs, */
6365         &omap44xx_l4_cfg__usb_host_hs,
6366         &omap44xx_l4_cfg__usb_otg_hs,
6367         &omap44xx_l4_cfg__usb_tll_hs,
6368         &omap44xx_l4_wkup__wd_timer2,
6369         &omap44xx_l4_abe__wd_timer3,
6370         &omap44xx_l4_abe__wd_timer3_dma,
6371         NULL,
6372 };
6373
6374 int __init omap44xx_hwmod_init(void)
6375 {
6376         omap_hwmod_init();
6377         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6378 }
6379