arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24
  25 #include <plat/omap_hwmod.h>
  26 #include <plat/i2c.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'c2c_target_fw' class
  53  * instance(s): c2c_target_fw
  54  */
  55 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  56         .name   = "c2c_target_fw",
  57 };
  58
  59 /* c2c_target_fw */
  60 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  61         .name           = "c2c_target_fw",
  62         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  63         .clkdm_name     = "d2d_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  67                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'dmm' class
  74  * instance(s): dmm
  75  */
  76 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  77         .name   = "dmm",
  78 };
  79
  80 /* dmm */
  81 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  82         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  83         { .irq = -1 }
  84 };
  85
  86 static struct omap_hwmod omap44xx_dmm_hwmod = {
  87         .name           = "dmm",
  88         .class          = &omap44xx_dmm_hwmod_class,
  89         .clkdm_name     = "l3_emif_clkdm",
  90         .mpu_irqs       = omap44xx_dmm_irqs,
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  94                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  95                 },
  96         },
  97 };
  98
  99 /*
 100  * 'emif_fw' class
 101  * instance(s): emif_fw
 102  */
 103 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 104         .name   = "emif_fw",
 105 };
 106
 107 /* emif_fw */
 108 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 109         .name           = "emif_fw",
 110         .class          = &omap44xx_emif_fw_hwmod_class,
 111         .clkdm_name     = "l3_emif_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 115                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 116                 },
 117         },
 118 };
 119
 120 /*
 121  * 'l3' class
 122  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 123  */
 124 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 125         .name   = "l3",
 126 };
 127
 128 /* l3_instr */
 129 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 130         .name           = "l3_instr",
 131         .class          = &omap44xx_l3_hwmod_class,
 132         .clkdm_name     = "l3_instr_clkdm",
 133         .prcm = {
 134                 .omap4 = {
 135                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 136                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 137                         .modulemode   = MODULEMODE_HWCTRL,
 138                 },
 139         },
 140 };
 141
 142 /* l3_main_1 */
 143 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 144         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 145         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 146         { .irq = -1 }
 147 };
 148
 149 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 150         .name           = "l3_main_1",
 151         .class          = &omap44xx_l3_hwmod_class,
 152         .clkdm_name     = "l3_1_clkdm",
 153         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 154         .prcm = {
 155                 .omap4 = {
 156                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 157                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 158                 },
 159         },
 160 };
 161
 162 /* l3_main_2 */
 163 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 164         .name           = "l3_main_2",
 165         .class          = &omap44xx_l3_hwmod_class,
 166         .clkdm_name     = "l3_2_clkdm",
 167         .prcm = {
 168                 .omap4 = {
 169                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 170                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 171                 },
 172         },
 173 };
 174
 175 /* l3_main_3 */
 176 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 177         .name           = "l3_main_3",
 178         .class          = &omap44xx_l3_hwmod_class,
 179         .clkdm_name     = "l3_instr_clkdm",
 180         .prcm = {
 181                 .omap4 = {
 182                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 183                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 184                         .modulemode   = MODULEMODE_HWCTRL,
 185                 },
 186         },
 187 };
 188
 189 /*
 190  * 'l4' class
 191  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 192  */
 193 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 194         .name   = "l4",
 195 };
 196
 197 /* l4_abe */
 198 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 199         .name           = "l4_abe",
 200         .class          = &omap44xx_l4_hwmod_class,
 201         .clkdm_name     = "abe_clkdm",
 202         .prcm = {
 203                 .omap4 = {
 204                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 205                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 206                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 207                 },
 208         },
 209 };
 210
 211 /* l4_cfg */
 212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213         .name           = "l4_cfg",
 214         .class          = &omap44xx_l4_hwmod_class,
 215         .clkdm_name     = "l4_cfg_clkdm",
 216         .prcm = {
 217                 .omap4 = {
 218                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220                 },
 221         },
 222 };
 223
 224 /* l4_per */
 225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226         .name           = "l4_per",
 227         .class          = &omap44xx_l4_hwmod_class,
 228         .clkdm_name     = "l4_per_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233                 },
 234         },
 235 };
 236
 237 /* l4_wkup */
 238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239         .name           = "l4_wkup",
 240         .class          = &omap44xx_l4_hwmod_class,
 241         .clkdm_name     = "l4_wkup_clkdm",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'mpu_bus' class
 252  * instance(s): mpu_private
 253  */
 254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255         .name   = "mpu_bus",
 256 };
 257
 258 /* mpu_private */
 259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260         .name           = "mpu_private",
 261         .class          = &omap44xx_mpu_bus_hwmod_class,
 262         .clkdm_name     = "mpuss_clkdm",
 263 };
 264
 265 /*
 266  * 'ocp_wp_noc' class
 267  * instance(s): ocp_wp_noc
 268  */
 269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270         .name   = "ocp_wp_noc",
 271 };
 272
 273 /* ocp_wp_noc */
 274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275         .name           = "ocp_wp_noc",
 276         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 277         .clkdm_name     = "l3_instr_clkdm",
 278         .prcm = {
 279                 .omap4 = {
 280                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282                         .modulemode   = MODULEMODE_HWCTRL,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * Modules omap_hwmod structures
 289  *
 290  * The following IPs are excluded for the moment because:
 291  * - They do not need an explicit SW control using omap_hwmod API.
 292  * - They still need to be validated with the driver
 293  *   properly adapted to omap_hwmod / omap_device
 294  *
 295  * usim
 296  */
 297
 298 /*
 299  * 'aess' class
 300  * audio engine sub system
 301  */
 302
 303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 304         .rev_offs       = 0x0000,
 305         .sysc_offs      = 0x0010,
 306         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 308                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 309                            MSTANDBY_SMART_WKUP),
 310         .sysc_fields    = &omap_hwmod_sysc_type2,
 311 };
 312
 313 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 314         .name   = "aess",
 315         .sysc   = &omap44xx_aess_sysc,
 316 };
 317
 318 /* aess */
 319 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 320         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 321         { .irq = -1 }
 322 };
 323
 324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 325         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 326         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 327         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 328         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 329         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 330         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 331         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 333         { .dma_req = -1 }
 334 };
 335
 336 static struct omap_hwmod omap44xx_aess_hwmod = {
 337         .name           = "aess",
 338         .class          = &omap44xx_aess_hwmod_class,
 339         .clkdm_name     = "abe_clkdm",
 340         .mpu_irqs       = omap44xx_aess_irqs,
 341         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 342         .main_clk       = "aess_fck",
 343         .prcm = {
 344                 .omap4 = {
 345                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 346                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 347                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 348                         .modulemode   = MODULEMODE_SWCTRL,
 349                 },
 350         },
 351 };
 352
 353 /*
 354  * 'c2c' class
 355  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 356  * soc
 357  */
 358
 359 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 360         .name   = "c2c",
 361 };
 362
 363 /* c2c */
 364 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 365         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 366         { .irq = -1 }
 367 };
 368
 369 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 370         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 371         { .dma_req = -1 }
 372 };
 373
 374 static struct omap_hwmod omap44xx_c2c_hwmod = {
 375         .name           = "c2c",
 376         .class          = &omap44xx_c2c_hwmod_class,
 377         .clkdm_name     = "d2d_clkdm",
 378         .mpu_irqs       = omap44xx_c2c_irqs,
 379         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 380         .prcm = {
 381                 .omap4 = {
 382                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 383                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 384                 },
 385         },
 386 };
 387
 388 /*
 389  * 'counter' class
 390  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 391  */
 392
 393 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 394         .rev_offs       = 0x0000,
 395         .sysc_offs      = 0x0004,
 396         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 397         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 398         .sysc_fields    = &omap_hwmod_sysc_type1,
 399 };
 400
 401 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 402         .name   = "counter",
 403         .sysc   = &omap44xx_counter_sysc,
 404 };
 405
 406 /* counter_32k */
 407 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 408         .name           = "counter_32k",
 409         .class          = &omap44xx_counter_hwmod_class,
 410         .clkdm_name     = "l4_wkup_clkdm",
 411         .flags          = HWMOD_SWSUP_SIDLE,
 412         .main_clk       = "sys_32k_ck",
 413         .prcm = {
 414                 .omap4 = {
 415                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 416                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 417                 },
 418         },
 419 };
 420
 421 /*
 422  * 'ctrl_module' class
 423  * attila core control module + core pad control module + wkup pad control
 424  * module + attila wkup control module
 425  */
 426
 427 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 428         .rev_offs       = 0x0000,
 429         .sysc_offs      = 0x0010,
 430         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 432                            SIDLE_SMART_WKUP),
 433         .sysc_fields    = &omap_hwmod_sysc_type2,
 434 };
 435
 436 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 437         .name   = "ctrl_module",
 438         .sysc   = &omap44xx_ctrl_module_sysc,
 439 };
 440
 441 /* ctrl_module_core */
 442 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 443         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 444         { .irq = -1 }
 445 };
 446
 447 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 448         .name           = "ctrl_module_core",
 449         .class          = &omap44xx_ctrl_module_hwmod_class,
 450         .clkdm_name     = "l4_cfg_clkdm",
 451         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 452 };
 453
 454 /* ctrl_module_pad_core */
 455 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 456         .name           = "ctrl_module_pad_core",
 457         .class          = &omap44xx_ctrl_module_hwmod_class,
 458         .clkdm_name     = "l4_cfg_clkdm",
 459 };
 460
 461 /* ctrl_module_wkup */
 462 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 463         .name           = "ctrl_module_wkup",
 464         .class          = &omap44xx_ctrl_module_hwmod_class,
 465         .clkdm_name     = "l4_wkup_clkdm",
 466 };
 467
 468 /* ctrl_module_pad_wkup */
 469 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 470         .name           = "ctrl_module_pad_wkup",
 471         .class          = &omap44xx_ctrl_module_hwmod_class,
 472         .clkdm_name     = "l4_wkup_clkdm",
 473 };
 474
 475 /*
 476  * 'debugss' class
 477  * debug and emulation sub system
 478  */
 479
 480 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 481         .name   = "debugss",
 482 };
 483
 484 /* debugss */
 485 static struct omap_hwmod omap44xx_debugss_hwmod = {
 486         .name           = "debugss",
 487         .class          = &omap44xx_debugss_hwmod_class,
 488         .clkdm_name     = "emu_sys_clkdm",
 489         .main_clk       = "trace_clk_div_ck",
 490         .prcm = {
 491                 .omap4 = {
 492                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 493                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 494                 },
 495         },
 496 };
 497
 498 /*
 499  * 'dma' class
 500  * dma controller for data exchange between memory to memory (i.e. internal or
 501  * external memory) and gp peripherals to memory or memory to gp peripherals
 502  */
 503
 504 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 505         .rev_offs       = 0x0000,
 506         .sysc_offs      = 0x002c,
 507         .syss_offs      = 0x0028,
 508         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 509                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 510                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 511                            SYSS_HAS_RESET_STATUS),
 512         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 513                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 514         .sysc_fields    = &omap_hwmod_sysc_type1,
 515 };
 516
 517 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 518         .name   = "dma",
 519         .sysc   = &omap44xx_dma_sysc,
 520 };
 521
 522 /* dma dev_attr */
 523 static struct omap_dma_dev_attr dma_dev_attr = {
 524         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 525                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 526         .lch_count      = 32,
 527 };
 528
 529 /* dma_system */
 530 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 531         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 532         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 533         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 534         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 535         { .irq = -1 }
 536 };
 537
 538 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 539         .name           = "dma_system",
 540         .class          = &omap44xx_dma_hwmod_class,
 541         .clkdm_name     = "l3_dma_clkdm",
 542         .mpu_irqs       = omap44xx_dma_system_irqs,
 543         .main_clk       = "l3_div_ck",
 544         .prcm = {
 545                 .omap4 = {
 546                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 547                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 548                 },
 549         },
 550         .dev_attr       = &dma_dev_attr,
 551 };
 552
 553 /*
 554  * 'dmic' class
 555  * digital microphone controller
 556  */
 557
 558 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 559         .rev_offs       = 0x0000,
 560         .sysc_offs      = 0x0010,
 561         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 562                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 564                            SIDLE_SMART_WKUP),
 565         .sysc_fields    = &omap_hwmod_sysc_type2,
 566 };
 567
 568 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 569         .name   = "dmic",
 570         .sysc   = &omap44xx_dmic_sysc,
 571 };
 572
 573 /* dmic */
 574 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 575         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 576         { .irq = -1 }
 577 };
 578
 579 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 580         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 581         { .dma_req = -1 }
 582 };
 583
 584 static struct omap_hwmod omap44xx_dmic_hwmod = {
 585         .name           = "dmic",
 586         .class          = &omap44xx_dmic_hwmod_class,
 587         .clkdm_name     = "abe_clkdm",
 588         .mpu_irqs       = omap44xx_dmic_irqs,
 589         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 590         .main_clk       = "dmic_fck",
 591         .prcm = {
 592                 .omap4 = {
 593                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 594                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 595                         .modulemode   = MODULEMODE_SWCTRL,
 596                 },
 597         },
 598 };
 599
 600 /*
 601  * 'dsp' class
 602  * dsp sub-system
 603  */
 604
 605 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 606         .name   = "dsp",
 607 };
 608
 609 /* dsp */
 610 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 611         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 612         { .irq = -1 }
 613 };
 614
 615 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 616         { .name = "dsp", .rst_shift = 0 },
 617         { .name = "mmu_cache", .rst_shift = 1 },
 618 };
 619
 620 static struct omap_hwmod omap44xx_dsp_hwmod = {
 621         .name           = "dsp",
 622         .class          = &omap44xx_dsp_hwmod_class,
 623         .clkdm_name     = "tesla_clkdm",
 624         .mpu_irqs       = omap44xx_dsp_irqs,
 625         .rst_lines      = omap44xx_dsp_resets,
 626         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 627         .main_clk       = "dsp_fck",
 628         .prcm = {
 629                 .omap4 = {
 630                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 631                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 632                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 633                         .modulemode   = MODULEMODE_HWCTRL,
 634                 },
 635         },
 636 };
 637
 638 /*
 639  * 'dss' class
 640  * display sub-system
 641  */
 642
 643 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 644         .rev_offs       = 0x0000,
 645         .syss_offs      = 0x0014,
 646         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 647 };
 648
 649 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 650         .name   = "dss",
 651         .sysc   = &omap44xx_dss_sysc,
 652         .reset  = omap_dss_reset,
 653 };
 654
 655 /* dss */
 656 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 657         { .role = "sys_clk", .clk = "dss_sys_clk" },
 658         { .role = "tv_clk", .clk = "dss_tv_clk" },
 659         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 660 };
 661
 662 static struct omap_hwmod omap44xx_dss_hwmod = {
 663         .name           = "dss_core",
 664         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 665         .class          = &omap44xx_dss_hwmod_class,
 666         .clkdm_name     = "l3_dss_clkdm",
 667         .main_clk       = "dss_dss_clk",
 668         .prcm = {
 669                 .omap4 = {
 670                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 671                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 672                 },
 673         },
 674         .opt_clks       = dss_opt_clks,
 675         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 676 };
 677
 678 /*
 679  * 'dispc' class
 680  * display controller
 681  */
 682
 683 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 684         .rev_offs       = 0x0000,
 685         .sysc_offs      = 0x0010,
 686         .syss_offs      = 0x0014,
 687         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 688                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 689                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 690                            SYSS_HAS_RESET_STATUS),
 691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 692                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 693         .sysc_fields    = &omap_hwmod_sysc_type1,
 694 };
 695
 696 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 697         .name   = "dispc",
 698         .sysc   = &omap44xx_dispc_sysc,
 699 };
 700
 701 /* dss_dispc */
 702 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 703         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 704         { .irq = -1 }
 705 };
 706
 707 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 708         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 709         { .dma_req = -1 }
 710 };
 711
 712 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 713         .manager_count          = 3,
 714         .has_framedonetv_irq    = 1
 715 };
 716
 717 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 718         .name           = "dss_dispc",
 719         .class          = &omap44xx_dispc_hwmod_class,
 720         .clkdm_name     = "l3_dss_clkdm",
 721         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 722         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 723         .main_clk       = "dss_dss_clk",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 727                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 728                 },
 729         },
 730         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 731 };
 732
 733 /*
 734  * 'dsi' class
 735  * display serial interface controller
 736  */
 737
 738 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 739         .rev_offs       = 0x0000,
 740         .sysc_offs      = 0x0010,
 741         .syss_offs      = 0x0014,
 742         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 743                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 744                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 745         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 746         .sysc_fields    = &omap_hwmod_sysc_type1,
 747 };
 748
 749 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 750         .name   = "dsi",
 751         .sysc   = &omap44xx_dsi_sysc,
 752 };
 753
 754 /* dss_dsi1 */
 755 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 756         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 757         { .irq = -1 }
 758 };
 759
 760 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 761         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 762         { .dma_req = -1 }
 763 };
 764
 765 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 766         { .role = "sys_clk", .clk = "dss_sys_clk" },
 767 };
 768
 769 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 770         .name           = "dss_dsi1",
 771         .class          = &omap44xx_dsi_hwmod_class,
 772         .clkdm_name     = "l3_dss_clkdm",
 773         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 774         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 775         .main_clk       = "dss_dss_clk",
 776         .prcm = {
 777                 .omap4 = {
 778                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 779                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 780                 },
 781         },
 782         .opt_clks       = dss_dsi1_opt_clks,
 783         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 784 };
 785
 786 /* dss_dsi2 */
 787 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 788         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 789         { .irq = -1 }
 790 };
 791
 792 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 793         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 794         { .dma_req = -1 }
 795 };
 796
 797 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 798         { .role = "sys_clk", .clk = "dss_sys_clk" },
 799 };
 800
 801 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 802         .name           = "dss_dsi2",
 803         .class          = &omap44xx_dsi_hwmod_class,
 804         .clkdm_name     = "l3_dss_clkdm",
 805         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 806         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 807         .main_clk       = "dss_dss_clk",
 808         .prcm = {
 809                 .omap4 = {
 810                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 811                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 812                 },
 813         },
 814         .opt_clks       = dss_dsi2_opt_clks,
 815         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 816 };
 817
 818 /*
 819  * 'hdmi' class
 820  * hdmi controller
 821  */
 822
 823 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 824         .rev_offs       = 0x0000,
 825         .sysc_offs      = 0x0010,
 826         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 827                            SYSC_HAS_SOFTRESET),
 828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 829                            SIDLE_SMART_WKUP),
 830         .sysc_fields    = &omap_hwmod_sysc_type2,
 831 };
 832
 833 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 834         .name   = "hdmi",
 835         .sysc   = &omap44xx_hdmi_sysc,
 836 };
 837
 838 /* dss_hdmi */
 839 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 840         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 841         { .irq = -1 }
 842 };
 843
 844 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 845         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 846         { .dma_req = -1 }
 847 };
 848
 849 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 850         { .role = "sys_clk", .clk = "dss_sys_clk" },
 851 };
 852
 853 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 854         .name           = "dss_hdmi",
 855         .class          = &omap44xx_hdmi_hwmod_class,
 856         .clkdm_name     = "l3_dss_clkdm",
 857         /*
 858          * HDMI audio requires to use no-idle mode. Hence,
 859          * set idle mode by software.
 860          */
 861         .flags          = HWMOD_SWSUP_SIDLE,
 862         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 863         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 864         .main_clk       = "dss_48mhz_clk",
 865         .prcm = {
 866                 .omap4 = {
 867                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 868                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 869                 },
 870         },
 871         .opt_clks       = dss_hdmi_opt_clks,
 872         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 873 };
 874
 875 /*
 876  * 'rfbi' class
 877  * remote frame buffer interface
 878  */
 879
 880 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 881         .rev_offs       = 0x0000,
 882         .sysc_offs      = 0x0010,
 883         .syss_offs      = 0x0014,
 884         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 885                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 886         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 887         .sysc_fields    = &omap_hwmod_sysc_type1,
 888 };
 889
 890 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 891         .name   = "rfbi",
 892         .sysc   = &omap44xx_rfbi_sysc,
 893 };
 894
 895 /* dss_rfbi */
 896 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 897         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 898         { .dma_req = -1 }
 899 };
 900
 901 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 902         { .role = "ick", .clk = "dss_fck" },
 903 };
 904
 905 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 906         .name           = "dss_rfbi",
 907         .class          = &omap44xx_rfbi_hwmod_class,
 908         .clkdm_name     = "l3_dss_clkdm",
 909         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 910         .main_clk       = "dss_dss_clk",
 911         .prcm = {
 912                 .omap4 = {
 913                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 914                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 915                 },
 916         },
 917         .opt_clks       = dss_rfbi_opt_clks,
 918         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 919 };
 920
 921 /*
 922  * 'venc' class
 923  * video encoder
 924  */
 925
 926 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 927         .name   = "venc",
 928 };
 929
 930 /* dss_venc */
 931 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 932         .name           = "dss_venc",
 933         .class          = &omap44xx_venc_hwmod_class,
 934         .clkdm_name     = "l3_dss_clkdm",
 935         .main_clk       = "dss_tv_clk",
 936         .prcm = {
 937                 .omap4 = {
 938                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 939                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 940                 },
 941         },
 942 };
 943
 944 /*
 945  * 'elm' class
 946  * bch error location module
 947  */
 948
 949 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 950         .rev_offs       = 0x0000,
 951         .sysc_offs      = 0x0010,
 952         .syss_offs      = 0x0014,
 953         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 954                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 955                            SYSS_HAS_RESET_STATUS),
 956         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 957         .sysc_fields    = &omap_hwmod_sysc_type1,
 958 };
 959
 960 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 961         .name   = "elm",
 962         .sysc   = &omap44xx_elm_sysc,
 963 };
 964
 965 /* elm */
 966 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 967         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 968         { .irq = -1 }
 969 };
 970
 971 static struct omap_hwmod omap44xx_elm_hwmod = {
 972         .name           = "elm",
 973         .class          = &omap44xx_elm_hwmod_class,
 974         .clkdm_name     = "l4_per_clkdm",
 975         .mpu_irqs       = omap44xx_elm_irqs,
 976         .prcm = {
 977                 .omap4 = {
 978                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 979                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 980                 },
 981         },
 982 };
 983
 984 /*
 985  * 'emif' class
 986  * external memory interface no1
 987  */
 988
 989 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 990         .rev_offs       = 0x0000,
 991 };
 992
 993 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 994         .name   = "emif",
 995         .sysc   = &omap44xx_emif_sysc,
 996 };
 997
 998 /* emif1 */
 999 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1000         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1001         { .irq = -1 }
1002 };
1003
1004 static struct omap_hwmod omap44xx_emif1_hwmod = {
1005         .name           = "emif1",
1006         .class          = &omap44xx_emif_hwmod_class,
1007         .clkdm_name     = "l3_emif_clkdm",
1008         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1009         .mpu_irqs       = omap44xx_emif1_irqs,
1010         .main_clk       = "ddrphy_ck",
1011         .prcm = {
1012                 .omap4 = {
1013                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1014                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1015                         .modulemode   = MODULEMODE_HWCTRL,
1016                 },
1017         },
1018 };
1019
1020 /* emif2 */
1021 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1022         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1023         { .irq = -1 }
1024 };
1025
1026 static struct omap_hwmod omap44xx_emif2_hwmod = {
1027         .name           = "emif2",
1028         .class          = &omap44xx_emif_hwmod_class,
1029         .clkdm_name     = "l3_emif_clkdm",
1030         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1031         .mpu_irqs       = omap44xx_emif2_irqs,
1032         .main_clk       = "ddrphy_ck",
1033         .prcm = {
1034                 .omap4 = {
1035                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1036                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1037                         .modulemode   = MODULEMODE_HWCTRL,
1038                 },
1039         },
1040 };
1041
1042 /*
1043  * 'fdif' class
1044  * face detection hw accelerator module
1045  */
1046
1047 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1048         .rev_offs       = 0x0000,
1049         .sysc_offs      = 0x0010,
1050         /*
1051          * FDIF needs 100 OCP clk cycles delay after a softreset before
1052          * accessing sysconfig again.
1053          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1054          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1055          *
1056          * TODO: Indicate errata when available.
1057          */
1058         .srst_udelay    = 2,
1059         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1060                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1061         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1062                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1063         .sysc_fields    = &omap_hwmod_sysc_type2,
1064 };
1065
1066 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1067         .name   = "fdif",
1068         .sysc   = &omap44xx_fdif_sysc,
1069 };
1070
1071 /* fdif */
1072 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1073         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1074         { .irq = -1 }
1075 };
1076
1077 static struct omap_hwmod omap44xx_fdif_hwmod = {
1078         .name           = "fdif",
1079         .class          = &omap44xx_fdif_hwmod_class,
1080         .clkdm_name     = "iss_clkdm",
1081         .mpu_irqs       = omap44xx_fdif_irqs,
1082         .main_clk       = "fdif_fck",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1086                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090 };
1091
1092 /*
1093  * 'gpio' class
1094  * general purpose io module
1095  */
1096
1097 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1098         .rev_offs       = 0x0000,
1099         .sysc_offs      = 0x0010,
1100         .syss_offs      = 0x0114,
1101         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1103                            SYSS_HAS_RESET_STATUS),
1104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1105                            SIDLE_SMART_WKUP),
1106         .sysc_fields    = &omap_hwmod_sysc_type1,
1107 };
1108
1109 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1110         .name   = "gpio",
1111         .sysc   = &omap44xx_gpio_sysc,
1112         .rev    = 2,
1113 };
1114
1115 /* gpio dev_attr */
1116 static struct omap_gpio_dev_attr gpio_dev_attr = {
1117         .bank_width     = 32,
1118         .dbck_flag      = true,
1119 };
1120
1121 /* gpio1 */
1122 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1123         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1124         { .irq = -1 }
1125 };
1126
1127 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1128         { .role = "dbclk", .clk = "gpio1_dbclk" },
1129 };
1130
1131 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1132         .name           = "gpio1",
1133         .class          = &omap44xx_gpio_hwmod_class,
1134         .clkdm_name     = "l4_wkup_clkdm",
1135         .mpu_irqs       = omap44xx_gpio1_irqs,
1136         .main_clk       = "gpio1_ick",
1137         .prcm = {
1138                 .omap4 = {
1139                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1140                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1141                         .modulemode   = MODULEMODE_HWCTRL,
1142                 },
1143         },
1144         .opt_clks       = gpio1_opt_clks,
1145         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1146         .dev_attr       = &gpio_dev_attr,
1147 };
1148
1149 /* gpio2 */
1150 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1151         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1152         { .irq = -1 }
1153 };
1154
1155 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1156         { .role = "dbclk", .clk = "gpio2_dbclk" },
1157 };
1158
1159 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1160         .name           = "gpio2",
1161         .class          = &omap44xx_gpio_hwmod_class,
1162         .clkdm_name     = "l4_per_clkdm",
1163         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1164         .mpu_irqs       = omap44xx_gpio2_irqs,
1165         .main_clk       = "gpio2_ick",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1169                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1170                         .modulemode   = MODULEMODE_HWCTRL,
1171                 },
1172         },
1173         .opt_clks       = gpio2_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1175         .dev_attr       = &gpio_dev_attr,
1176 };
1177
1178 /* gpio3 */
1179 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1180         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1181         { .irq = -1 }
1182 };
1183
1184 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio3_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1189         .name           = "gpio3",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .mpu_irqs       = omap44xx_gpio3_irqs,
1194         .main_clk       = "gpio3_ick",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1198                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_HWCTRL,
1200                 },
1201         },
1202         .opt_clks       = gpio3_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1204         .dev_attr       = &gpio_dev_attr,
1205 };
1206
1207 /* gpio4 */
1208 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1209         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1210         { .irq = -1 }
1211 };
1212
1213 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1214         { .role = "dbclk", .clk = "gpio4_dbclk" },
1215 };
1216
1217 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1218         .name           = "gpio4",
1219         .class          = &omap44xx_gpio_hwmod_class,
1220         .clkdm_name     = "l4_per_clkdm",
1221         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222         .mpu_irqs       = omap44xx_gpio4_irqs,
1223         .main_clk       = "gpio4_ick",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_HWCTRL,
1229                 },
1230         },
1231         .opt_clks       = gpio4_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1233         .dev_attr       = &gpio_dev_attr,
1234 };
1235
1236 /* gpio5 */
1237 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1238         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1239         { .irq = -1 }
1240 };
1241
1242 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1243         { .role = "dbclk", .clk = "gpio5_dbclk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1247         .name           = "gpio5",
1248         .class          = &omap44xx_gpio_hwmod_class,
1249         .clkdm_name     = "l4_per_clkdm",
1250         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251         .mpu_irqs       = omap44xx_gpio5_irqs,
1252         .main_clk       = "gpio5_ick",
1253         .prcm = {
1254                 .omap4 = {
1255                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1256                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1257                         .modulemode   = MODULEMODE_HWCTRL,
1258                 },
1259         },
1260         .opt_clks       = gpio5_opt_clks,
1261         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1262         .dev_attr       = &gpio_dev_attr,
1263 };
1264
1265 /* gpio6 */
1266 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1267         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1268         { .irq = -1 }
1269 };
1270
1271 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1272         { .role = "dbclk", .clk = "gpio6_dbclk" },
1273 };
1274
1275 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1276         .name           = "gpio6",
1277         .class          = &omap44xx_gpio_hwmod_class,
1278         .clkdm_name     = "l4_per_clkdm",
1279         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280         .mpu_irqs       = omap44xx_gpio6_irqs,
1281         .main_clk       = "gpio6_ick",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_HWCTRL,
1287                 },
1288         },
1289         .opt_clks       = gpio6_opt_clks,
1290         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1291         .dev_attr       = &gpio_dev_attr,
1292 };
1293
1294 /*
1295  * 'gpmc' class
1296  * general purpose memory controller
1297  */
1298
1299 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1300         .rev_offs       = 0x0000,
1301         .sysc_offs      = 0x0010,
1302         .syss_offs      = 0x0014,
1303         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1304                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1305         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1306         .sysc_fields    = &omap_hwmod_sysc_type1,
1307 };
1308
1309 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1310         .name   = "gpmc",
1311         .sysc   = &omap44xx_gpmc_sysc,
1312 };
1313
1314 /* gpmc */
1315 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1316         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1317         { .irq = -1 }
1318 };
1319
1320 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1321         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1322         { .dma_req = -1 }
1323 };
1324
1325 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1326         .name           = "gpmc",
1327         .class          = &omap44xx_gpmc_hwmod_class,
1328         .clkdm_name     = "l3_2_clkdm",
1329         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1330         .mpu_irqs       = omap44xx_gpmc_irqs,
1331         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1332         .prcm = {
1333                 .omap4 = {
1334                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1335                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1336                         .modulemode   = MODULEMODE_HWCTRL,
1337                 },
1338         },
1339 };
1340
1341 /*
1342  * 'gpu' class
1343  * 2d/3d graphics accelerator
1344  */
1345
1346 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1347         .rev_offs       = 0x1fc00,
1348         .sysc_offs      = 0x1fc10,
1349         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1350         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1351                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1352                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1353         .sysc_fields    = &omap_hwmod_sysc_type2,
1354 };
1355
1356 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1357         .name   = "gpu",
1358         .sysc   = &omap44xx_gpu_sysc,
1359 };
1360
1361 /* gpu */
1362 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1363         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1364         { .irq = -1 }
1365 };
1366
1367 static struct omap_hwmod omap44xx_gpu_hwmod = {
1368         .name           = "gpu",
1369         .class          = &omap44xx_gpu_hwmod_class,
1370         .clkdm_name     = "l3_gfx_clkdm",
1371         .mpu_irqs       = omap44xx_gpu_irqs,
1372         .main_clk       = "gpu_fck",
1373         .prcm = {
1374                 .omap4 = {
1375                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1376                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1377                         .modulemode   = MODULEMODE_SWCTRL,
1378                 },
1379         },
1380 };
1381
1382 /*
1383  * 'hdq1w' class
1384  * hdq / 1-wire serial interface controller
1385  */
1386
1387 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1388         .rev_offs       = 0x0000,
1389         .sysc_offs      = 0x0014,
1390         .syss_offs      = 0x0018,
1391         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1392                            SYSS_HAS_RESET_STATUS),
1393         .sysc_fields    = &omap_hwmod_sysc_type1,
1394 };
1395
1396 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1397         .name   = "hdq1w",
1398         .sysc   = &omap44xx_hdq1w_sysc,
1399 };
1400
1401 /* hdq1w */
1402 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1403         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1404         { .irq = -1 }
1405 };
1406
1407 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1408         .name           = "hdq1w",
1409         .class          = &omap44xx_hdq1w_hwmod_class,
1410         .clkdm_name     = "l4_per_clkdm",
1411         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1412         .mpu_irqs       = omap44xx_hdq1w_irqs,
1413         .main_clk       = "hdq1w_fck",
1414         .prcm = {
1415                 .omap4 = {
1416                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1417                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1418                         .modulemode   = MODULEMODE_SWCTRL,
1419                 },
1420         },
1421 };
1422
1423 /*
1424  * 'hsi' class
1425  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1426  * serial if)
1427  */
1428
1429 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1430         .rev_offs       = 0x0000,
1431         .sysc_offs      = 0x0010,
1432         .syss_offs      = 0x0014,
1433         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1434                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1435                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1436         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1437                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1438                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1439         .sysc_fields    = &omap_hwmod_sysc_type1,
1440 };
1441
1442 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1443         .name   = "hsi",
1444         .sysc   = &omap44xx_hsi_sysc,
1445 };
1446
1447 /* hsi */
1448 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1449         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1450         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1451         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1452         { .irq = -1 }
1453 };
1454
1455 static struct omap_hwmod omap44xx_hsi_hwmod = {
1456         .name           = "hsi",
1457         .class          = &omap44xx_hsi_hwmod_class,
1458         .clkdm_name     = "l3_init_clkdm",
1459         .mpu_irqs       = omap44xx_hsi_irqs,
1460         .main_clk       = "hsi_fck",
1461         .prcm = {
1462                 .omap4 = {
1463                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1464                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1465                         .modulemode   = MODULEMODE_HWCTRL,
1466                 },
1467         },
1468 };
1469
1470 /*
1471  * 'i2c' class
1472  * multimaster high-speed i2c controller
1473  */
1474
1475 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1476         .sysc_offs      = 0x0010,
1477         .syss_offs      = 0x0090,
1478         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1479                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1480                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1481         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1482                            SIDLE_SMART_WKUP),
1483         .clockact       = CLOCKACT_TEST_ICLK,
1484         .sysc_fields    = &omap_hwmod_sysc_type1,
1485 };
1486
1487 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1488         .name   = "i2c",
1489         .sysc   = &omap44xx_i2c_sysc,
1490         .rev    = OMAP_I2C_IP_VERSION_2,
1491         .reset  = &omap_i2c_reset,
1492 };
1493
1494 static struct omap_i2c_dev_attr i2c_dev_attr = {
1495         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1496                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1497 };
1498
1499 /* i2c1 */
1500 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1501         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1502         { .irq = -1 }
1503 };
1504
1505 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1506         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1507         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1508         { .dma_req = -1 }
1509 };
1510
1511 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1512         .name           = "i2c1",
1513         .class          = &omap44xx_i2c_hwmod_class,
1514         .clkdm_name     = "l4_per_clkdm",
1515         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1516         .mpu_irqs       = omap44xx_i2c1_irqs,
1517         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1518         .main_clk       = "i2c1_fck",
1519         .prcm = {
1520                 .omap4 = {
1521                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1522                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1523                         .modulemode   = MODULEMODE_SWCTRL,
1524                 },
1525         },
1526         .dev_attr       = &i2c_dev_attr,
1527 };
1528
1529 /* i2c2 */
1530 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1531         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1532         { .irq = -1 }
1533 };
1534
1535 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1536         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1537         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1538         { .dma_req = -1 }
1539 };
1540
1541 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1542         .name           = "i2c2",
1543         .class          = &omap44xx_i2c_hwmod_class,
1544         .clkdm_name     = "l4_per_clkdm",
1545         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1546         .mpu_irqs       = omap44xx_i2c2_irqs,
1547         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1548         .main_clk       = "i2c2_fck",
1549         .prcm = {
1550                 .omap4 = {
1551                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1552                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1553                         .modulemode   = MODULEMODE_SWCTRL,
1554                 },
1555         },
1556         .dev_attr       = &i2c_dev_attr,
1557 };
1558
1559 /* i2c3 */
1560 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1561         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1562         { .irq = -1 }
1563 };
1564
1565 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1566         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1567         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1568         { .dma_req = -1 }
1569 };
1570
1571 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1572         .name           = "i2c3",
1573         .class          = &omap44xx_i2c_hwmod_class,
1574         .clkdm_name     = "l4_per_clkdm",
1575         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1576         .mpu_irqs       = omap44xx_i2c3_irqs,
1577         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1578         .main_clk       = "i2c3_fck",
1579         .prcm = {
1580                 .omap4 = {
1581                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1582                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1583                         .modulemode   = MODULEMODE_SWCTRL,
1584                 },
1585         },
1586         .dev_attr       = &i2c_dev_attr,
1587 };
1588
1589 /* i2c4 */
1590 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1591         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1592         { .irq = -1 }
1593 };
1594
1595 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1596         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1597         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1598         { .dma_req = -1 }
1599 };
1600
1601 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1602         .name           = "i2c4",
1603         .class          = &omap44xx_i2c_hwmod_class,
1604         .clkdm_name     = "l4_per_clkdm",
1605         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1606         .mpu_irqs       = omap44xx_i2c4_irqs,
1607         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1608         .main_clk       = "i2c4_fck",
1609         .prcm = {
1610                 .omap4 = {
1611                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1612                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1613                         .modulemode   = MODULEMODE_SWCTRL,
1614                 },
1615         },
1616         .dev_attr       = &i2c_dev_attr,
1617 };
1618
1619 /*
1620  * 'ipu' class
1621  * imaging processor unit
1622  */
1623
1624 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1625         .name   = "ipu",
1626 };
1627
1628 /* ipu */
1629 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1630         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1631         { .irq = -1 }
1632 };
1633
1634 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1635         { .name = "cpu0", .rst_shift = 0 },
1636         { .name = "cpu1", .rst_shift = 1 },
1637         { .name = "mmu_cache", .rst_shift = 2 },
1638 };
1639
1640 static struct omap_hwmod omap44xx_ipu_hwmod = {
1641         .name           = "ipu",
1642         .class          = &omap44xx_ipu_hwmod_class,
1643         .clkdm_name     = "ducati_clkdm",
1644         .mpu_irqs       = omap44xx_ipu_irqs,
1645         .rst_lines      = omap44xx_ipu_resets,
1646         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1647         .main_clk       = "ipu_fck",
1648         .prcm = {
1649                 .omap4 = {
1650                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1651                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1652                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1653                         .modulemode   = MODULEMODE_HWCTRL,
1654                 },
1655         },
1656 };
1657
1658 /*
1659  * 'iss' class
1660  * external images sensor pixel data processor
1661  */
1662
1663 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1664         .rev_offs       = 0x0000,
1665         .sysc_offs      = 0x0010,
1666         /*
1667          * ISS needs 100 OCP clk cycles delay after a softreset before
1668          * accessing sysconfig again.
1669          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1670          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1671          *
1672          * TODO: Indicate errata when available.
1673          */
1674         .srst_udelay    = 2,
1675         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1676                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1677         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1678                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1679                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1680         .sysc_fields    = &omap_hwmod_sysc_type2,
1681 };
1682
1683 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1684         .name   = "iss",
1685         .sysc   = &omap44xx_iss_sysc,
1686 };
1687
1688 /* iss */
1689 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1690         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1691         { .irq = -1 }
1692 };
1693
1694 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1695         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1696         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1697         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1698         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1699         { .dma_req = -1 }
1700 };
1701
1702 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1703         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1704 };
1705
1706 static struct omap_hwmod omap44xx_iss_hwmod = {
1707         .name           = "iss",
1708         .class          = &omap44xx_iss_hwmod_class,
1709         .clkdm_name     = "iss_clkdm",
1710         .mpu_irqs       = omap44xx_iss_irqs,
1711         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1712         .main_clk       = "iss_fck",
1713         .prcm = {
1714                 .omap4 = {
1715                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1716                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1717                         .modulemode   = MODULEMODE_SWCTRL,
1718                 },
1719         },
1720         .opt_clks       = iss_opt_clks,
1721         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1722 };
1723
1724 /*
1725  * 'iva' class
1726  * multi-standard video encoder/decoder hardware accelerator
1727  */
1728
1729 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1730         .name   = "iva",
1731 };
1732
1733 /* iva */
1734 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1735         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1736         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1737         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1738         { .irq = -1 }
1739 };
1740
1741 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1742         { .name = "seq0", .rst_shift = 0 },
1743         { .name = "seq1", .rst_shift = 1 },
1744         { .name = "logic", .rst_shift = 2 },
1745 };
1746
1747 static struct omap_hwmod omap44xx_iva_hwmod = {
1748         .name           = "iva",
1749         .class          = &omap44xx_iva_hwmod_class,
1750         .clkdm_name     = "ivahd_clkdm",
1751         .mpu_irqs       = omap44xx_iva_irqs,
1752         .rst_lines      = omap44xx_iva_resets,
1753         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1754         .main_clk       = "iva_fck",
1755         .prcm = {
1756                 .omap4 = {
1757                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1758                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1759                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1760                         .modulemode   = MODULEMODE_HWCTRL,
1761                 },
1762         },
1763 };
1764
1765 /*
1766  * 'kbd' class
1767  * keyboard controller
1768  */
1769
1770 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1771         .rev_offs       = 0x0000,
1772         .sysc_offs      = 0x0010,
1773         .syss_offs      = 0x0014,
1774         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1775                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1776                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1777                            SYSS_HAS_RESET_STATUS),
1778         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1779         .sysc_fields    = &omap_hwmod_sysc_type1,
1780 };
1781
1782 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1783         .name   = "kbd",
1784         .sysc   = &omap44xx_kbd_sysc,
1785 };
1786
1787 /* kbd */
1788 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1789         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1790         { .irq = -1 }
1791 };
1792
1793 static struct omap_hwmod omap44xx_kbd_hwmod = {
1794         .name           = "kbd",
1795         .class          = &omap44xx_kbd_hwmod_class,
1796         .clkdm_name     = "l4_wkup_clkdm",
1797         .mpu_irqs       = omap44xx_kbd_irqs,
1798         .main_clk       = "kbd_fck",
1799         .prcm = {
1800                 .omap4 = {
1801                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1802                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1803                         .modulemode   = MODULEMODE_SWCTRL,
1804                 },
1805         },
1806 };
1807
1808 /*
1809  * 'mailbox' class
1810  * mailbox module allowing communication between the on-chip processors using a
1811  * queued mailbox-interrupt mechanism.
1812  */
1813
1814 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1815         .rev_offs       = 0x0000,
1816         .sysc_offs      = 0x0010,
1817         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1818                            SYSC_HAS_SOFTRESET),
1819         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1820         .sysc_fields    = &omap_hwmod_sysc_type2,
1821 };
1822
1823 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1824         .name   = "mailbox",
1825         .sysc   = &omap44xx_mailbox_sysc,
1826 };
1827
1828 /* mailbox */
1829 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1830         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1831         { .irq = -1 }
1832 };
1833
1834 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1835         .name           = "mailbox",
1836         .class          = &omap44xx_mailbox_hwmod_class,
1837         .clkdm_name     = "l4_cfg_clkdm",
1838         .mpu_irqs       = omap44xx_mailbox_irqs,
1839         .prcm = {
1840                 .omap4 = {
1841                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1842                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1843                 },
1844         },
1845 };
1846
1847 /*
1848  * 'mcasp' class
1849  * multi-channel audio serial port controller
1850  */
1851
1852 /* The IP is not compliant to type1 / type2 scheme */
1853 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1854         .sidle_shift    = 0,
1855 };
1856
1857 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1858         .sysc_offs      = 0x0004,
1859         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1860         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1861                            SIDLE_SMART_WKUP),
1862         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1863 };
1864
1865 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1866         .name   = "mcasp",
1867         .sysc   = &omap44xx_mcasp_sysc,
1868 };
1869
1870 /* mcasp */
1871 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1872         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1873         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1874         { .irq = -1 }
1875 };
1876
1877 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1878         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1879         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1880         { .dma_req = -1 }
1881 };
1882
1883 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1884         .name           = "mcasp",
1885         .class          = &omap44xx_mcasp_hwmod_class,
1886         .clkdm_name     = "abe_clkdm",
1887         .mpu_irqs       = omap44xx_mcasp_irqs,
1888         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1889         .main_clk       = "mcasp_fck",
1890         .prcm = {
1891                 .omap4 = {
1892                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1893                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1894                         .modulemode   = MODULEMODE_SWCTRL,
1895                 },
1896         },
1897 };
1898
1899 /*
1900  * 'mcbsp' class
1901  * multi channel buffered serial port controller
1902  */
1903
1904 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1905         .sysc_offs      = 0x008c,
1906         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1907                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1908         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1909         .sysc_fields    = &omap_hwmod_sysc_type1,
1910 };
1911
1912 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1913         .name   = "mcbsp",
1914         .sysc   = &omap44xx_mcbsp_sysc,
1915         .rev    = MCBSP_CONFIG_TYPE4,
1916 };
1917
1918 /* mcbsp1 */
1919 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1920         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1921         { .irq = -1 }
1922 };
1923
1924 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1925         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1926         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1927         { .dma_req = -1 }
1928 };
1929
1930 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1931         { .role = "pad_fck", .clk = "pad_clks_ck" },
1932         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1933 };
1934
1935 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1936         .name           = "mcbsp1",
1937         .class          = &omap44xx_mcbsp_hwmod_class,
1938         .clkdm_name     = "abe_clkdm",
1939         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1940         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1941         .main_clk       = "mcbsp1_fck",
1942         .prcm = {
1943                 .omap4 = {
1944                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1945                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1946                         .modulemode   = MODULEMODE_SWCTRL,
1947                 },
1948         },
1949         .opt_clks       = mcbsp1_opt_clks,
1950         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1951 };
1952
1953 /* mcbsp2 */
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1955         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1956         { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1960         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1961         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1962         { .dma_req = -1 }
1963 };
1964
1965 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1966         { .role = "pad_fck", .clk = "pad_clks_ck" },
1967         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1971         .name           = "mcbsp2",
1972         .class          = &omap44xx_mcbsp_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1975         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1976         .main_clk       = "mcbsp2_fck",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_SWCTRL,
1982                 },
1983         },
1984         .opt_clks       = mcbsp2_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1986 };
1987
1988 /* mcbsp3 */
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1990         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1991         { .irq = -1 }
1992 };
1993
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1995         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1996         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1997         { .dma_req = -1 }
1998 };
1999
2000 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2001         { .role = "pad_fck", .clk = "pad_clks_ck" },
2002         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2003 };
2004
2005 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2006         .name           = "mcbsp3",
2007         .class          = &omap44xx_mcbsp_hwmod_class,
2008         .clkdm_name     = "abe_clkdm",
2009         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2010         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2011         .main_clk       = "mcbsp3_fck",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2015                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019         .opt_clks       = mcbsp3_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2021 };
2022
2023 /* mcbsp4 */
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2025         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2030         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2031         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2032         { .dma_req = -1 }
2033 };
2034
2035 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2036         { .role = "pad_fck", .clk = "pad_clks_ck" },
2037         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2038 };
2039
2040 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2041         .name           = "mcbsp4",
2042         .class          = &omap44xx_mcbsp_hwmod_class,
2043         .clkdm_name     = "l4_per_clkdm",
2044         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2045         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2046         .main_clk       = "mcbsp4_fck",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054         .opt_clks       = mcbsp4_opt_clks,
2055         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2056 };
2057
2058 /*
2059  * 'mcpdm' class
2060  * multi channel pdm controller (proprietary interface with phoenix power
2061  * ic)
2062  */
2063
2064 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2065         .rev_offs       = 0x0000,
2066         .sysc_offs      = 0x0010,
2067         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2068                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2069         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2070                            SIDLE_SMART_WKUP),
2071         .sysc_fields    = &omap_hwmod_sysc_type2,
2072 };
2073
2074 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2075         .name   = "mcpdm",
2076         .sysc   = &omap44xx_mcpdm_sysc,
2077 };
2078
2079 /* mcpdm */
2080 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2081         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2082         { .irq = -1 }
2083 };
2084
2085 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2086         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2087         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2088         { .dma_req = -1 }
2089 };
2090
2091 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2092         .name           = "mcpdm",
2093         .class          = &omap44xx_mcpdm_hwmod_class,
2094         .clkdm_name     = "abe_clkdm",
2095         .mpu_irqs       = omap44xx_mcpdm_irqs,
2096         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2097         .main_clk       = "mcpdm_fck",
2098         .prcm = {
2099                 .omap4 = {
2100                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2101                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2102                         .modulemode   = MODULEMODE_SWCTRL,
2103                 },
2104         },
2105 };
2106
2107 /*
2108  * 'mcspi' class
2109  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2110  * bus
2111  */
2112
2113 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2114         .rev_offs       = 0x0000,
2115         .sysc_offs      = 0x0010,
2116         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2117                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2118         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2119                            SIDLE_SMART_WKUP),
2120         .sysc_fields    = &omap_hwmod_sysc_type2,
2121 };
2122
2123 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2124         .name   = "mcspi",
2125         .sysc   = &omap44xx_mcspi_sysc,
2126         .rev    = OMAP4_MCSPI_REV,
2127 };
2128
2129 /* mcspi1 */
2130 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2131         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2132         { .irq = -1 }
2133 };
2134
2135 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2136         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2137         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2138         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2139         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2140         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2141         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2142         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2143         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2144         { .dma_req = -1 }
2145 };
2146
2147 /* mcspi1 dev_attr */
2148 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2149         .num_chipselect = 4,
2150 };
2151
2152 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2153         .name           = "mcspi1",
2154         .class          = &omap44xx_mcspi_hwmod_class,
2155         .clkdm_name     = "l4_per_clkdm",
2156         .mpu_irqs       = omap44xx_mcspi1_irqs,
2157         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2158         .main_clk       = "mcspi1_fck",
2159         .prcm = {
2160                 .omap4 = {
2161                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2162                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2163                         .modulemode   = MODULEMODE_SWCTRL,
2164                 },
2165         },
2166         .dev_attr       = &mcspi1_dev_attr,
2167 };
2168
2169 /* mcspi2 */
2170 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2171         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2172         { .irq = -1 }
2173 };
2174
2175 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2176         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2177         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2178         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2179         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2180         { .dma_req = -1 }
2181 };
2182
2183 /* mcspi2 dev_attr */
2184 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2185         .num_chipselect = 2,
2186 };
2187
2188 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2189         .name           = "mcspi2",
2190         .class          = &omap44xx_mcspi_hwmod_class,
2191         .clkdm_name     = "l4_per_clkdm",
2192         .mpu_irqs       = omap44xx_mcspi2_irqs,
2193         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2194         .main_clk       = "mcspi2_fck",
2195         .prcm = {
2196                 .omap4 = {
2197                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2198                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2199                         .modulemode   = MODULEMODE_SWCTRL,
2200                 },
2201         },
2202         .dev_attr       = &mcspi2_dev_attr,
2203 };
2204
2205 /* mcspi3 */
2206 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2207         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2208         { .irq = -1 }
2209 };
2210
2211 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2212         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2213         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2214         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2215         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2216         { .dma_req = -1 }
2217 };
2218
2219 /* mcspi3 dev_attr */
2220 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2221         .num_chipselect = 2,
2222 };
2223
2224 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2225         .name           = "mcspi3",
2226         .class          = &omap44xx_mcspi_hwmod_class,
2227         .clkdm_name     = "l4_per_clkdm",
2228         .mpu_irqs       = omap44xx_mcspi3_irqs,
2229         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2230         .main_clk       = "mcspi3_fck",
2231         .prcm = {
2232                 .omap4 = {
2233                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2234                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2235                         .modulemode   = MODULEMODE_SWCTRL,
2236                 },
2237         },
2238         .dev_attr       = &mcspi3_dev_attr,
2239 };
2240
2241 /* mcspi4 */
2242 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2243         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2244         { .irq = -1 }
2245 };
2246
2247 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2248         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2249         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2250         { .dma_req = -1 }
2251 };
2252
2253 /* mcspi4 dev_attr */
2254 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2255         .num_chipselect = 1,
2256 };
2257
2258 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2259         .name           = "mcspi4",
2260         .class          = &omap44xx_mcspi_hwmod_class,
2261         .clkdm_name     = "l4_per_clkdm",
2262         .mpu_irqs       = omap44xx_mcspi4_irqs,
2263         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2264         .main_clk       = "mcspi4_fck",
2265         .prcm = {
2266                 .omap4 = {
2267                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2268                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2269                         .modulemode   = MODULEMODE_SWCTRL,
2270                 },
2271         },
2272         .dev_attr       = &mcspi4_dev_attr,
2273 };
2274
2275 /*
2276  * 'mmc' class
2277  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2278  */
2279
2280 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2281         .rev_offs       = 0x0000,
2282         .sysc_offs      = 0x0010,
2283         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2284                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2285                            SYSC_HAS_SOFTRESET),
2286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2287                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2288                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2289         .sysc_fields    = &omap_hwmod_sysc_type2,
2290 };
2291
2292 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2293         .name   = "mmc",
2294         .sysc   = &omap44xx_mmc_sysc,
2295 };
2296
2297 /* mmc1 */
2298 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2299         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2300         { .irq = -1 }
2301 };
2302
2303 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2304         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2305         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2306         { .dma_req = -1 }
2307 };
2308
2309 /* mmc1 dev_attr */
2310 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2311         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2312 };
2313
2314 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2315         .name           = "mmc1",
2316         .class          = &omap44xx_mmc_hwmod_class,
2317         .clkdm_name     = "l3_init_clkdm",
2318         .mpu_irqs       = omap44xx_mmc1_irqs,
2319         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2320         .main_clk       = "mmc1_fck",
2321         .prcm = {
2322                 .omap4 = {
2323                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2324                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2325                         .modulemode   = MODULEMODE_SWCTRL,
2326                 },
2327         },
2328         .dev_attr       = &mmc1_dev_attr,
2329 };
2330
2331 /* mmc2 */
2332 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2333         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2334         { .irq = -1 }
2335 };
2336
2337 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2338         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2339         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2340         { .dma_req = -1 }
2341 };
2342
2343 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2344         .name           = "mmc2",
2345         .class          = &omap44xx_mmc_hwmod_class,
2346         .clkdm_name     = "l3_init_clkdm",
2347         .mpu_irqs       = omap44xx_mmc2_irqs,
2348         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2349         .main_clk       = "mmc2_fck",
2350         .prcm = {
2351                 .omap4 = {
2352                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2353                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2354                         .modulemode   = MODULEMODE_SWCTRL,
2355                 },
2356         },
2357 };
2358
2359 /* mmc3 */
2360 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2361         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2362         { .irq = -1 }
2363 };
2364
2365 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2366         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2367         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2368         { .dma_req = -1 }
2369 };
2370
2371 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2372         .name           = "mmc3",
2373         .class          = &omap44xx_mmc_hwmod_class,
2374         .clkdm_name     = "l4_per_clkdm",
2375         .mpu_irqs       = omap44xx_mmc3_irqs,
2376         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2377         .main_clk       = "mmc3_fck",
2378         .prcm = {
2379                 .omap4 = {
2380                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2381                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2382                         .modulemode   = MODULEMODE_SWCTRL,
2383                 },
2384         },
2385 };
2386
2387 /* mmc4 */
2388 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2389         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2390         { .irq = -1 }
2391 };
2392
2393 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2394         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2395         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2396         { .dma_req = -1 }
2397 };
2398
2399 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2400         .name           = "mmc4",
2401         .class          = &omap44xx_mmc_hwmod_class,
2402         .clkdm_name     = "l4_per_clkdm",
2403         .mpu_irqs       = omap44xx_mmc4_irqs,
2404         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2405         .main_clk       = "mmc4_fck",
2406         .prcm = {
2407                 .omap4 = {
2408                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2409                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2410                         .modulemode   = MODULEMODE_SWCTRL,
2411                 },
2412         },
2413 };
2414
2415 /* mmc5 */
2416 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2417         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2418         { .irq = -1 }
2419 };
2420
2421 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2422         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2423         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2424         { .dma_req = -1 }
2425 };
2426
2427 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2428         .name           = "mmc5",
2429         .class          = &omap44xx_mmc_hwmod_class,
2430         .clkdm_name     = "l4_per_clkdm",
2431         .mpu_irqs       = omap44xx_mmc5_irqs,
2432         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2433         .main_clk       = "mmc5_fck",
2434         .prcm = {
2435                 .omap4 = {
2436                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2437                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2438                         .modulemode   = MODULEMODE_SWCTRL,
2439                 },
2440         },
2441 };
2442
2443 /*
2444  * 'mpu' class
2445  * mpu sub-system
2446  */
2447
2448 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2449         .name   = "mpu",
2450 };
2451
2452 /* mpu */
2453 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2454         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2455         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2456         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2457         { .irq = -1 }
2458 };
2459
2460 static struct omap_hwmod omap44xx_mpu_hwmod = {
2461         .name           = "mpu",
2462         .class          = &omap44xx_mpu_hwmod_class,
2463         .clkdm_name     = "mpuss_clkdm",
2464         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2465         .mpu_irqs       = omap44xx_mpu_irqs,
2466         .main_clk       = "dpll_mpu_m2_ck",
2467         .prcm = {
2468                 .omap4 = {
2469                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2470                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2471                 },
2472         },
2473 };
2474
2475 /*
2476  * 'ocmc_ram' class
2477  * top-level core on-chip ram
2478  */
2479
2480 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2481         .name   = "ocmc_ram",
2482 };
2483
2484 /* ocmc_ram */
2485 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2486         .name           = "ocmc_ram",
2487         .class          = &omap44xx_ocmc_ram_hwmod_class,
2488         .clkdm_name     = "l3_2_clkdm",
2489         .prcm = {
2490                 .omap4 = {
2491                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2492                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2493                 },
2494         },
2495 };
2496
2497 /*
2498  * 'ocp2scp' class
2499  * bridge to transform ocp interface protocol to scp (serial control port)
2500  * protocol
2501  */
2502
2503 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2504         .name   = "ocp2scp",
2505 };
2506
2507 /* ocp2scp_usb_phy */
2508 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2509         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2510 };
2511
2512 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2513         .name           = "ocp2scp_usb_phy",
2514         .class          = &omap44xx_ocp2scp_hwmod_class,
2515         .clkdm_name     = "l3_init_clkdm",
2516         .prcm = {
2517                 .omap4 = {
2518                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2519                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2520                         .modulemode   = MODULEMODE_HWCTRL,
2521                 },
2522         },
2523         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2524         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2525 };
2526
2527 /*
2528  * 'prcm' class
2529  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2530  * + clock manager 1 (in always on power domain) + local prm in mpu
2531  */
2532
2533 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2534         .name   = "prcm",
2535 };
2536
2537 /* prcm_mpu */
2538 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2539         .name           = "prcm_mpu",
2540         .class          = &omap44xx_prcm_hwmod_class,
2541         .clkdm_name     = "l4_wkup_clkdm",
2542 };
2543
2544 /* cm_core_aon */
2545 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2546         .name           = "cm_core_aon",
2547         .class          = &omap44xx_prcm_hwmod_class,
2548 };
2549
2550 /* cm_core */
2551 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2552         .name           = "cm_core",
2553         .class          = &omap44xx_prcm_hwmod_class,
2554 };
2555
2556 /* prm */
2557 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2558         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2559         { .irq = -1 }
2560 };
2561
2562 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2563         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2564         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2565 };
2566
2567 static struct omap_hwmod omap44xx_prm_hwmod = {
2568         .name           = "prm",
2569         .class          = &omap44xx_prcm_hwmod_class,
2570         .mpu_irqs       = omap44xx_prm_irqs,
2571         .rst_lines      = omap44xx_prm_resets,
2572         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2573 };
2574
2575 /*
2576  * 'scrm' class
2577  * system clock and reset manager
2578  */
2579
2580 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2581         .name   = "scrm",
2582 };
2583
2584 /* scrm */
2585 static struct omap_hwmod omap44xx_scrm_hwmod = {
2586         .name           = "scrm",
2587         .class          = &omap44xx_scrm_hwmod_class,
2588         .clkdm_name     = "l4_wkup_clkdm",
2589 };
2590
2591 /*
2592  * 'sl2if' class
2593  * shared level 2 memory interface
2594  */
2595
2596 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2597         .name   = "sl2if",
2598 };
2599
2600 /* sl2if */
2601 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2602         .name           = "sl2if",
2603         .class          = &omap44xx_sl2if_hwmod_class,
2604         .clkdm_name     = "ivahd_clkdm",
2605         .prcm = {
2606                 .omap4 = {
2607                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2608                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2609                         .modulemode   = MODULEMODE_HWCTRL,
2610                 },
2611         },
2612 };
2613
2614 /*
2615  * 'slimbus' class
2616  * bidirectional, multi-drop, multi-channel two-line serial interface between
2617  * the device and external components
2618  */
2619
2620 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2621         .rev_offs       = 0x0000,
2622         .sysc_offs      = 0x0010,
2623         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2624                            SYSC_HAS_SOFTRESET),
2625         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2626                            SIDLE_SMART_WKUP),
2627         .sysc_fields    = &omap_hwmod_sysc_type2,
2628 };
2629
2630 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2631         .name   = "slimbus",
2632         .sysc   = &omap44xx_slimbus_sysc,
2633 };
2634
2635 /* slimbus1 */
2636 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2637         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2638         { .irq = -1 }
2639 };
2640
2641 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2642         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2643         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2644         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2645         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2646         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2647         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2648         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2649         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2650         { .dma_req = -1 }
2651 };
2652
2653 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2654         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2655         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2656         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2657         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2658 };
2659
2660 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2661         .name           = "slimbus1",
2662         .class          = &omap44xx_slimbus_hwmod_class,
2663         .clkdm_name     = "abe_clkdm",
2664         .mpu_irqs       = omap44xx_slimbus1_irqs,
2665         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2666         .prcm = {
2667                 .omap4 = {
2668                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2669                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2670                         .modulemode   = MODULEMODE_SWCTRL,
2671                 },
2672         },
2673         .opt_clks       = slimbus1_opt_clks,
2674         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2675 };
2676
2677 /* slimbus2 */
2678 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2679         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2680         { .irq = -1 }
2681 };
2682
2683 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2684         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2685         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2686         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2687         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2688         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2689         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2690         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2691         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2692         { .dma_req = -1 }
2693 };
2694
2695 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2696         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2697         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2698         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2699 };
2700
2701 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2702         .name           = "slimbus2",
2703         .class          = &omap44xx_slimbus_hwmod_class,
2704         .clkdm_name     = "l4_per_clkdm",
2705         .mpu_irqs       = omap44xx_slimbus2_irqs,
2706         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2707         .prcm = {
2708                 .omap4 = {
2709                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2710                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2711                         .modulemode   = MODULEMODE_SWCTRL,
2712                 },
2713         },
2714         .opt_clks       = slimbus2_opt_clks,
2715         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2716 };
2717
2718 /*
2719  * 'smartreflex' class
2720  * smartreflex module (monitor silicon performance and outputs a measure of
2721  * performance error)
2722  */
2723
2724 /* The IP is not compliant to type1 / type2 scheme */
2725 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2726         .sidle_shift    = 24,
2727         .enwkup_shift   = 26,
2728 };
2729
2730 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2731         .sysc_offs      = 0x0038,
2732         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2733         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2734                            SIDLE_SMART_WKUP),
2735         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2736 };
2737
2738 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2739         .name   = "smartreflex",
2740         .sysc   = &omap44xx_smartreflex_sysc,
2741         .rev    = 2,
2742 };
2743
2744 /* smartreflex_core */
2745 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2746         .sensor_voltdm_name   = "core",
2747 };
2748
2749 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2750         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2751         { .irq = -1 }
2752 };
2753
2754 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2755         .name           = "smartreflex_core",
2756         .class          = &omap44xx_smartreflex_hwmod_class,
2757         .clkdm_name     = "l4_ao_clkdm",
2758         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2759
2760         .main_clk       = "smartreflex_core_fck",
2761         .prcm = {
2762                 .omap4 = {
2763                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2764                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2765                         .modulemode   = MODULEMODE_SWCTRL,
2766                 },
2767         },
2768         .dev_attr       = &smartreflex_core_dev_attr,
2769 };
2770
2771 /* smartreflex_iva */
2772 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2773         .sensor_voltdm_name     = "iva",
2774 };
2775
2776 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2777         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2778         { .irq = -1 }
2779 };
2780
2781 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2782         .name           = "smartreflex_iva",
2783         .class          = &omap44xx_smartreflex_hwmod_class,
2784         .clkdm_name     = "l4_ao_clkdm",
2785         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2786         .main_clk       = "smartreflex_iva_fck",
2787         .prcm = {
2788                 .omap4 = {
2789                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2790                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2791                         .modulemode   = MODULEMODE_SWCTRL,
2792                 },
2793         },
2794         .dev_attr       = &smartreflex_iva_dev_attr,
2795 };
2796
2797 /* smartreflex_mpu */
2798 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2799         .sensor_voltdm_name     = "mpu",
2800 };
2801
2802 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2803         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2804         { .irq = -1 }
2805 };
2806
2807 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2808         .name           = "smartreflex_mpu",
2809         .class          = &omap44xx_smartreflex_hwmod_class,
2810         .clkdm_name     = "l4_ao_clkdm",
2811         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2812         .main_clk       = "smartreflex_mpu_fck",
2813         .prcm = {
2814                 .omap4 = {
2815                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2816                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2817                         .modulemode   = MODULEMODE_SWCTRL,
2818                 },
2819         },
2820         .dev_attr       = &smartreflex_mpu_dev_attr,
2821 };
2822
2823 /*
2824  * 'spinlock' class
2825  * spinlock provides hardware assistance for synchronizing the processes
2826  * running on multiple processors
2827  */
2828
2829 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2830         .rev_offs       = 0x0000,
2831         .sysc_offs      = 0x0010,
2832         .syss_offs      = 0x0014,
2833         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2834                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2835                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2836         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2837                            SIDLE_SMART_WKUP),
2838         .sysc_fields    = &omap_hwmod_sysc_type1,
2839 };
2840
2841 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2842         .name   = "spinlock",
2843         .sysc   = &omap44xx_spinlock_sysc,
2844 };
2845
2846 /* spinlock */
2847 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2848         .name           = "spinlock",
2849         .class          = &omap44xx_spinlock_hwmod_class,
2850         .clkdm_name     = "l4_cfg_clkdm",
2851         .prcm = {
2852                 .omap4 = {
2853                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2854                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2855                 },
2856         },
2857 };
2858
2859 /*
2860  * 'timer' class
2861  * general purpose timer module with accurate 1ms tick
2862  * This class contains several variants: ['timer_1ms', 'timer']
2863  */
2864
2865 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2866         .rev_offs       = 0x0000,
2867         .sysc_offs      = 0x0010,
2868         .syss_offs      = 0x0014,
2869         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2870                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2871                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2872                            SYSS_HAS_RESET_STATUS),
2873         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2874         .sysc_fields    = &omap_hwmod_sysc_type1,
2875 };
2876
2877 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2878         .name   = "timer",
2879         .sysc   = &omap44xx_timer_1ms_sysc,
2880 };
2881
2882 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2883         .rev_offs       = 0x0000,
2884         .sysc_offs      = 0x0010,
2885         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2886                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2887         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2888                            SIDLE_SMART_WKUP),
2889         .sysc_fields    = &omap_hwmod_sysc_type2,
2890 };
2891
2892 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2893         .name   = "timer",
2894         .sysc   = &omap44xx_timer_sysc,
2895 };
2896
2897 /* always-on timers dev attribute */
2898 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2899         .timer_capability       = OMAP_TIMER_ALWON,
2900 };
2901
2902 /* pwm timers dev attribute */
2903 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2904         .timer_capability       = OMAP_TIMER_HAS_PWM,
2905 };
2906
2907 /* timer1 */
2908 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2909         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2910         { .irq = -1 }
2911 };
2912
2913 static struct omap_hwmod omap44xx_timer1_hwmod = {
2914         .name           = "timer1",
2915         .class          = &omap44xx_timer_1ms_hwmod_class,
2916         .clkdm_name     = "l4_wkup_clkdm",
2917         .mpu_irqs       = omap44xx_timer1_irqs,
2918         .main_clk       = "timer1_fck",
2919         .prcm = {
2920                 .omap4 = {
2921                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2922                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2923                         .modulemode   = MODULEMODE_SWCTRL,
2924                 },
2925         },
2926         .dev_attr       = &capability_alwon_dev_attr,
2927 };
2928
2929 /* timer2 */
2930 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2931         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2932         { .irq = -1 }
2933 };
2934
2935 static struct omap_hwmod omap44xx_timer2_hwmod = {
2936         .name           = "timer2",
2937         .class          = &omap44xx_timer_1ms_hwmod_class,
2938         .clkdm_name     = "l4_per_clkdm",
2939         .mpu_irqs       = omap44xx_timer2_irqs,
2940         .main_clk       = "timer2_fck",
2941         .prcm = {
2942                 .omap4 = {
2943                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2944                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2945                         .modulemode   = MODULEMODE_SWCTRL,
2946                 },
2947         },
2948 };
2949
2950 /* timer3 */
2951 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2952         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2953         { .irq = -1 }
2954 };
2955
2956 static struct omap_hwmod omap44xx_timer3_hwmod = {
2957         .name           = "timer3",
2958         .class          = &omap44xx_timer_hwmod_class,
2959         .clkdm_name     = "l4_per_clkdm",
2960         .mpu_irqs       = omap44xx_timer3_irqs,
2961         .main_clk       = "timer3_fck",
2962         .prcm = {
2963                 .omap4 = {
2964                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2965                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2966                         .modulemode   = MODULEMODE_SWCTRL,
2967                 },
2968         },
2969 };
2970
2971 /* timer4 */
2972 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2973         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2974         { .irq = -1 }
2975 };
2976
2977 static struct omap_hwmod omap44xx_timer4_hwmod = {
2978         .name           = "timer4",
2979         .class          = &omap44xx_timer_hwmod_class,
2980         .clkdm_name     = "l4_per_clkdm",
2981         .mpu_irqs       = omap44xx_timer4_irqs,
2982         .main_clk       = "timer4_fck",
2983         .prcm = {
2984                 .omap4 = {
2985                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2986                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2987                         .modulemode   = MODULEMODE_SWCTRL,
2988                 },
2989         },
2990 };
2991
2992 /* timer5 */
2993 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2994         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2995         { .irq = -1 }
2996 };
2997
2998 static struct omap_hwmod omap44xx_timer5_hwmod = {
2999         .name           = "timer5",
3000         .class          = &omap44xx_timer_hwmod_class,
3001         .clkdm_name     = "abe_clkdm",
3002         .mpu_irqs       = omap44xx_timer5_irqs,
3003         .main_clk       = "timer5_fck",
3004         .prcm = {
3005                 .omap4 = {
3006                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3007                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3008                         .modulemode   = MODULEMODE_SWCTRL,
3009                 },
3010         },
3011 };
3012
3013 /* timer6 */
3014 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3015         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3016         { .irq = -1 }
3017 };
3018
3019 static struct omap_hwmod omap44xx_timer6_hwmod = {
3020         .name           = "timer6",
3021         .class          = &omap44xx_timer_hwmod_class,
3022         .clkdm_name     = "abe_clkdm",
3023         .mpu_irqs       = omap44xx_timer6_irqs,
3024
3025         .main_clk       = "timer6_fck",
3026         .prcm = {
3027                 .omap4 = {
3028                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3029                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3030                         .modulemode   = MODULEMODE_SWCTRL,
3031                 },
3032         },
3033 };
3034
3035 /* timer7 */
3036 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3037         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3038         { .irq = -1 }
3039 };
3040
3041 static struct omap_hwmod omap44xx_timer7_hwmod = {
3042         .name           = "timer7",
3043         .class          = &omap44xx_timer_hwmod_class,
3044         .clkdm_name     = "abe_clkdm",
3045         .mpu_irqs       = omap44xx_timer7_irqs,
3046         .main_clk       = "timer7_fck",
3047         .prcm = {
3048                 .omap4 = {
3049                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3050                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3051                         .modulemode   = MODULEMODE_SWCTRL,
3052                 },
3053         },
3054 };
3055
3056 /* timer8 */
3057 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3058         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3059         { .irq = -1 }
3060 };
3061
3062 static struct omap_hwmod omap44xx_timer8_hwmod = {
3063         .name           = "timer8",
3064         .class          = &omap44xx_timer_hwmod_class,
3065         .clkdm_name     = "abe_clkdm",
3066         .mpu_irqs       = omap44xx_timer8_irqs,
3067         .main_clk       = "timer8_fck",
3068         .prcm = {
3069                 .omap4 = {
3070                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3071                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3072                         .modulemode   = MODULEMODE_SWCTRL,
3073                 },
3074         },
3075         .dev_attr       = &capability_pwm_dev_attr,
3076 };
3077
3078 /* timer9 */
3079 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3080         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3081         { .irq = -1 }
3082 };
3083
3084 static struct omap_hwmod omap44xx_timer9_hwmod = {
3085         .name           = "timer9",
3086         .class          = &omap44xx_timer_hwmod_class,
3087         .clkdm_name     = "l4_per_clkdm",
3088         .mpu_irqs       = omap44xx_timer9_irqs,
3089         .main_clk       = "timer9_fck",
3090         .prcm = {
3091                 .omap4 = {
3092                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3093                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3094                         .modulemode   = MODULEMODE_SWCTRL,
3095                 },
3096         },
3097         .dev_attr       = &capability_pwm_dev_attr,
3098 };
3099
3100 /* timer10 */
3101 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3102         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3103         { .irq = -1 }
3104 };
3105
3106 static struct omap_hwmod omap44xx_timer10_hwmod = {
3107         .name           = "timer10",
3108         .class          = &omap44xx_timer_1ms_hwmod_class,
3109         .clkdm_name     = "l4_per_clkdm",
3110         .mpu_irqs       = omap44xx_timer10_irqs,
3111         .main_clk       = "timer10_fck",
3112         .prcm = {
3113                 .omap4 = {
3114                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3115                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3116                         .modulemode   = MODULEMODE_SWCTRL,
3117                 },
3118         },
3119         .dev_attr       = &capability_pwm_dev_attr,
3120 };
3121
3122 /* timer11 */
3123 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3124         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3125         { .irq = -1 }
3126 };
3127
3128 static struct omap_hwmod omap44xx_timer11_hwmod = {
3129         .name           = "timer11",
3130         .class          = &omap44xx_timer_hwmod_class,
3131         .clkdm_name     = "l4_per_clkdm",
3132         .mpu_irqs       = omap44xx_timer11_irqs,
3133         .main_clk       = "timer11_fck",
3134         .prcm = {
3135                 .omap4 = {
3136                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3137                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3138                         .modulemode   = MODULEMODE_SWCTRL,
3139                 },
3140         },
3141         .dev_attr       = &capability_pwm_dev_attr,
3142 };
3143
3144 /*
3145  * 'uart' class
3146  * universal asynchronous receiver/transmitter (uart)
3147  */
3148
3149 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3150         .rev_offs       = 0x0050,
3151         .sysc_offs      = 0x0054,
3152         .syss_offs      = 0x0058,
3153         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3154                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3155                            SYSS_HAS_RESET_STATUS),
3156         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3157                            SIDLE_SMART_WKUP),
3158         .sysc_fields    = &omap_hwmod_sysc_type1,
3159 };
3160
3161 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3162         .name   = "uart",
3163         .sysc   = &omap44xx_uart_sysc,
3164 };
3165
3166 /* uart1 */
3167 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3168         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3169         { .irq = -1 }
3170 };
3171
3172 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3173         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3174         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3175         { .dma_req = -1 }
3176 };
3177
3178 static struct omap_hwmod omap44xx_uart1_hwmod = {
3179         .name           = "uart1",
3180         .class          = &omap44xx_uart_hwmod_class,
3181         .clkdm_name     = "l4_per_clkdm",
3182         .mpu_irqs       = omap44xx_uart1_irqs,
3183         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3184         .main_clk       = "uart1_fck",
3185         .prcm = {
3186                 .omap4 = {
3187                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3188                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3189                         .modulemode   = MODULEMODE_SWCTRL,
3190                 },
3191         },
3192 };
3193
3194 /* uart2 */
3195 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3196         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3197         { .irq = -1 }
3198 };
3199
3200 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3201         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3202         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3203         { .dma_req = -1 }
3204 };
3205
3206 static struct omap_hwmod omap44xx_uart2_hwmod = {
3207         .name           = "uart2",
3208         .class          = &omap44xx_uart_hwmod_class,
3209         .clkdm_name     = "l4_per_clkdm",
3210         .mpu_irqs       = omap44xx_uart2_irqs,
3211         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3212         .main_clk       = "uart2_fck",
3213         .prcm = {
3214                 .omap4 = {
3215                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3216                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3217                         .modulemode   = MODULEMODE_SWCTRL,
3218                 },
3219         },
3220 };
3221
3222 /* uart3 */
3223 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3224         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3225         { .irq = -1 }
3226 };
3227
3228 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3229         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3230         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3231         { .dma_req = -1 }
3232 };
3233
3234 static struct omap_hwmod omap44xx_uart3_hwmod = {
3235         .name           = "uart3",
3236         .class          = &omap44xx_uart_hwmod_class,
3237         .clkdm_name     = "l4_per_clkdm",
3238         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3239         .mpu_irqs       = omap44xx_uart3_irqs,
3240         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3241         .main_clk       = "uart3_fck",
3242         .prcm = {
3243                 .omap4 = {
3244                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3245                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3246                         .modulemode   = MODULEMODE_SWCTRL,
3247                 },
3248         },
3249 };
3250
3251 /* uart4 */
3252 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3253         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3254         { .irq = -1 }
3255 };
3256
3257 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3258         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3259         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3260         { .dma_req = -1 }
3261 };
3262
3263 static struct omap_hwmod omap44xx_uart4_hwmod = {
3264         .name           = "uart4",
3265         .class          = &omap44xx_uart_hwmod_class,
3266         .clkdm_name     = "l4_per_clkdm",
3267         .mpu_irqs       = omap44xx_uart4_irqs,
3268         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3269         .main_clk       = "uart4_fck",
3270         .prcm = {
3271                 .omap4 = {
3272                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3273                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3274                         .modulemode   = MODULEMODE_SWCTRL,
3275                 },
3276         },
3277 };
3278
3279 /*
3280  * 'usb_host_fs' class
3281  * full-speed usb host controller
3282  */
3283
3284 /* The IP is not compliant to type1 / type2 scheme */
3285 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3286         .midle_shift    = 4,
3287         .sidle_shift    = 2,
3288         .srst_shift     = 1,
3289 };
3290
3291 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3292         .rev_offs       = 0x0000,
3293         .sysc_offs      = 0x0210,
3294         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3295                            SYSC_HAS_SOFTRESET),
3296         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3297                            SIDLE_SMART_WKUP),
3298         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3299 };
3300
3301 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3302         .name   = "usb_host_fs",
3303         .sysc   = &omap44xx_usb_host_fs_sysc,
3304 };
3305
3306 /* usb_host_fs */
3307 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3308         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3309         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3310         { .irq = -1 }
3311 };
3312
3313 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3314         .name           = "usb_host_fs",
3315         .class          = &omap44xx_usb_host_fs_hwmod_class,
3316         .clkdm_name     = "l3_init_clkdm",
3317         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3318         .main_clk       = "usb_host_fs_fck",
3319         .prcm = {
3320                 .omap4 = {
3321                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3322                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3323                         .modulemode   = MODULEMODE_SWCTRL,
3324                 },
3325         },
3326 };
3327
3328 /*
3329  * 'usb_host_hs' class
3330  * high-speed multi-port usb host controller
3331  */
3332
3333 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3334         .rev_offs       = 0x0000,
3335         .sysc_offs      = 0x0010,
3336         .syss_offs      = 0x0014,
3337         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3338                            SYSC_HAS_SOFTRESET),
3339         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3340                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3341                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3342         .sysc_fields    = &omap_hwmod_sysc_type2,
3343 };
3344
3345 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3346         .name   = "usb_host_hs",
3347         .sysc   = &omap44xx_usb_host_hs_sysc,
3348 };
3349
3350 /* usb_host_hs */
3351 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3352         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3353         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3354         { .irq = -1 }
3355 };
3356
3357 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3358         .name           = "usb_host_hs",
3359         .class          = &omap44xx_usb_host_hs_hwmod_class,
3360         .clkdm_name     = "l3_init_clkdm",
3361         .main_clk       = "usb_host_hs_fck",
3362         .prcm = {
3363                 .omap4 = {
3364                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3365                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3366                         .modulemode   = MODULEMODE_SWCTRL,
3367                 },
3368         },
3369         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3370
3371         /*
3372          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3373          * id: i660
3374          *
3375          * Description:
3376          * In the following configuration :
3377          * - USBHOST module is set to smart-idle mode
3378          * - PRCM asserts idle_req to the USBHOST module ( This typically
3379          *   happens when the system is going to a low power mode : all ports
3380          *   have been suspended, the master part of the USBHOST module has
3381          *   entered the standby state, and SW has cut the functional clocks)
3382          * - an USBHOST interrupt occurs before the module is able to answer
3383          *   idle_ack, typically a remote wakeup IRQ.
3384          * Then the USB HOST module will enter a deadlock situation where it
3385          * is no more accessible nor functional.
3386          *
3387          * Workaround:
3388          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3389          */
3390
3391         /*
3392          * Errata: USB host EHCI may stall when entering smart-standby mode
3393          * Id: i571
3394          *
3395          * Description:
3396          * When the USBHOST module is set to smart-standby mode, and when it is
3397          * ready to enter the standby state (i.e. all ports are suspended and
3398          * all attached devices are in suspend mode), then it can wrongly assert
3399          * the Mstandby signal too early while there are still some residual OCP
3400          * transactions ongoing. If this condition occurs, the internal state
3401          * machine may go to an undefined state and the USB link may be stuck
3402          * upon the next resume.
3403          *
3404          * Workaround:
3405          * Don't use smart standby; use only force standby,
3406          * hence HWMOD_SWSUP_MSTANDBY
3407          */
3408
3409         /*
3410          * During system boot; If the hwmod framework resets the module
3411          * the module will have smart idle settings; which can lead to deadlock
3412          * (above Errata Id:i660); so, dont reset the module during boot;
3413          * Use HWMOD_INIT_NO_RESET.
3414          */
3415
3416         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3417                           HWMOD_INIT_NO_RESET,
3418 };
3419
3420 /*
3421  * 'usb_otg_hs' class
3422  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3423  */
3424
3425 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3426         .rev_offs       = 0x0400,
3427         .sysc_offs      = 0x0404,
3428         .syss_offs      = 0x0408,
3429         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3430                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3431                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3432         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3433                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3434                            MSTANDBY_SMART),
3435         .sysc_fields    = &omap_hwmod_sysc_type1,
3436 };
3437
3438 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3439         .name   = "usb_otg_hs",
3440         .sysc   = &omap44xx_usb_otg_hs_sysc,
3441 };
3442
3443 /* usb_otg_hs */
3444 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3445         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3446         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3447         { .irq = -1 }
3448 };
3449
3450 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3451         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3452 };
3453
3454 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3455         .name           = "usb_otg_hs",
3456         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3457         .clkdm_name     = "l3_init_clkdm",
3458         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3459         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3460         .main_clk       = "usb_otg_hs_ick",
3461         .prcm = {
3462                 .omap4 = {
3463                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3464                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3465                         .modulemode   = MODULEMODE_HWCTRL,
3466                 },
3467         },
3468         .opt_clks       = usb_otg_hs_opt_clks,
3469         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3470 };
3471
3472 /*
3473  * 'usb_tll_hs' class
3474  * usb_tll_hs module is the adapter on the usb_host_hs ports
3475  */
3476
3477 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3478         .rev_offs       = 0x0000,
3479         .sysc_offs      = 0x0010,
3480         .syss_offs      = 0x0014,
3481         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3482                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3483                            SYSC_HAS_AUTOIDLE),
3484         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3485         .sysc_fields    = &omap_hwmod_sysc_type1,
3486 };
3487
3488 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3489         .name   = "usb_tll_hs",
3490         .sysc   = &omap44xx_usb_tll_hs_sysc,
3491 };
3492
3493 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3494         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3495         { .irq = -1 }
3496 };
3497
3498 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3499         .name           = "usb_tll_hs",
3500         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3501         .clkdm_name     = "l3_init_clkdm",
3502         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3503         .main_clk       = "usb_tll_hs_ick",
3504         .prcm = {
3505                 .omap4 = {
3506                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3507                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3508                         .modulemode   = MODULEMODE_HWCTRL,
3509                 },
3510         },
3511 };
3512
3513 /*
3514  * 'wd_timer' class
3515  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3516  * overflow condition
3517  */
3518
3519 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3520         .rev_offs       = 0x0000,
3521         .sysc_offs      = 0x0010,
3522         .syss_offs      = 0x0014,
3523         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3524                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3525         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3526                            SIDLE_SMART_WKUP),
3527         .sysc_fields    = &omap_hwmod_sysc_type1,
3528 };
3529
3530 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3531         .name           = "wd_timer",
3532         .sysc           = &omap44xx_wd_timer_sysc,
3533         .pre_shutdown   = &omap2_wd_timer_disable,
3534         .reset          = &omap2_wd_timer_reset,
3535 };
3536
3537 /* wd_timer2 */
3538 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3539         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3540         { .irq = -1 }
3541 };
3542
3543 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3544         .name           = "wd_timer2",
3545         .class          = &omap44xx_wd_timer_hwmod_class,
3546         .clkdm_name     = "l4_wkup_clkdm",
3547         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3548         .main_clk       = "wd_timer2_fck",
3549         .prcm = {
3550                 .omap4 = {
3551                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3552                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3553                         .modulemode   = MODULEMODE_SWCTRL,
3554                 },
3555         },
3556 };
3557
3558 /* wd_timer3 */
3559 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3560         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3561         { .irq = -1 }
3562 };
3563
3564 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3565         .name           = "wd_timer3",
3566         .class          = &omap44xx_wd_timer_hwmod_class,
3567         .clkdm_name     = "abe_clkdm",
3568         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3569         .main_clk       = "wd_timer3_fck",
3570         .prcm = {
3571                 .omap4 = {
3572                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3573                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3574                         .modulemode   = MODULEMODE_SWCTRL,
3575                 },
3576         },
3577 };
3578
3579
3580 /*
3581  * interfaces
3582  */
3583
3584 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3585         {
3586                 .pa_start       = 0x4a204000,
3587                 .pa_end         = 0x4a2040ff,
3588                 .flags          = ADDR_TYPE_RT
3589         },
3590         { }
3591 };
3592
3593 /* c2c -> c2c_target_fw */
3594 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3595         .master         = &omap44xx_c2c_hwmod,
3596         .slave          = &omap44xx_c2c_target_fw_hwmod,
3597         .clk            = "div_core_ck",
3598         .addr           = omap44xx_c2c_target_fw_addrs,
3599         .user           = OCP_USER_MPU,
3600 };
3601
3602 /* l4_cfg -> c2c_target_fw */
3603 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3604         .master         = &omap44xx_l4_cfg_hwmod,
3605         .slave          = &omap44xx_c2c_target_fw_hwmod,
3606         .clk            = "l4_div_ck",
3607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3608 };
3609
3610 /* l3_main_1 -> dmm */
3611 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3612         .master         = &omap44xx_l3_main_1_hwmod,
3613         .slave          = &omap44xx_dmm_hwmod,
3614         .clk            = "l3_div_ck",
3615         .user           = OCP_USER_SDMA,
3616 };
3617
3618 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3619         {
3620                 .pa_start       = 0x4e000000,
3621                 .pa_end         = 0x4e0007ff,
3622                 .flags          = ADDR_TYPE_RT
3623         },
3624         { }
3625 };
3626
3627 /* mpu -> dmm */
3628 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3629         .master         = &omap44xx_mpu_hwmod,
3630         .slave          = &omap44xx_dmm_hwmod,
3631         .clk            = "l3_div_ck",
3632         .addr           = omap44xx_dmm_addrs,
3633         .user           = OCP_USER_MPU,
3634 };
3635
3636 /* c2c -> emif_fw */
3637 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3638         .master         = &omap44xx_c2c_hwmod,
3639         .slave          = &omap44xx_emif_fw_hwmod,
3640         .clk            = "div_core_ck",
3641         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3642 };
3643
3644 /* dmm -> emif_fw */
3645 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3646         .master         = &omap44xx_dmm_hwmod,
3647         .slave          = &omap44xx_emif_fw_hwmod,
3648         .clk            = "l3_div_ck",
3649         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3650 };
3651
3652 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3653         {
3654                 .pa_start       = 0x4a20c000,
3655                 .pa_end         = 0x4a20c0ff,
3656                 .flags          = ADDR_TYPE_RT
3657         },
3658         { }
3659 };
3660
3661 /* l4_cfg -> emif_fw */
3662 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3663         .master         = &omap44xx_l4_cfg_hwmod,
3664         .slave          = &omap44xx_emif_fw_hwmod,
3665         .clk            = "l4_div_ck",
3666         .addr           = omap44xx_emif_fw_addrs,
3667         .user           = OCP_USER_MPU,
3668 };
3669
3670 /* iva -> l3_instr */
3671 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3672         .master         = &omap44xx_iva_hwmod,
3673         .slave          = &omap44xx_l3_instr_hwmod,
3674         .clk            = "l3_div_ck",
3675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3676 };
3677
3678 /* l3_main_3 -> l3_instr */
3679 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3680         .master         = &omap44xx_l3_main_3_hwmod,
3681         .slave          = &omap44xx_l3_instr_hwmod,
3682         .clk            = "l3_div_ck",
3683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3684 };
3685
3686 /* ocp_wp_noc -> l3_instr */
3687 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3688         .master         = &omap44xx_ocp_wp_noc_hwmod,
3689         .slave          = &omap44xx_l3_instr_hwmod,
3690         .clk            = "l3_div_ck",
3691         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3692 };
3693
3694 /* dsp -> l3_main_1 */
3695 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3696         .master         = &omap44xx_dsp_hwmod,
3697         .slave          = &omap44xx_l3_main_1_hwmod,
3698         .clk            = "l3_div_ck",
3699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3700 };
3701
3702 /* dss -> l3_main_1 */
3703 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3704         .master         = &omap44xx_dss_hwmod,
3705         .slave          = &omap44xx_l3_main_1_hwmod,
3706         .clk            = "l3_div_ck",
3707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3708 };
3709
3710 /* l3_main_2 -> l3_main_1 */
3711 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3712         .master         = &omap44xx_l3_main_2_hwmod,
3713         .slave          = &omap44xx_l3_main_1_hwmod,
3714         .clk            = "l3_div_ck",
3715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3716 };
3717
3718 /* l4_cfg -> l3_main_1 */
3719 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3720         .master         = &omap44xx_l4_cfg_hwmod,
3721         .slave          = &omap44xx_l3_main_1_hwmod,
3722         .clk            = "l4_div_ck",
3723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3724 };
3725
3726 /* mmc1 -> l3_main_1 */
3727 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3728         .master         = &omap44xx_mmc1_hwmod,
3729         .slave          = &omap44xx_l3_main_1_hwmod,
3730         .clk            = "l3_div_ck",
3731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3732 };
3733
3734 /* mmc2 -> l3_main_1 */
3735 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3736         .master         = &omap44xx_mmc2_hwmod,
3737         .slave          = &omap44xx_l3_main_1_hwmod,
3738         .clk            = "l3_div_ck",
3739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3740 };
3741
3742 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3743         {
3744                 .pa_start       = 0x44000000,
3745                 .pa_end         = 0x44000fff,
3746                 .flags          = ADDR_TYPE_RT
3747         },
3748         { }
3749 };
3750
3751 /* mpu -> l3_main_1 */
3752 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3753         .master         = &omap44xx_mpu_hwmod,
3754         .slave          = &omap44xx_l3_main_1_hwmod,
3755         .clk            = "l3_div_ck",
3756         .addr           = omap44xx_l3_main_1_addrs,
3757         .user           = OCP_USER_MPU,
3758 };
3759
3760 /* c2c_target_fw -> l3_main_2 */
3761 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3762         .master         = &omap44xx_c2c_target_fw_hwmod,
3763         .slave          = &omap44xx_l3_main_2_hwmod,
3764         .clk            = "l3_div_ck",
3765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3766 };
3767
3768 /* debugss -> l3_main_2 */
3769 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3770         .master         = &omap44xx_debugss_hwmod,
3771         .slave          = &omap44xx_l3_main_2_hwmod,
3772         .clk            = "dbgclk_mux_ck",
3773         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3774 };
3775
3776 /* dma_system -> l3_main_2 */
3777 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3778         .master         = &omap44xx_dma_system_hwmod,
3779         .slave          = &omap44xx_l3_main_2_hwmod,
3780         .clk            = "l3_div_ck",
3781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3782 };
3783
3784 /* fdif -> l3_main_2 */
3785 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3786         .master         = &omap44xx_fdif_hwmod,
3787         .slave          = &omap44xx_l3_main_2_hwmod,
3788         .clk            = "l3_div_ck",
3789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3790 };
3791
3792 /* gpu -> l3_main_2 */
3793 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3794         .master         = &omap44xx_gpu_hwmod,
3795         .slave          = &omap44xx_l3_main_2_hwmod,
3796         .clk            = "l3_div_ck",
3797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3798 };
3799
3800 /* hsi -> l3_main_2 */
3801 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3802         .master         = &omap44xx_hsi_hwmod,
3803         .slave          = &omap44xx_l3_main_2_hwmod,
3804         .clk            = "l3_div_ck",
3805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3806 };
3807
3808 /* ipu -> l3_main_2 */
3809 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3810         .master         = &omap44xx_ipu_hwmod,
3811         .slave          = &omap44xx_l3_main_2_hwmod,
3812         .clk            = "l3_div_ck",
3813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3814 };
3815
3816 /* iss -> l3_main_2 */
3817 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3818         .master         = &omap44xx_iss_hwmod,
3819         .slave          = &omap44xx_l3_main_2_hwmod,
3820         .clk            = "l3_div_ck",
3821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3822 };
3823
3824 /* iva -> l3_main_2 */
3825 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3826         .master         = &omap44xx_iva_hwmod,
3827         .slave          = &omap44xx_l3_main_2_hwmod,
3828         .clk            = "l3_div_ck",
3829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3830 };
3831
3832 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3833         {
3834                 .pa_start       = 0x44800000,
3835                 .pa_end         = 0x44801fff,
3836                 .flags          = ADDR_TYPE_RT
3837         },
3838         { }
3839 };
3840
3841 /* l3_main_1 -> l3_main_2 */
3842 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3843         .master         = &omap44xx_l3_main_1_hwmod,
3844         .slave          = &omap44xx_l3_main_2_hwmod,
3845         .clk            = "l3_div_ck",
3846         .addr           = omap44xx_l3_main_2_addrs,
3847         .user           = OCP_USER_MPU,
3848 };
3849
3850 /* l4_cfg -> l3_main_2 */
3851 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3852         .master         = &omap44xx_l4_cfg_hwmod,
3853         .slave          = &omap44xx_l3_main_2_hwmod,
3854         .clk            = "l4_div_ck",
3855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3856 };
3857
3858 /* usb_host_fs -> l3_main_2 */
3859 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3860         .master         = &omap44xx_usb_host_fs_hwmod,
3861         .slave          = &omap44xx_l3_main_2_hwmod,
3862         .clk            = "l3_div_ck",
3863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3864 };
3865
3866 /* usb_host_hs -> l3_main_2 */
3867 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3868         .master         = &omap44xx_usb_host_hs_hwmod,
3869         .slave          = &omap44xx_l3_main_2_hwmod,
3870         .clk            = "l3_div_ck",
3871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3872 };
3873
3874 /* usb_otg_hs -> l3_main_2 */
3875 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3876         .master         = &omap44xx_usb_otg_hs_hwmod,
3877         .slave          = &omap44xx_l3_main_2_hwmod,
3878         .clk            = "l3_div_ck",
3879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3880 };
3881
3882 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3883         {
3884                 .pa_start       = 0x45000000,
3885                 .pa_end         = 0x45000fff,
3886                 .flags          = ADDR_TYPE_RT
3887         },
3888         { }
3889 };
3890
3891 /* l3_main_1 -> l3_main_3 */
3892 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3893         .master         = &omap44xx_l3_main_1_hwmod,
3894         .slave          = &omap44xx_l3_main_3_hwmod,
3895         .clk            = "l3_div_ck",
3896         .addr           = omap44xx_l3_main_3_addrs,
3897         .user           = OCP_USER_MPU,
3898 };
3899
3900 /* l3_main_2 -> l3_main_3 */
3901 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3902         .master         = &omap44xx_l3_main_2_hwmod,
3903         .slave          = &omap44xx_l3_main_3_hwmod,
3904         .clk            = "l3_div_ck",
3905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3906 };
3907
3908 /* l4_cfg -> l3_main_3 */
3909 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3910         .master         = &omap44xx_l4_cfg_hwmod,
3911         .slave          = &omap44xx_l3_main_3_hwmod,
3912         .clk            = "l4_div_ck",
3913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3914 };
3915
3916 /* aess -> l4_abe */
3917 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3918         .master         = &omap44xx_aess_hwmod,
3919         .slave          = &omap44xx_l4_abe_hwmod,
3920         .clk            = "ocp_abe_iclk",
3921         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3922 };
3923
3924 /* dsp -> l4_abe */
3925 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3926         .master         = &omap44xx_dsp_hwmod,
3927         .slave          = &omap44xx_l4_abe_hwmod,
3928         .clk            = "ocp_abe_iclk",
3929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3930 };
3931
3932 /* l3_main_1 -> l4_abe */
3933 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3934         .master         = &omap44xx_l3_main_1_hwmod,
3935         .slave          = &omap44xx_l4_abe_hwmod,
3936         .clk            = "l3_div_ck",
3937         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3938 };
3939
3940 /* mpu -> l4_abe */
3941 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3942         .master         = &omap44xx_mpu_hwmod,
3943         .slave          = &omap44xx_l4_abe_hwmod,
3944         .clk            = "ocp_abe_iclk",
3945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3946 };
3947
3948 /* l3_main_1 -> l4_cfg */
3949 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3950         .master         = &omap44xx_l3_main_1_hwmod,
3951         .slave          = &omap44xx_l4_cfg_hwmod,
3952         .clk            = "l3_div_ck",
3953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3954 };
3955
3956 /* l3_main_2 -> l4_per */
3957 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3958         .master         = &omap44xx_l3_main_2_hwmod,
3959         .slave          = &omap44xx_l4_per_hwmod,
3960         .clk            = "l3_div_ck",
3961         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3962 };
3963
3964 /* l4_cfg -> l4_wkup */
3965 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3966         .master         = &omap44xx_l4_cfg_hwmod,
3967         .slave          = &omap44xx_l4_wkup_hwmod,
3968         .clk            = "l4_div_ck",
3969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3970 };
3971
3972 /* mpu -> mpu_private */
3973 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3974         .master         = &omap44xx_mpu_hwmod,
3975         .slave          = &omap44xx_mpu_private_hwmod,
3976         .clk            = "l3_div_ck",
3977         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3978 };
3979
3980 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3981         {
3982                 .pa_start       = 0x4a102000,
3983                 .pa_end         = 0x4a10207f,
3984                 .flags          = ADDR_TYPE_RT
3985         },
3986         { }
3987 };
3988
3989 /* l4_cfg -> ocp_wp_noc */
3990 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3991         .master         = &omap44xx_l4_cfg_hwmod,
3992         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3993         .clk            = "l4_div_ck",
3994         .addr           = omap44xx_ocp_wp_noc_addrs,
3995         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3996 };
3997
3998 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3999         {
4000                 .pa_start       = 0x401f1000,
4001                 .pa_end         = 0x401f13ff,
4002                 .flags          = ADDR_TYPE_RT
4003         },
4004         { }
4005 };
4006
4007 /* l4_abe -> aess */
4008 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4009         .master         = &omap44xx_l4_abe_hwmod,
4010         .slave          = &omap44xx_aess_hwmod,
4011         .clk            = "ocp_abe_iclk",
4012         .addr           = omap44xx_aess_addrs,
4013         .user           = OCP_USER_MPU,
4014 };
4015
4016 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4017         {
4018                 .pa_start       = 0x490f1000,
4019                 .pa_end         = 0x490f13ff,
4020                 .flags          = ADDR_TYPE_RT
4021         },
4022         { }
4023 };
4024
4025 /* l4_abe -> aess (dma) */
4026 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4027         .master         = &omap44xx_l4_abe_hwmod,
4028         .slave          = &omap44xx_aess_hwmod,
4029         .clk            = "ocp_abe_iclk",
4030         .addr           = omap44xx_aess_dma_addrs,
4031         .user           = OCP_USER_SDMA,
4032 };
4033
4034 /* l3_main_2 -> c2c */
4035 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4036         .master         = &omap44xx_l3_main_2_hwmod,
4037         .slave          = &omap44xx_c2c_hwmod,
4038         .clk            = "l3_div_ck",
4039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4040 };
4041
4042 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4043         {
4044                 .pa_start       = 0x4a304000,
4045                 .pa_end         = 0x4a30401f,
4046                 .flags          = ADDR_TYPE_RT
4047         },
4048         { }
4049 };
4050
4051 /* l4_wkup -> counter_32k */
4052 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4053         .master         = &omap44xx_l4_wkup_hwmod,
4054         .slave          = &omap44xx_counter_32k_hwmod,
4055         .clk            = "l4_wkup_clk_mux_ck",
4056         .addr           = omap44xx_counter_32k_addrs,
4057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4058 };
4059
4060 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4061         {
4062                 .pa_start       = 0x4a002000,
4063                 .pa_end         = 0x4a0027ff,
4064                 .flags          = ADDR_TYPE_RT
4065         },
4066         { }
4067 };
4068
4069 /* l4_cfg -> ctrl_module_core */
4070 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4071         .master         = &omap44xx_l4_cfg_hwmod,
4072         .slave          = &omap44xx_ctrl_module_core_hwmod,
4073         .clk            = "l4_div_ck",
4074         .addr           = omap44xx_ctrl_module_core_addrs,
4075         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4076 };
4077
4078 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4079         {
4080                 .pa_start       = 0x4a100000,
4081                 .pa_end         = 0x4a1007ff,
4082                 .flags          = ADDR_TYPE_RT
4083         },
4084         { }
4085 };
4086
4087 /* l4_cfg -> ctrl_module_pad_core */
4088 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4089         .master         = &omap44xx_l4_cfg_hwmod,
4090         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4091         .clk            = "l4_div_ck",
4092         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4093         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4094 };
4095
4096 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4097         {
4098                 .pa_start       = 0x4a30c000,
4099                 .pa_end         = 0x4a30c7ff,
4100                 .flags          = ADDR_TYPE_RT
4101         },
4102         { }
4103 };
4104
4105 /* l4_wkup -> ctrl_module_wkup */
4106 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4107         .master         = &omap44xx_l4_wkup_hwmod,
4108         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4109         .clk            = "l4_wkup_clk_mux_ck",
4110         .addr           = omap44xx_ctrl_module_wkup_addrs,
4111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4112 };
4113
4114 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4115         {
4116                 .pa_start       = 0x4a31e000,
4117                 .pa_end         = 0x4a31e7ff,
4118                 .flags          = ADDR_TYPE_RT
4119         },
4120         { }
4121 };
4122
4123 /* l4_wkup -> ctrl_module_pad_wkup */
4124 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4125         .master         = &omap44xx_l4_wkup_hwmod,
4126         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4127         .clk            = "l4_wkup_clk_mux_ck",
4128         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4131
4132 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4133         {
4134                 .pa_start       = 0x54160000,
4135                 .pa_end         = 0x54167fff,
4136                 .flags          = ADDR_TYPE_RT
4137         },
4138         { }
4139 };
4140
4141 /* l3_instr -> debugss */
4142 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4143         .master         = &omap44xx_l3_instr_hwmod,
4144         .slave          = &omap44xx_debugss_hwmod,
4145         .clk            = "l3_div_ck",
4146         .addr           = omap44xx_debugss_addrs,
4147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4148 };
4149
4150 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4151         {
4152                 .pa_start       = 0x4a056000,
4153                 .pa_end         = 0x4a056fff,
4154                 .flags          = ADDR_TYPE_RT
4155         },
4156         { }
4157 };
4158
4159 /* l4_cfg -> dma_system */
4160 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4161         .master         = &omap44xx_l4_cfg_hwmod,
4162         .slave          = &omap44xx_dma_system_hwmod,
4163         .clk            = "l4_div_ck",
4164         .addr           = omap44xx_dma_system_addrs,
4165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4166 };
4167
4168 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4169         {
4170                 .name           = "mpu",
4171                 .pa_start       = 0x4012e000,
4172                 .pa_end         = 0x4012e07f,
4173                 .flags          = ADDR_TYPE_RT
4174         },
4175         { }
4176 };
4177
4178 /* l4_abe -> dmic */
4179 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4180         .master         = &omap44xx_l4_abe_hwmod,
4181         .slave          = &omap44xx_dmic_hwmod,
4182         .clk            = "ocp_abe_iclk",
4183         .addr           = omap44xx_dmic_addrs,
4184         .user           = OCP_USER_MPU,
4185 };
4186
4187 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4188         {
4189                 .name           = "dma",
4190                 .pa_start       = 0x4902e000,
4191                 .pa_end         = 0x4902e07f,
4192                 .flags          = ADDR_TYPE_RT
4193         },
4194         { }
4195 };
4196
4197 /* l4_abe -> dmic (dma) */
4198 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4199         .master         = &omap44xx_l4_abe_hwmod,
4200         .slave          = &omap44xx_dmic_hwmod,
4201         .clk            = "ocp_abe_iclk",
4202         .addr           = omap44xx_dmic_dma_addrs,
4203         .user           = OCP_USER_SDMA,
4204 };
4205
4206 /* dsp -> iva */
4207 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4208         .master         = &omap44xx_dsp_hwmod,
4209         .slave          = &omap44xx_iva_hwmod,
4210         .clk            = "dpll_iva_m5x2_ck",
4211         .user           = OCP_USER_DSP,
4212 };
4213
4214 /* dsp -> sl2if */
4215 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4216         .master         = &omap44xx_dsp_hwmod,
4217         .slave          = &omap44xx_sl2if_hwmod,
4218         .clk            = "dpll_iva_m5x2_ck",
4219         .user           = OCP_USER_DSP,
4220 };
4221
4222 /* l4_cfg -> dsp */
4223 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4224         .master         = &omap44xx_l4_cfg_hwmod,
4225         .slave          = &omap44xx_dsp_hwmod,
4226         .clk            = "l4_div_ck",
4227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4228 };
4229
4230 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4231         {
4232                 .pa_start       = 0x58000000,
4233                 .pa_end         = 0x5800007f,
4234                 .flags          = ADDR_TYPE_RT
4235         },
4236         { }
4237 };
4238
4239 /* l3_main_2 -> dss */
4240 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4241         .master         = &omap44xx_l3_main_2_hwmod,
4242         .slave          = &omap44xx_dss_hwmod,
4243         .clk            = "dss_fck",
4244         .addr           = omap44xx_dss_dma_addrs,
4245         .user           = OCP_USER_SDMA,
4246 };
4247
4248 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4249         {
4250                 .pa_start       = 0x48040000,
4251                 .pa_end         = 0x4804007f,
4252                 .flags          = ADDR_TYPE_RT
4253         },
4254         { }
4255 };
4256
4257 /* l4_per -> dss */
4258 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4259         .master         = &omap44xx_l4_per_hwmod,
4260         .slave          = &omap44xx_dss_hwmod,
4261         .clk            = "l4_div_ck",
4262         .addr           = omap44xx_dss_addrs,
4263         .user           = OCP_USER_MPU,
4264 };
4265
4266 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4267         {
4268                 .pa_start       = 0x58001000,
4269                 .pa_end         = 0x58001fff,
4270                 .flags          = ADDR_TYPE_RT
4271         },
4272         { }
4273 };
4274
4275 /* l3_main_2 -> dss_dispc */
4276 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4277         .master         = &omap44xx_l3_main_2_hwmod,
4278         .slave          = &omap44xx_dss_dispc_hwmod,
4279         .clk            = "dss_fck",
4280         .addr           = omap44xx_dss_dispc_dma_addrs,
4281         .user           = OCP_USER_SDMA,
4282 };
4283
4284 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4285         {
4286                 .pa_start       = 0x48041000,
4287                 .pa_end         = 0x48041fff,
4288                 .flags          = ADDR_TYPE_RT
4289         },
4290         { }
4291 };
4292
4293 /* l4_per -> dss_dispc */
4294 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4295         .master         = &omap44xx_l4_per_hwmod,
4296         .slave          = &omap44xx_dss_dispc_hwmod,
4297         .clk            = "l4_div_ck",
4298         .addr           = omap44xx_dss_dispc_addrs,
4299         .user           = OCP_USER_MPU,
4300 };
4301
4302 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4303         {
4304                 .pa_start       = 0x58004000,
4305                 .pa_end         = 0x580041ff,
4306                 .flags          = ADDR_TYPE_RT
4307         },
4308         { }
4309 };
4310
4311 /* l3_main_2 -> dss_dsi1 */
4312 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4313         .master         = &omap44xx_l3_main_2_hwmod,
4314         .slave          = &omap44xx_dss_dsi1_hwmod,
4315         .clk            = "dss_fck",
4316         .addr           = omap44xx_dss_dsi1_dma_addrs,
4317         .user           = OCP_USER_SDMA,
4318 };
4319
4320 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4321         {
4322                 .pa_start       = 0x48044000,
4323                 .pa_end         = 0x480441ff,
4324                 .flags          = ADDR_TYPE_RT
4325         },
4326         { }
4327 };
4328
4329 /* l4_per -> dss_dsi1 */
4330 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4331         .master         = &omap44xx_l4_per_hwmod,
4332         .slave          = &omap44xx_dss_dsi1_hwmod,
4333         .clk            = "l4_div_ck",
4334         .addr           = omap44xx_dss_dsi1_addrs,
4335         .user           = OCP_USER_MPU,
4336 };
4337
4338 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4339         {
4340                 .pa_start       = 0x58005000,
4341                 .pa_end         = 0x580051ff,
4342                 .flags          = ADDR_TYPE_RT
4343         },
4344         { }
4345 };
4346
4347 /* l3_main_2 -> dss_dsi2 */
4348 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4349         .master         = &omap44xx_l3_main_2_hwmod,
4350         .slave          = &omap44xx_dss_dsi2_hwmod,
4351         .clk            = "dss_fck",
4352         .addr           = omap44xx_dss_dsi2_dma_addrs,
4353         .user           = OCP_USER_SDMA,
4354 };
4355
4356 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4357         {
4358                 .pa_start       = 0x48045000,
4359                 .pa_end         = 0x480451ff,
4360                 .flags          = ADDR_TYPE_RT
4361         },
4362         { }
4363 };
4364
4365 /* l4_per -> dss_dsi2 */
4366 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4367         .master         = &omap44xx_l4_per_hwmod,
4368         .slave          = &omap44xx_dss_dsi2_hwmod,
4369         .clk            = "l4_div_ck",
4370         .addr           = omap44xx_dss_dsi2_addrs,
4371         .user           = OCP_USER_MPU,
4372 };
4373
4374 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4375         {
4376                 .pa_start       = 0x58006000,
4377                 .pa_end         = 0x58006fff,
4378                 .flags          = ADDR_TYPE_RT
4379         },
4380         { }
4381 };
4382
4383 /* l3_main_2 -> dss_hdmi */
4384 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4385         .master         = &omap44xx_l3_main_2_hwmod,
4386         .slave          = &omap44xx_dss_hdmi_hwmod,
4387         .clk            = "dss_fck",
4388         .addr           = omap44xx_dss_hdmi_dma_addrs,
4389         .user           = OCP_USER_SDMA,
4390 };
4391
4392 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4393         {
4394                 .pa_start       = 0x48046000,
4395                 .pa_end         = 0x48046fff,
4396                 .flags          = ADDR_TYPE_RT
4397         },
4398         { }
4399 };
4400
4401 /* l4_per -> dss_hdmi */
4402 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4403         .master         = &omap44xx_l4_per_hwmod,
4404         .slave          = &omap44xx_dss_hdmi_hwmod,
4405         .clk            = "l4_div_ck",
4406         .addr           = omap44xx_dss_hdmi_addrs,
4407         .user           = OCP_USER_MPU,
4408 };
4409
4410 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4411         {
4412                 .pa_start       = 0x58002000,
4413                 .pa_end         = 0x580020ff,
4414                 .flags          = ADDR_TYPE_RT
4415         },
4416         { }
4417 };
4418
4419 /* l3_main_2 -> dss_rfbi */
4420 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4421         .master         = &omap44xx_l3_main_2_hwmod,
4422         .slave          = &omap44xx_dss_rfbi_hwmod,
4423         .clk            = "dss_fck",
4424         .addr           = omap44xx_dss_rfbi_dma_addrs,
4425         .user           = OCP_USER_SDMA,
4426 };
4427
4428 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4429         {
4430                 .pa_start       = 0x48042000,
4431                 .pa_end         = 0x480420ff,
4432                 .flags          = ADDR_TYPE_RT
4433         },
4434         { }
4435 };
4436
4437 /* l4_per -> dss_rfbi */
4438 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4439         .master         = &omap44xx_l4_per_hwmod,
4440         .slave          = &omap44xx_dss_rfbi_hwmod,
4441         .clk            = "l4_div_ck",
4442         .addr           = omap44xx_dss_rfbi_addrs,
4443         .user           = OCP_USER_MPU,
4444 };
4445
4446 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4447         {
4448                 .pa_start       = 0x58003000,
4449                 .pa_end         = 0x580030ff,
4450                 .flags          = ADDR_TYPE_RT
4451         },
4452         { }
4453 };
4454
4455 /* l3_main_2 -> dss_venc */
4456 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4457         .master         = &omap44xx_l3_main_2_hwmod,
4458         .slave          = &omap44xx_dss_venc_hwmod,
4459         .clk            = "dss_fck",
4460         .addr           = omap44xx_dss_venc_dma_addrs,
4461         .user           = OCP_USER_SDMA,
4462 };
4463
4464 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4465         {
4466                 .pa_start       = 0x48043000,
4467                 .pa_end         = 0x480430ff,
4468                 .flags          = ADDR_TYPE_RT
4469         },
4470         { }
4471 };
4472
4473 /* l4_per -> dss_venc */
4474 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4475         .master         = &omap44xx_l4_per_hwmod,
4476         .slave          = &omap44xx_dss_venc_hwmod,
4477         .clk            = "l4_div_ck",
4478         .addr           = omap44xx_dss_venc_addrs,
4479         .user           = OCP_USER_MPU,
4480 };
4481
4482 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4483         {
4484                 .pa_start       = 0x48078000,
4485                 .pa_end         = 0x48078fff,
4486                 .flags          = ADDR_TYPE_RT
4487         },
4488         { }
4489 };
4490
4491 /* l4_per -> elm */
4492 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4493         .master         = &omap44xx_l4_per_hwmod,
4494         .slave          = &omap44xx_elm_hwmod,
4495         .clk            = "l4_div_ck",
4496         .addr           = omap44xx_elm_addrs,
4497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4498 };
4499
4500 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4501         {
4502                 .pa_start       = 0x4c000000,
4503                 .pa_end         = 0x4c0000ff,
4504                 .flags          = ADDR_TYPE_RT
4505         },
4506         { }
4507 };
4508
4509 /* emif_fw -> emif1 */
4510 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4511         .master         = &omap44xx_emif_fw_hwmod,
4512         .slave          = &omap44xx_emif1_hwmod,
4513         .clk            = "l3_div_ck",
4514         .addr           = omap44xx_emif1_addrs,
4515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4516 };
4517
4518 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4519         {
4520                 .pa_start       = 0x4d000000,
4521                 .pa_end         = 0x4d0000ff,
4522                 .flags          = ADDR_TYPE_RT
4523         },
4524         { }
4525 };
4526
4527 /* emif_fw -> emif2 */
4528 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4529         .master         = &omap44xx_emif_fw_hwmod,
4530         .slave          = &omap44xx_emif2_hwmod,
4531         .clk            = "l3_div_ck",
4532         .addr           = omap44xx_emif2_addrs,
4533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4534 };
4535
4536 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4537         {
4538                 .pa_start       = 0x4a10a000,
4539                 .pa_end         = 0x4a10a1ff,
4540                 .flags          = ADDR_TYPE_RT
4541         },
4542         { }
4543 };
4544
4545 /* l4_cfg -> fdif */
4546 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4547         .master         = &omap44xx_l4_cfg_hwmod,
4548         .slave          = &omap44xx_fdif_hwmod,
4549         .clk            = "l4_div_ck",
4550         .addr           = omap44xx_fdif_addrs,
4551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4552 };
4553
4554 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4555         {
4556                 .pa_start       = 0x4a310000,
4557                 .pa_end         = 0x4a3101ff,
4558                 .flags          = ADDR_TYPE_RT
4559         },
4560         { }
4561 };
4562
4563 /* l4_wkup -> gpio1 */
4564 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4565         .master         = &omap44xx_l4_wkup_hwmod,
4566         .slave          = &omap44xx_gpio1_hwmod,
4567         .clk            = "l4_wkup_clk_mux_ck",
4568         .addr           = omap44xx_gpio1_addrs,
4569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4570 };
4571
4572 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4573         {
4574                 .pa_start       = 0x48055000,
4575                 .pa_end         = 0x480551ff,
4576                 .flags          = ADDR_TYPE_RT
4577         },
4578         { }
4579 };
4580
4581 /* l4_per -> gpio2 */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4583         .master         = &omap44xx_l4_per_hwmod,
4584         .slave          = &omap44xx_gpio2_hwmod,
4585         .clk            = "l4_div_ck",
4586         .addr           = omap44xx_gpio2_addrs,
4587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4588 };
4589
4590 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4591         {
4592                 .pa_start       = 0x48057000,
4593                 .pa_end         = 0x480571ff,
4594                 .flags          = ADDR_TYPE_RT
4595         },
4596         { }
4597 };
4598
4599 /* l4_per -> gpio3 */
4600 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4601         .master         = &omap44xx_l4_per_hwmod,
4602         .slave          = &omap44xx_gpio3_hwmod,
4603         .clk            = "l4_div_ck",
4604         .addr           = omap44xx_gpio3_addrs,
4605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4606 };
4607
4608 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4609         {
4610                 .pa_start       = 0x48059000,
4611                 .pa_end         = 0x480591ff,
4612                 .flags          = ADDR_TYPE_RT
4613         },
4614         { }
4615 };
4616
4617 /* l4_per -> gpio4 */
4618 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4619         .master         = &omap44xx_l4_per_hwmod,
4620         .slave          = &omap44xx_gpio4_hwmod,
4621         .clk            = "l4_div_ck",
4622         .addr           = omap44xx_gpio4_addrs,
4623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4624 };
4625
4626 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4627         {
4628                 .pa_start       = 0x4805b000,
4629                 .pa_end         = 0x4805b1ff,
4630                 .flags          = ADDR_TYPE_RT
4631         },
4632         { }
4633 };
4634
4635 /* l4_per -> gpio5 */
4636 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4637         .master         = &omap44xx_l4_per_hwmod,
4638         .slave          = &omap44xx_gpio5_hwmod,
4639         .clk            = "l4_div_ck",
4640         .addr           = omap44xx_gpio5_addrs,
4641         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4642 };
4643
4644 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4645         {
4646                 .pa_start       = 0x4805d000,
4647                 .pa_end         = 0x4805d1ff,
4648                 .flags          = ADDR_TYPE_RT
4649         },
4650         { }
4651 };
4652
4653 /* l4_per -> gpio6 */
4654 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4655         .master         = &omap44xx_l4_per_hwmod,
4656         .slave          = &omap44xx_gpio6_hwmod,
4657         .clk            = "l4_div_ck",
4658         .addr           = omap44xx_gpio6_addrs,
4659         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4660 };
4661
4662 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4663         {
4664                 .pa_start       = 0x50000000,
4665                 .pa_end         = 0x500003ff,
4666                 .flags          = ADDR_TYPE_RT
4667         },
4668         { }
4669 };
4670
4671 /* l3_main_2 -> gpmc */
4672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4673         .master         = &omap44xx_l3_main_2_hwmod,
4674         .slave          = &omap44xx_gpmc_hwmod,
4675         .clk            = "l3_div_ck",
4676         .addr           = omap44xx_gpmc_addrs,
4677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4678 };
4679
4680 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4681         {
4682                 .pa_start       = 0x56000000,
4683                 .pa_end         = 0x5600ffff,
4684                 .flags          = ADDR_TYPE_RT
4685         },
4686         { }
4687 };
4688
4689 /* l3_main_2 -> gpu */
4690 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4691         .master         = &omap44xx_l3_main_2_hwmod,
4692         .slave          = &omap44xx_gpu_hwmod,
4693         .clk            = "l3_div_ck",
4694         .addr           = omap44xx_gpu_addrs,
4695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4696 };
4697
4698 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4699         {
4700                 .pa_start       = 0x480b2000,
4701                 .pa_end         = 0x480b201f,
4702                 .flags          = ADDR_TYPE_RT
4703         },
4704         { }
4705 };
4706
4707 /* l4_per -> hdq1w */
4708 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4709         .master         = &omap44xx_l4_per_hwmod,
4710         .slave          = &omap44xx_hdq1w_hwmod,
4711         .clk            = "l4_div_ck",
4712         .addr           = omap44xx_hdq1w_addrs,
4713         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4714 };
4715
4716 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4717         {
4718                 .pa_start       = 0x4a058000,
4719                 .pa_end         = 0x4a05bfff,
4720                 .flags          = ADDR_TYPE_RT
4721         },
4722         { }
4723 };
4724
4725 /* l4_cfg -> hsi */
4726 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4727         .master         = &omap44xx_l4_cfg_hwmod,
4728         .slave          = &omap44xx_hsi_hwmod,
4729         .clk            = "l4_div_ck",
4730         .addr           = omap44xx_hsi_addrs,
4731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4732 };
4733
4734 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4735         {
4736                 .pa_start       = 0x48070000,
4737                 .pa_end         = 0x480700ff,
4738                 .flags          = ADDR_TYPE_RT
4739         },
4740         { }
4741 };
4742
4743 /* l4_per -> i2c1 */
4744 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4745         .master         = &omap44xx_l4_per_hwmod,
4746         .slave          = &omap44xx_i2c1_hwmod,
4747         .clk            = "l4_div_ck",
4748         .addr           = omap44xx_i2c1_addrs,
4749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4750 };
4751
4752 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4753         {
4754                 .pa_start       = 0x48072000,
4755                 .pa_end         = 0x480720ff,
4756                 .flags          = ADDR_TYPE_RT
4757         },
4758         { }
4759 };
4760
4761 /* l4_per -> i2c2 */
4762 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4763         .master         = &omap44xx_l4_per_hwmod,
4764         .slave          = &omap44xx_i2c2_hwmod,
4765         .clk            = "l4_div_ck",
4766         .addr           = omap44xx_i2c2_addrs,
4767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4768 };
4769
4770 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4771         {
4772                 .pa_start       = 0x48060000,
4773                 .pa_end         = 0x480600ff,
4774                 .flags          = ADDR_TYPE_RT
4775         },
4776         { }
4777 };
4778
4779 /* l4_per -> i2c3 */
4780 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4781         .master         = &omap44xx_l4_per_hwmod,
4782         .slave          = &omap44xx_i2c3_hwmod,
4783         .clk            = "l4_div_ck",
4784         .addr           = omap44xx_i2c3_addrs,
4785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4786 };
4787
4788 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4789         {
4790                 .pa_start       = 0x48350000,
4791                 .pa_end         = 0x483500ff,
4792                 .flags          = ADDR_TYPE_RT
4793         },
4794         { }
4795 };
4796
4797 /* l4_per -> i2c4 */
4798 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4799         .master         = &omap44xx_l4_per_hwmod,
4800         .slave          = &omap44xx_i2c4_hwmod,
4801         .clk            = "l4_div_ck",
4802         .addr           = omap44xx_i2c4_addrs,
4803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4804 };
4805
4806 /* l3_main_2 -> ipu */
4807 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4808         .master         = &omap44xx_l3_main_2_hwmod,
4809         .slave          = &omap44xx_ipu_hwmod,
4810         .clk            = "l3_div_ck",
4811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4812 };
4813
4814 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4815         {
4816                 .pa_start       = 0x52000000,
4817                 .pa_end         = 0x520000ff,
4818                 .flags          = ADDR_TYPE_RT
4819         },
4820         { }
4821 };
4822
4823 /* l3_main_2 -> iss */
4824 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4825         .master         = &omap44xx_l3_main_2_hwmod,
4826         .slave          = &omap44xx_iss_hwmod,
4827         .clk            = "l3_div_ck",
4828         .addr           = omap44xx_iss_addrs,
4829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4830 };
4831
4832 /* iva -> sl2if */
4833 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4834         .master         = &omap44xx_iva_hwmod,
4835         .slave          = &omap44xx_sl2if_hwmod,
4836         .clk            = "dpll_iva_m5x2_ck",
4837         .user           = OCP_USER_IVA,
4838 };
4839
4840 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4841         {
4842                 .pa_start       = 0x5a000000,
4843                 .pa_end         = 0x5a07ffff,
4844                 .flags          = ADDR_TYPE_RT
4845         },
4846         { }
4847 };
4848
4849 /* l3_main_2 -> iva */
4850 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4851         .master         = &omap44xx_l3_main_2_hwmod,
4852         .slave          = &omap44xx_iva_hwmod,
4853         .clk            = "l3_div_ck",
4854         .addr           = omap44xx_iva_addrs,
4855         .user           = OCP_USER_MPU,
4856 };
4857
4858 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4859         {
4860                 .pa_start       = 0x4a31c000,
4861                 .pa_end         = 0x4a31c07f,
4862                 .flags          = ADDR_TYPE_RT
4863         },
4864         { }
4865 };
4866
4867 /* l4_wkup -> kbd */
4868 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4869         .master         = &omap44xx_l4_wkup_hwmod,
4870         .slave          = &omap44xx_kbd_hwmod,
4871         .clk            = "l4_wkup_clk_mux_ck",
4872         .addr           = omap44xx_kbd_addrs,
4873         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4874 };
4875
4876 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4877         {
4878                 .pa_start       = 0x4a0f4000,
4879                 .pa_end         = 0x4a0f41ff,
4880                 .flags          = ADDR_TYPE_RT
4881         },
4882         { }
4883 };
4884
4885 /* l4_cfg -> mailbox */
4886 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4887         .master         = &omap44xx_l4_cfg_hwmod,
4888         .slave          = &omap44xx_mailbox_hwmod,
4889         .clk            = "l4_div_ck",
4890         .addr           = omap44xx_mailbox_addrs,
4891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4892 };
4893
4894 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4895         {
4896                 .pa_start       = 0x40128000,
4897                 .pa_end         = 0x401283ff,
4898                 .flags          = ADDR_TYPE_RT
4899         },
4900         { }
4901 };
4902
4903 /* l4_abe -> mcasp */
4904 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4905         .master         = &omap44xx_l4_abe_hwmod,
4906         .slave          = &omap44xx_mcasp_hwmod,
4907         .clk            = "ocp_abe_iclk",
4908         .addr           = omap44xx_mcasp_addrs,
4909         .user           = OCP_USER_MPU,
4910 };
4911
4912 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4913         {
4914                 .pa_start       = 0x49028000,
4915                 .pa_end         = 0x490283ff,
4916                 .flags          = ADDR_TYPE_RT
4917         },
4918         { }
4919 };
4920
4921 /* l4_abe -> mcasp (dma) */
4922 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4923         .master         = &omap44xx_l4_abe_hwmod,
4924         .slave          = &omap44xx_mcasp_hwmod,
4925         .clk            = "ocp_abe_iclk",
4926         .addr           = omap44xx_mcasp_dma_addrs,
4927         .user           = OCP_USER_SDMA,
4928 };
4929
4930 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4931         {
4932                 .name           = "mpu",
4933                 .pa_start       = 0x40122000,
4934                 .pa_end         = 0x401220ff,
4935                 .flags          = ADDR_TYPE_RT
4936         },
4937         { }
4938 };
4939
4940 /* l4_abe -> mcbsp1 */
4941 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4942         .master         = &omap44xx_l4_abe_hwmod,
4943         .slave          = &omap44xx_mcbsp1_hwmod,
4944         .clk            = "ocp_abe_iclk",
4945         .addr           = omap44xx_mcbsp1_addrs,
4946         .user           = OCP_USER_MPU,
4947 };
4948
4949 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4950         {
4951                 .name           = "dma",
4952                 .pa_start       = 0x49022000,
4953                 .pa_end         = 0x490220ff,
4954                 .flags          = ADDR_TYPE_RT
4955         },
4956         { }
4957 };
4958
4959 /* l4_abe -> mcbsp1 (dma) */
4960 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4961         .master         = &omap44xx_l4_abe_hwmod,
4962         .slave          = &omap44xx_mcbsp1_hwmod,
4963         .clk            = "ocp_abe_iclk",
4964         .addr           = omap44xx_mcbsp1_dma_addrs,
4965         .user           = OCP_USER_SDMA,
4966 };
4967
4968 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4969         {
4970                 .name           = "mpu",
4971                 .pa_start       = 0x40124000,
4972                 .pa_end         = 0x401240ff,
4973                 .flags          = ADDR_TYPE_RT
4974         },
4975         { }
4976 };
4977
4978 /* l4_abe -> mcbsp2 */
4979 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4980         .master         = &omap44xx_l4_abe_hwmod,
4981         .slave          = &omap44xx_mcbsp2_hwmod,
4982         .clk            = "ocp_abe_iclk",
4983         .addr           = omap44xx_mcbsp2_addrs,
4984         .user           = OCP_USER_MPU,
4985 };
4986
4987 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4988         {
4989                 .name           = "dma",
4990                 .pa_start       = 0x49024000,
4991                 .pa_end         = 0x490240ff,
4992                 .flags          = ADDR_TYPE_RT
4993         },
4994         { }
4995 };
4996
4997 /* l4_abe -> mcbsp2 (dma) */
4998 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4999         .master         = &omap44xx_l4_abe_hwmod,
5000         .slave          = &omap44xx_mcbsp2_hwmod,
5001         .clk            = "ocp_abe_iclk",
5002         .addr           = omap44xx_mcbsp2_dma_addrs,
5003         .user           = OCP_USER_SDMA,
5004 };
5005
5006 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5007         {
5008                 .name           = "mpu",
5009                 .pa_start       = 0x40126000,
5010                 .pa_end         = 0x401260ff,
5011                 .flags          = ADDR_TYPE_RT
5012         },
5013         { }
5014 };
5015
5016 /* l4_abe -> mcbsp3 */
5017 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5018         .master         = &omap44xx_l4_abe_hwmod,
5019         .slave          = &omap44xx_mcbsp3_hwmod,
5020         .clk            = "ocp_abe_iclk",
5021         .addr           = omap44xx_mcbsp3_addrs,
5022         .user           = OCP_USER_MPU,
5023 };
5024
5025 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5026         {
5027                 .name           = "dma",
5028                 .pa_start       = 0x49026000,
5029                 .pa_end         = 0x490260ff,
5030                 .flags          = ADDR_TYPE_RT
5031         },
5032         { }
5033 };
5034
5035 /* l4_abe -> mcbsp3 (dma) */
5036 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5037         .master         = &omap44xx_l4_abe_hwmod,
5038         .slave          = &omap44xx_mcbsp3_hwmod,
5039         .clk            = "ocp_abe_iclk",
5040         .addr           = omap44xx_mcbsp3_dma_addrs,
5041         .user           = OCP_USER_SDMA,
5042 };
5043
5044 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5045         {
5046                 .pa_start       = 0x48096000,
5047                 .pa_end         = 0x480960ff,
5048                 .flags          = ADDR_TYPE_RT
5049         },
5050         { }
5051 };
5052
5053 /* l4_per -> mcbsp4 */
5054 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5055         .master         = &omap44xx_l4_per_hwmod,
5056         .slave          = &omap44xx_mcbsp4_hwmod,
5057         .clk            = "l4_div_ck",
5058         .addr           = omap44xx_mcbsp4_addrs,
5059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5060 };
5061
5062 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5063         {
5064                 .pa_start       = 0x40132000,
5065                 .pa_end         = 0x4013207f,
5066                 .flags          = ADDR_TYPE_RT
5067         },
5068         { }
5069 };
5070
5071 /* l4_abe -> mcpdm */
5072 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5073         .master         = &omap44xx_l4_abe_hwmod,
5074         .slave          = &omap44xx_mcpdm_hwmod,
5075         .clk            = "ocp_abe_iclk",
5076         .addr           = omap44xx_mcpdm_addrs,
5077         .user           = OCP_USER_MPU,
5078 };
5079
5080 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5081         {
5082                 .pa_start       = 0x49032000,
5083                 .pa_end         = 0x4903207f,
5084                 .flags          = ADDR_TYPE_RT
5085         },
5086         { }
5087 };
5088
5089 /* l4_abe -> mcpdm (dma) */
5090 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5091         .master         = &omap44xx_l4_abe_hwmod,
5092         .slave          = &omap44xx_mcpdm_hwmod,
5093         .clk            = "ocp_abe_iclk",
5094         .addr           = omap44xx_mcpdm_dma_addrs,
5095         .user           = OCP_USER_SDMA,
5096 };
5097
5098 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5099         {
5100                 .pa_start       = 0x48098000,
5101                 .pa_end         = 0x480981ff,
5102                 .flags          = ADDR_TYPE_RT
5103         },
5104         { }
5105 };
5106
5107 /* l4_per -> mcspi1 */
5108 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5109         .master         = &omap44xx_l4_per_hwmod,
5110         .slave          = &omap44xx_mcspi1_hwmod,
5111         .clk            = "l4_div_ck",
5112         .addr           = omap44xx_mcspi1_addrs,
5113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5114 };
5115
5116 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5117         {
5118                 .pa_start       = 0x4809a000,
5119                 .pa_end         = 0x4809a1ff,
5120                 .flags          = ADDR_TYPE_RT
5121         },
5122         { }
5123 };
5124
5125 /* l4_per -> mcspi2 */
5126 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5127         .master         = &omap44xx_l4_per_hwmod,
5128         .slave          = &omap44xx_mcspi2_hwmod,
5129         .clk            = "l4_div_ck",
5130         .addr           = omap44xx_mcspi2_addrs,
5131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5132 };
5133
5134 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5135         {
5136                 .pa_start       = 0x480b8000,
5137                 .pa_end         = 0x480b81ff,
5138                 .flags          = ADDR_TYPE_RT
5139         },
5140         { }
5141 };
5142
5143 /* l4_per -> mcspi3 */
5144 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5145         .master         = &omap44xx_l4_per_hwmod,
5146         .slave          = &omap44xx_mcspi3_hwmod,
5147         .clk            = "l4_div_ck",
5148         .addr           = omap44xx_mcspi3_addrs,
5149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5150 };
5151
5152 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5153         {
5154                 .pa_start       = 0x480ba000,
5155                 .pa_end         = 0x480ba1ff,
5156                 .flags          = ADDR_TYPE_RT
5157         },
5158         { }
5159 };
5160
5161 /* l4_per -> mcspi4 */
5162 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5163         .master         = &omap44xx_l4_per_hwmod,
5164         .slave          = &omap44xx_mcspi4_hwmod,
5165         .clk            = "l4_div_ck",
5166         .addr           = omap44xx_mcspi4_addrs,
5167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5168 };
5169
5170 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5171         {
5172                 .pa_start       = 0x4809c000,
5173                 .pa_end         = 0x4809c3ff,
5174                 .flags          = ADDR_TYPE_RT
5175         },
5176         { }
5177 };
5178
5179 /* l4_per -> mmc1 */
5180 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5181         .master         = &omap44xx_l4_per_hwmod,
5182         .slave          = &omap44xx_mmc1_hwmod,
5183         .clk            = "l4_div_ck",
5184         .addr           = omap44xx_mmc1_addrs,
5185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5186 };
5187
5188 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5189         {
5190                 .pa_start       = 0x480b4000,
5191                 .pa_end         = 0x480b43ff,
5192                 .flags          = ADDR_TYPE_RT
5193         },
5194         { }
5195 };
5196
5197 /* l4_per -> mmc2 */
5198 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5199         .master         = &omap44xx_l4_per_hwmod,
5200         .slave          = &omap44xx_mmc2_hwmod,
5201         .clk            = "l4_div_ck",
5202         .addr           = omap44xx_mmc2_addrs,
5203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5204 };
5205
5206 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5207         {
5208                 .pa_start       = 0x480ad000,
5209                 .pa_end         = 0x480ad3ff,
5210                 .flags          = ADDR_TYPE_RT
5211         },
5212         { }
5213 };
5214
5215 /* l4_per -> mmc3 */
5216 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5217         .master         = &omap44xx_l4_per_hwmod,
5218         .slave          = &omap44xx_mmc3_hwmod,
5219         .clk            = "l4_div_ck",
5220         .addr           = omap44xx_mmc3_addrs,
5221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5222 };
5223
5224 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5225         {
5226                 .pa_start       = 0x480d1000,
5227                 .pa_end         = 0x480d13ff,
5228                 .flags          = ADDR_TYPE_RT
5229         },
5230         { }
5231 };
5232
5233 /* l4_per -> mmc4 */
5234 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5235         .master         = &omap44xx_l4_per_hwmod,
5236         .slave          = &omap44xx_mmc4_hwmod,
5237         .clk            = "l4_div_ck",
5238         .addr           = omap44xx_mmc4_addrs,
5239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5240 };
5241
5242 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5243         {
5244                 .pa_start       = 0x480d5000,
5245                 .pa_end         = 0x480d53ff,
5246                 .flags          = ADDR_TYPE_RT
5247         },
5248         { }
5249 };
5250
5251 /* l4_per -> mmc5 */
5252 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5253         .master         = &omap44xx_l4_per_hwmod,
5254         .slave          = &omap44xx_mmc5_hwmod,
5255         .clk            = "l4_div_ck",
5256         .addr           = omap44xx_mmc5_addrs,
5257         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5258 };
5259
5260 /* l3_main_2 -> ocmc_ram */
5261 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5262         .master         = &omap44xx_l3_main_2_hwmod,
5263         .slave          = &omap44xx_ocmc_ram_hwmod,
5264         .clk            = "l3_div_ck",
5265         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5266 };
5267
5268 /* l4_cfg -> ocp2scp_usb_phy */
5269 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5270         .master         = &omap44xx_l4_cfg_hwmod,
5271         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5272         .clk            = "l4_div_ck",
5273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5274 };
5275
5276 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5277         {
5278                 .pa_start       = 0x48243000,
5279                 .pa_end         = 0x48243fff,
5280                 .flags          = ADDR_TYPE_RT
5281         },
5282         { }
5283 };
5284
5285 /* mpu_private -> prcm_mpu */
5286 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5287         .master         = &omap44xx_mpu_private_hwmod,
5288         .slave          = &omap44xx_prcm_mpu_hwmod,
5289         .clk            = "l3_div_ck",
5290         .addr           = omap44xx_prcm_mpu_addrs,
5291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5292 };
5293
5294 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5295         {
5296                 .pa_start       = 0x4a004000,
5297                 .pa_end         = 0x4a004fff,
5298                 .flags          = ADDR_TYPE_RT
5299         },
5300         { }
5301 };
5302
5303 /* l4_wkup -> cm_core_aon */
5304 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5305         .master         = &omap44xx_l4_wkup_hwmod,
5306         .slave          = &omap44xx_cm_core_aon_hwmod,
5307         .clk            = "l4_wkup_clk_mux_ck",
5308         .addr           = omap44xx_cm_core_aon_addrs,
5309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5310 };
5311
5312 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5313         {
5314                 .pa_start       = 0x4a008000,
5315                 .pa_end         = 0x4a009fff,
5316                 .flags          = ADDR_TYPE_RT
5317         },
5318         { }
5319 };
5320
5321 /* l4_cfg -> cm_core */
5322 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5323         .master         = &omap44xx_l4_cfg_hwmod,
5324         .slave          = &omap44xx_cm_core_hwmod,
5325         .clk            = "l4_div_ck",
5326         .addr           = omap44xx_cm_core_addrs,
5327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5328 };
5329
5330 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5331         {
5332                 .pa_start       = 0x4a306000,
5333                 .pa_end         = 0x4a307fff,
5334                 .flags          = ADDR_TYPE_RT
5335         },
5336         { }
5337 };
5338
5339 /* l4_wkup -> prm */
5340 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5341         .master         = &omap44xx_l4_wkup_hwmod,
5342         .slave          = &omap44xx_prm_hwmod,
5343         .clk            = "l4_wkup_clk_mux_ck",
5344         .addr           = omap44xx_prm_addrs,
5345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5346 };
5347
5348 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5349         {
5350                 .pa_start       = 0x4a30a000,
5351                 .pa_end         = 0x4a30a7ff,
5352                 .flags          = ADDR_TYPE_RT
5353         },
5354         { }
5355 };
5356
5357 /* l4_wkup -> scrm */
5358 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5359         .master         = &omap44xx_l4_wkup_hwmod,
5360         .slave          = &omap44xx_scrm_hwmod,
5361         .clk            = "l4_wkup_clk_mux_ck",
5362         .addr           = omap44xx_scrm_addrs,
5363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5364 };
5365
5366 /* l3_main_2 -> sl2if */
5367 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5368         .master         = &omap44xx_l3_main_2_hwmod,
5369         .slave          = &omap44xx_sl2if_hwmod,
5370         .clk            = "l3_div_ck",
5371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5372 };
5373
5374 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5375         {
5376                 .pa_start       = 0x4012c000,
5377                 .pa_end         = 0x4012c3ff,
5378                 .flags          = ADDR_TYPE_RT
5379         },
5380         { }
5381 };
5382
5383 /* l4_abe -> slimbus1 */
5384 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5385         .master         = &omap44xx_l4_abe_hwmod,
5386         .slave          = &omap44xx_slimbus1_hwmod,
5387         .clk            = "ocp_abe_iclk",
5388         .addr           = omap44xx_slimbus1_addrs,
5389         .user           = OCP_USER_MPU,
5390 };
5391
5392 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5393         {
5394                 .pa_start       = 0x4902c000,
5395                 .pa_end         = 0x4902c3ff,
5396                 .flags          = ADDR_TYPE_RT
5397         },
5398         { }
5399 };
5400
5401 /* l4_abe -> slimbus1 (dma) */
5402 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5403         .master         = &omap44xx_l4_abe_hwmod,
5404         .slave          = &omap44xx_slimbus1_hwmod,
5405         .clk            = "ocp_abe_iclk",
5406         .addr           = omap44xx_slimbus1_dma_addrs,
5407         .user           = OCP_USER_SDMA,
5408 };
5409
5410 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5411         {
5412                 .pa_start       = 0x48076000,
5413                 .pa_end         = 0x480763ff,
5414                 .flags          = ADDR_TYPE_RT
5415         },
5416         { }
5417 };
5418
5419 /* l4_per -> slimbus2 */
5420 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5421         .master         = &omap44xx_l4_per_hwmod,
5422         .slave          = &omap44xx_slimbus2_hwmod,
5423         .clk            = "l4_div_ck",
5424         .addr           = omap44xx_slimbus2_addrs,
5425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5426 };
5427
5428 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5429         {
5430                 .pa_start       = 0x4a0dd000,
5431                 .pa_end         = 0x4a0dd03f,
5432                 .flags          = ADDR_TYPE_RT
5433         },
5434         { }
5435 };
5436
5437 /* l4_cfg -> smartreflex_core */
5438 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5439         .master         = &omap44xx_l4_cfg_hwmod,
5440         .slave          = &omap44xx_smartreflex_core_hwmod,
5441         .clk            = "l4_div_ck",
5442         .addr           = omap44xx_smartreflex_core_addrs,
5443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5444 };
5445
5446 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5447         {
5448                 .pa_start       = 0x4a0db000,
5449                 .pa_end         = 0x4a0db03f,
5450                 .flags          = ADDR_TYPE_RT
5451         },
5452         { }
5453 };
5454
5455 /* l4_cfg -> smartreflex_iva */
5456 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5457         .master         = &omap44xx_l4_cfg_hwmod,
5458         .slave          = &omap44xx_smartreflex_iva_hwmod,
5459         .clk            = "l4_div_ck",
5460         .addr           = omap44xx_smartreflex_iva_addrs,
5461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5462 };
5463
5464 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5465         {
5466                 .pa_start       = 0x4a0d9000,
5467                 .pa_end         = 0x4a0d903f,
5468                 .flags          = ADDR_TYPE_RT
5469         },
5470         { }
5471 };
5472
5473 /* l4_cfg -> smartreflex_mpu */
5474 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5475         .master         = &omap44xx_l4_cfg_hwmod,
5476         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5477         .clk            = "l4_div_ck",
5478         .addr           = omap44xx_smartreflex_mpu_addrs,
5479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5480 };
5481
5482 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5483         {
5484                 .pa_start       = 0x4a0f6000,
5485                 .pa_end         = 0x4a0f6fff,
5486                 .flags          = ADDR_TYPE_RT
5487         },
5488         { }
5489 };
5490
5491 /* l4_cfg -> spinlock */
5492 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5493         .master         = &omap44xx_l4_cfg_hwmod,
5494         .slave          = &omap44xx_spinlock_hwmod,
5495         .clk            = "l4_div_ck",
5496         .addr           = omap44xx_spinlock_addrs,
5497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5498 };
5499
5500 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5501         {
5502                 .pa_start       = 0x4a318000,
5503                 .pa_end         = 0x4a31807f,
5504                 .flags          = ADDR_TYPE_RT
5505         },
5506         { }
5507 };
5508
5509 /* l4_wkup -> timer1 */
5510 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5511         .master         = &omap44xx_l4_wkup_hwmod,
5512         .slave          = &omap44xx_timer1_hwmod,
5513         .clk            = "l4_wkup_clk_mux_ck",
5514         .addr           = omap44xx_timer1_addrs,
5515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5516 };
5517
5518 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5519         {
5520                 .pa_start       = 0x48032000,
5521                 .pa_end         = 0x4803207f,
5522                 .flags          = ADDR_TYPE_RT
5523         },
5524         { }
5525 };
5526
5527 /* l4_per -> timer2 */
5528 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5529         .master         = &omap44xx_l4_per_hwmod,
5530         .slave          = &omap44xx_timer2_hwmod,
5531         .clk            = "l4_div_ck",
5532         .addr           = omap44xx_timer2_addrs,
5533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5534 };
5535
5536 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5537         {
5538                 .pa_start       = 0x48034000,
5539                 .pa_end         = 0x4803407f,
5540                 .flags          = ADDR_TYPE_RT
5541         },
5542         { }
5543 };
5544
5545 /* l4_per -> timer3 */
5546 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5547         .master         = &omap44xx_l4_per_hwmod,
5548         .slave          = &omap44xx_timer3_hwmod,
5549         .clk            = "l4_div_ck",
5550         .addr           = omap44xx_timer3_addrs,
5551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5552 };
5553
5554 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5555         {
5556                 .pa_start       = 0x48036000,
5557                 .pa_end         = 0x4803607f,
5558                 .flags          = ADDR_TYPE_RT
5559         },
5560         { }
5561 };
5562
5563 /* l4_per -> timer4 */
5564 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5565         .master         = &omap44xx_l4_per_hwmod,
5566         .slave          = &omap44xx_timer4_hwmod,
5567         .clk            = "l4_div_ck",
5568         .addr           = omap44xx_timer4_addrs,
5569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5570 };
5571
5572 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5573         {
5574                 .pa_start       = 0x40138000,
5575                 .pa_end         = 0x4013807f,
5576                 .flags          = ADDR_TYPE_RT
5577         },
5578         { }
5579 };
5580
5581 /* l4_abe -> timer5 */
5582 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5583         .master         = &omap44xx_l4_abe_hwmod,
5584         .slave          = &omap44xx_timer5_hwmod,
5585         .clk            = "ocp_abe_iclk",
5586         .addr           = omap44xx_timer5_addrs,
5587         .user           = OCP_USER_MPU,
5588 };
5589
5590 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5591         {
5592                 .pa_start       = 0x49038000,
5593                 .pa_end         = 0x4903807f,
5594                 .flags          = ADDR_TYPE_RT
5595         },
5596         { }
5597 };
5598
5599 /* l4_abe -> timer5 (dma) */
5600 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5601         .master         = &omap44xx_l4_abe_hwmod,
5602         .slave          = &omap44xx_timer5_hwmod,
5603         .clk            = "ocp_abe_iclk",
5604         .addr           = omap44xx_timer5_dma_addrs,
5605         .user           = OCP_USER_SDMA,
5606 };
5607
5608 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5609         {
5610                 .pa_start       = 0x4013a000,
5611                 .pa_end         = 0x4013a07f,
5612                 .flags          = ADDR_TYPE_RT
5613         },
5614         { }
5615 };
5616
5617 /* l4_abe -> timer6 */
5618 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5619         .master         = &omap44xx_l4_abe_hwmod,
5620         .slave          = &omap44xx_timer6_hwmod,
5621         .clk            = "ocp_abe_iclk",
5622         .addr           = omap44xx_timer6_addrs,
5623         .user           = OCP_USER_MPU,
5624 };
5625
5626 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5627         {
5628                 .pa_start       = 0x4903a000,
5629                 .pa_end         = 0x4903a07f,
5630                 .flags          = ADDR_TYPE_RT
5631         },
5632         { }
5633 };
5634
5635 /* l4_abe -> timer6 (dma) */
5636 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5637         .master         = &omap44xx_l4_abe_hwmod,
5638         .slave          = &omap44xx_timer6_hwmod,
5639         .clk            = "ocp_abe_iclk",
5640         .addr           = omap44xx_timer6_dma_addrs,
5641         .user           = OCP_USER_SDMA,
5642 };
5643
5644 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5645         {
5646                 .pa_start       = 0x4013c000,
5647                 .pa_end         = 0x4013c07f,
5648                 .flags          = ADDR_TYPE_RT
5649         },
5650         { }
5651 };
5652
5653 /* l4_abe -> timer7 */
5654 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5655         .master         = &omap44xx_l4_abe_hwmod,
5656         .slave          = &omap44xx_timer7_hwmod,
5657         .clk            = "ocp_abe_iclk",
5658         .addr           = omap44xx_timer7_addrs,
5659         .user           = OCP_USER_MPU,
5660 };
5661
5662 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5663         {
5664                 .pa_start       = 0x4903c000,
5665                 .pa_end         = 0x4903c07f,
5666                 .flags          = ADDR_TYPE_RT
5667         },
5668         { }
5669 };
5670
5671 /* l4_abe -> timer7 (dma) */
5672 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5673         .master         = &omap44xx_l4_abe_hwmod,
5674         .slave          = &omap44xx_timer7_hwmod,
5675         .clk            = "ocp_abe_iclk",
5676         .addr           = omap44xx_timer7_dma_addrs,
5677         .user           = OCP_USER_SDMA,
5678 };
5679
5680 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5681         {
5682                 .pa_start       = 0x4013e000,
5683                 .pa_end         = 0x4013e07f,
5684                 .flags          = ADDR_TYPE_RT
5685         },
5686         { }
5687 };
5688
5689 /* l4_abe -> timer8 */
5690 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5691         .master         = &omap44xx_l4_abe_hwmod,
5692         .slave          = &omap44xx_timer8_hwmod,
5693         .clk            = "ocp_abe_iclk",
5694         .addr           = omap44xx_timer8_addrs,
5695         .user           = OCP_USER_MPU,
5696 };
5697
5698 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5699         {
5700                 .pa_start       = 0x4903e000,
5701                 .pa_end         = 0x4903e07f,
5702                 .flags          = ADDR_TYPE_RT
5703         },
5704         { }
5705 };
5706
5707 /* l4_abe -> timer8 (dma) */
5708 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5709         .master         = &omap44xx_l4_abe_hwmod,
5710         .slave          = &omap44xx_timer8_hwmod,
5711         .clk            = "ocp_abe_iclk",
5712         .addr           = omap44xx_timer8_dma_addrs,
5713         .user           = OCP_USER_SDMA,
5714 };
5715
5716 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5717         {
5718                 .pa_start       = 0x4803e000,
5719                 .pa_end         = 0x4803e07f,
5720                 .flags          = ADDR_TYPE_RT
5721         },
5722         { }
5723 };
5724
5725 /* l4_per -> timer9 */
5726 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5727         .master         = &omap44xx_l4_per_hwmod,
5728         .slave          = &omap44xx_timer9_hwmod,
5729         .clk            = "l4_div_ck",
5730         .addr           = omap44xx_timer9_addrs,
5731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5732 };
5733
5734 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5735         {
5736                 .pa_start       = 0x48086000,
5737                 .pa_end         = 0x4808607f,
5738                 .flags          = ADDR_TYPE_RT
5739         },
5740         { }
5741 };
5742
5743 /* l4_per -> timer10 */
5744 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5745         .master         = &omap44xx_l4_per_hwmod,
5746         .slave          = &omap44xx_timer10_hwmod,
5747         .clk            = "l4_div_ck",
5748         .addr           = omap44xx_timer10_addrs,
5749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5750 };
5751
5752 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5753         {
5754                 .pa_start       = 0x48088000,
5755                 .pa_end         = 0x4808807f,
5756                 .flags          = ADDR_TYPE_RT
5757         },
5758         { }
5759 };
5760
5761 /* l4_per -> timer11 */
5762 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5763         .master         = &omap44xx_l4_per_hwmod,
5764         .slave          = &omap44xx_timer11_hwmod,
5765         .clk            = "l4_div_ck",
5766         .addr           = omap44xx_timer11_addrs,
5767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5768 };
5769
5770 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5771         {
5772                 .pa_start       = 0x4806a000,
5773                 .pa_end         = 0x4806a0ff,
5774                 .flags          = ADDR_TYPE_RT
5775         },
5776         { }
5777 };
5778
5779 /* l4_per -> uart1 */
5780 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5781         .master         = &omap44xx_l4_per_hwmod,
5782         .slave          = &omap44xx_uart1_hwmod,
5783         .clk            = "l4_div_ck",
5784         .addr           = omap44xx_uart1_addrs,
5785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5786 };
5787
5788 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5789         {
5790                 .pa_start       = 0x4806c000,
5791                 .pa_end         = 0x4806c0ff,
5792                 .flags          = ADDR_TYPE_RT
5793         },
5794         { }
5795 };
5796
5797 /* l4_per -> uart2 */
5798 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5799         .master         = &omap44xx_l4_per_hwmod,
5800         .slave          = &omap44xx_uart2_hwmod,
5801         .clk            = "l4_div_ck",
5802         .addr           = omap44xx_uart2_addrs,
5803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5804 };
5805
5806 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5807         {
5808                 .pa_start       = 0x48020000,
5809                 .pa_end         = 0x480200ff,
5810                 .flags          = ADDR_TYPE_RT
5811         },
5812         { }
5813 };
5814
5815 /* l4_per -> uart3 */
5816 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5817         .master         = &omap44xx_l4_per_hwmod,
5818         .slave          = &omap44xx_uart3_hwmod,
5819         .clk            = "l4_div_ck",
5820         .addr           = omap44xx_uart3_addrs,
5821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5822 };
5823
5824 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5825         {
5826                 .pa_start       = 0x4806e000,
5827                 .pa_end         = 0x4806e0ff,
5828                 .flags          = ADDR_TYPE_RT
5829         },
5830         { }
5831 };
5832
5833 /* l4_per -> uart4 */
5834 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5835         .master         = &omap44xx_l4_per_hwmod,
5836         .slave          = &omap44xx_uart4_hwmod,
5837         .clk            = "l4_div_ck",
5838         .addr           = omap44xx_uart4_addrs,
5839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5840 };
5841
5842 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5843         {
5844                 .pa_start       = 0x4a0a9000,
5845                 .pa_end         = 0x4a0a93ff,
5846                 .flags          = ADDR_TYPE_RT
5847         },
5848         { }
5849 };
5850
5851 /* l4_cfg -> usb_host_fs */
5852 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5853         .master         = &omap44xx_l4_cfg_hwmod,
5854         .slave          = &omap44xx_usb_host_fs_hwmod,
5855         .clk            = "l4_div_ck",
5856         .addr           = omap44xx_usb_host_fs_addrs,
5857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5858 };
5859
5860 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5861         {
5862                 .name           = "uhh",
5863                 .pa_start       = 0x4a064000,
5864                 .pa_end         = 0x4a0647ff,
5865                 .flags          = ADDR_TYPE_RT
5866         },
5867         {
5868                 .name           = "ohci",
5869                 .pa_start       = 0x4a064800,
5870                 .pa_end         = 0x4a064bff,
5871         },
5872         {
5873                 .name           = "ehci",
5874                 .pa_start       = 0x4a064c00,
5875                 .pa_end         = 0x4a064fff,
5876         },
5877         {}
5878 };
5879
5880 /* l4_cfg -> usb_host_hs */
5881 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5882         .master         = &omap44xx_l4_cfg_hwmod,
5883         .slave          = &omap44xx_usb_host_hs_hwmod,
5884         .clk            = "l4_div_ck",
5885         .addr           = omap44xx_usb_host_hs_addrs,
5886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5887 };
5888
5889 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5890         {
5891                 .pa_start       = 0x4a0ab000,
5892                 .pa_end         = 0x4a0ab003,
5893                 .flags          = ADDR_TYPE_RT
5894         },
5895         { }
5896 };
5897
5898 /* l4_cfg -> usb_otg_hs */
5899 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5900         .master         = &omap44xx_l4_cfg_hwmod,
5901         .slave          = &omap44xx_usb_otg_hs_hwmod,
5902         .clk            = "l4_div_ck",
5903         .addr           = omap44xx_usb_otg_hs_addrs,
5904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5905 };
5906
5907 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5908         {
5909                 .name           = "tll",
5910                 .pa_start       = 0x4a062000,
5911                 .pa_end         = 0x4a063fff,
5912                 .flags          = ADDR_TYPE_RT
5913         },
5914         {}
5915 };
5916
5917 /* l4_cfg -> usb_tll_hs */
5918 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5919         .master         = &omap44xx_l4_cfg_hwmod,
5920         .slave          = &omap44xx_usb_tll_hs_hwmod,
5921         .clk            = "l4_div_ck",
5922         .addr           = omap44xx_usb_tll_hs_addrs,
5923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5924 };
5925
5926 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5927         {
5928                 .pa_start       = 0x4a314000,
5929                 .pa_end         = 0x4a31407f,
5930                 .flags          = ADDR_TYPE_RT
5931         },
5932         { }
5933 };
5934
5935 /* l4_wkup -> wd_timer2 */
5936 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5937         .master         = &omap44xx_l4_wkup_hwmod,
5938         .slave          = &omap44xx_wd_timer2_hwmod,
5939         .clk            = "l4_wkup_clk_mux_ck",
5940         .addr           = omap44xx_wd_timer2_addrs,
5941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5942 };
5943
5944 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5945         {
5946                 .pa_start       = 0x40130000,
5947                 .pa_end         = 0x4013007f,
5948                 .flags          = ADDR_TYPE_RT
5949         },
5950         { }
5951 };
5952
5953 /* l4_abe -> wd_timer3 */
5954 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5955         .master         = &omap44xx_l4_abe_hwmod,
5956         .slave          = &omap44xx_wd_timer3_hwmod,
5957         .clk            = "ocp_abe_iclk",
5958         .addr           = omap44xx_wd_timer3_addrs,
5959         .user           = OCP_USER_MPU,
5960 };
5961
5962 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5963         {
5964                 .pa_start       = 0x49030000,
5965                 .pa_end         = 0x4903007f,
5966                 .flags          = ADDR_TYPE_RT
5967         },
5968         { }
5969 };
5970
5971 /* l4_abe -> wd_timer3 (dma) */
5972 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5973         .master         = &omap44xx_l4_abe_hwmod,
5974         .slave          = &omap44xx_wd_timer3_hwmod,
5975         .clk            = "ocp_abe_iclk",
5976         .addr           = omap44xx_wd_timer3_dma_addrs,
5977         .user           = OCP_USER_SDMA,
5978 };
5979
5980 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5981         &omap44xx_c2c__c2c_target_fw,
5982         &omap44xx_l4_cfg__c2c_target_fw,
5983         &omap44xx_l3_main_1__dmm,
5984         &omap44xx_mpu__dmm,
5985         &omap44xx_c2c__emif_fw,
5986         &omap44xx_dmm__emif_fw,
5987         &omap44xx_l4_cfg__emif_fw,
5988         &omap44xx_iva__l3_instr,
5989         &omap44xx_l3_main_3__l3_instr,
5990         &omap44xx_ocp_wp_noc__l3_instr,
5991         &omap44xx_dsp__l3_main_1,
5992         &omap44xx_dss__l3_main_1,
5993         &omap44xx_l3_main_2__l3_main_1,
5994         &omap44xx_l4_cfg__l3_main_1,
5995         &omap44xx_mmc1__l3_main_1,
5996         &omap44xx_mmc2__l3_main_1,
5997         &omap44xx_mpu__l3_main_1,
5998         &omap44xx_c2c_target_fw__l3_main_2,
5999         &omap44xx_debugss__l3_main_2,
6000         &omap44xx_dma_system__l3_main_2,
6001         &omap44xx_fdif__l3_main_2,
6002         &omap44xx_gpu__l3_main_2,
6003         &omap44xx_hsi__l3_main_2,
6004         &omap44xx_ipu__l3_main_2,
6005         &omap44xx_iss__l3_main_2,
6006         &omap44xx_iva__l3_main_2,
6007         &omap44xx_l3_main_1__l3_main_2,
6008         &omap44xx_l4_cfg__l3_main_2,
6009         /* &omap44xx_usb_host_fs__l3_main_2, */
6010         &omap44xx_usb_host_hs__l3_main_2,
6011         &omap44xx_usb_otg_hs__l3_main_2,
6012         &omap44xx_l3_main_1__l3_main_3,
6013         &omap44xx_l3_main_2__l3_main_3,
6014         &omap44xx_l4_cfg__l3_main_3,
6015         /* &omap44xx_aess__l4_abe, */
6016         &omap44xx_dsp__l4_abe,
6017         &omap44xx_l3_main_1__l4_abe,
6018         &omap44xx_mpu__l4_abe,
6019         &omap44xx_l3_main_1__l4_cfg,
6020         &omap44xx_l3_main_2__l4_per,
6021         &omap44xx_l4_cfg__l4_wkup,
6022         &omap44xx_mpu__mpu_private,
6023         &omap44xx_l4_cfg__ocp_wp_noc,
6024         /* &omap44xx_l4_abe__aess, */
6025         /* &omap44xx_l4_abe__aess_dma, */
6026         &omap44xx_l3_main_2__c2c,
6027         &omap44xx_l4_wkup__counter_32k,
6028         &omap44xx_l4_cfg__ctrl_module_core,
6029         &omap44xx_l4_cfg__ctrl_module_pad_core,
6030         &omap44xx_l4_wkup__ctrl_module_wkup,
6031         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6032         &omap44xx_l3_instr__debugss,
6033         &omap44xx_l4_cfg__dma_system,
6034         &omap44xx_l4_abe__dmic,
6035         &omap44xx_l4_abe__dmic_dma,
6036         &omap44xx_dsp__iva,
6037         /* &omap44xx_dsp__sl2if, */
6038         &omap44xx_l4_cfg__dsp,
6039         &omap44xx_l3_main_2__dss,
6040         &omap44xx_l4_per__dss,
6041         &omap44xx_l3_main_2__dss_dispc,
6042         &omap44xx_l4_per__dss_dispc,
6043         &omap44xx_l3_main_2__dss_dsi1,
6044         &omap44xx_l4_per__dss_dsi1,
6045         &omap44xx_l3_main_2__dss_dsi2,
6046         &omap44xx_l4_per__dss_dsi2,
6047         &omap44xx_l3_main_2__dss_hdmi,
6048         &omap44xx_l4_per__dss_hdmi,
6049         &omap44xx_l3_main_2__dss_rfbi,
6050         &omap44xx_l4_per__dss_rfbi,
6051         &omap44xx_l3_main_2__dss_venc,
6052         &omap44xx_l4_per__dss_venc,
6053         &omap44xx_l4_per__elm,
6054         &omap44xx_emif_fw__emif1,
6055         &omap44xx_emif_fw__emif2,
6056         &omap44xx_l4_cfg__fdif,
6057         &omap44xx_l4_wkup__gpio1,
6058         &omap44xx_l4_per__gpio2,
6059         &omap44xx_l4_per__gpio3,
6060         &omap44xx_l4_per__gpio4,
6061         &omap44xx_l4_per__gpio5,
6062         &omap44xx_l4_per__gpio6,
6063         &omap44xx_l3_main_2__gpmc,
6064         &omap44xx_l3_main_2__gpu,
6065         &omap44xx_l4_per__hdq1w,
6066         &omap44xx_l4_cfg__hsi,
6067         &omap44xx_l4_per__i2c1,
6068         &omap44xx_l4_per__i2c2,
6069         &omap44xx_l4_per__i2c3,
6070         &omap44xx_l4_per__i2c4,
6071         &omap44xx_l3_main_2__ipu,
6072         &omap44xx_l3_main_2__iss,
6073         /* &omap44xx_iva__sl2if, */
6074         &omap44xx_l3_main_2__iva,
6075         &omap44xx_l4_wkup__kbd,
6076         &omap44xx_l4_cfg__mailbox,
6077         &omap44xx_l4_abe__mcasp,
6078         &omap44xx_l4_abe__mcasp_dma,
6079         &omap44xx_l4_abe__mcbsp1,
6080         &omap44xx_l4_abe__mcbsp1_dma,
6081         &omap44xx_l4_abe__mcbsp2,
6082         &omap44xx_l4_abe__mcbsp2_dma,
6083         &omap44xx_l4_abe__mcbsp3,
6084         &omap44xx_l4_abe__mcbsp3_dma,
6085         &omap44xx_l4_per__mcbsp4,
6086         &omap44xx_l4_abe__mcpdm,
6087         &omap44xx_l4_abe__mcpdm_dma,
6088         &omap44xx_l4_per__mcspi1,
6089         &omap44xx_l4_per__mcspi2,
6090         &omap44xx_l4_per__mcspi3,
6091         &omap44xx_l4_per__mcspi4,
6092         &omap44xx_l4_per__mmc1,
6093         &omap44xx_l4_per__mmc2,
6094         &omap44xx_l4_per__mmc3,
6095         &omap44xx_l4_per__mmc4,
6096         &omap44xx_l4_per__mmc5,
6097         &omap44xx_l3_main_2__ocmc_ram,
6098         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6099         &omap44xx_mpu_private__prcm_mpu,
6100         &omap44xx_l4_wkup__cm_core_aon,
6101         &omap44xx_l4_cfg__cm_core,
6102         &omap44xx_l4_wkup__prm,
6103         &omap44xx_l4_wkup__scrm,
6104         /* &omap44xx_l3_main_2__sl2if, */
6105         &omap44xx_l4_abe__slimbus1,
6106         &omap44xx_l4_abe__slimbus1_dma,
6107         &omap44xx_l4_per__slimbus2,
6108         &omap44xx_l4_cfg__smartreflex_core,
6109         &omap44xx_l4_cfg__smartreflex_iva,
6110         &omap44xx_l4_cfg__smartreflex_mpu,
6111         &omap44xx_l4_cfg__spinlock,
6112         &omap44xx_l4_wkup__timer1,
6113         &omap44xx_l4_per__timer2,
6114         &omap44xx_l4_per__timer3,
6115         &omap44xx_l4_per__timer4,
6116         &omap44xx_l4_abe__timer5,
6117         &omap44xx_l4_abe__timer5_dma,
6118         &omap44xx_l4_abe__timer6,
6119         &omap44xx_l4_abe__timer6_dma,
6120         &omap44xx_l4_abe__timer7,
6121         &omap44xx_l4_abe__timer7_dma,
6122         &omap44xx_l4_abe__timer8,
6123         &omap44xx_l4_abe__timer8_dma,
6124         &omap44xx_l4_per__timer9,
6125         &omap44xx_l4_per__timer10,
6126         &omap44xx_l4_per__timer11,
6127         &omap44xx_l4_per__uart1,
6128         &omap44xx_l4_per__uart2,
6129         &omap44xx_l4_per__uart3,
6130         &omap44xx_l4_per__uart4,
6131         /* &omap44xx_l4_cfg__usb_host_fs, */
6132         &omap44xx_l4_cfg__usb_host_hs,
6133         &omap44xx_l4_cfg__usb_otg_hs,
6134         &omap44xx_l4_cfg__usb_tll_hs,
6135         &omap44xx_l4_wkup__wd_timer2,
6136         &omap44xx_l4_abe__wd_timer3,
6137         &omap44xx_l4_abe__wd_timer3_dma,
6138         NULL,
6139 };
6140
6141 int __init omap44xx_hwmod_init(void)
6142 {
6143         omap_hwmod_init();
6144         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6145 }
6146