arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24
  25 #include <plat/omap_hwmod.h>
  26 #include <plat/i2c.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'c2c_target_fw' class
  53  * instance(s): c2c_target_fw
  54  */
  55 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  56         .name   = "c2c_target_fw",
  57 };
  58
  59 /* c2c_target_fw */
  60 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  61         .name           = "c2c_target_fw",
  62         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  63         .clkdm_name     = "d2d_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  67                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'dmm' class
  74  * instance(s): dmm
  75  */
  76 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  77         .name   = "dmm",
  78 };
  79
  80 /* dmm */
  81 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  82         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  83         { .irq = -1 }
  84 };
  85
  86 static struct omap_hwmod omap44xx_dmm_hwmod = {
  87         .name           = "dmm",
  88         .class          = &omap44xx_dmm_hwmod_class,
  89         .clkdm_name     = "l3_emif_clkdm",
  90         .mpu_irqs       = omap44xx_dmm_irqs,
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  94                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  95                 },
  96         },
  97 };
  98
  99 /*
 100  * 'emif_fw' class
 101  * instance(s): emif_fw
 102  */
 103 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 104         .name   = "emif_fw",
 105 };
 106
 107 /* emif_fw */
 108 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 109         .name           = "emif_fw",
 110         .class          = &omap44xx_emif_fw_hwmod_class,
 111         .clkdm_name     = "l3_emif_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 115                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 116                 },
 117         },
 118 };
 119
 120 /*
 121  * 'l3' class
 122  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 123  */
 124 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 125         .name   = "l3",
 126 };
 127
 128 /* l3_instr */
 129 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 130         .name           = "l3_instr",
 131         .class          = &omap44xx_l3_hwmod_class,
 132         .clkdm_name     = "l3_instr_clkdm",
 133         .prcm = {
 134                 .omap4 = {
 135                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 136                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 137                         .modulemode   = MODULEMODE_HWCTRL,
 138                 },
 139         },
 140 };
 141
 142 /* l3_main_1 */
 143 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 144         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 145         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 146         { .irq = -1 }
 147 };
 148
 149 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 150         .name           = "l3_main_1",
 151         .class          = &omap44xx_l3_hwmod_class,
 152         .clkdm_name     = "l3_1_clkdm",
 153         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 154         .prcm = {
 155                 .omap4 = {
 156                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 157                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 158                 },
 159         },
 160 };
 161
 162 /* l3_main_2 */
 163 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 164         .name           = "l3_main_2",
 165         .class          = &omap44xx_l3_hwmod_class,
 166         .clkdm_name     = "l3_2_clkdm",
 167         .prcm = {
 168                 .omap4 = {
 169                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 170                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 171                 },
 172         },
 173 };
 174
 175 /* l3_main_3 */
 176 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 177         .name           = "l3_main_3",
 178         .class          = &omap44xx_l3_hwmod_class,
 179         .clkdm_name     = "l3_instr_clkdm",
 180         .prcm = {
 181                 .omap4 = {
 182                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 183                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 184                         .modulemode   = MODULEMODE_HWCTRL,
 185                 },
 186         },
 187 };
 188
 189 /*
 190  * 'l4' class
 191  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 192  */
 193 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 194         .name   = "l4",
 195 };
 196
 197 /* l4_abe */
 198 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 199         .name           = "l4_abe",
 200         .class          = &omap44xx_l4_hwmod_class,
 201         .clkdm_name     = "abe_clkdm",
 202         .prcm = {
 203                 .omap4 = {
 204                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 205                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 206                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 207                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 208                 },
 209         },
 210 };
 211
 212 /* l4_cfg */
 213 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 214         .name           = "l4_cfg",
 215         .class          = &omap44xx_l4_hwmod_class,
 216         .clkdm_name     = "l4_cfg_clkdm",
 217         .prcm = {
 218                 .omap4 = {
 219                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 220                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 221                 },
 222         },
 223 };
 224
 225 /* l4_per */
 226 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 227         .name           = "l4_per",
 228         .class          = &omap44xx_l4_hwmod_class,
 229         .clkdm_name     = "l4_per_clkdm",
 230         .prcm = {
 231                 .omap4 = {
 232                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 233                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 234                 },
 235         },
 236 };
 237
 238 /* l4_wkup */
 239 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 240         .name           = "l4_wkup",
 241         .class          = &omap44xx_l4_hwmod_class,
 242         .clkdm_name     = "l4_wkup_clkdm",
 243         .prcm = {
 244                 .omap4 = {
 245                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 246                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 247                 },
 248         },
 249 };
 250
 251 /*
 252  * 'mpu_bus' class
 253  * instance(s): mpu_private
 254  */
 255 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 256         .name   = "mpu_bus",
 257 };
 258
 259 /* mpu_private */
 260 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 261         .name           = "mpu_private",
 262         .class          = &omap44xx_mpu_bus_hwmod_class,
 263         .clkdm_name     = "mpuss_clkdm",
 264         .prcm = {
 265                 .omap4 = {
 266                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 267                 },
 268         },
 269 };
 270
 271 /*
 272  * 'ocp_wp_noc' class
 273  * instance(s): ocp_wp_noc
 274  */
 275 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 276         .name   = "ocp_wp_noc",
 277 };
 278
 279 /* ocp_wp_noc */
 280 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 281         .name           = "ocp_wp_noc",
 282         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 283         .clkdm_name     = "l3_instr_clkdm",
 284         .prcm = {
 285                 .omap4 = {
 286                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 287                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 288                         .modulemode   = MODULEMODE_HWCTRL,
 289                 },
 290         },
 291 };
 292
 293 /*
 294  * Modules omap_hwmod structures
 295  *
 296  * The following IPs are excluded for the moment because:
 297  * - They do not need an explicit SW control using omap_hwmod API.
 298  * - They still need to be validated with the driver
 299  *   properly adapted to omap_hwmod / omap_device
 300  *
 301  * usim
 302  */
 303
 304 /*
 305  * 'aess' class
 306  * audio engine sub system
 307  */
 308
 309 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 310         .rev_offs       = 0x0000,
 311         .sysc_offs      = 0x0010,
 312         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 313         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 314                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 315                            MSTANDBY_SMART_WKUP),
 316         .sysc_fields    = &omap_hwmod_sysc_type2,
 317 };
 318
 319 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 320         .name   = "aess",
 321         .sysc   = &omap44xx_aess_sysc,
 322 };
 323
 324 /* aess */
 325 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 326         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 327         { .irq = -1 }
 328 };
 329
 330 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 331         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 333         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 334         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 339         { .dma_req = -1 }
 340 };
 341
 342 static struct omap_hwmod omap44xx_aess_hwmod = {
 343         .name           = "aess",
 344         .class          = &omap44xx_aess_hwmod_class,
 345         .clkdm_name     = "abe_clkdm",
 346         .mpu_irqs       = omap44xx_aess_irqs,
 347         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 348         .main_clk       = "aess_fck",
 349         .prcm = {
 350                 .omap4 = {
 351                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 352                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 353                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 354                         .modulemode   = MODULEMODE_SWCTRL,
 355                 },
 356         },
 357 };
 358
 359 /*
 360  * 'c2c' class
 361  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 362  * soc
 363  */
 364
 365 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 366         .name   = "c2c",
 367 };
 368
 369 /* c2c */
 370 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 371         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 372         { .irq = -1 }
 373 };
 374
 375 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 376         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 377         { .dma_req = -1 }
 378 };
 379
 380 static struct omap_hwmod omap44xx_c2c_hwmod = {
 381         .name           = "c2c",
 382         .class          = &omap44xx_c2c_hwmod_class,
 383         .clkdm_name     = "d2d_clkdm",
 384         .mpu_irqs       = omap44xx_c2c_irqs,
 385         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 386         .prcm = {
 387                 .omap4 = {
 388                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 389                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 390                 },
 391         },
 392 };
 393
 394 /*
 395  * 'counter' class
 396  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 397  */
 398
 399 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 400         .rev_offs       = 0x0000,
 401         .sysc_offs      = 0x0004,
 402         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 403         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 404         .sysc_fields    = &omap_hwmod_sysc_type1,
 405 };
 406
 407 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 408         .name   = "counter",
 409         .sysc   = &omap44xx_counter_sysc,
 410 };
 411
 412 /* counter_32k */
 413 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 414         .name           = "counter_32k",
 415         .class          = &omap44xx_counter_hwmod_class,
 416         .clkdm_name     = "l4_wkup_clkdm",
 417         .flags          = HWMOD_SWSUP_SIDLE,
 418         .main_clk       = "sys_32k_ck",
 419         .prcm = {
 420                 .omap4 = {
 421                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 422                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 423                 },
 424         },
 425 };
 426
 427 /*
 428  * 'ctrl_module' class
 429  * attila core control module + core pad control module + wkup pad control
 430  * module + attila wkup control module
 431  */
 432
 433 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 434         .rev_offs       = 0x0000,
 435         .sysc_offs      = 0x0010,
 436         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 437         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 438                            SIDLE_SMART_WKUP),
 439         .sysc_fields    = &omap_hwmod_sysc_type2,
 440 };
 441
 442 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 443         .name   = "ctrl_module",
 444         .sysc   = &omap44xx_ctrl_module_sysc,
 445 };
 446
 447 /* ctrl_module_core */
 448 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 449         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 450         { .irq = -1 }
 451 };
 452
 453 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 454         .name           = "ctrl_module_core",
 455         .class          = &omap44xx_ctrl_module_hwmod_class,
 456         .clkdm_name     = "l4_cfg_clkdm",
 457         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 458         .prcm = {
 459                 .omap4 = {
 460                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 461                 },
 462         },
 463 };
 464
 465 /* ctrl_module_pad_core */
 466 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 467         .name           = "ctrl_module_pad_core",
 468         .class          = &omap44xx_ctrl_module_hwmod_class,
 469         .clkdm_name     = "l4_cfg_clkdm",
 470         .prcm = {
 471                 .omap4 = {
 472                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 473                 },
 474         },
 475 };
 476
 477 /* ctrl_module_wkup */
 478 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 479         .name           = "ctrl_module_wkup",
 480         .class          = &omap44xx_ctrl_module_hwmod_class,
 481         .clkdm_name     = "l4_wkup_clkdm",
 482         .prcm = {
 483                 .omap4 = {
 484                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 485                 },
 486         },
 487 };
 488
 489 /* ctrl_module_pad_wkup */
 490 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 491         .name           = "ctrl_module_pad_wkup",
 492         .class          = &omap44xx_ctrl_module_hwmod_class,
 493         .clkdm_name     = "l4_wkup_clkdm",
 494         .prcm = {
 495                 .omap4 = {
 496                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 497                 },
 498         },
 499 };
 500
 501 /*
 502  * 'debugss' class
 503  * debug and emulation sub system
 504  */
 505
 506 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 507         .name   = "debugss",
 508 };
 509
 510 /* debugss */
 511 static struct omap_hwmod omap44xx_debugss_hwmod = {
 512         .name           = "debugss",
 513         .class          = &omap44xx_debugss_hwmod_class,
 514         .clkdm_name     = "emu_sys_clkdm",
 515         .main_clk       = "trace_clk_div_ck",
 516         .prcm = {
 517                 .omap4 = {
 518                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 519                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 520                 },
 521         },
 522 };
 523
 524 /*
 525  * 'dma' class
 526  * dma controller for data exchange between memory to memory (i.e. internal or
 527  * external memory) and gp peripherals to memory or memory to gp peripherals
 528  */
 529
 530 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 531         .rev_offs       = 0x0000,
 532         .sysc_offs      = 0x002c,
 533         .syss_offs      = 0x0028,
 534         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 535                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 536                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 537                            SYSS_HAS_RESET_STATUS),
 538         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 539                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 540         .sysc_fields    = &omap_hwmod_sysc_type1,
 541 };
 542
 543 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 544         .name   = "dma",
 545         .sysc   = &omap44xx_dma_sysc,
 546 };
 547
 548 /* dma dev_attr */
 549 static struct omap_dma_dev_attr dma_dev_attr = {
 550         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 551                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 552         .lch_count      = 32,
 553 };
 554
 555 /* dma_system */
 556 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 557         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 558         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 559         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 560         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 561         { .irq = -1 }
 562 };
 563
 564 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 565         .name           = "dma_system",
 566         .class          = &omap44xx_dma_hwmod_class,
 567         .clkdm_name     = "l3_dma_clkdm",
 568         .mpu_irqs       = omap44xx_dma_system_irqs,
 569         .main_clk       = "l3_div_ck",
 570         .prcm = {
 571                 .omap4 = {
 572                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 573                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 574                 },
 575         },
 576         .dev_attr       = &dma_dev_attr,
 577 };
 578
 579 /*
 580  * 'dmic' class
 581  * digital microphone controller
 582  */
 583
 584 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 585         .rev_offs       = 0x0000,
 586         .sysc_offs      = 0x0010,
 587         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 588                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 589         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 590                            SIDLE_SMART_WKUP),
 591         .sysc_fields    = &omap_hwmod_sysc_type2,
 592 };
 593
 594 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 595         .name   = "dmic",
 596         .sysc   = &omap44xx_dmic_sysc,
 597 };
 598
 599 /* dmic */
 600 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 601         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 602         { .irq = -1 }
 603 };
 604
 605 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 606         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 607         { .dma_req = -1 }
 608 };
 609
 610 static struct omap_hwmod omap44xx_dmic_hwmod = {
 611         .name           = "dmic",
 612         .class          = &omap44xx_dmic_hwmod_class,
 613         .clkdm_name     = "abe_clkdm",
 614         .mpu_irqs       = omap44xx_dmic_irqs,
 615         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 616         .main_clk       = "dmic_fck",
 617         .prcm = {
 618                 .omap4 = {
 619                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 620                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 621                         .modulemode   = MODULEMODE_SWCTRL,
 622                 },
 623         },
 624 };
 625
 626 /*
 627  * 'dsp' class
 628  * dsp sub-system
 629  */
 630
 631 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 632         .name   = "dsp",
 633 };
 634
 635 /* dsp */
 636 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 637         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 638         { .irq = -1 }
 639 };
 640
 641 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 642         { .name = "dsp", .rst_shift = 0 },
 643         { .name = "mmu_cache", .rst_shift = 1 },
 644 };
 645
 646 static struct omap_hwmod omap44xx_dsp_hwmod = {
 647         .name           = "dsp",
 648         .class          = &omap44xx_dsp_hwmod_class,
 649         .clkdm_name     = "tesla_clkdm",
 650         .mpu_irqs       = omap44xx_dsp_irqs,
 651         .rst_lines      = omap44xx_dsp_resets,
 652         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 653         .main_clk       = "dsp_fck",
 654         .prcm = {
 655                 .omap4 = {
 656                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 657                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 658                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 659                         .modulemode   = MODULEMODE_HWCTRL,
 660                 },
 661         },
 662 };
 663
 664 /*
 665  * 'dss' class
 666  * display sub-system
 667  */
 668
 669 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 670         .rev_offs       = 0x0000,
 671         .syss_offs      = 0x0014,
 672         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 673 };
 674
 675 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 676         .name   = "dss",
 677         .sysc   = &omap44xx_dss_sysc,
 678         .reset  = omap_dss_reset,
 679 };
 680
 681 /* dss */
 682 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 683         { .role = "sys_clk", .clk = "dss_sys_clk" },
 684         { .role = "tv_clk", .clk = "dss_tv_clk" },
 685         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 686 };
 687
 688 static struct omap_hwmod omap44xx_dss_hwmod = {
 689         .name           = "dss_core",
 690         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 691         .class          = &omap44xx_dss_hwmod_class,
 692         .clkdm_name     = "l3_dss_clkdm",
 693         .main_clk       = "dss_dss_clk",
 694         .prcm = {
 695                 .omap4 = {
 696                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 697                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 698                 },
 699         },
 700         .opt_clks       = dss_opt_clks,
 701         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 702 };
 703
 704 /*
 705  * 'dispc' class
 706  * display controller
 707  */
 708
 709 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 710         .rev_offs       = 0x0000,
 711         .sysc_offs      = 0x0010,
 712         .syss_offs      = 0x0014,
 713         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 714                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 715                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 716                            SYSS_HAS_RESET_STATUS),
 717         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 718                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 719         .sysc_fields    = &omap_hwmod_sysc_type1,
 720 };
 721
 722 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 723         .name   = "dispc",
 724         .sysc   = &omap44xx_dispc_sysc,
 725 };
 726
 727 /* dss_dispc */
 728 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 729         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 730         { .irq = -1 }
 731 };
 732
 733 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 734         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 735         { .dma_req = -1 }
 736 };
 737
 738 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 739         .manager_count          = 3,
 740         .has_framedonetv_irq    = 1
 741 };
 742
 743 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 744         .name           = "dss_dispc",
 745         .class          = &omap44xx_dispc_hwmod_class,
 746         .clkdm_name     = "l3_dss_clkdm",
 747         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 748         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 749         .main_clk       = "dss_dss_clk",
 750         .prcm = {
 751                 .omap4 = {
 752                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 753                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 754                 },
 755         },
 756         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 757 };
 758
 759 /*
 760  * 'dsi' class
 761  * display serial interface controller
 762  */
 763
 764 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 765         .rev_offs       = 0x0000,
 766         .sysc_offs      = 0x0010,
 767         .syss_offs      = 0x0014,
 768         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 769                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 770                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 771         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 772         .sysc_fields    = &omap_hwmod_sysc_type1,
 773 };
 774
 775 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 776         .name   = "dsi",
 777         .sysc   = &omap44xx_dsi_sysc,
 778 };
 779
 780 /* dss_dsi1 */
 781 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 782         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 783         { .irq = -1 }
 784 };
 785
 786 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 787         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 788         { .dma_req = -1 }
 789 };
 790
 791 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 792         { .role = "sys_clk", .clk = "dss_sys_clk" },
 793 };
 794
 795 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 796         .name           = "dss_dsi1",
 797         .class          = &omap44xx_dsi_hwmod_class,
 798         .clkdm_name     = "l3_dss_clkdm",
 799         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 800         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 801         .main_clk       = "dss_dss_clk",
 802         .prcm = {
 803                 .omap4 = {
 804                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 805                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 806                 },
 807         },
 808         .opt_clks       = dss_dsi1_opt_clks,
 809         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 810 };
 811
 812 /* dss_dsi2 */
 813 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 814         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 815         { .irq = -1 }
 816 };
 817
 818 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 819         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 820         { .dma_req = -1 }
 821 };
 822
 823 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 824         { .role = "sys_clk", .clk = "dss_sys_clk" },
 825 };
 826
 827 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 828         .name           = "dss_dsi2",
 829         .class          = &omap44xx_dsi_hwmod_class,
 830         .clkdm_name     = "l3_dss_clkdm",
 831         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 832         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 833         .main_clk       = "dss_dss_clk",
 834         .prcm = {
 835                 .omap4 = {
 836                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 837                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 838                 },
 839         },
 840         .opt_clks       = dss_dsi2_opt_clks,
 841         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 842 };
 843
 844 /*
 845  * 'hdmi' class
 846  * hdmi controller
 847  */
 848
 849 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 850         .rev_offs       = 0x0000,
 851         .sysc_offs      = 0x0010,
 852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 853                            SYSC_HAS_SOFTRESET),
 854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 855                            SIDLE_SMART_WKUP),
 856         .sysc_fields    = &omap_hwmod_sysc_type2,
 857 };
 858
 859 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 860         .name   = "hdmi",
 861         .sysc   = &omap44xx_hdmi_sysc,
 862 };
 863
 864 /* dss_hdmi */
 865 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 866         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 867         { .irq = -1 }
 868 };
 869
 870 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 871         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 872         { .dma_req = -1 }
 873 };
 874
 875 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 876         { .role = "sys_clk", .clk = "dss_sys_clk" },
 877 };
 878
 879 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 880         .name           = "dss_hdmi",
 881         .class          = &omap44xx_hdmi_hwmod_class,
 882         .clkdm_name     = "l3_dss_clkdm",
 883         /*
 884          * HDMI audio requires to use no-idle mode. Hence,
 885          * set idle mode by software.
 886          */
 887         .flags          = HWMOD_SWSUP_SIDLE,
 888         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 889         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 890         .main_clk       = "dss_48mhz_clk",
 891         .prcm = {
 892                 .omap4 = {
 893                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 894                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 895                 },
 896         },
 897         .opt_clks       = dss_hdmi_opt_clks,
 898         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 899 };
 900
 901 /*
 902  * 'rfbi' class
 903  * remote frame buffer interface
 904  */
 905
 906 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 907         .rev_offs       = 0x0000,
 908         .sysc_offs      = 0x0010,
 909         .syss_offs      = 0x0014,
 910         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 911                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 912         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 913         .sysc_fields    = &omap_hwmod_sysc_type1,
 914 };
 915
 916 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 917         .name   = "rfbi",
 918         .sysc   = &omap44xx_rfbi_sysc,
 919 };
 920
 921 /* dss_rfbi */
 922 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 923         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 924         { .dma_req = -1 }
 925 };
 926
 927 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 928         { .role = "ick", .clk = "dss_fck" },
 929 };
 930
 931 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 932         .name           = "dss_rfbi",
 933         .class          = &omap44xx_rfbi_hwmod_class,
 934         .clkdm_name     = "l3_dss_clkdm",
 935         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 936         .main_clk       = "dss_dss_clk",
 937         .prcm = {
 938                 .omap4 = {
 939                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 940                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 941                 },
 942         },
 943         .opt_clks       = dss_rfbi_opt_clks,
 944         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 945 };
 946
 947 /*
 948  * 'venc' class
 949  * video encoder
 950  */
 951
 952 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 953         .name   = "venc",
 954 };
 955
 956 /* dss_venc */
 957 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 958         .name           = "dss_venc",
 959         .class          = &omap44xx_venc_hwmod_class,
 960         .clkdm_name     = "l3_dss_clkdm",
 961         .main_clk       = "dss_tv_clk",
 962         .prcm = {
 963                 .omap4 = {
 964                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 965                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 966                 },
 967         },
 968 };
 969
 970 /*
 971  * 'elm' class
 972  * bch error location module
 973  */
 974
 975 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 976         .rev_offs       = 0x0000,
 977         .sysc_offs      = 0x0010,
 978         .syss_offs      = 0x0014,
 979         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 980                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 981                            SYSS_HAS_RESET_STATUS),
 982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 983         .sysc_fields    = &omap_hwmod_sysc_type1,
 984 };
 985
 986 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 987         .name   = "elm",
 988         .sysc   = &omap44xx_elm_sysc,
 989 };
 990
 991 /* elm */
 992 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 993         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 994         { .irq = -1 }
 995 };
 996
 997 static struct omap_hwmod omap44xx_elm_hwmod = {
 998         .name           = "elm",
 999         .class          = &omap44xx_elm_hwmod_class,
1000         .clkdm_name     = "l4_per_clkdm",
1001         .mpu_irqs       = omap44xx_elm_irqs,
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1005                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1006                 },
1007         },
1008 };
1009
1010 /*
1011  * 'emif' class
1012  * external memory interface no1
1013  */
1014
1015 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1016         .rev_offs       = 0x0000,
1017 };
1018
1019 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1020         .name   = "emif",
1021         .sysc   = &omap44xx_emif_sysc,
1022 };
1023
1024 /* emif1 */
1025 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1026         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1027         { .irq = -1 }
1028 };
1029
1030 static struct omap_hwmod omap44xx_emif1_hwmod = {
1031         .name           = "emif1",
1032         .class          = &omap44xx_emif_hwmod_class,
1033         .clkdm_name     = "l3_emif_clkdm",
1034         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1035         .mpu_irqs       = omap44xx_emif1_irqs,
1036         .main_clk       = "ddrphy_ck",
1037         .prcm = {
1038                 .omap4 = {
1039                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1040                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1041                         .modulemode   = MODULEMODE_HWCTRL,
1042                 },
1043         },
1044 };
1045
1046 /* emif2 */
1047 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1048         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1049         { .irq = -1 }
1050 };
1051
1052 static struct omap_hwmod omap44xx_emif2_hwmod = {
1053         .name           = "emif2",
1054         .class          = &omap44xx_emif_hwmod_class,
1055         .clkdm_name     = "l3_emif_clkdm",
1056         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1057         .mpu_irqs       = omap44xx_emif2_irqs,
1058         .main_clk       = "ddrphy_ck",
1059         .prcm = {
1060                 .omap4 = {
1061                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1062                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1063                         .modulemode   = MODULEMODE_HWCTRL,
1064                 },
1065         },
1066 };
1067
1068 /*
1069  * 'fdif' class
1070  * face detection hw accelerator module
1071  */
1072
1073 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1074         .rev_offs       = 0x0000,
1075         .sysc_offs      = 0x0010,
1076         /*
1077          * FDIF needs 100 OCP clk cycles delay after a softreset before
1078          * accessing sysconfig again.
1079          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1080          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1081          *
1082          * TODO: Indicate errata when available.
1083          */
1084         .srst_udelay    = 2,
1085         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1086                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089         .sysc_fields    = &omap_hwmod_sysc_type2,
1090 };
1091
1092 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1093         .name   = "fdif",
1094         .sysc   = &omap44xx_fdif_sysc,
1095 };
1096
1097 /* fdif */
1098 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1099         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1100         { .irq = -1 }
1101 };
1102
1103 static struct omap_hwmod omap44xx_fdif_hwmod = {
1104         .name           = "fdif",
1105         .class          = &omap44xx_fdif_hwmod_class,
1106         .clkdm_name     = "iss_clkdm",
1107         .mpu_irqs       = omap44xx_fdif_irqs,
1108         .main_clk       = "fdif_fck",
1109         .prcm = {
1110                 .omap4 = {
1111                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1112                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1113                         .modulemode   = MODULEMODE_SWCTRL,
1114                 },
1115         },
1116 };
1117
1118 /*
1119  * 'gpio' class
1120  * general purpose io module
1121  */
1122
1123 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1124         .rev_offs       = 0x0000,
1125         .sysc_offs      = 0x0010,
1126         .syss_offs      = 0x0114,
1127         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1128                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1129                            SYSS_HAS_RESET_STATUS),
1130         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1131                            SIDLE_SMART_WKUP),
1132         .sysc_fields    = &omap_hwmod_sysc_type1,
1133 };
1134
1135 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1136         .name   = "gpio",
1137         .sysc   = &omap44xx_gpio_sysc,
1138         .rev    = 2,
1139 };
1140
1141 /* gpio dev_attr */
1142 static struct omap_gpio_dev_attr gpio_dev_attr = {
1143         .bank_width     = 32,
1144         .dbck_flag      = true,
1145 };
1146
1147 /* gpio1 */
1148 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1149         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1150         { .irq = -1 }
1151 };
1152
1153 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1154         { .role = "dbclk", .clk = "gpio1_dbclk" },
1155 };
1156
1157 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1158         .name           = "gpio1",
1159         .class          = &omap44xx_gpio_hwmod_class,
1160         .clkdm_name     = "l4_wkup_clkdm",
1161         .mpu_irqs       = omap44xx_gpio1_irqs,
1162         .main_clk       = "gpio1_ick",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1166                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_HWCTRL,
1168                 },
1169         },
1170         .opt_clks       = gpio1_opt_clks,
1171         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1172         .dev_attr       = &gpio_dev_attr,
1173 };
1174
1175 /* gpio2 */
1176 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1177         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1178         { .irq = -1 }
1179 };
1180
1181 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1182         { .role = "dbclk", .clk = "gpio2_dbclk" },
1183 };
1184
1185 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1186         .name           = "gpio2",
1187         .class          = &omap44xx_gpio_hwmod_class,
1188         .clkdm_name     = "l4_per_clkdm",
1189         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190         .mpu_irqs       = omap44xx_gpio2_irqs,
1191         .main_clk       = "gpio2_ick",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1195                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_HWCTRL,
1197                 },
1198         },
1199         .opt_clks       = gpio2_opt_clks,
1200         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1201         .dev_attr       = &gpio_dev_attr,
1202 };
1203
1204 /* gpio3 */
1205 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1206         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1207         { .irq = -1 }
1208 };
1209
1210 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1211         { .role = "dbclk", .clk = "gpio3_dbclk" },
1212 };
1213
1214 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1215         .name           = "gpio3",
1216         .class          = &omap44xx_gpio_hwmod_class,
1217         .clkdm_name     = "l4_per_clkdm",
1218         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1219         .mpu_irqs       = omap44xx_gpio3_irqs,
1220         .main_clk       = "gpio3_ick",
1221         .prcm = {
1222                 .omap4 = {
1223                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1224                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1225                         .modulemode   = MODULEMODE_HWCTRL,
1226                 },
1227         },
1228         .opt_clks       = gpio3_opt_clks,
1229         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1230         .dev_attr       = &gpio_dev_attr,
1231 };
1232
1233 /* gpio4 */
1234 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1235         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1236         { .irq = -1 }
1237 };
1238
1239 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1240         { .role = "dbclk", .clk = "gpio4_dbclk" },
1241 };
1242
1243 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1244         .name           = "gpio4",
1245         .class          = &omap44xx_gpio_hwmod_class,
1246         .clkdm_name     = "l4_per_clkdm",
1247         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1248         .mpu_irqs       = omap44xx_gpio4_irqs,
1249         .main_clk       = "gpio4_ick",
1250         .prcm = {
1251                 .omap4 = {
1252                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1253                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1254                         .modulemode   = MODULEMODE_HWCTRL,
1255                 },
1256         },
1257         .opt_clks       = gpio4_opt_clks,
1258         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1259         .dev_attr       = &gpio_dev_attr,
1260 };
1261
1262 /* gpio5 */
1263 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1264         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1265         { .irq = -1 }
1266 };
1267
1268 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1269         { .role = "dbclk", .clk = "gpio5_dbclk" },
1270 };
1271
1272 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1273         .name           = "gpio5",
1274         .class          = &omap44xx_gpio_hwmod_class,
1275         .clkdm_name     = "l4_per_clkdm",
1276         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1277         .mpu_irqs       = omap44xx_gpio5_irqs,
1278         .main_clk       = "gpio5_ick",
1279         .prcm = {
1280                 .omap4 = {
1281                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1282                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1283                         .modulemode   = MODULEMODE_HWCTRL,
1284                 },
1285         },
1286         .opt_clks       = gpio5_opt_clks,
1287         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1288         .dev_attr       = &gpio_dev_attr,
1289 };
1290
1291 /* gpio6 */
1292 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1293         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1294         { .irq = -1 }
1295 };
1296
1297 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1298         { .role = "dbclk", .clk = "gpio6_dbclk" },
1299 };
1300
1301 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1302         .name           = "gpio6",
1303         .class          = &omap44xx_gpio_hwmod_class,
1304         .clkdm_name     = "l4_per_clkdm",
1305         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1306         .mpu_irqs       = omap44xx_gpio6_irqs,
1307         .main_clk       = "gpio6_ick",
1308         .prcm = {
1309                 .omap4 = {
1310                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1311                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1312                         .modulemode   = MODULEMODE_HWCTRL,
1313                 },
1314         },
1315         .opt_clks       = gpio6_opt_clks,
1316         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1317         .dev_attr       = &gpio_dev_attr,
1318 };
1319
1320 /*
1321  * 'gpmc' class
1322  * general purpose memory controller
1323  */
1324
1325 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1326         .rev_offs       = 0x0000,
1327         .sysc_offs      = 0x0010,
1328         .syss_offs      = 0x0014,
1329         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1330                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1331         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1332         .sysc_fields    = &omap_hwmod_sysc_type1,
1333 };
1334
1335 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1336         .name   = "gpmc",
1337         .sysc   = &omap44xx_gpmc_sysc,
1338 };
1339
1340 /* gpmc */
1341 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1342         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1343         { .irq = -1 }
1344 };
1345
1346 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1347         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1348         { .dma_req = -1 }
1349 };
1350
1351 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1352         .name           = "gpmc",
1353         .class          = &omap44xx_gpmc_hwmod_class,
1354         .clkdm_name     = "l3_2_clkdm",
1355         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1356         .mpu_irqs       = omap44xx_gpmc_irqs,
1357         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1358         .prcm = {
1359                 .omap4 = {
1360                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1361                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1362                         .modulemode   = MODULEMODE_HWCTRL,
1363                 },
1364         },
1365 };
1366
1367 /*
1368  * 'gpu' class
1369  * 2d/3d graphics accelerator
1370  */
1371
1372 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1373         .rev_offs       = 0x1fc00,
1374         .sysc_offs      = 0x1fc10,
1375         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1376         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1377                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1378                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1379         .sysc_fields    = &omap_hwmod_sysc_type2,
1380 };
1381
1382 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1383         .name   = "gpu",
1384         .sysc   = &omap44xx_gpu_sysc,
1385 };
1386
1387 /* gpu */
1388 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1389         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1390         { .irq = -1 }
1391 };
1392
1393 static struct omap_hwmod omap44xx_gpu_hwmod = {
1394         .name           = "gpu",
1395         .class          = &omap44xx_gpu_hwmod_class,
1396         .clkdm_name     = "l3_gfx_clkdm",
1397         .mpu_irqs       = omap44xx_gpu_irqs,
1398         .main_clk       = "gpu_fck",
1399         .prcm = {
1400                 .omap4 = {
1401                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1402                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1403                         .modulemode   = MODULEMODE_SWCTRL,
1404                 },
1405         },
1406 };
1407
1408 /*
1409  * 'hdq1w' class
1410  * hdq / 1-wire serial interface controller
1411  */
1412
1413 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1414         .rev_offs       = 0x0000,
1415         .sysc_offs      = 0x0014,
1416         .syss_offs      = 0x0018,
1417         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1418                            SYSS_HAS_RESET_STATUS),
1419         .sysc_fields    = &omap_hwmod_sysc_type1,
1420 };
1421
1422 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1423         .name   = "hdq1w",
1424         .sysc   = &omap44xx_hdq1w_sysc,
1425 };
1426
1427 /* hdq1w */
1428 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1429         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1430         { .irq = -1 }
1431 };
1432
1433 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1434         .name           = "hdq1w",
1435         .class          = &omap44xx_hdq1w_hwmod_class,
1436         .clkdm_name     = "l4_per_clkdm",
1437         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1438         .mpu_irqs       = omap44xx_hdq1w_irqs,
1439         .main_clk       = "hdq1w_fck",
1440         .prcm = {
1441                 .omap4 = {
1442                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1443                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1444                         .modulemode   = MODULEMODE_SWCTRL,
1445                 },
1446         },
1447 };
1448
1449 /*
1450  * 'hsi' class
1451  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1452  * serial if)
1453  */
1454
1455 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1456         .rev_offs       = 0x0000,
1457         .sysc_offs      = 0x0010,
1458         .syss_offs      = 0x0014,
1459         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1460                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1461                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1462         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1463                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1464                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1465         .sysc_fields    = &omap_hwmod_sysc_type1,
1466 };
1467
1468 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1469         .name   = "hsi",
1470         .sysc   = &omap44xx_hsi_sysc,
1471 };
1472
1473 /* hsi */
1474 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1475         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1476         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1477         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1478         { .irq = -1 }
1479 };
1480
1481 static struct omap_hwmod omap44xx_hsi_hwmod = {
1482         .name           = "hsi",
1483         .class          = &omap44xx_hsi_hwmod_class,
1484         .clkdm_name     = "l3_init_clkdm",
1485         .mpu_irqs       = omap44xx_hsi_irqs,
1486         .main_clk       = "hsi_fck",
1487         .prcm = {
1488                 .omap4 = {
1489                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1490                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1491                         .modulemode   = MODULEMODE_HWCTRL,
1492                 },
1493         },
1494 };
1495
1496 /*
1497  * 'i2c' class
1498  * multimaster high-speed i2c controller
1499  */
1500
1501 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1502         .sysc_offs      = 0x0010,
1503         .syss_offs      = 0x0090,
1504         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1505                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1506                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1507         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1508                            SIDLE_SMART_WKUP),
1509         .clockact       = CLOCKACT_TEST_ICLK,
1510         .sysc_fields    = &omap_hwmod_sysc_type1,
1511 };
1512
1513 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1514         .name   = "i2c",
1515         .sysc   = &omap44xx_i2c_sysc,
1516         .rev    = OMAP_I2C_IP_VERSION_2,
1517         .reset  = &omap_i2c_reset,
1518 };
1519
1520 static struct omap_i2c_dev_attr i2c_dev_attr = {
1521         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1522                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1523 };
1524
1525 /* i2c1 */
1526 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1527         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1528         { .irq = -1 }
1529 };
1530
1531 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1532         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1533         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1534         { .dma_req = -1 }
1535 };
1536
1537 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1538         .name           = "i2c1",
1539         .class          = &omap44xx_i2c_hwmod_class,
1540         .clkdm_name     = "l4_per_clkdm",
1541         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1542         .mpu_irqs       = omap44xx_i2c1_irqs,
1543         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1544         .main_clk       = "i2c1_fck",
1545         .prcm = {
1546                 .omap4 = {
1547                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1548                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1549                         .modulemode   = MODULEMODE_SWCTRL,
1550                 },
1551         },
1552         .dev_attr       = &i2c_dev_attr,
1553 };
1554
1555 /* i2c2 */
1556 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1557         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1558         { .irq = -1 }
1559 };
1560
1561 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1562         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1563         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1564         { .dma_req = -1 }
1565 };
1566
1567 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1568         .name           = "i2c2",
1569         .class          = &omap44xx_i2c_hwmod_class,
1570         .clkdm_name     = "l4_per_clkdm",
1571         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1572         .mpu_irqs       = omap44xx_i2c2_irqs,
1573         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1574         .main_clk       = "i2c2_fck",
1575         .prcm = {
1576                 .omap4 = {
1577                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1578                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1579                         .modulemode   = MODULEMODE_SWCTRL,
1580                 },
1581         },
1582         .dev_attr       = &i2c_dev_attr,
1583 };
1584
1585 /* i2c3 */
1586 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1587         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1588         { .irq = -1 }
1589 };
1590
1591 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1592         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1593         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1594         { .dma_req = -1 }
1595 };
1596
1597 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1598         .name           = "i2c3",
1599         .class          = &omap44xx_i2c_hwmod_class,
1600         .clkdm_name     = "l4_per_clkdm",
1601         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1602         .mpu_irqs       = omap44xx_i2c3_irqs,
1603         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1604         .main_clk       = "i2c3_fck",
1605         .prcm = {
1606                 .omap4 = {
1607                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1608                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1609                         .modulemode   = MODULEMODE_SWCTRL,
1610                 },
1611         },
1612         .dev_attr       = &i2c_dev_attr,
1613 };
1614
1615 /* i2c4 */
1616 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1617         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1618         { .irq = -1 }
1619 };
1620
1621 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1622         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1623         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1624         { .dma_req = -1 }
1625 };
1626
1627 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1628         .name           = "i2c4",
1629         .class          = &omap44xx_i2c_hwmod_class,
1630         .clkdm_name     = "l4_per_clkdm",
1631         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1632         .mpu_irqs       = omap44xx_i2c4_irqs,
1633         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1634         .main_clk       = "i2c4_fck",
1635         .prcm = {
1636                 .omap4 = {
1637                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1638                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1639                         .modulemode   = MODULEMODE_SWCTRL,
1640                 },
1641         },
1642         .dev_attr       = &i2c_dev_attr,
1643 };
1644
1645 /*
1646  * 'ipu' class
1647  * imaging processor unit
1648  */
1649
1650 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1651         .name   = "ipu",
1652 };
1653
1654 /* ipu */
1655 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1656         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1657         { .irq = -1 }
1658 };
1659
1660 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1661         { .name = "cpu0", .rst_shift = 0 },
1662         { .name = "cpu1", .rst_shift = 1 },
1663         { .name = "mmu_cache", .rst_shift = 2 },
1664 };
1665
1666 static struct omap_hwmod omap44xx_ipu_hwmod = {
1667         .name           = "ipu",
1668         .class          = &omap44xx_ipu_hwmod_class,
1669         .clkdm_name     = "ducati_clkdm",
1670         .mpu_irqs       = omap44xx_ipu_irqs,
1671         .rst_lines      = omap44xx_ipu_resets,
1672         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1673         .main_clk       = "ipu_fck",
1674         .prcm = {
1675                 .omap4 = {
1676                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1677                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1678                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1679                         .modulemode   = MODULEMODE_HWCTRL,
1680                 },
1681         },
1682 };
1683
1684 /*
1685  * 'iss' class
1686  * external images sensor pixel data processor
1687  */
1688
1689 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1690         .rev_offs       = 0x0000,
1691         .sysc_offs      = 0x0010,
1692         /*
1693          * ISS needs 100 OCP clk cycles delay after a softreset before
1694          * accessing sysconfig again.
1695          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1696          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1697          *
1698          * TODO: Indicate errata when available.
1699          */
1700         .srst_udelay    = 2,
1701         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1702                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1703         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1704                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1705                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1706         .sysc_fields    = &omap_hwmod_sysc_type2,
1707 };
1708
1709 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1710         .name   = "iss",
1711         .sysc   = &omap44xx_iss_sysc,
1712 };
1713
1714 /* iss */
1715 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1716         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1717         { .irq = -1 }
1718 };
1719
1720 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1721         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1722         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1723         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1724         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1725         { .dma_req = -1 }
1726 };
1727
1728 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1729         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1730 };
1731
1732 static struct omap_hwmod omap44xx_iss_hwmod = {
1733         .name           = "iss",
1734         .class          = &omap44xx_iss_hwmod_class,
1735         .clkdm_name     = "iss_clkdm",
1736         .mpu_irqs       = omap44xx_iss_irqs,
1737         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1738         .main_clk       = "iss_fck",
1739         .prcm = {
1740                 .omap4 = {
1741                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1742                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1743                         .modulemode   = MODULEMODE_SWCTRL,
1744                 },
1745         },
1746         .opt_clks       = iss_opt_clks,
1747         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1748 };
1749
1750 /*
1751  * 'iva' class
1752  * multi-standard video encoder/decoder hardware accelerator
1753  */
1754
1755 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1756         .name   = "iva",
1757 };
1758
1759 /* iva */
1760 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1761         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1762         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1763         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1764         { .irq = -1 }
1765 };
1766
1767 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1768         { .name = "seq0", .rst_shift = 0 },
1769         { .name = "seq1", .rst_shift = 1 },
1770         { .name = "logic", .rst_shift = 2 },
1771 };
1772
1773 static struct omap_hwmod omap44xx_iva_hwmod = {
1774         .name           = "iva",
1775         .class          = &omap44xx_iva_hwmod_class,
1776         .clkdm_name     = "ivahd_clkdm",
1777         .mpu_irqs       = omap44xx_iva_irqs,
1778         .rst_lines      = omap44xx_iva_resets,
1779         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1780         .main_clk       = "iva_fck",
1781         .prcm = {
1782                 .omap4 = {
1783                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1784                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1785                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1786                         .modulemode   = MODULEMODE_HWCTRL,
1787                 },
1788         },
1789 };
1790
1791 /*
1792  * 'kbd' class
1793  * keyboard controller
1794  */
1795
1796 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1797         .rev_offs       = 0x0000,
1798         .sysc_offs      = 0x0010,
1799         .syss_offs      = 0x0014,
1800         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1801                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1802                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1803                            SYSS_HAS_RESET_STATUS),
1804         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1805         .sysc_fields    = &omap_hwmod_sysc_type1,
1806 };
1807
1808 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1809         .name   = "kbd",
1810         .sysc   = &omap44xx_kbd_sysc,
1811 };
1812
1813 /* kbd */
1814 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1815         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1816         { .irq = -1 }
1817 };
1818
1819 static struct omap_hwmod omap44xx_kbd_hwmod = {
1820         .name           = "kbd",
1821         .class          = &omap44xx_kbd_hwmod_class,
1822         .clkdm_name     = "l4_wkup_clkdm",
1823         .mpu_irqs       = omap44xx_kbd_irqs,
1824         .main_clk       = "kbd_fck",
1825         .prcm = {
1826                 .omap4 = {
1827                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1828                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1829                         .modulemode   = MODULEMODE_SWCTRL,
1830                 },
1831         },
1832 };
1833
1834 /*
1835  * 'mailbox' class
1836  * mailbox module allowing communication between the on-chip processors using a
1837  * queued mailbox-interrupt mechanism.
1838  */
1839
1840 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1841         .rev_offs       = 0x0000,
1842         .sysc_offs      = 0x0010,
1843         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1844                            SYSC_HAS_SOFTRESET),
1845         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1846         .sysc_fields    = &omap_hwmod_sysc_type2,
1847 };
1848
1849 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1850         .name   = "mailbox",
1851         .sysc   = &omap44xx_mailbox_sysc,
1852 };
1853
1854 /* mailbox */
1855 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1856         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1857         { .irq = -1 }
1858 };
1859
1860 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1861         .name           = "mailbox",
1862         .class          = &omap44xx_mailbox_hwmod_class,
1863         .clkdm_name     = "l4_cfg_clkdm",
1864         .mpu_irqs       = omap44xx_mailbox_irqs,
1865         .prcm = {
1866                 .omap4 = {
1867                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1868                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1869                 },
1870         },
1871 };
1872
1873 /*
1874  * 'mcasp' class
1875  * multi-channel audio serial port controller
1876  */
1877
1878 /* The IP is not compliant to type1 / type2 scheme */
1879 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1880         .sidle_shift    = 0,
1881 };
1882
1883 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1884         .sysc_offs      = 0x0004,
1885         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1886         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1887                            SIDLE_SMART_WKUP),
1888         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1889 };
1890
1891 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1892         .name   = "mcasp",
1893         .sysc   = &omap44xx_mcasp_sysc,
1894 };
1895
1896 /* mcasp */
1897 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1898         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1899         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1900         { .irq = -1 }
1901 };
1902
1903 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1904         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1905         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1906         { .dma_req = -1 }
1907 };
1908
1909 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1910         .name           = "mcasp",
1911         .class          = &omap44xx_mcasp_hwmod_class,
1912         .clkdm_name     = "abe_clkdm",
1913         .mpu_irqs       = omap44xx_mcasp_irqs,
1914         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1915         .main_clk       = "mcasp_fck",
1916         .prcm = {
1917                 .omap4 = {
1918                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1919                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1920                         .modulemode   = MODULEMODE_SWCTRL,
1921                 },
1922         },
1923 };
1924
1925 /*
1926  * 'mcbsp' class
1927  * multi channel buffered serial port controller
1928  */
1929
1930 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1931         .sysc_offs      = 0x008c,
1932         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1933                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1934         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1935         .sysc_fields    = &omap_hwmod_sysc_type1,
1936 };
1937
1938 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1939         .name   = "mcbsp",
1940         .sysc   = &omap44xx_mcbsp_sysc,
1941         .rev    = MCBSP_CONFIG_TYPE4,
1942 };
1943
1944 /* mcbsp1 */
1945 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1946         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1947         { .irq = -1 }
1948 };
1949
1950 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1951         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1952         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1953         { .dma_req = -1 }
1954 };
1955
1956 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1957         { .role = "pad_fck", .clk = "pad_clks_ck" },
1958         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1959 };
1960
1961 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1962         .name           = "mcbsp1",
1963         .class          = &omap44xx_mcbsp_hwmod_class,
1964         .clkdm_name     = "abe_clkdm",
1965         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1966         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1967         .main_clk       = "mcbsp1_fck",
1968         .prcm = {
1969                 .omap4 = {
1970                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1971                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1972                         .modulemode   = MODULEMODE_SWCTRL,
1973                 },
1974         },
1975         .opt_clks       = mcbsp1_opt_clks,
1976         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1977 };
1978
1979 /* mcbsp2 */
1980 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1981         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1982         { .irq = -1 }
1983 };
1984
1985 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1986         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1987         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1988         { .dma_req = -1 }
1989 };
1990
1991 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1992         { .role = "pad_fck", .clk = "pad_clks_ck" },
1993         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1994 };
1995
1996 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1997         .name           = "mcbsp2",
1998         .class          = &omap44xx_mcbsp_hwmod_class,
1999         .clkdm_name     = "abe_clkdm",
2000         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2001         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2002         .main_clk       = "mcbsp2_fck",
2003         .prcm = {
2004                 .omap4 = {
2005                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2006                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2007                         .modulemode   = MODULEMODE_SWCTRL,
2008                 },
2009         },
2010         .opt_clks       = mcbsp2_opt_clks,
2011         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2012 };
2013
2014 /* mcbsp3 */
2015 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2016         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2017         { .irq = -1 }
2018 };
2019
2020 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2021         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2022         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2023         { .dma_req = -1 }
2024 };
2025
2026 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2027         { .role = "pad_fck", .clk = "pad_clks_ck" },
2028         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2029 };
2030
2031 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2032         .name           = "mcbsp3",
2033         .class          = &omap44xx_mcbsp_hwmod_class,
2034         .clkdm_name     = "abe_clkdm",
2035         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2036         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2037         .main_clk       = "mcbsp3_fck",
2038         .prcm = {
2039                 .omap4 = {
2040                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2041                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2042                         .modulemode   = MODULEMODE_SWCTRL,
2043                 },
2044         },
2045         .opt_clks       = mcbsp3_opt_clks,
2046         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2047 };
2048
2049 /* mcbsp4 */
2050 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2051         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2052         { .irq = -1 }
2053 };
2054
2055 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2056         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2057         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2058         { .dma_req = -1 }
2059 };
2060
2061 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2062         { .role = "pad_fck", .clk = "pad_clks_ck" },
2063         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2064 };
2065
2066 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2067         .name           = "mcbsp4",
2068         .class          = &omap44xx_mcbsp_hwmod_class,
2069         .clkdm_name     = "l4_per_clkdm",
2070         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2071         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2072         .main_clk       = "mcbsp4_fck",
2073         .prcm = {
2074                 .omap4 = {
2075                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2076                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2077                         .modulemode   = MODULEMODE_SWCTRL,
2078                 },
2079         },
2080         .opt_clks       = mcbsp4_opt_clks,
2081         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2082 };
2083
2084 /*
2085  * 'mcpdm' class
2086  * multi channel pdm controller (proprietary interface with phoenix power
2087  * ic)
2088  */
2089
2090 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2091         .rev_offs       = 0x0000,
2092         .sysc_offs      = 0x0010,
2093         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2094                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2095         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2096                            SIDLE_SMART_WKUP),
2097         .sysc_fields    = &omap_hwmod_sysc_type2,
2098 };
2099
2100 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2101         .name   = "mcpdm",
2102         .sysc   = &omap44xx_mcpdm_sysc,
2103 };
2104
2105 /* mcpdm */
2106 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2107         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2108         { .irq = -1 }
2109 };
2110
2111 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2112         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2113         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2114         { .dma_req = -1 }
2115 };
2116
2117 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2118         .name           = "mcpdm",
2119         .class          = &omap44xx_mcpdm_hwmod_class,
2120         .clkdm_name     = "abe_clkdm",
2121         .mpu_irqs       = omap44xx_mcpdm_irqs,
2122         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2123         .main_clk       = "mcpdm_fck",
2124         .prcm = {
2125                 .omap4 = {
2126                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2127                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2128                         .modulemode   = MODULEMODE_SWCTRL,
2129                 },
2130         },
2131 };
2132
2133 /*
2134  * 'mcspi' class
2135  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2136  * bus
2137  */
2138
2139 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2140         .rev_offs       = 0x0000,
2141         .sysc_offs      = 0x0010,
2142         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2143                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2144         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2145                            SIDLE_SMART_WKUP),
2146         .sysc_fields    = &omap_hwmod_sysc_type2,
2147 };
2148
2149 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2150         .name   = "mcspi",
2151         .sysc   = &omap44xx_mcspi_sysc,
2152         .rev    = OMAP4_MCSPI_REV,
2153 };
2154
2155 /* mcspi1 */
2156 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2157         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2158         { .irq = -1 }
2159 };
2160
2161 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2162         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2163         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2164         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2165         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2166         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2167         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2168         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2169         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2170         { .dma_req = -1 }
2171 };
2172
2173 /* mcspi1 dev_attr */
2174 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2175         .num_chipselect = 4,
2176 };
2177
2178 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2179         .name           = "mcspi1",
2180         .class          = &omap44xx_mcspi_hwmod_class,
2181         .clkdm_name     = "l4_per_clkdm",
2182         .mpu_irqs       = omap44xx_mcspi1_irqs,
2183         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2184         .main_clk       = "mcspi1_fck",
2185         .prcm = {
2186                 .omap4 = {
2187                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2188                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2189                         .modulemode   = MODULEMODE_SWCTRL,
2190                 },
2191         },
2192         .dev_attr       = &mcspi1_dev_attr,
2193 };
2194
2195 /* mcspi2 */
2196 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2197         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2198         { .irq = -1 }
2199 };
2200
2201 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2202         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2203         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2204         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2205         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2206         { .dma_req = -1 }
2207 };
2208
2209 /* mcspi2 dev_attr */
2210 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2211         .num_chipselect = 2,
2212 };
2213
2214 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2215         .name           = "mcspi2",
2216         .class          = &omap44xx_mcspi_hwmod_class,
2217         .clkdm_name     = "l4_per_clkdm",
2218         .mpu_irqs       = omap44xx_mcspi2_irqs,
2219         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2220         .main_clk       = "mcspi2_fck",
2221         .prcm = {
2222                 .omap4 = {
2223                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2224                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2225                         .modulemode   = MODULEMODE_SWCTRL,
2226                 },
2227         },
2228         .dev_attr       = &mcspi2_dev_attr,
2229 };
2230
2231 /* mcspi3 */
2232 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2233         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2234         { .irq = -1 }
2235 };
2236
2237 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2238         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2239         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2240         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2241         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2242         { .dma_req = -1 }
2243 };
2244
2245 /* mcspi3 dev_attr */
2246 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2247         .num_chipselect = 2,
2248 };
2249
2250 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2251         .name           = "mcspi3",
2252         .class          = &omap44xx_mcspi_hwmod_class,
2253         .clkdm_name     = "l4_per_clkdm",
2254         .mpu_irqs       = omap44xx_mcspi3_irqs,
2255         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2256         .main_clk       = "mcspi3_fck",
2257         .prcm = {
2258                 .omap4 = {
2259                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2260                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2261                         .modulemode   = MODULEMODE_SWCTRL,
2262                 },
2263         },
2264         .dev_attr       = &mcspi3_dev_attr,
2265 };
2266
2267 /* mcspi4 */
2268 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2269         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2270         { .irq = -1 }
2271 };
2272
2273 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2274         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2275         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2276         { .dma_req = -1 }
2277 };
2278
2279 /* mcspi4 dev_attr */
2280 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2281         .num_chipselect = 1,
2282 };
2283
2284 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2285         .name           = "mcspi4",
2286         .class          = &omap44xx_mcspi_hwmod_class,
2287         .clkdm_name     = "l4_per_clkdm",
2288         .mpu_irqs       = omap44xx_mcspi4_irqs,
2289         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2290         .main_clk       = "mcspi4_fck",
2291         .prcm = {
2292                 .omap4 = {
2293                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2294                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2295                         .modulemode   = MODULEMODE_SWCTRL,
2296                 },
2297         },
2298         .dev_attr       = &mcspi4_dev_attr,
2299 };
2300
2301 /*
2302  * 'mmc' class
2303  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2304  */
2305
2306 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2307         .rev_offs       = 0x0000,
2308         .sysc_offs      = 0x0010,
2309         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2310                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2311                            SYSC_HAS_SOFTRESET),
2312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2313                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2314                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2315         .sysc_fields    = &omap_hwmod_sysc_type2,
2316 };
2317
2318 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2319         .name   = "mmc",
2320         .sysc   = &omap44xx_mmc_sysc,
2321 };
2322
2323 /* mmc1 */
2324 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2325         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2326         { .irq = -1 }
2327 };
2328
2329 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2330         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2331         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2332         { .dma_req = -1 }
2333 };
2334
2335 /* mmc1 dev_attr */
2336 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2337         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2338 };
2339
2340 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2341         .name           = "mmc1",
2342         .class          = &omap44xx_mmc_hwmod_class,
2343         .clkdm_name     = "l3_init_clkdm",
2344         .mpu_irqs       = omap44xx_mmc1_irqs,
2345         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2346         .main_clk       = "mmc1_fck",
2347         .prcm = {
2348                 .omap4 = {
2349                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2350                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2351                         .modulemode   = MODULEMODE_SWCTRL,
2352                 },
2353         },
2354         .dev_attr       = &mmc1_dev_attr,
2355 };
2356
2357 /* mmc2 */
2358 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2359         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2360         { .irq = -1 }
2361 };
2362
2363 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2364         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2365         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2366         { .dma_req = -1 }
2367 };
2368
2369 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2370         .name           = "mmc2",
2371         .class          = &omap44xx_mmc_hwmod_class,
2372         .clkdm_name     = "l3_init_clkdm",
2373         .mpu_irqs       = omap44xx_mmc2_irqs,
2374         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2375         .main_clk       = "mmc2_fck",
2376         .prcm = {
2377                 .omap4 = {
2378                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2379                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2380                         .modulemode   = MODULEMODE_SWCTRL,
2381                 },
2382         },
2383 };
2384
2385 /* mmc3 */
2386 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2387         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2388         { .irq = -1 }
2389 };
2390
2391 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2392         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2393         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2394         { .dma_req = -1 }
2395 };
2396
2397 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2398         .name           = "mmc3",
2399         .class          = &omap44xx_mmc_hwmod_class,
2400         .clkdm_name     = "l4_per_clkdm",
2401         .mpu_irqs       = omap44xx_mmc3_irqs,
2402         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2403         .main_clk       = "mmc3_fck",
2404         .prcm = {
2405                 .omap4 = {
2406                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2407                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2408                         .modulemode   = MODULEMODE_SWCTRL,
2409                 },
2410         },
2411 };
2412
2413 /* mmc4 */
2414 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2415         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2416         { .irq = -1 }
2417 };
2418
2419 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2420         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2421         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2422         { .dma_req = -1 }
2423 };
2424
2425 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2426         .name           = "mmc4",
2427         .class          = &omap44xx_mmc_hwmod_class,
2428         .clkdm_name     = "l4_per_clkdm",
2429         .mpu_irqs       = omap44xx_mmc4_irqs,
2430         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2431         .main_clk       = "mmc4_fck",
2432         .prcm = {
2433                 .omap4 = {
2434                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2435                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2436                         .modulemode   = MODULEMODE_SWCTRL,
2437                 },
2438         },
2439 };
2440
2441 /* mmc5 */
2442 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2443         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2444         { .irq = -1 }
2445 };
2446
2447 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2448         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2449         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2450         { .dma_req = -1 }
2451 };
2452
2453 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2454         .name           = "mmc5",
2455         .class          = &omap44xx_mmc_hwmod_class,
2456         .clkdm_name     = "l4_per_clkdm",
2457         .mpu_irqs       = omap44xx_mmc5_irqs,
2458         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2459         .main_clk       = "mmc5_fck",
2460         .prcm = {
2461                 .omap4 = {
2462                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2463                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2464                         .modulemode   = MODULEMODE_SWCTRL,
2465                 },
2466         },
2467 };
2468
2469 /*
2470  * 'mpu' class
2471  * mpu sub-system
2472  */
2473
2474 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2475         .name   = "mpu",
2476 };
2477
2478 /* mpu */
2479 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2480         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2481         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2482         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2483         { .irq = -1 }
2484 };
2485
2486 static struct omap_hwmod omap44xx_mpu_hwmod = {
2487         .name           = "mpu",
2488         .class          = &omap44xx_mpu_hwmod_class,
2489         .clkdm_name     = "mpuss_clkdm",
2490         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2491         .mpu_irqs       = omap44xx_mpu_irqs,
2492         .main_clk       = "dpll_mpu_m2_ck",
2493         .prcm = {
2494                 .omap4 = {
2495                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2496                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2497                 },
2498         },
2499 };
2500
2501 /*
2502  * 'ocmc_ram' class
2503  * top-level core on-chip ram
2504  */
2505
2506 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2507         .name   = "ocmc_ram",
2508 };
2509
2510 /* ocmc_ram */
2511 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2512         .name           = "ocmc_ram",
2513         .class          = &omap44xx_ocmc_ram_hwmod_class,
2514         .clkdm_name     = "l3_2_clkdm",
2515         .prcm = {
2516                 .omap4 = {
2517                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2518                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2519                 },
2520         },
2521 };
2522
2523 /*
2524  * 'ocp2scp' class
2525  * bridge to transform ocp interface protocol to scp (serial control port)
2526  * protocol
2527  */
2528
2529 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2530         .name   = "ocp2scp",
2531 };
2532
2533 /* ocp2scp_usb_phy */
2534 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2535         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2536 };
2537
2538 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2539         .name           = "ocp2scp_usb_phy",
2540         .class          = &omap44xx_ocp2scp_hwmod_class,
2541         .clkdm_name     = "l3_init_clkdm",
2542         .prcm = {
2543                 .omap4 = {
2544                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2545                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2546                         .modulemode   = MODULEMODE_HWCTRL,
2547                 },
2548         },
2549         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2550         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2551 };
2552
2553 /*
2554  * 'prcm' class
2555  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2556  * + clock manager 1 (in always on power domain) + local prm in mpu
2557  */
2558
2559 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2560         .name   = "prcm",
2561 };
2562
2563 /* prcm_mpu */
2564 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2565         .name           = "prcm_mpu",
2566         .class          = &omap44xx_prcm_hwmod_class,
2567         .clkdm_name     = "l4_wkup_clkdm",
2568         .prcm = {
2569                 .omap4 = {
2570                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2571                 },
2572         },
2573 };
2574
2575 /* cm_core_aon */
2576 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2577         .name           = "cm_core_aon",
2578         .class          = &omap44xx_prcm_hwmod_class,
2579         .prcm = {
2580                 .omap4 = {
2581                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2582                 },
2583         },
2584 };
2585
2586 /* cm_core */
2587 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2588         .name           = "cm_core",
2589         .class          = &omap44xx_prcm_hwmod_class,
2590         .prcm = {
2591                 .omap4 = {
2592                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2593                 },
2594         },
2595 };
2596
2597 /* prm */
2598 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2599         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2600         { .irq = -1 }
2601 };
2602
2603 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2604         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2605         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2606 };
2607
2608 static struct omap_hwmod omap44xx_prm_hwmod = {
2609         .name           = "prm",
2610         .class          = &omap44xx_prcm_hwmod_class,
2611         .mpu_irqs       = omap44xx_prm_irqs,
2612         .rst_lines      = omap44xx_prm_resets,
2613         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2614 };
2615
2616 /*
2617  * 'scrm' class
2618  * system clock and reset manager
2619  */
2620
2621 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2622         .name   = "scrm",
2623 };
2624
2625 /* scrm */
2626 static struct omap_hwmod omap44xx_scrm_hwmod = {
2627         .name           = "scrm",
2628         .class          = &omap44xx_scrm_hwmod_class,
2629         .clkdm_name     = "l4_wkup_clkdm",
2630         .prcm = {
2631                 .omap4 = {
2632                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2633                 },
2634         },
2635 };
2636
2637 /*
2638  * 'sl2if' class
2639  * shared level 2 memory interface
2640  */
2641
2642 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2643         .name   = "sl2if",
2644 };
2645
2646 /* sl2if */
2647 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2648         .name           = "sl2if",
2649         .class          = &omap44xx_sl2if_hwmod_class,
2650         .clkdm_name     = "ivahd_clkdm",
2651         .prcm = {
2652                 .omap4 = {
2653                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2654                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2655                         .modulemode   = MODULEMODE_HWCTRL,
2656                 },
2657         },
2658 };
2659
2660 /*
2661  * 'slimbus' class
2662  * bidirectional, multi-drop, multi-channel two-line serial interface between
2663  * the device and external components
2664  */
2665
2666 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2667         .rev_offs       = 0x0000,
2668         .sysc_offs      = 0x0010,
2669         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2670                            SYSC_HAS_SOFTRESET),
2671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2672                            SIDLE_SMART_WKUP),
2673         .sysc_fields    = &omap_hwmod_sysc_type2,
2674 };
2675
2676 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2677         .name   = "slimbus",
2678         .sysc   = &omap44xx_slimbus_sysc,
2679 };
2680
2681 /* slimbus1 */
2682 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2683         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2684         { .irq = -1 }
2685 };
2686
2687 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2688         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2689         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2690         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2691         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2692         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2693         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2694         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2695         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2696         { .dma_req = -1 }
2697 };
2698
2699 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2700         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2701         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2702         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2703         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2704 };
2705
2706 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2707         .name           = "slimbus1",
2708         .class          = &omap44xx_slimbus_hwmod_class,
2709         .clkdm_name     = "abe_clkdm",
2710         .mpu_irqs       = omap44xx_slimbus1_irqs,
2711         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2712         .prcm = {
2713                 .omap4 = {
2714                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2715                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2716                         .modulemode   = MODULEMODE_SWCTRL,
2717                 },
2718         },
2719         .opt_clks       = slimbus1_opt_clks,
2720         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2721 };
2722
2723 /* slimbus2 */
2724 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2725         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2726         { .irq = -1 }
2727 };
2728
2729 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2730         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2731         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2732         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2733         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2734         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2735         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2736         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2737         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2738         { .dma_req = -1 }
2739 };
2740
2741 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2742         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2743         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2744         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2745 };
2746
2747 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2748         .name           = "slimbus2",
2749         .class          = &omap44xx_slimbus_hwmod_class,
2750         .clkdm_name     = "l4_per_clkdm",
2751         .mpu_irqs       = omap44xx_slimbus2_irqs,
2752         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2753         .prcm = {
2754                 .omap4 = {
2755                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2756                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2757                         .modulemode   = MODULEMODE_SWCTRL,
2758                 },
2759         },
2760         .opt_clks       = slimbus2_opt_clks,
2761         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2762 };
2763
2764 /*
2765  * 'smartreflex' class
2766  * smartreflex module (monitor silicon performance and outputs a measure of
2767  * performance error)
2768  */
2769
2770 /* The IP is not compliant to type1 / type2 scheme */
2771 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2772         .sidle_shift    = 24,
2773         .enwkup_shift   = 26,
2774 };
2775
2776 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2777         .sysc_offs      = 0x0038,
2778         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2779         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2780                            SIDLE_SMART_WKUP),
2781         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2782 };
2783
2784 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2785         .name   = "smartreflex",
2786         .sysc   = &omap44xx_smartreflex_sysc,
2787         .rev    = 2,
2788 };
2789
2790 /* smartreflex_core */
2791 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2792         .sensor_voltdm_name   = "core",
2793 };
2794
2795 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2796         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2797         { .irq = -1 }
2798 };
2799
2800 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2801         .name           = "smartreflex_core",
2802         .class          = &omap44xx_smartreflex_hwmod_class,
2803         .clkdm_name     = "l4_ao_clkdm",
2804         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2805
2806         .main_clk       = "smartreflex_core_fck",
2807         .prcm = {
2808                 .omap4 = {
2809                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2810                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2811                         .modulemode   = MODULEMODE_SWCTRL,
2812                 },
2813         },
2814         .dev_attr       = &smartreflex_core_dev_attr,
2815 };
2816
2817 /* smartreflex_iva */
2818 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2819         .sensor_voltdm_name     = "iva",
2820 };
2821
2822 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2823         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2824         { .irq = -1 }
2825 };
2826
2827 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2828         .name           = "smartreflex_iva",
2829         .class          = &omap44xx_smartreflex_hwmod_class,
2830         .clkdm_name     = "l4_ao_clkdm",
2831         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2832         .main_clk       = "smartreflex_iva_fck",
2833         .prcm = {
2834                 .omap4 = {
2835                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2836                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2837                         .modulemode   = MODULEMODE_SWCTRL,
2838                 },
2839         },
2840         .dev_attr       = &smartreflex_iva_dev_attr,
2841 };
2842
2843 /* smartreflex_mpu */
2844 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2845         .sensor_voltdm_name     = "mpu",
2846 };
2847
2848 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2849         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2850         { .irq = -1 }
2851 };
2852
2853 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2854         .name           = "smartreflex_mpu",
2855         .class          = &omap44xx_smartreflex_hwmod_class,
2856         .clkdm_name     = "l4_ao_clkdm",
2857         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2858         .main_clk       = "smartreflex_mpu_fck",
2859         .prcm = {
2860                 .omap4 = {
2861                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2862                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2863                         .modulemode   = MODULEMODE_SWCTRL,
2864                 },
2865         },
2866         .dev_attr       = &smartreflex_mpu_dev_attr,
2867 };
2868
2869 /*
2870  * 'spinlock' class
2871  * spinlock provides hardware assistance for synchronizing the processes
2872  * running on multiple processors
2873  */
2874
2875 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2876         .rev_offs       = 0x0000,
2877         .sysc_offs      = 0x0010,
2878         .syss_offs      = 0x0014,
2879         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2880                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2881                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2882         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2883                            SIDLE_SMART_WKUP),
2884         .sysc_fields    = &omap_hwmod_sysc_type1,
2885 };
2886
2887 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2888         .name   = "spinlock",
2889         .sysc   = &omap44xx_spinlock_sysc,
2890 };
2891
2892 /* spinlock */
2893 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2894         .name           = "spinlock",
2895         .class          = &omap44xx_spinlock_hwmod_class,
2896         .clkdm_name     = "l4_cfg_clkdm",
2897         .prcm = {
2898                 .omap4 = {
2899                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2900                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2901                 },
2902         },
2903 };
2904
2905 /*
2906  * 'timer' class
2907  * general purpose timer module with accurate 1ms tick
2908  * This class contains several variants: ['timer_1ms', 'timer']
2909  */
2910
2911 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2912         .rev_offs       = 0x0000,
2913         .sysc_offs      = 0x0010,
2914         .syss_offs      = 0x0014,
2915         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2916                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2917                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2918                            SYSS_HAS_RESET_STATUS),
2919         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2920         .sysc_fields    = &omap_hwmod_sysc_type1,
2921 };
2922
2923 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2924         .name   = "timer",
2925         .sysc   = &omap44xx_timer_1ms_sysc,
2926 };
2927
2928 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2929         .rev_offs       = 0x0000,
2930         .sysc_offs      = 0x0010,
2931         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2932                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2933         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2934                            SIDLE_SMART_WKUP),
2935         .sysc_fields    = &omap_hwmod_sysc_type2,
2936 };
2937
2938 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2939         .name   = "timer",
2940         .sysc   = &omap44xx_timer_sysc,
2941 };
2942
2943 /* always-on timers dev attribute */
2944 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2945         .timer_capability       = OMAP_TIMER_ALWON,
2946 };
2947
2948 /* pwm timers dev attribute */
2949 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2950         .timer_capability       = OMAP_TIMER_HAS_PWM,
2951 };
2952
2953 /* timer1 */
2954 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2955         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2956         { .irq = -1 }
2957 };
2958
2959 static struct omap_hwmod omap44xx_timer1_hwmod = {
2960         .name           = "timer1",
2961         .class          = &omap44xx_timer_1ms_hwmod_class,
2962         .clkdm_name     = "l4_wkup_clkdm",
2963         .mpu_irqs       = omap44xx_timer1_irqs,
2964         .main_clk       = "timer1_fck",
2965         .prcm = {
2966                 .omap4 = {
2967                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2968                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2969                         .modulemode   = MODULEMODE_SWCTRL,
2970                 },
2971         },
2972         .dev_attr       = &capability_alwon_dev_attr,
2973 };
2974
2975 /* timer2 */
2976 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2977         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2978         { .irq = -1 }
2979 };
2980
2981 static struct omap_hwmod omap44xx_timer2_hwmod = {
2982         .name           = "timer2",
2983         .class          = &omap44xx_timer_1ms_hwmod_class,
2984         .clkdm_name     = "l4_per_clkdm",
2985         .mpu_irqs       = omap44xx_timer2_irqs,
2986         .main_clk       = "timer2_fck",
2987         .prcm = {
2988                 .omap4 = {
2989                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2990                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2991                         .modulemode   = MODULEMODE_SWCTRL,
2992                 },
2993         },
2994 };
2995
2996 /* timer3 */
2997 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2998         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2999         { .irq = -1 }
3000 };
3001
3002 static struct omap_hwmod omap44xx_timer3_hwmod = {
3003         .name           = "timer3",
3004         .class          = &omap44xx_timer_hwmod_class,
3005         .clkdm_name     = "l4_per_clkdm",
3006         .mpu_irqs       = omap44xx_timer3_irqs,
3007         .main_clk       = "timer3_fck",
3008         .prcm = {
3009                 .omap4 = {
3010                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3011                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3012                         .modulemode   = MODULEMODE_SWCTRL,
3013                 },
3014         },
3015 };
3016
3017 /* timer4 */
3018 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3019         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3020         { .irq = -1 }
3021 };
3022
3023 static struct omap_hwmod omap44xx_timer4_hwmod = {
3024         .name           = "timer4",
3025         .class          = &omap44xx_timer_hwmod_class,
3026         .clkdm_name     = "l4_per_clkdm",
3027         .mpu_irqs       = omap44xx_timer4_irqs,
3028         .main_clk       = "timer4_fck",
3029         .prcm = {
3030                 .omap4 = {
3031                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3032                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3033                         .modulemode   = MODULEMODE_SWCTRL,
3034                 },
3035         },
3036 };
3037
3038 /* timer5 */
3039 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3040         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3041         { .irq = -1 }
3042 };
3043
3044 static struct omap_hwmod omap44xx_timer5_hwmod = {
3045         .name           = "timer5",
3046         .class          = &omap44xx_timer_hwmod_class,
3047         .clkdm_name     = "abe_clkdm",
3048         .mpu_irqs       = omap44xx_timer5_irqs,
3049         .main_clk       = "timer5_fck",
3050         .prcm = {
3051                 .omap4 = {
3052                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3053                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3054                         .modulemode   = MODULEMODE_SWCTRL,
3055                 },
3056         },
3057 };
3058
3059 /* timer6 */
3060 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3061         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3062         { .irq = -1 }
3063 };
3064
3065 static struct omap_hwmod omap44xx_timer6_hwmod = {
3066         .name           = "timer6",
3067         .class          = &omap44xx_timer_hwmod_class,
3068         .clkdm_name     = "abe_clkdm",
3069         .mpu_irqs       = omap44xx_timer6_irqs,
3070
3071         .main_clk       = "timer6_fck",
3072         .prcm = {
3073                 .omap4 = {
3074                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3075                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3076                         .modulemode   = MODULEMODE_SWCTRL,
3077                 },
3078         },
3079 };
3080
3081 /* timer7 */
3082 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3083         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3084         { .irq = -1 }
3085 };
3086
3087 static struct omap_hwmod omap44xx_timer7_hwmod = {
3088         .name           = "timer7",
3089         .class          = &omap44xx_timer_hwmod_class,
3090         .clkdm_name     = "abe_clkdm",
3091         .mpu_irqs       = omap44xx_timer7_irqs,
3092         .main_clk       = "timer7_fck",
3093         .prcm = {
3094                 .omap4 = {
3095                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3096                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3097                         .modulemode   = MODULEMODE_SWCTRL,
3098                 },
3099         },
3100 };
3101
3102 /* timer8 */
3103 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3104         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3105         { .irq = -1 }
3106 };
3107
3108 static struct omap_hwmod omap44xx_timer8_hwmod = {
3109         .name           = "timer8",
3110         .class          = &omap44xx_timer_hwmod_class,
3111         .clkdm_name     = "abe_clkdm",
3112         .mpu_irqs       = omap44xx_timer8_irqs,
3113         .main_clk       = "timer8_fck",
3114         .prcm = {
3115                 .omap4 = {
3116                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3117                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3118                         .modulemode   = MODULEMODE_SWCTRL,
3119                 },
3120         },
3121         .dev_attr       = &capability_pwm_dev_attr,
3122 };
3123
3124 /* timer9 */
3125 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3126         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3127         { .irq = -1 }
3128 };
3129
3130 static struct omap_hwmod omap44xx_timer9_hwmod = {
3131         .name           = "timer9",
3132         .class          = &omap44xx_timer_hwmod_class,
3133         .clkdm_name     = "l4_per_clkdm",
3134         .mpu_irqs       = omap44xx_timer9_irqs,
3135         .main_clk       = "timer9_fck",
3136         .prcm = {
3137                 .omap4 = {
3138                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3139                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3140                         .modulemode   = MODULEMODE_SWCTRL,
3141                 },
3142         },
3143         .dev_attr       = &capability_pwm_dev_attr,
3144 };
3145
3146 /* timer10 */
3147 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3148         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3149         { .irq = -1 }
3150 };
3151
3152 static struct omap_hwmod omap44xx_timer10_hwmod = {
3153         .name           = "timer10",
3154         .class          = &omap44xx_timer_1ms_hwmod_class,
3155         .clkdm_name     = "l4_per_clkdm",
3156         .mpu_irqs       = omap44xx_timer10_irqs,
3157         .main_clk       = "timer10_fck",
3158         .prcm = {
3159                 .omap4 = {
3160                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3161                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3162                         .modulemode   = MODULEMODE_SWCTRL,
3163                 },
3164         },
3165         .dev_attr       = &capability_pwm_dev_attr,
3166 };
3167
3168 /* timer11 */
3169 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3170         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3171         { .irq = -1 }
3172 };
3173
3174 static struct omap_hwmod omap44xx_timer11_hwmod = {
3175         .name           = "timer11",
3176         .class          = &omap44xx_timer_hwmod_class,
3177         .clkdm_name     = "l4_per_clkdm",
3178         .mpu_irqs       = omap44xx_timer11_irqs,
3179         .main_clk       = "timer11_fck",
3180         .prcm = {
3181                 .omap4 = {
3182                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3183                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3184                         .modulemode   = MODULEMODE_SWCTRL,
3185                 },
3186         },
3187         .dev_attr       = &capability_pwm_dev_attr,
3188 };
3189
3190 /*
3191  * 'uart' class
3192  * universal asynchronous receiver/transmitter (uart)
3193  */
3194
3195 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3196         .rev_offs       = 0x0050,
3197         .sysc_offs      = 0x0054,
3198         .syss_offs      = 0x0058,
3199         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3200                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3201                            SYSS_HAS_RESET_STATUS),
3202         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3203                            SIDLE_SMART_WKUP),
3204         .sysc_fields    = &omap_hwmod_sysc_type1,
3205 };
3206
3207 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3208         .name   = "uart",
3209         .sysc   = &omap44xx_uart_sysc,
3210 };
3211
3212 /* uart1 */
3213 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3214         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3215         { .irq = -1 }
3216 };
3217
3218 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3219         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3220         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3221         { .dma_req = -1 }
3222 };
3223
3224 static struct omap_hwmod omap44xx_uart1_hwmod = {
3225         .name           = "uart1",
3226         .class          = &omap44xx_uart_hwmod_class,
3227         .clkdm_name     = "l4_per_clkdm",
3228         .mpu_irqs       = omap44xx_uart1_irqs,
3229         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3230         .main_clk       = "uart1_fck",
3231         .prcm = {
3232                 .omap4 = {
3233                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3234                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3235                         .modulemode   = MODULEMODE_SWCTRL,
3236                 },
3237         },
3238 };
3239
3240 /* uart2 */
3241 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3242         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3243         { .irq = -1 }
3244 };
3245
3246 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3247         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3248         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3249         { .dma_req = -1 }
3250 };
3251
3252 static struct omap_hwmod omap44xx_uart2_hwmod = {
3253         .name           = "uart2",
3254         .class          = &omap44xx_uart_hwmod_class,
3255         .clkdm_name     = "l4_per_clkdm",
3256         .mpu_irqs       = omap44xx_uart2_irqs,
3257         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3258         .main_clk       = "uart2_fck",
3259         .prcm = {
3260                 .omap4 = {
3261                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3262                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3263                         .modulemode   = MODULEMODE_SWCTRL,
3264                 },
3265         },
3266 };
3267
3268 /* uart3 */
3269 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3270         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3271         { .irq = -1 }
3272 };
3273
3274 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3275         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3276         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3277         { .dma_req = -1 }
3278 };
3279
3280 static struct omap_hwmod omap44xx_uart3_hwmod = {
3281         .name           = "uart3",
3282         .class          = &omap44xx_uart_hwmod_class,
3283         .clkdm_name     = "l4_per_clkdm",
3284         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3285         .mpu_irqs       = omap44xx_uart3_irqs,
3286         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3287         .main_clk       = "uart3_fck",
3288         .prcm = {
3289                 .omap4 = {
3290                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3291                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3292                         .modulemode   = MODULEMODE_SWCTRL,
3293                 },
3294         },
3295 };
3296
3297 /* uart4 */
3298 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3299         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3300         { .irq = -1 }
3301 };
3302
3303 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3304         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3305         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3306         { .dma_req = -1 }
3307 };
3308
3309 static struct omap_hwmod omap44xx_uart4_hwmod = {
3310         .name           = "uart4",
3311         .class          = &omap44xx_uart_hwmod_class,
3312         .clkdm_name     = "l4_per_clkdm",
3313         .mpu_irqs       = omap44xx_uart4_irqs,
3314         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3315         .main_clk       = "uart4_fck",
3316         .prcm = {
3317                 .omap4 = {
3318                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3319                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3320                         .modulemode   = MODULEMODE_SWCTRL,
3321                 },
3322         },
3323 };
3324
3325 /*
3326  * 'usb_host_fs' class
3327  * full-speed usb host controller
3328  */
3329
3330 /* The IP is not compliant to type1 / type2 scheme */
3331 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3332         .midle_shift    = 4,
3333         .sidle_shift    = 2,
3334         .srst_shift     = 1,
3335 };
3336
3337 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3338         .rev_offs       = 0x0000,
3339         .sysc_offs      = 0x0210,
3340         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3341                            SYSC_HAS_SOFTRESET),
3342         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3343                            SIDLE_SMART_WKUP),
3344         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3345 };
3346
3347 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3348         .name   = "usb_host_fs",
3349         .sysc   = &omap44xx_usb_host_fs_sysc,
3350 };
3351
3352 /* usb_host_fs */
3353 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3354         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3355         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3356         { .irq = -1 }
3357 };
3358
3359 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3360         .name           = "usb_host_fs",
3361         .class          = &omap44xx_usb_host_fs_hwmod_class,
3362         .clkdm_name     = "l3_init_clkdm",
3363         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3364         .main_clk       = "usb_host_fs_fck",
3365         .prcm = {
3366                 .omap4 = {
3367                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3368                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3369                         .modulemode   = MODULEMODE_SWCTRL,
3370                 },
3371         },
3372 };
3373
3374 /*
3375  * 'usb_host_hs' class
3376  * high-speed multi-port usb host controller
3377  */
3378
3379 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3380         .rev_offs       = 0x0000,
3381         .sysc_offs      = 0x0010,
3382         .syss_offs      = 0x0014,
3383         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3384                            SYSC_HAS_SOFTRESET),
3385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3386                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3387                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3388         .sysc_fields    = &omap_hwmod_sysc_type2,
3389 };
3390
3391 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3392         .name   = "usb_host_hs",
3393         .sysc   = &omap44xx_usb_host_hs_sysc,
3394 };
3395
3396 /* usb_host_hs */
3397 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3398         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3399         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3400         { .irq = -1 }
3401 };
3402
3403 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3404         .name           = "usb_host_hs",
3405         .class          = &omap44xx_usb_host_hs_hwmod_class,
3406         .clkdm_name     = "l3_init_clkdm",
3407         .main_clk       = "usb_host_hs_fck",
3408         .prcm = {
3409                 .omap4 = {
3410                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3411                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3412                         .modulemode   = MODULEMODE_SWCTRL,
3413                 },
3414         },
3415         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3416
3417         /*
3418          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3419          * id: i660
3420          *
3421          * Description:
3422          * In the following configuration :
3423          * - USBHOST module is set to smart-idle mode
3424          * - PRCM asserts idle_req to the USBHOST module ( This typically
3425          *   happens when the system is going to a low power mode : all ports
3426          *   have been suspended, the master part of the USBHOST module has
3427          *   entered the standby state, and SW has cut the functional clocks)
3428          * - an USBHOST interrupt occurs before the module is able to answer
3429          *   idle_ack, typically a remote wakeup IRQ.
3430          * Then the USB HOST module will enter a deadlock situation where it
3431          * is no more accessible nor functional.
3432          *
3433          * Workaround:
3434          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3435          */
3436
3437         /*
3438          * Errata: USB host EHCI may stall when entering smart-standby mode
3439          * Id: i571
3440          *
3441          * Description:
3442          * When the USBHOST module is set to smart-standby mode, and when it is
3443          * ready to enter the standby state (i.e. all ports are suspended and
3444          * all attached devices are in suspend mode), then it can wrongly assert
3445          * the Mstandby signal too early while there are still some residual OCP
3446          * transactions ongoing. If this condition occurs, the internal state
3447          * machine may go to an undefined state and the USB link may be stuck
3448          * upon the next resume.
3449          *
3450          * Workaround:
3451          * Don't use smart standby; use only force standby,
3452          * hence HWMOD_SWSUP_MSTANDBY
3453          */
3454
3455         /*
3456          * During system boot; If the hwmod framework resets the module
3457          * the module will have smart idle settings; which can lead to deadlock
3458          * (above Errata Id:i660); so, dont reset the module during boot;
3459          * Use HWMOD_INIT_NO_RESET.
3460          */
3461
3462         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3463                           HWMOD_INIT_NO_RESET,
3464 };
3465
3466 /*
3467  * 'usb_otg_hs' class
3468  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3469  */
3470
3471 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3472         .rev_offs       = 0x0400,
3473         .sysc_offs      = 0x0404,
3474         .syss_offs      = 0x0408,
3475         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3476                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3477                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3478         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3479                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3480                            MSTANDBY_SMART),
3481         .sysc_fields    = &omap_hwmod_sysc_type1,
3482 };
3483
3484 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3485         .name   = "usb_otg_hs",
3486         .sysc   = &omap44xx_usb_otg_hs_sysc,
3487 };
3488
3489 /* usb_otg_hs */
3490 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3491         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3492         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3493         { .irq = -1 }
3494 };
3495
3496 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3497         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3498 };
3499
3500 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3501         .name           = "usb_otg_hs",
3502         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3503         .clkdm_name     = "l3_init_clkdm",
3504         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3505         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3506         .main_clk       = "usb_otg_hs_ick",
3507         .prcm = {
3508                 .omap4 = {
3509                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3510                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3511                         .modulemode   = MODULEMODE_HWCTRL,
3512                 },
3513         },
3514         .opt_clks       = usb_otg_hs_opt_clks,
3515         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3516 };
3517
3518 /*
3519  * 'usb_tll_hs' class
3520  * usb_tll_hs module is the adapter on the usb_host_hs ports
3521  */
3522
3523 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3524         .rev_offs       = 0x0000,
3525         .sysc_offs      = 0x0010,
3526         .syss_offs      = 0x0014,
3527         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3528                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3529                            SYSC_HAS_AUTOIDLE),
3530         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3531         .sysc_fields    = &omap_hwmod_sysc_type1,
3532 };
3533
3534 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3535         .name   = "usb_tll_hs",
3536         .sysc   = &omap44xx_usb_tll_hs_sysc,
3537 };
3538
3539 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3540         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3541         { .irq = -1 }
3542 };
3543
3544 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3545         .name           = "usb_tll_hs",
3546         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3547         .clkdm_name     = "l3_init_clkdm",
3548         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3549         .main_clk       = "usb_tll_hs_ick",
3550         .prcm = {
3551                 .omap4 = {
3552                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3553                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3554                         .modulemode   = MODULEMODE_HWCTRL,
3555                 },
3556         },
3557 };
3558
3559 /*
3560  * 'wd_timer' class
3561  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3562  * overflow condition
3563  */
3564
3565 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3566         .rev_offs       = 0x0000,
3567         .sysc_offs      = 0x0010,
3568         .syss_offs      = 0x0014,
3569         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3570                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3571         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3572                            SIDLE_SMART_WKUP),
3573         .sysc_fields    = &omap_hwmod_sysc_type1,
3574 };
3575
3576 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3577         .name           = "wd_timer",
3578         .sysc           = &omap44xx_wd_timer_sysc,
3579         .pre_shutdown   = &omap2_wd_timer_disable,
3580         .reset          = &omap2_wd_timer_reset,
3581 };
3582
3583 /* wd_timer2 */
3584 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3585         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3586         { .irq = -1 }
3587 };
3588
3589 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3590         .name           = "wd_timer2",
3591         .class          = &omap44xx_wd_timer_hwmod_class,
3592         .clkdm_name     = "l4_wkup_clkdm",
3593         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3594         .main_clk       = "wd_timer2_fck",
3595         .prcm = {
3596                 .omap4 = {
3597                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3598                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3599                         .modulemode   = MODULEMODE_SWCTRL,
3600                 },
3601         },
3602 };
3603
3604 /* wd_timer3 */
3605 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3606         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3607         { .irq = -1 }
3608 };
3609
3610 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3611         .name           = "wd_timer3",
3612         .class          = &omap44xx_wd_timer_hwmod_class,
3613         .clkdm_name     = "abe_clkdm",
3614         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3615         .main_clk       = "wd_timer3_fck",
3616         .prcm = {
3617                 .omap4 = {
3618                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3619                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3620                         .modulemode   = MODULEMODE_SWCTRL,
3621                 },
3622         },
3623 };
3624
3625
3626 /*
3627  * interfaces
3628  */
3629
3630 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3631         {
3632                 .pa_start       = 0x4a204000,
3633                 .pa_end         = 0x4a2040ff,
3634                 .flags          = ADDR_TYPE_RT
3635         },
3636         { }
3637 };
3638
3639 /* c2c -> c2c_target_fw */
3640 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3641         .master         = &omap44xx_c2c_hwmod,
3642         .slave          = &omap44xx_c2c_target_fw_hwmod,
3643         .clk            = "div_core_ck",
3644         .addr           = omap44xx_c2c_target_fw_addrs,
3645         .user           = OCP_USER_MPU,
3646 };
3647
3648 /* l4_cfg -> c2c_target_fw */
3649 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3650         .master         = &omap44xx_l4_cfg_hwmod,
3651         .slave          = &omap44xx_c2c_target_fw_hwmod,
3652         .clk            = "l4_div_ck",
3653         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3654 };
3655
3656 /* l3_main_1 -> dmm */
3657 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3658         .master         = &omap44xx_l3_main_1_hwmod,
3659         .slave          = &omap44xx_dmm_hwmod,
3660         .clk            = "l3_div_ck",
3661         .user           = OCP_USER_SDMA,
3662 };
3663
3664 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3665         {
3666                 .pa_start       = 0x4e000000,
3667                 .pa_end         = 0x4e0007ff,
3668                 .flags          = ADDR_TYPE_RT
3669         },
3670         { }
3671 };
3672
3673 /* mpu -> dmm */
3674 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3675         .master         = &omap44xx_mpu_hwmod,
3676         .slave          = &omap44xx_dmm_hwmod,
3677         .clk            = "l3_div_ck",
3678         .addr           = omap44xx_dmm_addrs,
3679         .user           = OCP_USER_MPU,
3680 };
3681
3682 /* c2c -> emif_fw */
3683 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3684         .master         = &omap44xx_c2c_hwmod,
3685         .slave          = &omap44xx_emif_fw_hwmod,
3686         .clk            = "div_core_ck",
3687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3688 };
3689
3690 /* dmm -> emif_fw */
3691 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3692         .master         = &omap44xx_dmm_hwmod,
3693         .slave          = &omap44xx_emif_fw_hwmod,
3694         .clk            = "l3_div_ck",
3695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3696 };
3697
3698 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3699         {
3700                 .pa_start       = 0x4a20c000,
3701                 .pa_end         = 0x4a20c0ff,
3702                 .flags          = ADDR_TYPE_RT
3703         },
3704         { }
3705 };
3706
3707 /* l4_cfg -> emif_fw */
3708 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3709         .master         = &omap44xx_l4_cfg_hwmod,
3710         .slave          = &omap44xx_emif_fw_hwmod,
3711         .clk            = "l4_div_ck",
3712         .addr           = omap44xx_emif_fw_addrs,
3713         .user           = OCP_USER_MPU,
3714 };
3715
3716 /* iva -> l3_instr */
3717 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3718         .master         = &omap44xx_iva_hwmod,
3719         .slave          = &omap44xx_l3_instr_hwmod,
3720         .clk            = "l3_div_ck",
3721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3722 };
3723
3724 /* l3_main_3 -> l3_instr */
3725 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3726         .master         = &omap44xx_l3_main_3_hwmod,
3727         .slave          = &omap44xx_l3_instr_hwmod,
3728         .clk            = "l3_div_ck",
3729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3730 };
3731
3732 /* ocp_wp_noc -> l3_instr */
3733 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3734         .master         = &omap44xx_ocp_wp_noc_hwmod,
3735         .slave          = &omap44xx_l3_instr_hwmod,
3736         .clk            = "l3_div_ck",
3737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3738 };
3739
3740 /* dsp -> l3_main_1 */
3741 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3742         .master         = &omap44xx_dsp_hwmod,
3743         .slave          = &omap44xx_l3_main_1_hwmod,
3744         .clk            = "l3_div_ck",
3745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3746 };
3747
3748 /* dss -> l3_main_1 */
3749 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3750         .master         = &omap44xx_dss_hwmod,
3751         .slave          = &omap44xx_l3_main_1_hwmod,
3752         .clk            = "l3_div_ck",
3753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3754 };
3755
3756 /* l3_main_2 -> l3_main_1 */
3757 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3758         .master         = &omap44xx_l3_main_2_hwmod,
3759         .slave          = &omap44xx_l3_main_1_hwmod,
3760         .clk            = "l3_div_ck",
3761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3762 };
3763
3764 /* l4_cfg -> l3_main_1 */
3765 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3766         .master         = &omap44xx_l4_cfg_hwmod,
3767         .slave          = &omap44xx_l3_main_1_hwmod,
3768         .clk            = "l4_div_ck",
3769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3770 };
3771
3772 /* mmc1 -> l3_main_1 */
3773 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3774         .master         = &omap44xx_mmc1_hwmod,
3775         .slave          = &omap44xx_l3_main_1_hwmod,
3776         .clk            = "l3_div_ck",
3777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3778 };
3779
3780 /* mmc2 -> l3_main_1 */
3781 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3782         .master         = &omap44xx_mmc2_hwmod,
3783         .slave          = &omap44xx_l3_main_1_hwmod,
3784         .clk            = "l3_div_ck",
3785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3786 };
3787
3788 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3789         {
3790                 .pa_start       = 0x44000000,
3791                 .pa_end         = 0x44000fff,
3792                 .flags          = ADDR_TYPE_RT
3793         },
3794         { }
3795 };
3796
3797 /* mpu -> l3_main_1 */
3798 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3799         .master         = &omap44xx_mpu_hwmod,
3800         .slave          = &omap44xx_l3_main_1_hwmod,
3801         .clk            = "l3_div_ck",
3802         .addr           = omap44xx_l3_main_1_addrs,
3803         .user           = OCP_USER_MPU,
3804 };
3805
3806 /* c2c_target_fw -> l3_main_2 */
3807 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3808         .master         = &omap44xx_c2c_target_fw_hwmod,
3809         .slave          = &omap44xx_l3_main_2_hwmod,
3810         .clk            = "l3_div_ck",
3811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3812 };
3813
3814 /* debugss -> l3_main_2 */
3815 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3816         .master         = &omap44xx_debugss_hwmod,
3817         .slave          = &omap44xx_l3_main_2_hwmod,
3818         .clk            = "dbgclk_mux_ck",
3819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3820 };
3821
3822 /* dma_system -> l3_main_2 */
3823 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3824         .master         = &omap44xx_dma_system_hwmod,
3825         .slave          = &omap44xx_l3_main_2_hwmod,
3826         .clk            = "l3_div_ck",
3827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3828 };
3829
3830 /* fdif -> l3_main_2 */
3831 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3832         .master         = &omap44xx_fdif_hwmod,
3833         .slave          = &omap44xx_l3_main_2_hwmod,
3834         .clk            = "l3_div_ck",
3835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3836 };
3837
3838 /* gpu -> l3_main_2 */
3839 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3840         .master         = &omap44xx_gpu_hwmod,
3841         .slave          = &omap44xx_l3_main_2_hwmod,
3842         .clk            = "l3_div_ck",
3843         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3844 };
3845
3846 /* hsi -> l3_main_2 */
3847 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3848         .master         = &omap44xx_hsi_hwmod,
3849         .slave          = &omap44xx_l3_main_2_hwmod,
3850         .clk            = "l3_div_ck",
3851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3852 };
3853
3854 /* ipu -> l3_main_2 */
3855 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3856         .master         = &omap44xx_ipu_hwmod,
3857         .slave          = &omap44xx_l3_main_2_hwmod,
3858         .clk            = "l3_div_ck",
3859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3860 };
3861
3862 /* iss -> l3_main_2 */
3863 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3864         .master         = &omap44xx_iss_hwmod,
3865         .slave          = &omap44xx_l3_main_2_hwmod,
3866         .clk            = "l3_div_ck",
3867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3868 };
3869
3870 /* iva -> l3_main_2 */
3871 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3872         .master         = &omap44xx_iva_hwmod,
3873         .slave          = &omap44xx_l3_main_2_hwmod,
3874         .clk            = "l3_div_ck",
3875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3876 };
3877
3878 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3879         {
3880                 .pa_start       = 0x44800000,
3881                 .pa_end         = 0x44801fff,
3882                 .flags          = ADDR_TYPE_RT
3883         },
3884         { }
3885 };
3886
3887 /* l3_main_1 -> l3_main_2 */
3888 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3889         .master         = &omap44xx_l3_main_1_hwmod,
3890         .slave          = &omap44xx_l3_main_2_hwmod,
3891         .clk            = "l3_div_ck",
3892         .addr           = omap44xx_l3_main_2_addrs,
3893         .user           = OCP_USER_MPU,
3894 };
3895
3896 /* l4_cfg -> l3_main_2 */
3897 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3898         .master         = &omap44xx_l4_cfg_hwmod,
3899         .slave          = &omap44xx_l3_main_2_hwmod,
3900         .clk            = "l4_div_ck",
3901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3902 };
3903
3904 /* usb_host_fs -> l3_main_2 */
3905 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3906         .master         = &omap44xx_usb_host_fs_hwmod,
3907         .slave          = &omap44xx_l3_main_2_hwmod,
3908         .clk            = "l3_div_ck",
3909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3910 };
3911
3912 /* usb_host_hs -> l3_main_2 */
3913 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3914         .master         = &omap44xx_usb_host_hs_hwmod,
3915         .slave          = &omap44xx_l3_main_2_hwmod,
3916         .clk            = "l3_div_ck",
3917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3918 };
3919
3920 /* usb_otg_hs -> l3_main_2 */
3921 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3922         .master         = &omap44xx_usb_otg_hs_hwmod,
3923         .slave          = &omap44xx_l3_main_2_hwmod,
3924         .clk            = "l3_div_ck",
3925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3926 };
3927
3928 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3929         {
3930                 .pa_start       = 0x45000000,
3931                 .pa_end         = 0x45000fff,
3932                 .flags          = ADDR_TYPE_RT
3933         },
3934         { }
3935 };
3936
3937 /* l3_main_1 -> l3_main_3 */
3938 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3939         .master         = &omap44xx_l3_main_1_hwmod,
3940         .slave          = &omap44xx_l3_main_3_hwmod,
3941         .clk            = "l3_div_ck",
3942         .addr           = omap44xx_l3_main_3_addrs,
3943         .user           = OCP_USER_MPU,
3944 };
3945
3946 /* l3_main_2 -> l3_main_3 */
3947 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3948         .master         = &omap44xx_l3_main_2_hwmod,
3949         .slave          = &omap44xx_l3_main_3_hwmod,
3950         .clk            = "l3_div_ck",
3951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3952 };
3953
3954 /* l4_cfg -> l3_main_3 */
3955 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3956         .master         = &omap44xx_l4_cfg_hwmod,
3957         .slave          = &omap44xx_l3_main_3_hwmod,
3958         .clk            = "l4_div_ck",
3959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3960 };
3961
3962 /* aess -> l4_abe */
3963 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3964         .master         = &omap44xx_aess_hwmod,
3965         .slave          = &omap44xx_l4_abe_hwmod,
3966         .clk            = "ocp_abe_iclk",
3967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3969
3970 /* dsp -> l4_abe */
3971 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3972         .master         = &omap44xx_dsp_hwmod,
3973         .slave          = &omap44xx_l4_abe_hwmod,
3974         .clk            = "ocp_abe_iclk",
3975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 /* l3_main_1 -> l4_abe */
3979 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3980         .master         = &omap44xx_l3_main_1_hwmod,
3981         .slave          = &omap44xx_l4_abe_hwmod,
3982         .clk            = "l3_div_ck",
3983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3984 };
3985
3986 /* mpu -> l4_abe */
3987 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3988         .master         = &omap44xx_mpu_hwmod,
3989         .slave          = &omap44xx_l4_abe_hwmod,
3990         .clk            = "ocp_abe_iclk",
3991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3992 };
3993
3994 /* l3_main_1 -> l4_cfg */
3995 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3996         .master         = &omap44xx_l3_main_1_hwmod,
3997         .slave          = &omap44xx_l4_cfg_hwmod,
3998         .clk            = "l3_div_ck",
3999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4000 };
4001
4002 /* l3_main_2 -> l4_per */
4003 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4004         .master         = &omap44xx_l3_main_2_hwmod,
4005         .slave          = &omap44xx_l4_per_hwmod,
4006         .clk            = "l3_div_ck",
4007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4008 };
4009
4010 /* l4_cfg -> l4_wkup */
4011 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4012         .master         = &omap44xx_l4_cfg_hwmod,
4013         .slave          = &omap44xx_l4_wkup_hwmod,
4014         .clk            = "l4_div_ck",
4015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4016 };
4017
4018 /* mpu -> mpu_private */
4019 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4020         .master         = &omap44xx_mpu_hwmod,
4021         .slave          = &omap44xx_mpu_private_hwmod,
4022         .clk            = "l3_div_ck",
4023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4024 };
4025
4026 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4027         {
4028                 .pa_start       = 0x4a102000,
4029                 .pa_end         = 0x4a10207f,
4030                 .flags          = ADDR_TYPE_RT
4031         },
4032         { }
4033 };
4034
4035 /* l4_cfg -> ocp_wp_noc */
4036 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4037         .master         = &omap44xx_l4_cfg_hwmod,
4038         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4039         .clk            = "l4_div_ck",
4040         .addr           = omap44xx_ocp_wp_noc_addrs,
4041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4045         {
4046                 .pa_start       = 0x401f1000,
4047                 .pa_end         = 0x401f13ff,
4048                 .flags          = ADDR_TYPE_RT
4049         },
4050         { }
4051 };
4052
4053 /* l4_abe -> aess */
4054 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4055         .master         = &omap44xx_l4_abe_hwmod,
4056         .slave          = &omap44xx_aess_hwmod,
4057         .clk            = "ocp_abe_iclk",
4058         .addr           = omap44xx_aess_addrs,
4059         .user           = OCP_USER_MPU,
4060 };
4061
4062 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4063         {
4064                 .pa_start       = 0x490f1000,
4065                 .pa_end         = 0x490f13ff,
4066                 .flags          = ADDR_TYPE_RT
4067         },
4068         { }
4069 };
4070
4071 /* l4_abe -> aess (dma) */
4072 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4073         .master         = &omap44xx_l4_abe_hwmod,
4074         .slave          = &omap44xx_aess_hwmod,
4075         .clk            = "ocp_abe_iclk",
4076         .addr           = omap44xx_aess_dma_addrs,
4077         .user           = OCP_USER_SDMA,
4078 };
4079
4080 /* l3_main_2 -> c2c */
4081 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4082         .master         = &omap44xx_l3_main_2_hwmod,
4083         .slave          = &omap44xx_c2c_hwmod,
4084         .clk            = "l3_div_ck",
4085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4086 };
4087
4088 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4089         {
4090                 .pa_start       = 0x4a304000,
4091                 .pa_end         = 0x4a30401f,
4092                 .flags          = ADDR_TYPE_RT
4093         },
4094         { }
4095 };
4096
4097 /* l4_wkup -> counter_32k */
4098 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4099         .master         = &omap44xx_l4_wkup_hwmod,
4100         .slave          = &omap44xx_counter_32k_hwmod,
4101         .clk            = "l4_wkup_clk_mux_ck",
4102         .addr           = omap44xx_counter_32k_addrs,
4103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4104 };
4105
4106 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4107         {
4108                 .pa_start       = 0x4a002000,
4109                 .pa_end         = 0x4a0027ff,
4110                 .flags          = ADDR_TYPE_RT
4111         },
4112         { }
4113 };
4114
4115 /* l4_cfg -> ctrl_module_core */
4116 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4117         .master         = &omap44xx_l4_cfg_hwmod,
4118         .slave          = &omap44xx_ctrl_module_core_hwmod,
4119         .clk            = "l4_div_ck",
4120         .addr           = omap44xx_ctrl_module_core_addrs,
4121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4122 };
4123
4124 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4125         {
4126                 .pa_start       = 0x4a100000,
4127                 .pa_end         = 0x4a1007ff,
4128                 .flags          = ADDR_TYPE_RT
4129         },
4130         { }
4131 };
4132
4133 /* l4_cfg -> ctrl_module_pad_core */
4134 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4135         .master         = &omap44xx_l4_cfg_hwmod,
4136         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4137         .clk            = "l4_div_ck",
4138         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4140 };
4141
4142 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4143         {
4144                 .pa_start       = 0x4a30c000,
4145                 .pa_end         = 0x4a30c7ff,
4146                 .flags          = ADDR_TYPE_RT
4147         },
4148         { }
4149 };
4150
4151 /* l4_wkup -> ctrl_module_wkup */
4152 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4153         .master         = &omap44xx_l4_wkup_hwmod,
4154         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4155         .clk            = "l4_wkup_clk_mux_ck",
4156         .addr           = omap44xx_ctrl_module_wkup_addrs,
4157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4158 };
4159
4160 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4161         {
4162                 .pa_start       = 0x4a31e000,
4163                 .pa_end         = 0x4a31e7ff,
4164                 .flags          = ADDR_TYPE_RT
4165         },
4166         { }
4167 };
4168
4169 /* l4_wkup -> ctrl_module_pad_wkup */
4170 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4171         .master         = &omap44xx_l4_wkup_hwmod,
4172         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4173         .clk            = "l4_wkup_clk_mux_ck",
4174         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4175         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4176 };
4177
4178 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4179         {
4180                 .pa_start       = 0x54160000,
4181                 .pa_end         = 0x54167fff,
4182                 .flags          = ADDR_TYPE_RT
4183         },
4184         { }
4185 };
4186
4187 /* l3_instr -> debugss */
4188 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4189         .master         = &omap44xx_l3_instr_hwmod,
4190         .slave          = &omap44xx_debugss_hwmod,
4191         .clk            = "l3_div_ck",
4192         .addr           = omap44xx_debugss_addrs,
4193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4194 };
4195
4196 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4197         {
4198                 .pa_start       = 0x4a056000,
4199                 .pa_end         = 0x4a056fff,
4200                 .flags          = ADDR_TYPE_RT
4201         },
4202         { }
4203 };
4204
4205 /* l4_cfg -> dma_system */
4206 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4207         .master         = &omap44xx_l4_cfg_hwmod,
4208         .slave          = &omap44xx_dma_system_hwmod,
4209         .clk            = "l4_div_ck",
4210         .addr           = omap44xx_dma_system_addrs,
4211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4212 };
4213
4214 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4215         {
4216                 .name           = "mpu",
4217                 .pa_start       = 0x4012e000,
4218                 .pa_end         = 0x4012e07f,
4219                 .flags          = ADDR_TYPE_RT
4220         },
4221         { }
4222 };
4223
4224 /* l4_abe -> dmic */
4225 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4226         .master         = &omap44xx_l4_abe_hwmod,
4227         .slave          = &omap44xx_dmic_hwmod,
4228         .clk            = "ocp_abe_iclk",
4229         .addr           = omap44xx_dmic_addrs,
4230         .user           = OCP_USER_MPU,
4231 };
4232
4233 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4234         {
4235                 .name           = "dma",
4236                 .pa_start       = 0x4902e000,
4237                 .pa_end         = 0x4902e07f,
4238                 .flags          = ADDR_TYPE_RT
4239         },
4240         { }
4241 };
4242
4243 /* l4_abe -> dmic (dma) */
4244 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4245         .master         = &omap44xx_l4_abe_hwmod,
4246         .slave          = &omap44xx_dmic_hwmod,
4247         .clk            = "ocp_abe_iclk",
4248         .addr           = omap44xx_dmic_dma_addrs,
4249         .user           = OCP_USER_SDMA,
4250 };
4251
4252 /* dsp -> iva */
4253 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4254         .master         = &omap44xx_dsp_hwmod,
4255         .slave          = &omap44xx_iva_hwmod,
4256         .clk            = "dpll_iva_m5x2_ck",
4257         .user           = OCP_USER_DSP,
4258 };
4259
4260 /* dsp -> sl2if */
4261 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4262         .master         = &omap44xx_dsp_hwmod,
4263         .slave          = &omap44xx_sl2if_hwmod,
4264         .clk            = "dpll_iva_m5x2_ck",
4265         .user           = OCP_USER_DSP,
4266 };
4267
4268 /* l4_cfg -> dsp */
4269 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4270         .master         = &omap44xx_l4_cfg_hwmod,
4271         .slave          = &omap44xx_dsp_hwmod,
4272         .clk            = "l4_div_ck",
4273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4274 };
4275
4276 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4277         {
4278                 .pa_start       = 0x58000000,
4279                 .pa_end         = 0x5800007f,
4280                 .flags          = ADDR_TYPE_RT
4281         },
4282         { }
4283 };
4284
4285 /* l3_main_2 -> dss */
4286 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4287         .master         = &omap44xx_l3_main_2_hwmod,
4288         .slave          = &omap44xx_dss_hwmod,
4289         .clk            = "dss_fck",
4290         .addr           = omap44xx_dss_dma_addrs,
4291         .user           = OCP_USER_SDMA,
4292 };
4293
4294 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4295         {
4296                 .pa_start       = 0x48040000,
4297                 .pa_end         = 0x4804007f,
4298                 .flags          = ADDR_TYPE_RT
4299         },
4300         { }
4301 };
4302
4303 /* l4_per -> dss */
4304 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4305         .master         = &omap44xx_l4_per_hwmod,
4306         .slave          = &omap44xx_dss_hwmod,
4307         .clk            = "l4_div_ck",
4308         .addr           = omap44xx_dss_addrs,
4309         .user           = OCP_USER_MPU,
4310 };
4311
4312 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4313         {
4314                 .pa_start       = 0x58001000,
4315                 .pa_end         = 0x58001fff,
4316                 .flags          = ADDR_TYPE_RT
4317         },
4318         { }
4319 };
4320
4321 /* l3_main_2 -> dss_dispc */
4322 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4323         .master         = &omap44xx_l3_main_2_hwmod,
4324         .slave          = &omap44xx_dss_dispc_hwmod,
4325         .clk            = "dss_fck",
4326         .addr           = omap44xx_dss_dispc_dma_addrs,
4327         .user           = OCP_USER_SDMA,
4328 };
4329
4330 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4331         {
4332                 .pa_start       = 0x48041000,
4333                 .pa_end         = 0x48041fff,
4334                 .flags          = ADDR_TYPE_RT
4335         },
4336         { }
4337 };
4338
4339 /* l4_per -> dss_dispc */
4340 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4341         .master         = &omap44xx_l4_per_hwmod,
4342         .slave          = &omap44xx_dss_dispc_hwmod,
4343         .clk            = "l4_div_ck",
4344         .addr           = omap44xx_dss_dispc_addrs,
4345         .user           = OCP_USER_MPU,
4346 };
4347
4348 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4349         {
4350                 .pa_start       = 0x58004000,
4351                 .pa_end         = 0x580041ff,
4352                 .flags          = ADDR_TYPE_RT
4353         },
4354         { }
4355 };
4356
4357 /* l3_main_2 -> dss_dsi1 */
4358 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4359         .master         = &omap44xx_l3_main_2_hwmod,
4360         .slave          = &omap44xx_dss_dsi1_hwmod,
4361         .clk            = "dss_fck",
4362         .addr           = omap44xx_dss_dsi1_dma_addrs,
4363         .user           = OCP_USER_SDMA,
4364 };
4365
4366 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4367         {
4368                 .pa_start       = 0x48044000,
4369                 .pa_end         = 0x480441ff,
4370                 .flags          = ADDR_TYPE_RT
4371         },
4372         { }
4373 };
4374
4375 /* l4_per -> dss_dsi1 */
4376 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4377         .master         = &omap44xx_l4_per_hwmod,
4378         .slave          = &omap44xx_dss_dsi1_hwmod,
4379         .clk            = "l4_div_ck",
4380         .addr           = omap44xx_dss_dsi1_addrs,
4381         .user           = OCP_USER_MPU,
4382 };
4383
4384 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4385         {
4386                 .pa_start       = 0x58005000,
4387                 .pa_end         = 0x580051ff,
4388                 .flags          = ADDR_TYPE_RT
4389         },
4390         { }
4391 };
4392
4393 /* l3_main_2 -> dss_dsi2 */
4394 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4395         .master         = &omap44xx_l3_main_2_hwmod,
4396         .slave          = &omap44xx_dss_dsi2_hwmod,
4397         .clk            = "dss_fck",
4398         .addr           = omap44xx_dss_dsi2_dma_addrs,
4399         .user           = OCP_USER_SDMA,
4400 };
4401
4402 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4403         {
4404                 .pa_start       = 0x48045000,
4405                 .pa_end         = 0x480451ff,
4406                 .flags          = ADDR_TYPE_RT
4407         },
4408         { }
4409 };
4410
4411 /* l4_per -> dss_dsi2 */
4412 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4413         .master         = &omap44xx_l4_per_hwmod,
4414         .slave          = &omap44xx_dss_dsi2_hwmod,
4415         .clk            = "l4_div_ck",
4416         .addr           = omap44xx_dss_dsi2_addrs,
4417         .user           = OCP_USER_MPU,
4418 };
4419
4420 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4421         {
4422                 .pa_start       = 0x58006000,
4423                 .pa_end         = 0x58006fff,
4424                 .flags          = ADDR_TYPE_RT
4425         },
4426         { }
4427 };
4428
4429 /* l3_main_2 -> dss_hdmi */
4430 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4431         .master         = &omap44xx_l3_main_2_hwmod,
4432         .slave          = &omap44xx_dss_hdmi_hwmod,
4433         .clk            = "dss_fck",
4434         .addr           = omap44xx_dss_hdmi_dma_addrs,
4435         .user           = OCP_USER_SDMA,
4436 };
4437
4438 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4439         {
4440                 .pa_start       = 0x48046000,
4441                 .pa_end         = 0x48046fff,
4442                 .flags          = ADDR_TYPE_RT
4443         },
4444         { }
4445 };
4446
4447 /* l4_per -> dss_hdmi */
4448 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4449         .master         = &omap44xx_l4_per_hwmod,
4450         .slave          = &omap44xx_dss_hdmi_hwmod,
4451         .clk            = "l4_div_ck",
4452         .addr           = omap44xx_dss_hdmi_addrs,
4453         .user           = OCP_USER_MPU,
4454 };
4455
4456 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4457         {
4458                 .pa_start       = 0x58002000,
4459                 .pa_end         = 0x580020ff,
4460                 .flags          = ADDR_TYPE_RT
4461         },
4462         { }
4463 };
4464
4465 /* l3_main_2 -> dss_rfbi */
4466 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4467         .master         = &omap44xx_l3_main_2_hwmod,
4468         .slave          = &omap44xx_dss_rfbi_hwmod,
4469         .clk            = "dss_fck",
4470         .addr           = omap44xx_dss_rfbi_dma_addrs,
4471         .user           = OCP_USER_SDMA,
4472 };
4473
4474 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4475         {
4476                 .pa_start       = 0x48042000,
4477                 .pa_end         = 0x480420ff,
4478                 .flags          = ADDR_TYPE_RT
4479         },
4480         { }
4481 };
4482
4483 /* l4_per -> dss_rfbi */
4484 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4485         .master         = &omap44xx_l4_per_hwmod,
4486         .slave          = &omap44xx_dss_rfbi_hwmod,
4487         .clk            = "l4_div_ck",
4488         .addr           = omap44xx_dss_rfbi_addrs,
4489         .user           = OCP_USER_MPU,
4490 };
4491
4492 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4493         {
4494                 .pa_start       = 0x58003000,
4495                 .pa_end         = 0x580030ff,
4496                 .flags          = ADDR_TYPE_RT
4497         },
4498         { }
4499 };
4500
4501 /* l3_main_2 -> dss_venc */
4502 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4503         .master         = &omap44xx_l3_main_2_hwmod,
4504         .slave          = &omap44xx_dss_venc_hwmod,
4505         .clk            = "dss_fck",
4506         .addr           = omap44xx_dss_venc_dma_addrs,
4507         .user           = OCP_USER_SDMA,
4508 };
4509
4510 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4511         {
4512                 .pa_start       = 0x48043000,
4513                 .pa_end         = 0x480430ff,
4514                 .flags          = ADDR_TYPE_RT
4515         },
4516         { }
4517 };
4518
4519 /* l4_per -> dss_venc */
4520 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4521         .master         = &omap44xx_l4_per_hwmod,
4522         .slave          = &omap44xx_dss_venc_hwmod,
4523         .clk            = "l4_div_ck",
4524         .addr           = omap44xx_dss_venc_addrs,
4525         .user           = OCP_USER_MPU,
4526 };
4527
4528 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4529         {
4530                 .pa_start       = 0x48078000,
4531                 .pa_end         = 0x48078fff,
4532                 .flags          = ADDR_TYPE_RT
4533         },
4534         { }
4535 };
4536
4537 /* l4_per -> elm */
4538 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4539         .master         = &omap44xx_l4_per_hwmod,
4540         .slave          = &omap44xx_elm_hwmod,
4541         .clk            = "l4_div_ck",
4542         .addr           = omap44xx_elm_addrs,
4543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4544 };
4545
4546 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4547         {
4548                 .pa_start       = 0x4c000000,
4549                 .pa_end         = 0x4c0000ff,
4550                 .flags          = ADDR_TYPE_RT
4551         },
4552         { }
4553 };
4554
4555 /* emif_fw -> emif1 */
4556 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4557         .master         = &omap44xx_emif_fw_hwmod,
4558         .slave          = &omap44xx_emif1_hwmod,
4559         .clk            = "l3_div_ck",
4560         .addr           = omap44xx_emif1_addrs,
4561         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4562 };
4563
4564 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4565         {
4566                 .pa_start       = 0x4d000000,
4567                 .pa_end         = 0x4d0000ff,
4568                 .flags          = ADDR_TYPE_RT
4569         },
4570         { }
4571 };
4572
4573 /* emif_fw -> emif2 */
4574 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4575         .master         = &omap44xx_emif_fw_hwmod,
4576         .slave          = &omap44xx_emif2_hwmod,
4577         .clk            = "l3_div_ck",
4578         .addr           = omap44xx_emif2_addrs,
4579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4580 };
4581
4582 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4583         {
4584                 .pa_start       = 0x4a10a000,
4585                 .pa_end         = 0x4a10a1ff,
4586                 .flags          = ADDR_TYPE_RT
4587         },
4588         { }
4589 };
4590
4591 /* l4_cfg -> fdif */
4592 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4593         .master         = &omap44xx_l4_cfg_hwmod,
4594         .slave          = &omap44xx_fdif_hwmod,
4595         .clk            = "l4_div_ck",
4596         .addr           = omap44xx_fdif_addrs,
4597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4598 };
4599
4600 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4601         {
4602                 .pa_start       = 0x4a310000,
4603                 .pa_end         = 0x4a3101ff,
4604                 .flags          = ADDR_TYPE_RT
4605         },
4606         { }
4607 };
4608
4609 /* l4_wkup -> gpio1 */
4610 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4611         .master         = &omap44xx_l4_wkup_hwmod,
4612         .slave          = &omap44xx_gpio1_hwmod,
4613         .clk            = "l4_wkup_clk_mux_ck",
4614         .addr           = omap44xx_gpio1_addrs,
4615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4616 };
4617
4618 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4619         {
4620                 .pa_start       = 0x48055000,
4621                 .pa_end         = 0x480551ff,
4622                 .flags          = ADDR_TYPE_RT
4623         },
4624         { }
4625 };
4626
4627 /* l4_per -> gpio2 */
4628 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4629         .master         = &omap44xx_l4_per_hwmod,
4630         .slave          = &omap44xx_gpio2_hwmod,
4631         .clk            = "l4_div_ck",
4632         .addr           = omap44xx_gpio2_addrs,
4633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4634 };
4635
4636 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4637         {
4638                 .pa_start       = 0x48057000,
4639                 .pa_end         = 0x480571ff,
4640                 .flags          = ADDR_TYPE_RT
4641         },
4642         { }
4643 };
4644
4645 /* l4_per -> gpio3 */
4646 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4647         .master         = &omap44xx_l4_per_hwmod,
4648         .slave          = &omap44xx_gpio3_hwmod,
4649         .clk            = "l4_div_ck",
4650         .addr           = omap44xx_gpio3_addrs,
4651         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4652 };
4653
4654 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4655         {
4656                 .pa_start       = 0x48059000,
4657                 .pa_end         = 0x480591ff,
4658                 .flags          = ADDR_TYPE_RT
4659         },
4660         { }
4661 };
4662
4663 /* l4_per -> gpio4 */
4664 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4665         .master         = &omap44xx_l4_per_hwmod,
4666         .slave          = &omap44xx_gpio4_hwmod,
4667         .clk            = "l4_div_ck",
4668         .addr           = omap44xx_gpio4_addrs,
4669         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4670 };
4671
4672 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4673         {
4674                 .pa_start       = 0x4805b000,
4675                 .pa_end         = 0x4805b1ff,
4676                 .flags          = ADDR_TYPE_RT
4677         },
4678         { }
4679 };
4680
4681 /* l4_per -> gpio5 */
4682 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4683         .master         = &omap44xx_l4_per_hwmod,
4684         .slave          = &omap44xx_gpio5_hwmod,
4685         .clk            = "l4_div_ck",
4686         .addr           = omap44xx_gpio5_addrs,
4687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4688 };
4689
4690 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4691         {
4692                 .pa_start       = 0x4805d000,
4693                 .pa_end         = 0x4805d1ff,
4694                 .flags          = ADDR_TYPE_RT
4695         },
4696         { }
4697 };
4698
4699 /* l4_per -> gpio6 */
4700 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4701         .master         = &omap44xx_l4_per_hwmod,
4702         .slave          = &omap44xx_gpio6_hwmod,
4703         .clk            = "l4_div_ck",
4704         .addr           = omap44xx_gpio6_addrs,
4705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4706 };
4707
4708 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4709         {
4710                 .pa_start       = 0x50000000,
4711                 .pa_end         = 0x500003ff,
4712                 .flags          = ADDR_TYPE_RT
4713         },
4714         { }
4715 };
4716
4717 /* l3_main_2 -> gpmc */
4718 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4719         .master         = &omap44xx_l3_main_2_hwmod,
4720         .slave          = &omap44xx_gpmc_hwmod,
4721         .clk            = "l3_div_ck",
4722         .addr           = omap44xx_gpmc_addrs,
4723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4724 };
4725
4726 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4727         {
4728                 .pa_start       = 0x56000000,
4729                 .pa_end         = 0x5600ffff,
4730                 .flags          = ADDR_TYPE_RT
4731         },
4732         { }
4733 };
4734
4735 /* l3_main_2 -> gpu */
4736 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4737         .master         = &omap44xx_l3_main_2_hwmod,
4738         .slave          = &omap44xx_gpu_hwmod,
4739         .clk            = "l3_div_ck",
4740         .addr           = omap44xx_gpu_addrs,
4741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4742 };
4743
4744 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4745         {
4746                 .pa_start       = 0x480b2000,
4747                 .pa_end         = 0x480b201f,
4748                 .flags          = ADDR_TYPE_RT
4749         },
4750         { }
4751 };
4752
4753 /* l4_per -> hdq1w */
4754 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4755         .master         = &omap44xx_l4_per_hwmod,
4756         .slave          = &omap44xx_hdq1w_hwmod,
4757         .clk            = "l4_div_ck",
4758         .addr           = omap44xx_hdq1w_addrs,
4759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4760 };
4761
4762 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4763         {
4764                 .pa_start       = 0x4a058000,
4765                 .pa_end         = 0x4a05bfff,
4766                 .flags          = ADDR_TYPE_RT
4767         },
4768         { }
4769 };
4770
4771 /* l4_cfg -> hsi */
4772 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4773         .master         = &omap44xx_l4_cfg_hwmod,
4774         .slave          = &omap44xx_hsi_hwmod,
4775         .clk            = "l4_div_ck",
4776         .addr           = omap44xx_hsi_addrs,
4777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4778 };
4779
4780 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4781         {
4782                 .pa_start       = 0x48070000,
4783                 .pa_end         = 0x480700ff,
4784                 .flags          = ADDR_TYPE_RT
4785         },
4786         { }
4787 };
4788
4789 /* l4_per -> i2c1 */
4790 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4791         .master         = &omap44xx_l4_per_hwmod,
4792         .slave          = &omap44xx_i2c1_hwmod,
4793         .clk            = "l4_div_ck",
4794         .addr           = omap44xx_i2c1_addrs,
4795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4796 };
4797
4798 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4799         {
4800                 .pa_start       = 0x48072000,
4801                 .pa_end         = 0x480720ff,
4802                 .flags          = ADDR_TYPE_RT
4803         },
4804         { }
4805 };
4806
4807 /* l4_per -> i2c2 */
4808 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4809         .master         = &omap44xx_l4_per_hwmod,
4810         .slave          = &omap44xx_i2c2_hwmod,
4811         .clk            = "l4_div_ck",
4812         .addr           = omap44xx_i2c2_addrs,
4813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4814 };
4815
4816 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4817         {
4818                 .pa_start       = 0x48060000,
4819                 .pa_end         = 0x480600ff,
4820                 .flags          = ADDR_TYPE_RT
4821         },
4822         { }
4823 };
4824
4825 /* l4_per -> i2c3 */
4826 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4827         .master         = &omap44xx_l4_per_hwmod,
4828         .slave          = &omap44xx_i2c3_hwmod,
4829         .clk            = "l4_div_ck",
4830         .addr           = omap44xx_i2c3_addrs,
4831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4832 };
4833
4834 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4835         {
4836                 .pa_start       = 0x48350000,
4837                 .pa_end         = 0x483500ff,
4838                 .flags          = ADDR_TYPE_RT
4839         },
4840         { }
4841 };
4842
4843 /* l4_per -> i2c4 */
4844 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4845         .master         = &omap44xx_l4_per_hwmod,
4846         .slave          = &omap44xx_i2c4_hwmod,
4847         .clk            = "l4_div_ck",
4848         .addr           = omap44xx_i2c4_addrs,
4849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4850 };
4851
4852 /* l3_main_2 -> ipu */
4853 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4854         .master         = &omap44xx_l3_main_2_hwmod,
4855         .slave          = &omap44xx_ipu_hwmod,
4856         .clk            = "l3_div_ck",
4857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4858 };
4859
4860 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4861         {
4862                 .pa_start       = 0x52000000,
4863                 .pa_end         = 0x520000ff,
4864                 .flags          = ADDR_TYPE_RT
4865         },
4866         { }
4867 };
4868
4869 /* l3_main_2 -> iss */
4870 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4871         .master         = &omap44xx_l3_main_2_hwmod,
4872         .slave          = &omap44xx_iss_hwmod,
4873         .clk            = "l3_div_ck",
4874         .addr           = omap44xx_iss_addrs,
4875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4876 };
4877
4878 /* iva -> sl2if */
4879 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4880         .master         = &omap44xx_iva_hwmod,
4881         .slave          = &omap44xx_sl2if_hwmod,
4882         .clk            = "dpll_iva_m5x2_ck",
4883         .user           = OCP_USER_IVA,
4884 };
4885
4886 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4887         {
4888                 .pa_start       = 0x5a000000,
4889                 .pa_end         = 0x5a07ffff,
4890                 .flags          = ADDR_TYPE_RT
4891         },
4892         { }
4893 };
4894
4895 /* l3_main_2 -> iva */
4896 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4897         .master         = &omap44xx_l3_main_2_hwmod,
4898         .slave          = &omap44xx_iva_hwmod,
4899         .clk            = "l3_div_ck",
4900         .addr           = omap44xx_iva_addrs,
4901         .user           = OCP_USER_MPU,
4902 };
4903
4904 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4905         {
4906                 .pa_start       = 0x4a31c000,
4907                 .pa_end         = 0x4a31c07f,
4908                 .flags          = ADDR_TYPE_RT
4909         },
4910         { }
4911 };
4912
4913 /* l4_wkup -> kbd */
4914 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4915         .master         = &omap44xx_l4_wkup_hwmod,
4916         .slave          = &omap44xx_kbd_hwmod,
4917         .clk            = "l4_wkup_clk_mux_ck",
4918         .addr           = omap44xx_kbd_addrs,
4919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4920 };
4921
4922 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4923         {
4924                 .pa_start       = 0x4a0f4000,
4925                 .pa_end         = 0x4a0f41ff,
4926                 .flags          = ADDR_TYPE_RT
4927         },
4928         { }
4929 };
4930
4931 /* l4_cfg -> mailbox */
4932 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4933         .master         = &omap44xx_l4_cfg_hwmod,
4934         .slave          = &omap44xx_mailbox_hwmod,
4935         .clk            = "l4_div_ck",
4936         .addr           = omap44xx_mailbox_addrs,
4937         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4938 };
4939
4940 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4941         {
4942                 .pa_start       = 0x40128000,
4943                 .pa_end         = 0x401283ff,
4944                 .flags          = ADDR_TYPE_RT
4945         },
4946         { }
4947 };
4948
4949 /* l4_abe -> mcasp */
4950 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4951         .master         = &omap44xx_l4_abe_hwmod,
4952         .slave          = &omap44xx_mcasp_hwmod,
4953         .clk            = "ocp_abe_iclk",
4954         .addr           = omap44xx_mcasp_addrs,
4955         .user           = OCP_USER_MPU,
4956 };
4957
4958 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4959         {
4960                 .pa_start       = 0x49028000,
4961                 .pa_end         = 0x490283ff,
4962                 .flags          = ADDR_TYPE_RT
4963         },
4964         { }
4965 };
4966
4967 /* l4_abe -> mcasp (dma) */
4968 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4969         .master         = &omap44xx_l4_abe_hwmod,
4970         .slave          = &omap44xx_mcasp_hwmod,
4971         .clk            = "ocp_abe_iclk",
4972         .addr           = omap44xx_mcasp_dma_addrs,
4973         .user           = OCP_USER_SDMA,
4974 };
4975
4976 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4977         {
4978                 .name           = "mpu",
4979                 .pa_start       = 0x40122000,
4980                 .pa_end         = 0x401220ff,
4981                 .flags          = ADDR_TYPE_RT
4982         },
4983         { }
4984 };
4985
4986 /* l4_abe -> mcbsp1 */
4987 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4988         .master         = &omap44xx_l4_abe_hwmod,
4989         .slave          = &omap44xx_mcbsp1_hwmod,
4990         .clk            = "ocp_abe_iclk",
4991         .addr           = omap44xx_mcbsp1_addrs,
4992         .user           = OCP_USER_MPU,
4993 };
4994
4995 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4996         {
4997                 .name           = "dma",
4998                 .pa_start       = 0x49022000,
4999                 .pa_end         = 0x490220ff,
5000                 .flags          = ADDR_TYPE_RT
5001         },
5002         { }
5003 };
5004
5005 /* l4_abe -> mcbsp1 (dma) */
5006 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5007         .master         = &omap44xx_l4_abe_hwmod,
5008         .slave          = &omap44xx_mcbsp1_hwmod,
5009         .clk            = "ocp_abe_iclk",
5010         .addr           = omap44xx_mcbsp1_dma_addrs,
5011         .user           = OCP_USER_SDMA,
5012 };
5013
5014 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5015         {
5016                 .name           = "mpu",
5017                 .pa_start       = 0x40124000,
5018                 .pa_end         = 0x401240ff,
5019                 .flags          = ADDR_TYPE_RT
5020         },
5021         { }
5022 };
5023
5024 /* l4_abe -> mcbsp2 */
5025 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5026         .master         = &omap44xx_l4_abe_hwmod,
5027         .slave          = &omap44xx_mcbsp2_hwmod,
5028         .clk            = "ocp_abe_iclk",
5029         .addr           = omap44xx_mcbsp2_addrs,
5030         .user           = OCP_USER_MPU,
5031 };
5032
5033 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5034         {
5035                 .name           = "dma",
5036                 .pa_start       = 0x49024000,
5037                 .pa_end         = 0x490240ff,
5038                 .flags          = ADDR_TYPE_RT
5039         },
5040         { }
5041 };
5042
5043 /* l4_abe -> mcbsp2 (dma) */
5044 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5045         .master         = &omap44xx_l4_abe_hwmod,
5046         .slave          = &omap44xx_mcbsp2_hwmod,
5047         .clk            = "ocp_abe_iclk",
5048         .addr           = omap44xx_mcbsp2_dma_addrs,
5049         .user           = OCP_USER_SDMA,
5050 };
5051
5052 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5053         {
5054                 .name           = "mpu",
5055                 .pa_start       = 0x40126000,
5056                 .pa_end         = 0x401260ff,
5057                 .flags          = ADDR_TYPE_RT
5058         },
5059         { }
5060 };
5061
5062 /* l4_abe -> mcbsp3 */
5063 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5064         .master         = &omap44xx_l4_abe_hwmod,
5065         .slave          = &omap44xx_mcbsp3_hwmod,
5066         .clk            = "ocp_abe_iclk",
5067         .addr           = omap44xx_mcbsp3_addrs,
5068         .user           = OCP_USER_MPU,
5069 };
5070
5071 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5072         {
5073                 .name           = "dma",
5074                 .pa_start       = 0x49026000,
5075                 .pa_end         = 0x490260ff,
5076                 .flags          = ADDR_TYPE_RT
5077         },
5078         { }
5079 };
5080
5081 /* l4_abe -> mcbsp3 (dma) */
5082 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5083         .master         = &omap44xx_l4_abe_hwmod,
5084         .slave          = &omap44xx_mcbsp3_hwmod,
5085         .clk            = "ocp_abe_iclk",
5086         .addr           = omap44xx_mcbsp3_dma_addrs,
5087         .user           = OCP_USER_SDMA,
5088 };
5089
5090 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5091         {
5092                 .pa_start       = 0x48096000,
5093                 .pa_end         = 0x480960ff,
5094                 .flags          = ADDR_TYPE_RT
5095         },
5096         { }
5097 };
5098
5099 /* l4_per -> mcbsp4 */
5100 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5101         .master         = &omap44xx_l4_per_hwmod,
5102         .slave          = &omap44xx_mcbsp4_hwmod,
5103         .clk            = "l4_div_ck",
5104         .addr           = omap44xx_mcbsp4_addrs,
5105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5106 };
5107
5108 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5109         {
5110                 .pa_start       = 0x40132000,
5111                 .pa_end         = 0x4013207f,
5112                 .flags          = ADDR_TYPE_RT
5113         },
5114         { }
5115 };
5116
5117 /* l4_abe -> mcpdm */
5118 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5119         .master         = &omap44xx_l4_abe_hwmod,
5120         .slave          = &omap44xx_mcpdm_hwmod,
5121         .clk            = "ocp_abe_iclk",
5122         .addr           = omap44xx_mcpdm_addrs,
5123         .user           = OCP_USER_MPU,
5124 };
5125
5126 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5127         {
5128                 .pa_start       = 0x49032000,
5129                 .pa_end         = 0x4903207f,
5130                 .flags          = ADDR_TYPE_RT
5131         },
5132         { }
5133 };
5134
5135 /* l4_abe -> mcpdm (dma) */
5136 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5137         .master         = &omap44xx_l4_abe_hwmod,
5138         .slave          = &omap44xx_mcpdm_hwmod,
5139         .clk            = "ocp_abe_iclk",
5140         .addr           = omap44xx_mcpdm_dma_addrs,
5141         .user           = OCP_USER_SDMA,
5142 };
5143
5144 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5145         {
5146                 .pa_start       = 0x48098000,
5147                 .pa_end         = 0x480981ff,
5148                 .flags          = ADDR_TYPE_RT
5149         },
5150         { }
5151 };
5152
5153 /* l4_per -> mcspi1 */
5154 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5155         .master         = &omap44xx_l4_per_hwmod,
5156         .slave          = &omap44xx_mcspi1_hwmod,
5157         .clk            = "l4_div_ck",
5158         .addr           = omap44xx_mcspi1_addrs,
5159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5160 };
5161
5162 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5163         {
5164                 .pa_start       = 0x4809a000,
5165                 .pa_end         = 0x4809a1ff,
5166                 .flags          = ADDR_TYPE_RT
5167         },
5168         { }
5169 };
5170
5171 /* l4_per -> mcspi2 */
5172 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5173         .master         = &omap44xx_l4_per_hwmod,
5174         .slave          = &omap44xx_mcspi2_hwmod,
5175         .clk            = "l4_div_ck",
5176         .addr           = omap44xx_mcspi2_addrs,
5177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5178 };
5179
5180 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5181         {
5182                 .pa_start       = 0x480b8000,
5183                 .pa_end         = 0x480b81ff,
5184                 .flags          = ADDR_TYPE_RT
5185         },
5186         { }
5187 };
5188
5189 /* l4_per -> mcspi3 */
5190 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5191         .master         = &omap44xx_l4_per_hwmod,
5192         .slave          = &omap44xx_mcspi3_hwmod,
5193         .clk            = "l4_div_ck",
5194         .addr           = omap44xx_mcspi3_addrs,
5195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5196 };
5197
5198 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5199         {
5200                 .pa_start       = 0x480ba000,
5201                 .pa_end         = 0x480ba1ff,
5202                 .flags          = ADDR_TYPE_RT
5203         },
5204         { }
5205 };
5206
5207 /* l4_per -> mcspi4 */
5208 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5209         .master         = &omap44xx_l4_per_hwmod,
5210         .slave          = &omap44xx_mcspi4_hwmod,
5211         .clk            = "l4_div_ck",
5212         .addr           = omap44xx_mcspi4_addrs,
5213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5214 };
5215
5216 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5217         {
5218                 .pa_start       = 0x4809c000,
5219                 .pa_end         = 0x4809c3ff,
5220                 .flags          = ADDR_TYPE_RT
5221         },
5222         { }
5223 };
5224
5225 /* l4_per -> mmc1 */
5226 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5227         .master         = &omap44xx_l4_per_hwmod,
5228         .slave          = &omap44xx_mmc1_hwmod,
5229         .clk            = "l4_div_ck",
5230         .addr           = omap44xx_mmc1_addrs,
5231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5232 };
5233
5234 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5235         {
5236                 .pa_start       = 0x480b4000,
5237                 .pa_end         = 0x480b43ff,
5238                 .flags          = ADDR_TYPE_RT
5239         },
5240         { }
5241 };
5242
5243 /* l4_per -> mmc2 */
5244 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5245         .master         = &omap44xx_l4_per_hwmod,
5246         .slave          = &omap44xx_mmc2_hwmod,
5247         .clk            = "l4_div_ck",
5248         .addr           = omap44xx_mmc2_addrs,
5249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5250 };
5251
5252 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5253         {
5254                 .pa_start       = 0x480ad000,
5255                 .pa_end         = 0x480ad3ff,
5256                 .flags          = ADDR_TYPE_RT
5257         },
5258         { }
5259 };
5260
5261 /* l4_per -> mmc3 */
5262 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5263         .master         = &omap44xx_l4_per_hwmod,
5264         .slave          = &omap44xx_mmc3_hwmod,
5265         .clk            = "l4_div_ck",
5266         .addr           = omap44xx_mmc3_addrs,
5267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5268 };
5269
5270 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5271         {
5272                 .pa_start       = 0x480d1000,
5273                 .pa_end         = 0x480d13ff,
5274                 .flags          = ADDR_TYPE_RT
5275         },
5276         { }
5277 };
5278
5279 /* l4_per -> mmc4 */
5280 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5281         .master         = &omap44xx_l4_per_hwmod,
5282         .slave          = &omap44xx_mmc4_hwmod,
5283         .clk            = "l4_div_ck",
5284         .addr           = omap44xx_mmc4_addrs,
5285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5286 };
5287
5288 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5289         {
5290                 .pa_start       = 0x480d5000,
5291                 .pa_end         = 0x480d53ff,
5292                 .flags          = ADDR_TYPE_RT
5293         },
5294         { }
5295 };
5296
5297 /* l4_per -> mmc5 */
5298 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5299         .master         = &omap44xx_l4_per_hwmod,
5300         .slave          = &omap44xx_mmc5_hwmod,
5301         .clk            = "l4_div_ck",
5302         .addr           = omap44xx_mmc5_addrs,
5303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5304 };
5305
5306 /* l3_main_2 -> ocmc_ram */
5307 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5308         .master         = &omap44xx_l3_main_2_hwmod,
5309         .slave          = &omap44xx_ocmc_ram_hwmod,
5310         .clk            = "l3_div_ck",
5311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5312 };
5313
5314 /* l4_cfg -> ocp2scp_usb_phy */
5315 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5316         .master         = &omap44xx_l4_cfg_hwmod,
5317         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5318         .clk            = "l4_div_ck",
5319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5320 };
5321
5322 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5323         {
5324                 .pa_start       = 0x48243000,
5325                 .pa_end         = 0x48243fff,
5326                 .flags          = ADDR_TYPE_RT
5327         },
5328         { }
5329 };
5330
5331 /* mpu_private -> prcm_mpu */
5332 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5333         .master         = &omap44xx_mpu_private_hwmod,
5334         .slave          = &omap44xx_prcm_mpu_hwmod,
5335         .clk            = "l3_div_ck",
5336         .addr           = omap44xx_prcm_mpu_addrs,
5337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5338 };
5339
5340 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5341         {
5342                 .pa_start       = 0x4a004000,
5343                 .pa_end         = 0x4a004fff,
5344                 .flags          = ADDR_TYPE_RT
5345         },
5346         { }
5347 };
5348
5349 /* l4_wkup -> cm_core_aon */
5350 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5351         .master         = &omap44xx_l4_wkup_hwmod,
5352         .slave          = &omap44xx_cm_core_aon_hwmod,
5353         .clk            = "l4_wkup_clk_mux_ck",
5354         .addr           = omap44xx_cm_core_aon_addrs,
5355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5356 };
5357
5358 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5359         {
5360                 .pa_start       = 0x4a008000,
5361                 .pa_end         = 0x4a009fff,
5362                 .flags          = ADDR_TYPE_RT
5363         },
5364         { }
5365 };
5366
5367 /* l4_cfg -> cm_core */
5368 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5369         .master         = &omap44xx_l4_cfg_hwmod,
5370         .slave          = &omap44xx_cm_core_hwmod,
5371         .clk            = "l4_div_ck",
5372         .addr           = omap44xx_cm_core_addrs,
5373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5374 };
5375
5376 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5377         {
5378                 .pa_start       = 0x4a306000,
5379                 .pa_end         = 0x4a307fff,
5380                 .flags          = ADDR_TYPE_RT
5381         },
5382         { }
5383 };
5384
5385 /* l4_wkup -> prm */
5386 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5387         .master         = &omap44xx_l4_wkup_hwmod,
5388         .slave          = &omap44xx_prm_hwmod,
5389         .clk            = "l4_wkup_clk_mux_ck",
5390         .addr           = omap44xx_prm_addrs,
5391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5392 };
5393
5394 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5395         {
5396                 .pa_start       = 0x4a30a000,
5397                 .pa_end         = 0x4a30a7ff,
5398                 .flags          = ADDR_TYPE_RT
5399         },
5400         { }
5401 };
5402
5403 /* l4_wkup -> scrm */
5404 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5405         .master         = &omap44xx_l4_wkup_hwmod,
5406         .slave          = &omap44xx_scrm_hwmod,
5407         .clk            = "l4_wkup_clk_mux_ck",
5408         .addr           = omap44xx_scrm_addrs,
5409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5410 };
5411
5412 /* l3_main_2 -> sl2if */
5413 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5414         .master         = &omap44xx_l3_main_2_hwmod,
5415         .slave          = &omap44xx_sl2if_hwmod,
5416         .clk            = "l3_div_ck",
5417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5418 };
5419
5420 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5421         {
5422                 .pa_start       = 0x4012c000,
5423                 .pa_end         = 0x4012c3ff,
5424                 .flags          = ADDR_TYPE_RT
5425         },
5426         { }
5427 };
5428
5429 /* l4_abe -> slimbus1 */
5430 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5431         .master         = &omap44xx_l4_abe_hwmod,
5432         .slave          = &omap44xx_slimbus1_hwmod,
5433         .clk            = "ocp_abe_iclk",
5434         .addr           = omap44xx_slimbus1_addrs,
5435         .user           = OCP_USER_MPU,
5436 };
5437
5438 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5439         {
5440                 .pa_start       = 0x4902c000,
5441                 .pa_end         = 0x4902c3ff,
5442                 .flags          = ADDR_TYPE_RT
5443         },
5444         { }
5445 };
5446
5447 /* l4_abe -> slimbus1 (dma) */
5448 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5449         .master         = &omap44xx_l4_abe_hwmod,
5450         .slave          = &omap44xx_slimbus1_hwmod,
5451         .clk            = "ocp_abe_iclk",
5452         .addr           = omap44xx_slimbus1_dma_addrs,
5453         .user           = OCP_USER_SDMA,
5454 };
5455
5456 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5457         {
5458                 .pa_start       = 0x48076000,
5459                 .pa_end         = 0x480763ff,
5460                 .flags          = ADDR_TYPE_RT
5461         },
5462         { }
5463 };
5464
5465 /* l4_per -> slimbus2 */
5466 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5467         .master         = &omap44xx_l4_per_hwmod,
5468         .slave          = &omap44xx_slimbus2_hwmod,
5469         .clk            = "l4_div_ck",
5470         .addr           = omap44xx_slimbus2_addrs,
5471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5472 };
5473
5474 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5475         {
5476                 .pa_start       = 0x4a0dd000,
5477                 .pa_end         = 0x4a0dd03f,
5478                 .flags          = ADDR_TYPE_RT
5479         },
5480         { }
5481 };
5482
5483 /* l4_cfg -> smartreflex_core */
5484 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5485         .master         = &omap44xx_l4_cfg_hwmod,
5486         .slave          = &omap44xx_smartreflex_core_hwmod,
5487         .clk            = "l4_div_ck",
5488         .addr           = omap44xx_smartreflex_core_addrs,
5489         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5490 };
5491
5492 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5493         {
5494                 .pa_start       = 0x4a0db000,
5495                 .pa_end         = 0x4a0db03f,
5496                 .flags          = ADDR_TYPE_RT
5497         },
5498         { }
5499 };
5500
5501 /* l4_cfg -> smartreflex_iva */
5502 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5503         .master         = &omap44xx_l4_cfg_hwmod,
5504         .slave          = &omap44xx_smartreflex_iva_hwmod,
5505         .clk            = "l4_div_ck",
5506         .addr           = omap44xx_smartreflex_iva_addrs,
5507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5508 };
5509
5510 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5511         {
5512                 .pa_start       = 0x4a0d9000,
5513                 .pa_end         = 0x4a0d903f,
5514                 .flags          = ADDR_TYPE_RT
5515         },
5516         { }
5517 };
5518
5519 /* l4_cfg -> smartreflex_mpu */
5520 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5521         .master         = &omap44xx_l4_cfg_hwmod,
5522         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5523         .clk            = "l4_div_ck",
5524         .addr           = omap44xx_smartreflex_mpu_addrs,
5525         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5526 };
5527
5528 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5529         {
5530                 .pa_start       = 0x4a0f6000,
5531                 .pa_end         = 0x4a0f6fff,
5532                 .flags          = ADDR_TYPE_RT
5533         },
5534         { }
5535 };
5536
5537 /* l4_cfg -> spinlock */
5538 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5539         .master         = &omap44xx_l4_cfg_hwmod,
5540         .slave          = &omap44xx_spinlock_hwmod,
5541         .clk            = "l4_div_ck",
5542         .addr           = omap44xx_spinlock_addrs,
5543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5544 };
5545
5546 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5547         {
5548                 .pa_start       = 0x4a318000,
5549                 .pa_end         = 0x4a31807f,
5550                 .flags          = ADDR_TYPE_RT
5551         },
5552         { }
5553 };
5554
5555 /* l4_wkup -> timer1 */
5556 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5557         .master         = &omap44xx_l4_wkup_hwmod,
5558         .slave          = &omap44xx_timer1_hwmod,
5559         .clk            = "l4_wkup_clk_mux_ck",
5560         .addr           = omap44xx_timer1_addrs,
5561         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5562 };
5563
5564 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5565         {
5566                 .pa_start       = 0x48032000,
5567                 .pa_end         = 0x4803207f,
5568                 .flags          = ADDR_TYPE_RT
5569         },
5570         { }
5571 };
5572
5573 /* l4_per -> timer2 */
5574 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5575         .master         = &omap44xx_l4_per_hwmod,
5576         .slave          = &omap44xx_timer2_hwmod,
5577         .clk            = "l4_div_ck",
5578         .addr           = omap44xx_timer2_addrs,
5579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5580 };
5581
5582 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5583         {
5584                 .pa_start       = 0x48034000,
5585                 .pa_end         = 0x4803407f,
5586                 .flags          = ADDR_TYPE_RT
5587         },
5588         { }
5589 };
5590
5591 /* l4_per -> timer3 */
5592 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5593         .master         = &omap44xx_l4_per_hwmod,
5594         .slave          = &omap44xx_timer3_hwmod,
5595         .clk            = "l4_div_ck",
5596         .addr           = omap44xx_timer3_addrs,
5597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5598 };
5599
5600 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5601         {
5602                 .pa_start       = 0x48036000,
5603                 .pa_end         = 0x4803607f,
5604                 .flags          = ADDR_TYPE_RT
5605         },
5606         { }
5607 };
5608
5609 /* l4_per -> timer4 */
5610 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5611         .master         = &omap44xx_l4_per_hwmod,
5612         .slave          = &omap44xx_timer4_hwmod,
5613         .clk            = "l4_div_ck",
5614         .addr           = omap44xx_timer4_addrs,
5615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5616 };
5617
5618 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5619         {
5620                 .pa_start       = 0x40138000,
5621                 .pa_end         = 0x4013807f,
5622                 .flags          = ADDR_TYPE_RT
5623         },
5624         { }
5625 };
5626
5627 /* l4_abe -> timer5 */
5628 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5629         .master         = &omap44xx_l4_abe_hwmod,
5630         .slave          = &omap44xx_timer5_hwmod,
5631         .clk            = "ocp_abe_iclk",
5632         .addr           = omap44xx_timer5_addrs,
5633         .user           = OCP_USER_MPU,
5634 };
5635
5636 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5637         {
5638                 .pa_start       = 0x49038000,
5639                 .pa_end         = 0x4903807f,
5640                 .flags          = ADDR_TYPE_RT
5641         },
5642         { }
5643 };
5644
5645 /* l4_abe -> timer5 (dma) */
5646 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5647         .master         = &omap44xx_l4_abe_hwmod,
5648         .slave          = &omap44xx_timer5_hwmod,
5649         .clk            = "ocp_abe_iclk",
5650         .addr           = omap44xx_timer5_dma_addrs,
5651         .user           = OCP_USER_SDMA,
5652 };
5653
5654 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5655         {
5656                 .pa_start       = 0x4013a000,
5657                 .pa_end         = 0x4013a07f,
5658                 .flags          = ADDR_TYPE_RT
5659         },
5660         { }
5661 };
5662
5663 /* l4_abe -> timer6 */
5664 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5665         .master         = &omap44xx_l4_abe_hwmod,
5666         .slave          = &omap44xx_timer6_hwmod,
5667         .clk            = "ocp_abe_iclk",
5668         .addr           = omap44xx_timer6_addrs,
5669         .user           = OCP_USER_MPU,
5670 };
5671
5672 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5673         {
5674                 .pa_start       = 0x4903a000,
5675                 .pa_end         = 0x4903a07f,
5676                 .flags          = ADDR_TYPE_RT
5677         },
5678         { }
5679 };
5680
5681 /* l4_abe -> timer6 (dma) */
5682 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5683         .master         = &omap44xx_l4_abe_hwmod,
5684         .slave          = &omap44xx_timer6_hwmod,
5685         .clk            = "ocp_abe_iclk",
5686         .addr           = omap44xx_timer6_dma_addrs,
5687         .user           = OCP_USER_SDMA,
5688 };
5689
5690 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5691         {
5692                 .pa_start       = 0x4013c000,
5693                 .pa_end         = 0x4013c07f,
5694                 .flags          = ADDR_TYPE_RT
5695         },
5696         { }
5697 };
5698
5699 /* l4_abe -> timer7 */
5700 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5701         .master         = &omap44xx_l4_abe_hwmod,
5702         .slave          = &omap44xx_timer7_hwmod,
5703         .clk            = "ocp_abe_iclk",
5704         .addr           = omap44xx_timer7_addrs,
5705         .user           = OCP_USER_MPU,
5706 };
5707
5708 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5709         {
5710                 .pa_start       = 0x4903c000,
5711                 .pa_end         = 0x4903c07f,
5712                 .flags          = ADDR_TYPE_RT
5713         },
5714         { }
5715 };
5716
5717 /* l4_abe -> timer7 (dma) */
5718 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5719         .master         = &omap44xx_l4_abe_hwmod,
5720         .slave          = &omap44xx_timer7_hwmod,
5721         .clk            = "ocp_abe_iclk",
5722         .addr           = omap44xx_timer7_dma_addrs,
5723         .user           = OCP_USER_SDMA,
5724 };
5725
5726 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5727         {
5728                 .pa_start       = 0x4013e000,
5729                 .pa_end         = 0x4013e07f,
5730                 .flags          = ADDR_TYPE_RT
5731         },
5732         { }
5733 };
5734
5735 /* l4_abe -> timer8 */
5736 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5737         .master         = &omap44xx_l4_abe_hwmod,
5738         .slave          = &omap44xx_timer8_hwmod,
5739         .clk            = "ocp_abe_iclk",
5740         .addr           = omap44xx_timer8_addrs,
5741         .user           = OCP_USER_MPU,
5742 };
5743
5744 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5745         {
5746                 .pa_start       = 0x4903e000,
5747                 .pa_end         = 0x4903e07f,
5748                 .flags          = ADDR_TYPE_RT
5749         },
5750         { }
5751 };
5752
5753 /* l4_abe -> timer8 (dma) */
5754 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5755         .master         = &omap44xx_l4_abe_hwmod,
5756         .slave          = &omap44xx_timer8_hwmod,
5757         .clk            = "ocp_abe_iclk",
5758         .addr           = omap44xx_timer8_dma_addrs,
5759         .user           = OCP_USER_SDMA,
5760 };
5761
5762 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5763         {
5764                 .pa_start       = 0x4803e000,
5765                 .pa_end         = 0x4803e07f,
5766                 .flags          = ADDR_TYPE_RT
5767         },
5768         { }
5769 };
5770
5771 /* l4_per -> timer9 */
5772 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5773         .master         = &omap44xx_l4_per_hwmod,
5774         .slave          = &omap44xx_timer9_hwmod,
5775         .clk            = "l4_div_ck",
5776         .addr           = omap44xx_timer9_addrs,
5777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5778 };
5779
5780 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5781         {
5782                 .pa_start       = 0x48086000,
5783                 .pa_end         = 0x4808607f,
5784                 .flags          = ADDR_TYPE_RT
5785         },
5786         { }
5787 };
5788
5789 /* l4_per -> timer10 */
5790 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5791         .master         = &omap44xx_l4_per_hwmod,
5792         .slave          = &omap44xx_timer10_hwmod,
5793         .clk            = "l4_div_ck",
5794         .addr           = omap44xx_timer10_addrs,
5795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5796 };
5797
5798 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5799         {
5800                 .pa_start       = 0x48088000,
5801                 .pa_end         = 0x4808807f,
5802                 .flags          = ADDR_TYPE_RT
5803         },
5804         { }
5805 };
5806
5807 /* l4_per -> timer11 */
5808 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5809         .master         = &omap44xx_l4_per_hwmod,
5810         .slave          = &omap44xx_timer11_hwmod,
5811         .clk            = "l4_div_ck",
5812         .addr           = omap44xx_timer11_addrs,
5813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5814 };
5815
5816 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5817         {
5818                 .pa_start       = 0x4806a000,
5819                 .pa_end         = 0x4806a0ff,
5820                 .flags          = ADDR_TYPE_RT
5821         },
5822         { }
5823 };
5824
5825 /* l4_per -> uart1 */
5826 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5827         .master         = &omap44xx_l4_per_hwmod,
5828         .slave          = &omap44xx_uart1_hwmod,
5829         .clk            = "l4_div_ck",
5830         .addr           = omap44xx_uart1_addrs,
5831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5832 };
5833
5834 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5835         {
5836                 .pa_start       = 0x4806c000,
5837                 .pa_end         = 0x4806c0ff,
5838                 .flags          = ADDR_TYPE_RT
5839         },
5840         { }
5841 };
5842
5843 /* l4_per -> uart2 */
5844 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5845         .master         = &omap44xx_l4_per_hwmod,
5846         .slave          = &omap44xx_uart2_hwmod,
5847         .clk            = "l4_div_ck",
5848         .addr           = omap44xx_uart2_addrs,
5849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5850 };
5851
5852 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5853         {
5854                 .pa_start       = 0x48020000,
5855                 .pa_end         = 0x480200ff,
5856                 .flags          = ADDR_TYPE_RT
5857         },
5858         { }
5859 };
5860
5861 /* l4_per -> uart3 */
5862 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5863         .master         = &omap44xx_l4_per_hwmod,
5864         .slave          = &omap44xx_uart3_hwmod,
5865         .clk            = "l4_div_ck",
5866         .addr           = omap44xx_uart3_addrs,
5867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5868 };
5869
5870 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5871         {
5872                 .pa_start       = 0x4806e000,
5873                 .pa_end         = 0x4806e0ff,
5874                 .flags          = ADDR_TYPE_RT
5875         },
5876         { }
5877 };
5878
5879 /* l4_per -> uart4 */
5880 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5881         .master         = &omap44xx_l4_per_hwmod,
5882         .slave          = &omap44xx_uart4_hwmod,
5883         .clk            = "l4_div_ck",
5884         .addr           = omap44xx_uart4_addrs,
5885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5886 };
5887
5888 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5889         {
5890                 .pa_start       = 0x4a0a9000,
5891                 .pa_end         = 0x4a0a93ff,
5892                 .flags          = ADDR_TYPE_RT
5893         },
5894         { }
5895 };
5896
5897 /* l4_cfg -> usb_host_fs */
5898 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5899         .master         = &omap44xx_l4_cfg_hwmod,
5900         .slave          = &omap44xx_usb_host_fs_hwmod,
5901         .clk            = "l4_div_ck",
5902         .addr           = omap44xx_usb_host_fs_addrs,
5903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5904 };
5905
5906 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5907         {
5908                 .name           = "uhh",
5909                 .pa_start       = 0x4a064000,
5910                 .pa_end         = 0x4a0647ff,
5911                 .flags          = ADDR_TYPE_RT
5912         },
5913         {
5914                 .name           = "ohci",
5915                 .pa_start       = 0x4a064800,
5916                 .pa_end         = 0x4a064bff,
5917         },
5918         {
5919                 .name           = "ehci",
5920                 .pa_start       = 0x4a064c00,
5921                 .pa_end         = 0x4a064fff,
5922         },
5923         {}
5924 };
5925
5926 /* l4_cfg -> usb_host_hs */
5927 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5928         .master         = &omap44xx_l4_cfg_hwmod,
5929         .slave          = &omap44xx_usb_host_hs_hwmod,
5930         .clk            = "l4_div_ck",
5931         .addr           = omap44xx_usb_host_hs_addrs,
5932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5933 };
5934
5935 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5936         {
5937                 .pa_start       = 0x4a0ab000,
5938                 .pa_end         = 0x4a0ab003,
5939                 .flags          = ADDR_TYPE_RT
5940         },
5941         { }
5942 };
5943
5944 /* l4_cfg -> usb_otg_hs */
5945 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5946         .master         = &omap44xx_l4_cfg_hwmod,
5947         .slave          = &omap44xx_usb_otg_hs_hwmod,
5948         .clk            = "l4_div_ck",
5949         .addr           = omap44xx_usb_otg_hs_addrs,
5950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5951 };
5952
5953 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5954         {
5955                 .name           = "tll",
5956                 .pa_start       = 0x4a062000,
5957                 .pa_end         = 0x4a063fff,
5958                 .flags          = ADDR_TYPE_RT
5959         },
5960         {}
5961 };
5962
5963 /* l4_cfg -> usb_tll_hs */
5964 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5965         .master         = &omap44xx_l4_cfg_hwmod,
5966         .slave          = &omap44xx_usb_tll_hs_hwmod,
5967         .clk            = "l4_div_ck",
5968         .addr           = omap44xx_usb_tll_hs_addrs,
5969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5970 };
5971
5972 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5973         {
5974                 .pa_start       = 0x4a314000,
5975                 .pa_end         = 0x4a31407f,
5976                 .flags          = ADDR_TYPE_RT
5977         },
5978         { }
5979 };
5980
5981 /* l4_wkup -> wd_timer2 */
5982 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5983         .master         = &omap44xx_l4_wkup_hwmod,
5984         .slave          = &omap44xx_wd_timer2_hwmod,
5985         .clk            = "l4_wkup_clk_mux_ck",
5986         .addr           = omap44xx_wd_timer2_addrs,
5987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5988 };
5989
5990 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5991         {
5992                 .pa_start       = 0x40130000,
5993                 .pa_end         = 0x4013007f,
5994                 .flags          = ADDR_TYPE_RT
5995         },
5996         { }
5997 };
5998
5999 /* l4_abe -> wd_timer3 */
6000 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6001         .master         = &omap44xx_l4_abe_hwmod,
6002         .slave          = &omap44xx_wd_timer3_hwmod,
6003         .clk            = "ocp_abe_iclk",
6004         .addr           = omap44xx_wd_timer3_addrs,
6005         .user           = OCP_USER_MPU,
6006 };
6007
6008 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6009         {
6010                 .pa_start       = 0x49030000,
6011                 .pa_end         = 0x4903007f,
6012                 .flags          = ADDR_TYPE_RT
6013         },
6014         { }
6015 };
6016
6017 /* l4_abe -> wd_timer3 (dma) */
6018 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6019         .master         = &omap44xx_l4_abe_hwmod,
6020         .slave          = &omap44xx_wd_timer3_hwmod,
6021         .clk            = "ocp_abe_iclk",
6022         .addr           = omap44xx_wd_timer3_dma_addrs,
6023         .user           = OCP_USER_SDMA,
6024 };
6025
6026 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6027         &omap44xx_c2c__c2c_target_fw,
6028         &omap44xx_l4_cfg__c2c_target_fw,
6029         &omap44xx_l3_main_1__dmm,
6030         &omap44xx_mpu__dmm,
6031         &omap44xx_c2c__emif_fw,
6032         &omap44xx_dmm__emif_fw,
6033         &omap44xx_l4_cfg__emif_fw,
6034         &omap44xx_iva__l3_instr,
6035         &omap44xx_l3_main_3__l3_instr,
6036         &omap44xx_ocp_wp_noc__l3_instr,
6037         &omap44xx_dsp__l3_main_1,
6038         &omap44xx_dss__l3_main_1,
6039         &omap44xx_l3_main_2__l3_main_1,
6040         &omap44xx_l4_cfg__l3_main_1,
6041         &omap44xx_mmc1__l3_main_1,
6042         &omap44xx_mmc2__l3_main_1,
6043         &omap44xx_mpu__l3_main_1,
6044         &omap44xx_c2c_target_fw__l3_main_2,
6045         &omap44xx_debugss__l3_main_2,
6046         &omap44xx_dma_system__l3_main_2,
6047         &omap44xx_fdif__l3_main_2,
6048         &omap44xx_gpu__l3_main_2,
6049         &omap44xx_hsi__l3_main_2,
6050         &omap44xx_ipu__l3_main_2,
6051         &omap44xx_iss__l3_main_2,
6052         &omap44xx_iva__l3_main_2,
6053         &omap44xx_l3_main_1__l3_main_2,
6054         &omap44xx_l4_cfg__l3_main_2,
6055         /* &omap44xx_usb_host_fs__l3_main_2, */
6056         &omap44xx_usb_host_hs__l3_main_2,
6057         &omap44xx_usb_otg_hs__l3_main_2,
6058         &omap44xx_l3_main_1__l3_main_3,
6059         &omap44xx_l3_main_2__l3_main_3,
6060         &omap44xx_l4_cfg__l3_main_3,
6061         /* &omap44xx_aess__l4_abe, */
6062         &omap44xx_dsp__l4_abe,
6063         &omap44xx_l3_main_1__l4_abe,
6064         &omap44xx_mpu__l4_abe,
6065         &omap44xx_l3_main_1__l4_cfg,
6066         &omap44xx_l3_main_2__l4_per,
6067         &omap44xx_l4_cfg__l4_wkup,
6068         &omap44xx_mpu__mpu_private,
6069         &omap44xx_l4_cfg__ocp_wp_noc,
6070         /* &omap44xx_l4_abe__aess, */
6071         /* &omap44xx_l4_abe__aess_dma, */
6072         &omap44xx_l3_main_2__c2c,
6073         &omap44xx_l4_wkup__counter_32k,
6074         &omap44xx_l4_cfg__ctrl_module_core,
6075         &omap44xx_l4_cfg__ctrl_module_pad_core,
6076         &omap44xx_l4_wkup__ctrl_module_wkup,
6077         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6078         &omap44xx_l3_instr__debugss,
6079         &omap44xx_l4_cfg__dma_system,
6080         &omap44xx_l4_abe__dmic,
6081         &omap44xx_l4_abe__dmic_dma,
6082         &omap44xx_dsp__iva,
6083         /* &omap44xx_dsp__sl2if, */
6084         &omap44xx_l4_cfg__dsp,
6085         &omap44xx_l3_main_2__dss,
6086         &omap44xx_l4_per__dss,
6087         &omap44xx_l3_main_2__dss_dispc,
6088         &omap44xx_l4_per__dss_dispc,
6089         &omap44xx_l3_main_2__dss_dsi1,
6090         &omap44xx_l4_per__dss_dsi1,
6091         &omap44xx_l3_main_2__dss_dsi2,
6092         &omap44xx_l4_per__dss_dsi2,
6093         &omap44xx_l3_main_2__dss_hdmi,
6094         &omap44xx_l4_per__dss_hdmi,
6095         &omap44xx_l3_main_2__dss_rfbi,
6096         &omap44xx_l4_per__dss_rfbi,
6097         &omap44xx_l3_main_2__dss_venc,
6098         &omap44xx_l4_per__dss_venc,
6099         &omap44xx_l4_per__elm,
6100         &omap44xx_emif_fw__emif1,
6101         &omap44xx_emif_fw__emif2,
6102         &omap44xx_l4_cfg__fdif,
6103         &omap44xx_l4_wkup__gpio1,
6104         &omap44xx_l4_per__gpio2,
6105         &omap44xx_l4_per__gpio3,
6106         &omap44xx_l4_per__gpio4,
6107         &omap44xx_l4_per__gpio5,
6108         &omap44xx_l4_per__gpio6,
6109         &omap44xx_l3_main_2__gpmc,
6110         &omap44xx_l3_main_2__gpu,
6111         &omap44xx_l4_per__hdq1w,
6112         &omap44xx_l4_cfg__hsi,
6113         &omap44xx_l4_per__i2c1,
6114         &omap44xx_l4_per__i2c2,
6115         &omap44xx_l4_per__i2c3,
6116         &omap44xx_l4_per__i2c4,
6117         &omap44xx_l3_main_2__ipu,
6118         &omap44xx_l3_main_2__iss,
6119         /* &omap44xx_iva__sl2if, */
6120         &omap44xx_l3_main_2__iva,
6121         &omap44xx_l4_wkup__kbd,
6122         &omap44xx_l4_cfg__mailbox,
6123         &omap44xx_l4_abe__mcasp,
6124         &omap44xx_l4_abe__mcasp_dma,
6125         &omap44xx_l4_abe__mcbsp1,
6126         &omap44xx_l4_abe__mcbsp1_dma,
6127         &omap44xx_l4_abe__mcbsp2,
6128         &omap44xx_l4_abe__mcbsp2_dma,
6129         &omap44xx_l4_abe__mcbsp3,
6130         &omap44xx_l4_abe__mcbsp3_dma,
6131         &omap44xx_l4_per__mcbsp4,
6132         &omap44xx_l4_abe__mcpdm,
6133         &omap44xx_l4_abe__mcpdm_dma,
6134         &omap44xx_l4_per__mcspi1,
6135         &omap44xx_l4_per__mcspi2,
6136         &omap44xx_l4_per__mcspi3,
6137         &omap44xx_l4_per__mcspi4,
6138         &omap44xx_l4_per__mmc1,
6139         &omap44xx_l4_per__mmc2,
6140         &omap44xx_l4_per__mmc3,
6141         &omap44xx_l4_per__mmc4,
6142         &omap44xx_l4_per__mmc5,
6143         &omap44xx_l3_main_2__ocmc_ram,
6144         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6145         &omap44xx_mpu_private__prcm_mpu,
6146         &omap44xx_l4_wkup__cm_core_aon,
6147         &omap44xx_l4_cfg__cm_core,
6148         &omap44xx_l4_wkup__prm,
6149         &omap44xx_l4_wkup__scrm,
6150         /* &omap44xx_l3_main_2__sl2if, */
6151         &omap44xx_l4_abe__slimbus1,
6152         &omap44xx_l4_abe__slimbus1_dma,
6153         &omap44xx_l4_per__slimbus2,
6154         &omap44xx_l4_cfg__smartreflex_core,
6155         &omap44xx_l4_cfg__smartreflex_iva,
6156         &omap44xx_l4_cfg__smartreflex_mpu,
6157         &omap44xx_l4_cfg__spinlock,
6158         &omap44xx_l4_wkup__timer1,
6159         &omap44xx_l4_per__timer2,
6160         &omap44xx_l4_per__timer3,
6161         &omap44xx_l4_per__timer4,
6162         &omap44xx_l4_abe__timer5,
6163         &omap44xx_l4_abe__timer5_dma,
6164         &omap44xx_l4_abe__timer6,
6165         &omap44xx_l4_abe__timer6_dma,
6166         &omap44xx_l4_abe__timer7,
6167         &omap44xx_l4_abe__timer7_dma,
6168         &omap44xx_l4_abe__timer8,
6169         &omap44xx_l4_abe__timer8_dma,
6170         &omap44xx_l4_per__timer9,
6171         &omap44xx_l4_per__timer10,
6172         &omap44xx_l4_per__timer11,
6173         &omap44xx_l4_per__uart1,
6174         &omap44xx_l4_per__uart2,
6175         &omap44xx_l4_per__uart3,
6176         &omap44xx_l4_per__uart4,
6177         /* &omap44xx_l4_cfg__usb_host_fs, */
6178         &omap44xx_l4_cfg__usb_host_hs,
6179         &omap44xx_l4_cfg__usb_otg_hs,
6180         &omap44xx_l4_cfg__usb_tll_hs,
6181         &omap44xx_l4_wkup__wd_timer2,
6182         &omap44xx_l4_abe__wd_timer3,
6183         &omap44xx_l4_abe__wd_timer3_dma,
6184         NULL,
6185 };
6186
6187 int __init omap44xx_hwmod_init(void)
6188 {
6189         omap_hwmod_init();
6190         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6191 }
6192