2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
15 * XXX these should be marked initdata for multi-OMAP kernels
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/omap-dma.h>
25 #include <linux/platform_data/asoc-ti-mcbsp.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/iommu-omap.h>
28 #include <plat/dmtimer.h>
33 #include "omap_hwmod.h"
34 #include "omap_hwmod_common_data.h"
35 #include "prm-regbits-34xx.h"
36 #include "cm-regbits-34xx.h"
45 * OMAP3xxx hardware module integration data
47 * All of the data in this section should be autogeneratable from the
48 * TI hardware database or other technical documentation. Data that
49 * is driver-specific or driver-kernel integration-specific belongs
58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
59 { .irq = 9 + OMAP_INTC_START, },
60 { .irq = 10 + OMAP_INTC_START, },
64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
66 .class = &l3_hwmod_class,
67 .mpu_irqs = omap3xxx_l3_main_irqs,
68 .flags = HWMOD_NO_IDLEST,
72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
74 .class = &l4_hwmod_class,
75 .flags = HWMOD_NO_IDLEST,
79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
81 .class = &l4_hwmod_class,
82 .flags = HWMOD_NO_IDLEST,
86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
88 .class = &l4_hwmod_class,
89 .flags = HWMOD_NO_IDLEST,
93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
95 .class = &l4_hwmod_class,
96 .flags = HWMOD_NO_IDLEST,
100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
101 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
107 .mpu_irqs = omap3xxx_mpu_irqs,
108 .class = &mpu_hwmod_class,
109 .main_clk = "arm_fck",
113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
114 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
119 static struct omap_hwmod omap3xxx_iva_hwmod = {
121 .class = &iva_hwmod_class,
122 .clkdm_name = "iva2_clkdm",
123 .rst_lines = omap3xxx_iva_resets,
124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
125 .main_clk = "iva2_ck",
128 .module_offs = OMAP3430_IVA2_MOD,
130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
139 * debug and emulation sub system
142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
149 .class = &omap3xxx_debugss_hwmod_class,
150 .clkdm_name = "emu_clkdm",
151 .main_clk = "emu_src_ck",
152 .flags = HWMOD_NO_IDLEST,
156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
166 .sysc_fields = &omap_hwmod_sysc_type1,
169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
171 .sysc = &omap3xxx_timer_sysc,
174 /* secure timers dev attribute */
175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
179 /* always-on timers dev attribute */
180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
181 .timer_capability = OMAP_TIMER_ALWON,
184 /* pwm timers dev attribute */
185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
186 .timer_capability = OMAP_TIMER_HAS_PWM,
189 /* timers with DSP interrupt dev attribute */
190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
194 /* pwm timers with DSP interrupt dev attribute */
195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
202 .mpu_irqs = omap2_timer1_mpu_irqs,
203 .main_clk = "gpt1_fck",
207 .module_bit = OMAP3430_EN_GPT1_SHIFT,
208 .module_offs = WKUP_MOD,
210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
213 .dev_attr = &capability_alwon_dev_attr,
214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
221 .mpu_irqs = omap2_timer2_mpu_irqs,
222 .main_clk = "gpt2_fck",
226 .module_bit = OMAP3430_EN_GPT2_SHIFT,
227 .module_offs = OMAP3430_PER_MOD,
229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
239 .mpu_irqs = omap2_timer3_mpu_irqs,
240 .main_clk = "gpt3_fck",
244 .module_bit = OMAP3430_EN_GPT3_SHIFT,
245 .module_offs = OMAP3430_PER_MOD,
247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
257 .mpu_irqs = omap2_timer4_mpu_irqs,
258 .main_clk = "gpt4_fck",
262 .module_bit = OMAP3430_EN_GPT4_SHIFT,
263 .module_offs = OMAP3430_PER_MOD,
265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
275 .mpu_irqs = omap2_timer5_mpu_irqs,
276 .main_clk = "gpt5_fck",
280 .module_bit = OMAP3430_EN_GPT5_SHIFT,
281 .module_offs = OMAP3430_PER_MOD,
283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
286 .dev_attr = &capability_dsp_dev_attr,
287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
294 .mpu_irqs = omap2_timer6_mpu_irqs,
295 .main_clk = "gpt6_fck",
299 .module_bit = OMAP3430_EN_GPT6_SHIFT,
300 .module_offs = OMAP3430_PER_MOD,
302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
305 .dev_attr = &capability_dsp_dev_attr,
306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
313 .mpu_irqs = omap2_timer7_mpu_irqs,
314 .main_clk = "gpt7_fck",
318 .module_bit = OMAP3430_EN_GPT7_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
324 .dev_attr = &capability_dsp_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
332 .mpu_irqs = omap2_timer8_mpu_irqs,
333 .main_clk = "gpt8_fck",
337 .module_bit = OMAP3430_EN_GPT8_SHIFT,
338 .module_offs = OMAP3430_PER_MOD,
340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
343 .dev_attr = &capability_dsp_pwm_dev_attr,
344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
351 .mpu_irqs = omap2_timer9_mpu_irqs,
352 .main_clk = "gpt9_fck",
356 .module_bit = OMAP3430_EN_GPT9_SHIFT,
357 .module_offs = OMAP3430_PER_MOD,
359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
362 .dev_attr = &capability_pwm_dev_attr,
363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
370 .mpu_irqs = omap2_timer10_mpu_irqs,
371 .main_clk = "gpt10_fck",
375 .module_bit = OMAP3430_EN_GPT10_SHIFT,
376 .module_offs = CORE_MOD,
378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
381 .dev_attr = &capability_pwm_dev_attr,
382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
389 .mpu_irqs = omap2_timer11_mpu_irqs,
390 .main_clk = "gpt11_fck",
394 .module_bit = OMAP3430_EN_GPT11_SHIFT,
395 .module_offs = CORE_MOD,
397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
400 .dev_attr = &capability_pwm_dev_attr,
401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
407 { .irq = 95 + OMAP_INTC_START, },
411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
413 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
414 .main_clk = "gpt12_fck",
418 .module_bit = OMAP3430_EN_GPT12_SHIFT,
419 .module_offs = WKUP_MOD,
421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
424 .dev_attr = &capability_secure_dev_attr,
425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444 .sysc_fields = &omap_hwmod_sysc_type1,
448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
456 .clockact = CLOCKACT_TEST_ICLK,
457 .sysc_fields = &omap_hwmod_sysc_type1,
460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
462 .sysc = &omap3xxx_wd_timer_sysc,
463 .pre_shutdown = &omap2_wd_timer_disable,
464 .reset = &omap2_wd_timer_reset,
467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
469 .class = &omap3xxx_wd_timer_hwmod_class,
470 .main_clk = "wdt2_fck",
474 .module_bit = OMAP3430_EN_WDT2_SHIFT,
475 .module_offs = WKUP_MOD,
477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
481 * XXX: Use software supervised mode, HW supervised smartidle seems to
482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
484 .flags = HWMOD_SWSUP_SIDLE,
488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck",
493 .flags = HWMOD_SWSUP_SIDLE_ACT,
496 .module_offs = CORE_MOD,
498 .module_bit = OMAP3430_EN_UART1_SHIFT,
500 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
503 .class = &omap2_uart_class,
507 static struct omap_hwmod omap3xxx_uart2_hwmod = {
509 .mpu_irqs = omap2_uart2_mpu_irqs,
510 .sdma_reqs = omap2_uart2_sdma_reqs,
511 .main_clk = "uart2_fck",
512 .flags = HWMOD_SWSUP_SIDLE_ACT,
515 .module_offs = CORE_MOD,
517 .module_bit = OMAP3430_EN_UART2_SHIFT,
519 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
522 .class = &omap2_uart_class,
526 static struct omap_hwmod omap3xxx_uart3_hwmod = {
528 .mpu_irqs = omap2_uart3_mpu_irqs,
529 .sdma_reqs = omap2_uart3_sdma_reqs,
530 .main_clk = "uart3_fck",
531 .flags = HWMOD_SWSUP_SIDLE_ACT,
534 .module_offs = OMAP3430_PER_MOD,
536 .module_bit = OMAP3430_EN_UART3_SHIFT,
538 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
541 .class = &omap2_uart_class,
545 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
546 { .irq = 80 + OMAP_INTC_START, },
550 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
551 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
552 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
556 static struct omap_hwmod omap36xx_uart4_hwmod = {
558 .mpu_irqs = uart4_mpu_irqs,
559 .sdma_reqs = uart4_sdma_reqs,
560 .main_clk = "uart4_fck",
561 .flags = HWMOD_SWSUP_SIDLE_ACT,
564 .module_offs = OMAP3430_PER_MOD,
566 .module_bit = OMAP3630_EN_UART4_SHIFT,
568 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
571 .class = &omap2_uart_class,
574 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
575 { .irq = 84 + OMAP_INTC_START, },
579 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
580 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
581 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
586 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
587 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
588 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
589 * should not be needed. The functional clock structure of the AM35xx
590 * UART4 is extremely unclear and opaque; it is unclear what the role
591 * of uart1/2_fck is for the UART4. Any clarification from either
592 * empirical testing or the AM3505/3517 hardware designers would be
595 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
596 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
599 static struct omap_hwmod am35xx_uart4_hwmod = {
601 .mpu_irqs = am35xx_uart4_mpu_irqs,
602 .sdma_reqs = am35xx_uart4_sdma_reqs,
603 .main_clk = "uart4_fck",
606 .module_offs = CORE_MOD,
608 .module_bit = AM35XX_EN_UART4_SHIFT,
610 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
613 .opt_clks = am35xx_uart4_opt_clks,
614 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
615 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
616 .class = &omap2_uart_class,
619 static struct omap_hwmod_class i2c_class = {
622 .rev = OMAP_I2C_IP_VERSION_1,
623 .reset = &omap_i2c_reset,
626 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
627 { .name = "dispc", .dma_req = 5 },
628 { .name = "dsi1", .dma_req = 74 },
633 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
635 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
636 * driver does not use these clocks.
638 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
639 { .role = "tv_clk", .clk = "dss_tv_fck" },
640 /* required only on OMAP3430 */
641 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
644 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
646 .class = &omap2_dss_hwmod_class,
647 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
648 .sdma_reqs = omap3xxx_dss_sdma_chs,
652 .module_bit = OMAP3430_EN_DSS1_SHIFT,
653 .module_offs = OMAP3430_DSS_MOD,
655 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
658 .opt_clks = dss_opt_clks,
659 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
660 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
663 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
665 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
666 .class = &omap2_dss_hwmod_class,
667 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
668 .sdma_reqs = omap3xxx_dss_sdma_chs,
672 .module_bit = OMAP3430_EN_DSS1_SHIFT,
673 .module_offs = OMAP3430_DSS_MOD,
675 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
676 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
679 .opt_clks = dss_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
688 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
692 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
693 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
695 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
696 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
697 .sysc_fields = &omap_hwmod_sysc_type1,
700 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
702 .sysc = &omap3_dispc_sysc,
705 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
707 .class = &omap3_dispc_hwmod_class,
708 .mpu_irqs = omap2_dispc_irqs,
709 .main_clk = "dss1_alwon_fck",
713 .module_bit = OMAP3430_EN_DSS1_SHIFT,
714 .module_offs = OMAP3430_DSS_MOD,
717 .flags = HWMOD_NO_IDLEST,
718 .dev_attr = &omap2_3_dss_dispc_dev_attr
723 * display serial interface controller
726 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
730 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
731 { .irq = 25 + OMAP_INTC_START, },
736 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
737 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
740 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
742 .class = &omap3xxx_dsi_hwmod_class,
743 .mpu_irqs = omap3xxx_dsi1_irqs,
744 .main_clk = "dss1_alwon_fck",
748 .module_bit = OMAP3430_EN_DSS1_SHIFT,
749 .module_offs = OMAP3430_DSS_MOD,
752 .opt_clks = dss_dsi1_opt_clks,
753 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
754 .flags = HWMOD_NO_IDLEST,
757 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
758 { .role = "ick", .clk = "dss_ick" },
761 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
763 .class = &omap2_rfbi_hwmod_class,
764 .main_clk = "dss1_alwon_fck",
768 .module_bit = OMAP3430_EN_DSS1_SHIFT,
769 .module_offs = OMAP3430_DSS_MOD,
772 .opt_clks = dss_rfbi_opt_clks,
773 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
774 .flags = HWMOD_NO_IDLEST,
777 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
778 /* required only on OMAP3430 */
779 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
782 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
784 .class = &omap2_venc_hwmod_class,
785 .main_clk = "dss_tv_fck",
789 .module_bit = OMAP3430_EN_DSS1_SHIFT,
790 .module_offs = OMAP3430_DSS_MOD,
793 .opt_clks = dss_venc_opt_clks,
794 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
795 .flags = HWMOD_NO_IDLEST,
799 static struct omap_i2c_dev_attr i2c1_dev_attr = {
800 .fifo_depth = 8, /* bytes */
801 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
804 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
806 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
807 .mpu_irqs = omap2_i2c1_mpu_irqs,
808 .sdma_reqs = omap2_i2c1_sdma_reqs,
809 .main_clk = "i2c1_fck",
812 .module_offs = CORE_MOD,
814 .module_bit = OMAP3430_EN_I2C1_SHIFT,
816 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
820 .dev_attr = &i2c1_dev_attr,
824 static struct omap_i2c_dev_attr i2c2_dev_attr = {
825 .fifo_depth = 8, /* bytes */
826 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
829 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
831 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
832 .mpu_irqs = omap2_i2c2_mpu_irqs,
833 .sdma_reqs = omap2_i2c2_sdma_reqs,
834 .main_clk = "i2c2_fck",
837 .module_offs = CORE_MOD,
839 .module_bit = OMAP3430_EN_I2C2_SHIFT,
841 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
845 .dev_attr = &i2c2_dev_attr,
849 static struct omap_i2c_dev_attr i2c3_dev_attr = {
850 .fifo_depth = 64, /* bytes */
851 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
854 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
855 { .irq = 61 + OMAP_INTC_START, },
859 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
860 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
861 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
865 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
867 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
868 .mpu_irqs = i2c3_mpu_irqs,
869 .sdma_reqs = i2c3_sdma_reqs,
870 .main_clk = "i2c3_fck",
873 .module_offs = CORE_MOD,
875 .module_bit = OMAP3430_EN_I2C3_SHIFT,
877 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
881 .dev_attr = &i2c3_dev_attr,
886 * general purpose io module
889 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
893 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
894 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
895 SYSS_HAS_RESET_STATUS),
896 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
897 .sysc_fields = &omap_hwmod_sysc_type1,
900 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
902 .sysc = &omap3xxx_gpio_sysc,
907 static struct omap_gpio_dev_attr gpio_dev_attr = {
913 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
914 { .role = "dbclk", .clk = "gpio1_dbck", },
917 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
919 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
920 .mpu_irqs = omap2_gpio1_irqs,
921 .main_clk = "gpio1_ick",
922 .opt_clks = gpio1_opt_clks,
923 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
927 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
928 .module_offs = WKUP_MOD,
930 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
933 .class = &omap3xxx_gpio_hwmod_class,
934 .dev_attr = &gpio_dev_attr,
938 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
939 { .role = "dbclk", .clk = "gpio2_dbck", },
942 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
944 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
945 .mpu_irqs = omap2_gpio2_irqs,
946 .main_clk = "gpio2_ick",
947 .opt_clks = gpio2_opt_clks,
948 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
952 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
953 .module_offs = OMAP3430_PER_MOD,
955 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
958 .class = &omap3xxx_gpio_hwmod_class,
959 .dev_attr = &gpio_dev_attr,
963 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
964 { .role = "dbclk", .clk = "gpio3_dbck", },
967 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
969 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
970 .mpu_irqs = omap2_gpio3_irqs,
971 .main_clk = "gpio3_ick",
972 .opt_clks = gpio3_opt_clks,
973 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
977 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
978 .module_offs = OMAP3430_PER_MOD,
980 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
983 .class = &omap3xxx_gpio_hwmod_class,
984 .dev_attr = &gpio_dev_attr,
988 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
989 { .role = "dbclk", .clk = "gpio4_dbck", },
992 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
994 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
995 .mpu_irqs = omap2_gpio4_irqs,
996 .main_clk = "gpio4_ick",
997 .opt_clks = gpio4_opt_clks,
998 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1002 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1003 .module_offs = OMAP3430_PER_MOD,
1005 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1008 .class = &omap3xxx_gpio_hwmod_class,
1009 .dev_attr = &gpio_dev_attr,
1013 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1014 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1018 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1019 { .role = "dbclk", .clk = "gpio5_dbck", },
1022 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1024 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1025 .mpu_irqs = omap3xxx_gpio5_irqs,
1026 .main_clk = "gpio5_ick",
1027 .opt_clks = gpio5_opt_clks,
1028 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1032 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1033 .module_offs = OMAP3430_PER_MOD,
1035 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1038 .class = &omap3xxx_gpio_hwmod_class,
1039 .dev_attr = &gpio_dev_attr,
1043 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1044 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1048 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1049 { .role = "dbclk", .clk = "gpio6_dbck", },
1052 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1054 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1055 .mpu_irqs = omap3xxx_gpio6_irqs,
1056 .main_clk = "gpio6_ick",
1057 .opt_clks = gpio6_opt_clks,
1058 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1062 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1063 .module_offs = OMAP3430_PER_MOD,
1065 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1068 .class = &omap3xxx_gpio_hwmod_class,
1069 .dev_attr = &gpio_dev_attr,
1072 /* dma attributes */
1073 static struct omap_dma_dev_attr dma_dev_attr = {
1074 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1075 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1079 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1081 .sysc_offs = 0x002c,
1082 .syss_offs = 0x0028,
1083 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1084 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1085 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1086 SYSS_HAS_RESET_STATUS),
1087 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089 .sysc_fields = &omap_hwmod_sysc_type1,
1092 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1094 .sysc = &omap3xxx_dma_sysc,
1098 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1100 .class = &omap3xxx_dma_hwmod_class,
1101 .mpu_irqs = omap2_dma_system_irqs,
1102 .main_clk = "core_l3_ick",
1105 .module_offs = CORE_MOD,
1107 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1109 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1112 .dev_attr = &dma_dev_attr,
1113 .flags = HWMOD_NO_IDLEST,
1118 * multi channel buffered serial port controller
1121 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1122 .sysc_offs = 0x008c,
1123 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1124 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1126 .sysc_fields = &omap_hwmod_sysc_type1,
1130 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1132 .sysc = &omap3xxx_mcbsp_sysc,
1133 .rev = MCBSP_CONFIG_TYPE3,
1136 /* McBSP functional clock mapping */
1137 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1138 { .role = "pad_fck", .clk = "mcbsp_clks" },
1139 { .role = "prcm_fck", .clk = "core_96m_fck" },
1142 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1143 { .role = "pad_fck", .clk = "mcbsp_clks" },
1144 { .role = "prcm_fck", .clk = "per_96m_fck" },
1148 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1149 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1150 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1151 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1155 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1157 .class = &omap3xxx_mcbsp_hwmod_class,
1158 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1159 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1160 .main_clk = "mcbsp1_fck",
1164 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1165 .module_offs = CORE_MOD,
1167 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1170 .opt_clks = mcbsp15_opt_clks,
1171 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1175 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1176 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1177 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1178 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1182 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1183 .sidetone = "mcbsp2_sidetone",
1186 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1188 .class = &omap3xxx_mcbsp_hwmod_class,
1189 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1190 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1191 .main_clk = "mcbsp2_fck",
1195 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1196 .module_offs = OMAP3430_PER_MOD,
1198 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1201 .opt_clks = mcbsp234_opt_clks,
1202 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1203 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1207 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1208 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1209 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1210 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1214 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1215 .sidetone = "mcbsp3_sidetone",
1218 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1220 .class = &omap3xxx_mcbsp_hwmod_class,
1221 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1222 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1223 .main_clk = "mcbsp3_fck",
1227 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1228 .module_offs = OMAP3430_PER_MOD,
1230 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1233 .opt_clks = mcbsp234_opt_clks,
1234 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1235 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1239 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1240 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1241 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1242 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1246 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1247 { .name = "rx", .dma_req = 20 },
1248 { .name = "tx", .dma_req = 19 },
1252 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1254 .class = &omap3xxx_mcbsp_hwmod_class,
1255 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1256 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1257 .main_clk = "mcbsp4_fck",
1261 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1262 .module_offs = OMAP3430_PER_MOD,
1264 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1267 .opt_clks = mcbsp234_opt_clks,
1268 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1272 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1273 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1274 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1275 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1279 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1280 { .name = "rx", .dma_req = 22 },
1281 { .name = "tx", .dma_req = 21 },
1285 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1287 .class = &omap3xxx_mcbsp_hwmod_class,
1288 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1289 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1290 .main_clk = "mcbsp5_fck",
1294 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1295 .module_offs = CORE_MOD,
1297 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1300 .opt_clks = mcbsp15_opt_clks,
1301 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1304 /* 'mcbsp sidetone' class */
1305 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1306 .sysc_offs = 0x0010,
1307 .sysc_flags = SYSC_HAS_AUTOIDLE,
1308 .sysc_fields = &omap_hwmod_sysc_type1,
1311 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1312 .name = "mcbsp_sidetone",
1313 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1316 /* mcbsp2_sidetone */
1317 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1318 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1322 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1323 .name = "mcbsp2_sidetone",
1324 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1325 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1326 .main_clk = "mcbsp2_fck",
1330 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1331 .module_offs = OMAP3430_PER_MOD,
1333 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1338 /* mcbsp3_sidetone */
1339 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1340 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1344 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1345 .name = "mcbsp3_sidetone",
1346 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1347 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1348 .main_clk = "mcbsp3_fck",
1352 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1353 .module_offs = OMAP3430_PER_MOD,
1355 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1361 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1365 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1367 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1368 .clockact = CLOCKACT_TEST_ICLK,
1369 .sysc_fields = &omap34xx_sr_sysc_fields,
1372 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1373 .name = "smartreflex",
1374 .sysc = &omap34xx_sr_sysc,
1378 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1383 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1386 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1388 .sysc_fields = &omap36xx_sr_sysc_fields,
1391 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1392 .name = "smartreflex",
1393 .sysc = &omap36xx_sr_sysc,
1398 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1399 .sensor_voltdm_name = "mpu_iva",
1402 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1403 { .irq = 18 + OMAP_INTC_START, },
1407 static struct omap_hwmod omap34xx_sr1_hwmod = {
1408 .name = "smartreflex_mpu_iva",
1409 .class = &omap34xx_smartreflex_hwmod_class,
1410 .main_clk = "sr1_fck",
1414 .module_bit = OMAP3430_EN_SR1_SHIFT,
1415 .module_offs = WKUP_MOD,
1417 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1420 .dev_attr = &sr1_dev_attr,
1421 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1422 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1425 static struct omap_hwmod omap36xx_sr1_hwmod = {
1426 .name = "smartreflex_mpu_iva",
1427 .class = &omap36xx_smartreflex_hwmod_class,
1428 .main_clk = "sr1_fck",
1432 .module_bit = OMAP3430_EN_SR1_SHIFT,
1433 .module_offs = WKUP_MOD,
1435 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1438 .dev_attr = &sr1_dev_attr,
1439 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1443 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1444 .sensor_voltdm_name = "core",
1447 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1448 { .irq = 19 + OMAP_INTC_START, },
1452 static struct omap_hwmod omap34xx_sr2_hwmod = {
1453 .name = "smartreflex_core",
1454 .class = &omap34xx_smartreflex_hwmod_class,
1455 .main_clk = "sr2_fck",
1459 .module_bit = OMAP3430_EN_SR2_SHIFT,
1460 .module_offs = WKUP_MOD,
1462 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1465 .dev_attr = &sr2_dev_attr,
1466 .mpu_irqs = omap3_smartreflex_core_irqs,
1467 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1470 static struct omap_hwmod omap36xx_sr2_hwmod = {
1471 .name = "smartreflex_core",
1472 .class = &omap36xx_smartreflex_hwmod_class,
1473 .main_clk = "sr2_fck",
1477 .module_bit = OMAP3430_EN_SR2_SHIFT,
1478 .module_offs = WKUP_MOD,
1480 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1483 .dev_attr = &sr2_dev_attr,
1484 .mpu_irqs = omap3_smartreflex_core_irqs,
1489 * mailbox module allowing communication between the on-chip processors
1490 * using a queued mailbox-interrupt mechanism.
1493 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1497 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1498 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1499 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1500 .sysc_fields = &omap_hwmod_sysc_type1,
1503 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1505 .sysc = &omap3xxx_mailbox_sysc,
1508 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1509 { .irq = 26 + OMAP_INTC_START, },
1513 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1515 .class = &omap3xxx_mailbox_hwmod_class,
1516 .mpu_irqs = omap3xxx_mailbox_irqs,
1517 .main_clk = "mailboxes_ick",
1521 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1522 .module_offs = CORE_MOD,
1524 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1531 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1535 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1537 .sysc_offs = 0x0010,
1538 .syss_offs = 0x0014,
1539 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1540 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1541 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1542 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1543 .sysc_fields = &omap_hwmod_sysc_type1,
1546 static struct omap_hwmod_class omap34xx_mcspi_class = {
1548 .sysc = &omap34xx_mcspi_sysc,
1549 .rev = OMAP3_MCSPI_REV,
1553 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1554 .num_chipselect = 4,
1557 static struct omap_hwmod omap34xx_mcspi1 = {
1559 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1560 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1561 .main_clk = "mcspi1_fck",
1564 .module_offs = CORE_MOD,
1566 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1568 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1571 .class = &omap34xx_mcspi_class,
1572 .dev_attr = &omap_mcspi1_dev_attr,
1576 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1577 .num_chipselect = 2,
1580 static struct omap_hwmod omap34xx_mcspi2 = {
1582 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1583 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1584 .main_clk = "mcspi2_fck",
1587 .module_offs = CORE_MOD,
1589 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1591 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1594 .class = &omap34xx_mcspi_class,
1595 .dev_attr = &omap_mcspi2_dev_attr,
1599 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1600 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1604 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1605 { .name = "tx0", .dma_req = 15 },
1606 { .name = "rx0", .dma_req = 16 },
1607 { .name = "tx1", .dma_req = 23 },
1608 { .name = "rx1", .dma_req = 24 },
1612 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1613 .num_chipselect = 2,
1616 static struct omap_hwmod omap34xx_mcspi3 = {
1618 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1619 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1620 .main_clk = "mcspi3_fck",
1623 .module_offs = CORE_MOD,
1625 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1627 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1630 .class = &omap34xx_mcspi_class,
1631 .dev_attr = &omap_mcspi3_dev_attr,
1635 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1636 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1640 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1641 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1642 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1646 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1647 .num_chipselect = 1,
1650 static struct omap_hwmod omap34xx_mcspi4 = {
1652 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1653 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1654 .main_clk = "mcspi4_fck",
1657 .module_offs = CORE_MOD,
1659 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1661 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1664 .class = &omap34xx_mcspi_class,
1665 .dev_attr = &omap_mcspi4_dev_attr,
1669 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1671 .sysc_offs = 0x0404,
1672 .syss_offs = 0x0408,
1673 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1674 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1676 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1677 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1678 .sysc_fields = &omap_hwmod_sysc_type1,
1681 static struct omap_hwmod_class usbotg_class = {
1683 .sysc = &omap3xxx_usbhsotg_sysc,
1687 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1689 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1690 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1694 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1695 .name = "usb_otg_hs",
1696 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1697 .main_clk = "hsotgusb_ick",
1701 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1702 .module_offs = CORE_MOD,
1704 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1705 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1708 .class = &usbotg_class,
1711 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1712 * broken when autoidle is enabled
1713 * workaround is to disable the autoidle bit at module level.
1715 * Enabling the device in any other MIDLEMODE setting but force-idle
1716 * causes core_pwrdm not enter idle states at least on OMAP3630.
1717 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1718 * signal when MIDLEMODE is set to force-idle.
1720 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1721 | HWMOD_FORCE_MSTANDBY,
1725 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1726 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1730 static struct omap_hwmod_class am35xx_usbotg_class = {
1731 .name = "am35xx_usbotg",
1734 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1735 .name = "am35x_otg_hs",
1736 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1737 .main_clk = "hsotgusb_fck",
1738 .class = &am35xx_usbotg_class,
1739 .flags = HWMOD_NO_IDLEST,
1742 /* MMC/SD/SDIO common */
1743 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1747 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1748 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1749 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1750 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1751 .sysc_fields = &omap_hwmod_sysc_type1,
1754 static struct omap_hwmod_class omap34xx_mmc_class = {
1756 .sysc = &omap34xx_mmc_sysc,
1761 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1762 { .irq = 83 + OMAP_INTC_START, },
1766 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1767 { .name = "tx", .dma_req = 61, },
1768 { .name = "rx", .dma_req = 62, },
1772 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1773 { .role = "dbck", .clk = "omap_32k_fck", },
1776 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1777 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1780 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1781 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1782 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1783 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1786 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1788 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1789 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1790 .opt_clks = omap34xx_mmc1_opt_clks,
1791 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1792 .main_clk = "mmchs1_fck",
1795 .module_offs = CORE_MOD,
1797 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1799 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1802 .dev_attr = &mmc1_pre_es3_dev_attr,
1803 .class = &omap34xx_mmc_class,
1806 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1808 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1809 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1810 .opt_clks = omap34xx_mmc1_opt_clks,
1811 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1812 .main_clk = "mmchs1_fck",
1815 .module_offs = CORE_MOD,
1817 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1819 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1822 .dev_attr = &mmc1_dev_attr,
1823 .class = &omap34xx_mmc_class,
1828 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1829 { .irq = 86 + OMAP_INTC_START, },
1833 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1834 { .name = "tx", .dma_req = 47, },
1835 { .name = "rx", .dma_req = 48, },
1839 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1840 { .role = "dbck", .clk = "omap_32k_fck", },
1843 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1844 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1845 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1848 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1850 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1851 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1852 .opt_clks = omap34xx_mmc2_opt_clks,
1853 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1854 .main_clk = "mmchs2_fck",
1857 .module_offs = CORE_MOD,
1859 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1861 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1864 .dev_attr = &mmc2_pre_es3_dev_attr,
1865 .class = &omap34xx_mmc_class,
1868 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1870 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1871 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1872 .opt_clks = omap34xx_mmc2_opt_clks,
1873 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1874 .main_clk = "mmchs2_fck",
1877 .module_offs = CORE_MOD,
1879 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1881 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1884 .class = &omap34xx_mmc_class,
1889 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1890 { .irq = 94 + OMAP_INTC_START, },
1894 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1895 { .name = "tx", .dma_req = 77, },
1896 { .name = "rx", .dma_req = 78, },
1900 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1901 { .role = "dbck", .clk = "omap_32k_fck", },
1904 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1906 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1907 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1908 .opt_clks = omap34xx_mmc3_opt_clks,
1909 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1910 .main_clk = "mmchs3_fck",
1914 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1916 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1919 .class = &omap34xx_mmc_class,
1923 * 'usb_host_hs' class
1924 * high-speed multi-port usb host controller
1927 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1929 .sysc_offs = 0x0010,
1930 .syss_offs = 0x0014,
1931 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1932 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1933 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1934 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1935 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1936 .sysc_fields = &omap_hwmod_sysc_type1,
1939 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1940 .name = "usb_host_hs",
1941 .sysc = &omap3xxx_usb_host_hs_sysc,
1944 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1945 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1948 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1949 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1950 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1954 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1955 .name = "usb_host_hs",
1956 .class = &omap3xxx_usb_host_hs_hwmod_class,
1957 .clkdm_name = "l3_init_clkdm",
1958 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1959 .main_clk = "usbhost_48m_fck",
1962 .module_offs = OMAP3430ES2_USBHOST_MOD,
1964 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1966 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1967 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1970 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1971 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1974 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1978 * In the following configuration :
1979 * - USBHOST module is set to smart-idle mode
1980 * - PRCM asserts idle_req to the USBHOST module ( This typically
1981 * happens when the system is going to a low power mode : all ports
1982 * have been suspended, the master part of the USBHOST module has
1983 * entered the standby state, and SW has cut the functional clocks)
1984 * - an USBHOST interrupt occurs before the module is able to answer
1985 * idle_ack, typically a remote wakeup IRQ.
1986 * Then the USB HOST module will enter a deadlock situation where it
1987 * is no more accessible nor functional.
1990 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1994 * Errata: USB host EHCI may stall when entering smart-standby mode
1998 * When the USBHOST module is set to smart-standby mode, and when it is
1999 * ready to enter the standby state (i.e. all ports are suspended and
2000 * all attached devices are in suspend mode), then it can wrongly assert
2001 * the Mstandby signal too early while there are still some residual OCP
2002 * transactions ongoing. If this condition occurs, the internal state
2003 * machine may go to an undefined state and the USB link may be stuck
2004 * upon the next resume.
2007 * Don't use smart standby; use only force standby,
2008 * hence HWMOD_SWSUP_MSTANDBY
2012 * During system boot; If the hwmod framework resets the module
2013 * the module will have smart idle settings; which can lead to deadlock
2014 * (above Errata Id:i660); so, dont reset the module during boot;
2015 * Use HWMOD_INIT_NO_RESET.
2018 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2019 HWMOD_INIT_NO_RESET,
2023 * 'usb_tll_hs' class
2024 * usb_tll_hs module is the adapter on the usb_host_hs ports
2026 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2028 .sysc_offs = 0x0010,
2029 .syss_offs = 0x0014,
2030 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2034 .sysc_fields = &omap_hwmod_sysc_type1,
2037 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2038 .name = "usb_tll_hs",
2039 .sysc = &omap3xxx_usb_tll_hs_sysc,
2042 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2043 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2047 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2048 .name = "usb_tll_hs",
2049 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2050 .clkdm_name = "l3_init_clkdm",
2051 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2052 .main_clk = "usbtll_fck",
2055 .module_offs = CORE_MOD,
2057 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2059 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2064 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2066 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2067 .main_clk = "hdq_fck",
2070 .module_offs = CORE_MOD,
2072 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2074 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2077 .class = &omap2_hdq1w_class,
2081 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2082 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2083 { .name = "rst_modem_sw", .rst_shift = 1 },
2086 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2090 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2092 .rst_lines = omap3xxx_sad2d_resets,
2093 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2094 .main_clk = "sad2d_ick",
2097 .module_offs = CORE_MOD,
2099 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2101 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2104 .class = &omap3xxx_sad2d_class,
2108 * '32K sync counter' class
2109 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2111 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2113 .sysc_offs = 0x0004,
2114 .sysc_flags = SYSC_HAS_SIDLEMODE,
2115 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2116 .sysc_fields = &omap_hwmod_sysc_type1,
2119 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2121 .sysc = &omap3xxx_counter_sysc,
2124 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2125 .name = "counter_32k",
2126 .class = &omap3xxx_counter_hwmod_class,
2127 .clkdm_name = "wkup_clkdm",
2128 .flags = HWMOD_SWSUP_SIDLE,
2129 .main_clk = "wkup_32k_fck",
2132 .module_offs = WKUP_MOD,
2134 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2136 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2143 * general purpose memory controller
2146 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2148 .sysc_offs = 0x0010,
2149 .syss_offs = 0x0014,
2150 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2151 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2152 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2153 .sysc_fields = &omap_hwmod_sysc_type1,
2156 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2158 .sysc = &omap3xxx_gpmc_sysc,
2161 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2166 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2168 .class = &omap3xxx_gpmc_hwmod_class,
2169 .clkdm_name = "core_l3_clkdm",
2170 .mpu_irqs = omap3xxx_gpmc_irqs,
2171 .main_clk = "gpmc_fck",
2173 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2174 * block. It is not being added due to any known bugs with
2175 * resetting the GPMC IP block, but rather because any timings
2176 * set by the bootloader are not being correctly programmed by
2177 * the kernel from the board file or DT data.
2178 * HWMOD_INIT_NO_RESET should be removed ASAP.
2180 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2188 /* L3 -> L4_CORE interface */
2189 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2190 .master = &omap3xxx_l3_main_hwmod,
2191 .slave = &omap3xxx_l4_core_hwmod,
2192 .user = OCP_USER_MPU | OCP_USER_SDMA,
2195 /* L3 -> L4_PER interface */
2196 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2197 .master = &omap3xxx_l3_main_hwmod,
2198 .slave = &omap3xxx_l4_per_hwmod,
2199 .user = OCP_USER_MPU | OCP_USER_SDMA,
2202 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2204 .pa_start = 0x68000000,
2205 .pa_end = 0x6800ffff,
2206 .flags = ADDR_TYPE_RT,
2211 /* MPU -> L3 interface */
2212 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2213 .master = &omap3xxx_mpu_hwmod,
2214 .slave = &omap3xxx_l3_main_hwmod,
2215 .addr = omap3xxx_l3_main_addrs,
2216 .user = OCP_USER_MPU,
2219 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2221 .pa_start = 0x54000000,
2222 .pa_end = 0x547fffff,
2223 .flags = ADDR_TYPE_RT,
2229 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2230 .master = &omap3xxx_l3_main_hwmod,
2231 .slave = &omap3xxx_debugss_hwmod,
2232 .addr = omap3xxx_l4_emu_addrs,
2233 .user = OCP_USER_MPU,
2237 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2238 .master = &omap3430es1_dss_core_hwmod,
2239 .slave = &omap3xxx_l3_main_hwmod,
2240 .user = OCP_USER_MPU | OCP_USER_SDMA,
2243 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2244 .master = &omap3xxx_dss_core_hwmod,
2245 .slave = &omap3xxx_l3_main_hwmod,
2248 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2249 .flags = OMAP_FIREWALL_L3,
2252 .user = OCP_USER_MPU | OCP_USER_SDMA,
2255 /* l3_core -> usbhsotg interface */
2256 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2257 .master = &omap3xxx_usbhsotg_hwmod,
2258 .slave = &omap3xxx_l3_main_hwmod,
2259 .clk = "core_l3_ick",
2260 .user = OCP_USER_MPU,
2263 /* l3_core -> am35xx_usbhsotg interface */
2264 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2265 .master = &am35xx_usbhsotg_hwmod,
2266 .slave = &omap3xxx_l3_main_hwmod,
2267 .clk = "hsotgusb_ick",
2268 .user = OCP_USER_MPU,
2271 /* l3_core -> sad2d interface */
2272 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2273 .master = &omap3xxx_sad2d_hwmod,
2274 .slave = &omap3xxx_l3_main_hwmod,
2275 .clk = "core_l3_ick",
2276 .user = OCP_USER_MPU,
2279 /* L4_CORE -> L4_WKUP interface */
2280 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2281 .master = &omap3xxx_l4_core_hwmod,
2282 .slave = &omap3xxx_l4_wkup_hwmod,
2283 .user = OCP_USER_MPU | OCP_USER_SDMA,
2286 /* L4 CORE -> MMC1 interface */
2287 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2288 .master = &omap3xxx_l4_core_hwmod,
2289 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2290 .clk = "mmchs1_ick",
2291 .addr = omap2430_mmc1_addr_space,
2292 .user = OCP_USER_MPU | OCP_USER_SDMA,
2293 .flags = OMAP_FIREWALL_L4
2296 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2297 .master = &omap3xxx_l4_core_hwmod,
2298 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2299 .clk = "mmchs1_ick",
2300 .addr = omap2430_mmc1_addr_space,
2301 .user = OCP_USER_MPU | OCP_USER_SDMA,
2302 .flags = OMAP_FIREWALL_L4
2305 /* L4 CORE -> MMC2 interface */
2306 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2307 .master = &omap3xxx_l4_core_hwmod,
2308 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2309 .clk = "mmchs2_ick",
2310 .addr = omap2430_mmc2_addr_space,
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312 .flags = OMAP_FIREWALL_L4
2315 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2316 .master = &omap3xxx_l4_core_hwmod,
2317 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2318 .clk = "mmchs2_ick",
2319 .addr = omap2430_mmc2_addr_space,
2320 .user = OCP_USER_MPU | OCP_USER_SDMA,
2321 .flags = OMAP_FIREWALL_L4
2324 /* L4 CORE -> MMC3 interface */
2325 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2327 .pa_start = 0x480ad000,
2328 .pa_end = 0x480ad1ff,
2329 .flags = ADDR_TYPE_RT,
2334 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2335 .master = &omap3xxx_l4_core_hwmod,
2336 .slave = &omap3xxx_mmc3_hwmod,
2337 .clk = "mmchs3_ick",
2338 .addr = omap3xxx_mmc3_addr_space,
2339 .user = OCP_USER_MPU | OCP_USER_SDMA,
2340 .flags = OMAP_FIREWALL_L4
2343 /* L4 CORE -> UART1 interface */
2344 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2346 .pa_start = OMAP3_UART1_BASE,
2347 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2348 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2353 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2354 .master = &omap3xxx_l4_core_hwmod,
2355 .slave = &omap3xxx_uart1_hwmod,
2357 .addr = omap3xxx_uart1_addr_space,
2358 .user = OCP_USER_MPU | OCP_USER_SDMA,
2361 /* L4 CORE -> UART2 interface */
2362 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2364 .pa_start = OMAP3_UART2_BASE,
2365 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2366 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2371 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2372 .master = &omap3xxx_l4_core_hwmod,
2373 .slave = &omap3xxx_uart2_hwmod,
2375 .addr = omap3xxx_uart2_addr_space,
2376 .user = OCP_USER_MPU | OCP_USER_SDMA,
2379 /* L4 PER -> UART3 interface */
2380 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2382 .pa_start = OMAP3_UART3_BASE,
2383 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2384 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2389 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2390 .master = &omap3xxx_l4_per_hwmod,
2391 .slave = &omap3xxx_uart3_hwmod,
2393 .addr = omap3xxx_uart3_addr_space,
2394 .user = OCP_USER_MPU | OCP_USER_SDMA,
2397 /* L4 PER -> UART4 interface */
2398 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2400 .pa_start = OMAP3_UART4_BASE,
2401 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2402 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2407 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2408 .master = &omap3xxx_l4_per_hwmod,
2409 .slave = &omap36xx_uart4_hwmod,
2411 .addr = omap36xx_uart4_addr_space,
2412 .user = OCP_USER_MPU | OCP_USER_SDMA,
2415 /* AM35xx: L4 CORE -> UART4 interface */
2416 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2418 .pa_start = OMAP3_UART4_AM35XX_BASE,
2419 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2420 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2425 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2426 .master = &omap3xxx_l4_core_hwmod,
2427 .slave = &am35xx_uart4_hwmod,
2429 .addr = am35xx_uart4_addr_space,
2430 .user = OCP_USER_MPU | OCP_USER_SDMA,
2433 /* L4 CORE -> I2C1 interface */
2434 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2435 .master = &omap3xxx_l4_core_hwmod,
2436 .slave = &omap3xxx_i2c1_hwmod,
2438 .addr = omap2_i2c1_addr_space,
2441 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2443 .flags = OMAP_FIREWALL_L4,
2446 .user = OCP_USER_MPU | OCP_USER_SDMA,
2449 /* L4 CORE -> I2C2 interface */
2450 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2451 .master = &omap3xxx_l4_core_hwmod,
2452 .slave = &omap3xxx_i2c2_hwmod,
2454 .addr = omap2_i2c2_addr_space,
2457 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2459 .flags = OMAP_FIREWALL_L4,
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465 /* L4 CORE -> I2C3 interface */
2466 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2468 .pa_start = 0x48060000,
2469 .pa_end = 0x48060000 + SZ_128 - 1,
2470 .flags = ADDR_TYPE_RT,
2475 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2476 .master = &omap3xxx_l4_core_hwmod,
2477 .slave = &omap3xxx_i2c3_hwmod,
2479 .addr = omap3xxx_i2c3_addr_space,
2482 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2484 .flags = OMAP_FIREWALL_L4,
2487 .user = OCP_USER_MPU | OCP_USER_SDMA,
2490 /* L4 CORE -> SR1 interface */
2491 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2493 .pa_start = OMAP34XX_SR1_BASE,
2494 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2495 .flags = ADDR_TYPE_RT,
2500 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2501 .master = &omap3xxx_l4_core_hwmod,
2502 .slave = &omap34xx_sr1_hwmod,
2504 .addr = omap3_sr1_addr_space,
2505 .user = OCP_USER_MPU,
2508 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2509 .master = &omap3xxx_l4_core_hwmod,
2510 .slave = &omap36xx_sr1_hwmod,
2512 .addr = omap3_sr1_addr_space,
2513 .user = OCP_USER_MPU,
2516 /* L4 CORE -> SR1 interface */
2517 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2519 .pa_start = OMAP34XX_SR2_BASE,
2520 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2521 .flags = ADDR_TYPE_RT,
2526 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2527 .master = &omap3xxx_l4_core_hwmod,
2528 .slave = &omap34xx_sr2_hwmod,
2530 .addr = omap3_sr2_addr_space,
2531 .user = OCP_USER_MPU,
2534 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2535 .master = &omap3xxx_l4_core_hwmod,
2536 .slave = &omap36xx_sr2_hwmod,
2538 .addr = omap3_sr2_addr_space,
2539 .user = OCP_USER_MPU,
2542 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2544 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2545 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2546 .flags = ADDR_TYPE_RT
2551 /* l4_core -> usbhsotg */
2552 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2553 .master = &omap3xxx_l4_core_hwmod,
2554 .slave = &omap3xxx_usbhsotg_hwmod,
2556 .addr = omap3xxx_usbhsotg_addrs,
2557 .user = OCP_USER_MPU,
2560 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2562 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2563 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2564 .flags = ADDR_TYPE_RT
2569 /* l4_core -> usbhsotg */
2570 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2571 .master = &omap3xxx_l4_core_hwmod,
2572 .slave = &am35xx_usbhsotg_hwmod,
2573 .clk = "hsotgusb_ick",
2574 .addr = am35xx_usbhsotg_addrs,
2575 .user = OCP_USER_MPU,
2578 /* L4_WKUP -> L4_SEC interface */
2579 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2580 .master = &omap3xxx_l4_wkup_hwmod,
2581 .slave = &omap3xxx_l4_sec_hwmod,
2582 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585 /* IVA2 <- L3 interface */
2586 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2587 .master = &omap3xxx_l3_main_hwmod,
2588 .slave = &omap3xxx_iva_hwmod,
2589 .clk = "core_l3_ick",
2590 .user = OCP_USER_MPU | OCP_USER_SDMA,
2593 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2595 .pa_start = 0x48318000,
2596 .pa_end = 0x48318000 + SZ_1K - 1,
2597 .flags = ADDR_TYPE_RT
2602 /* l4_wkup -> timer1 */
2603 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2604 .master = &omap3xxx_l4_wkup_hwmod,
2605 .slave = &omap3xxx_timer1_hwmod,
2607 .addr = omap3xxx_timer1_addrs,
2608 .user = OCP_USER_MPU | OCP_USER_SDMA,
2611 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2613 .pa_start = 0x49032000,
2614 .pa_end = 0x49032000 + SZ_1K - 1,
2615 .flags = ADDR_TYPE_RT
2620 /* l4_per -> timer2 */
2621 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2622 .master = &omap3xxx_l4_per_hwmod,
2623 .slave = &omap3xxx_timer2_hwmod,
2625 .addr = omap3xxx_timer2_addrs,
2626 .user = OCP_USER_MPU | OCP_USER_SDMA,
2629 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2631 .pa_start = 0x49034000,
2632 .pa_end = 0x49034000 + SZ_1K - 1,
2633 .flags = ADDR_TYPE_RT
2638 /* l4_per -> timer3 */
2639 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2640 .master = &omap3xxx_l4_per_hwmod,
2641 .slave = &omap3xxx_timer3_hwmod,
2643 .addr = omap3xxx_timer3_addrs,
2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
2647 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2649 .pa_start = 0x49036000,
2650 .pa_end = 0x49036000 + SZ_1K - 1,
2651 .flags = ADDR_TYPE_RT
2656 /* l4_per -> timer4 */
2657 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2658 .master = &omap3xxx_l4_per_hwmod,
2659 .slave = &omap3xxx_timer4_hwmod,
2661 .addr = omap3xxx_timer4_addrs,
2662 .user = OCP_USER_MPU | OCP_USER_SDMA,
2665 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2667 .pa_start = 0x49038000,
2668 .pa_end = 0x49038000 + SZ_1K - 1,
2669 .flags = ADDR_TYPE_RT
2674 /* l4_per -> timer5 */
2675 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2676 .master = &omap3xxx_l4_per_hwmod,
2677 .slave = &omap3xxx_timer5_hwmod,
2679 .addr = omap3xxx_timer5_addrs,
2680 .user = OCP_USER_MPU | OCP_USER_SDMA,
2683 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2685 .pa_start = 0x4903A000,
2686 .pa_end = 0x4903A000 + SZ_1K - 1,
2687 .flags = ADDR_TYPE_RT
2692 /* l4_per -> timer6 */
2693 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2694 .master = &omap3xxx_l4_per_hwmod,
2695 .slave = &omap3xxx_timer6_hwmod,
2697 .addr = omap3xxx_timer6_addrs,
2698 .user = OCP_USER_MPU | OCP_USER_SDMA,
2701 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2703 .pa_start = 0x4903C000,
2704 .pa_end = 0x4903C000 + SZ_1K - 1,
2705 .flags = ADDR_TYPE_RT
2710 /* l4_per -> timer7 */
2711 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2712 .master = &omap3xxx_l4_per_hwmod,
2713 .slave = &omap3xxx_timer7_hwmod,
2715 .addr = omap3xxx_timer7_addrs,
2716 .user = OCP_USER_MPU | OCP_USER_SDMA,
2719 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2721 .pa_start = 0x4903E000,
2722 .pa_end = 0x4903E000 + SZ_1K - 1,
2723 .flags = ADDR_TYPE_RT
2728 /* l4_per -> timer8 */
2729 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2730 .master = &omap3xxx_l4_per_hwmod,
2731 .slave = &omap3xxx_timer8_hwmod,
2733 .addr = omap3xxx_timer8_addrs,
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2737 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2739 .pa_start = 0x49040000,
2740 .pa_end = 0x49040000 + SZ_1K - 1,
2741 .flags = ADDR_TYPE_RT
2746 /* l4_per -> timer9 */
2747 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2748 .master = &omap3xxx_l4_per_hwmod,
2749 .slave = &omap3xxx_timer9_hwmod,
2751 .addr = omap3xxx_timer9_addrs,
2752 .user = OCP_USER_MPU | OCP_USER_SDMA,
2755 /* l4_core -> timer10 */
2756 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2757 .master = &omap3xxx_l4_core_hwmod,
2758 .slave = &omap3xxx_timer10_hwmod,
2760 .addr = omap2_timer10_addrs,
2761 .user = OCP_USER_MPU | OCP_USER_SDMA,
2764 /* l4_core -> timer11 */
2765 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2766 .master = &omap3xxx_l4_core_hwmod,
2767 .slave = &omap3xxx_timer11_hwmod,
2769 .addr = omap2_timer11_addrs,
2770 .user = OCP_USER_MPU | OCP_USER_SDMA,
2773 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2775 .pa_start = 0x48304000,
2776 .pa_end = 0x48304000 + SZ_1K - 1,
2777 .flags = ADDR_TYPE_RT
2782 /* l4_core -> timer12 */
2783 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2784 .master = &omap3xxx_l4_sec_hwmod,
2785 .slave = &omap3xxx_timer12_hwmod,
2787 .addr = omap3xxx_timer12_addrs,
2788 .user = OCP_USER_MPU | OCP_USER_SDMA,
2791 /* l4_wkup -> wd_timer2 */
2792 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2794 .pa_start = 0x48314000,
2795 .pa_end = 0x4831407f,
2796 .flags = ADDR_TYPE_RT
2801 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2802 .master = &omap3xxx_l4_wkup_hwmod,
2803 .slave = &omap3xxx_wd_timer2_hwmod,
2805 .addr = omap3xxx_wd_timer2_addrs,
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2809 /* l4_core -> dss */
2810 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2811 .master = &omap3xxx_l4_core_hwmod,
2812 .slave = &omap3430es1_dss_core_hwmod,
2814 .addr = omap2_dss_addrs,
2817 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2818 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2819 .flags = OMAP_FIREWALL_L4,
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2825 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2826 .master = &omap3xxx_l4_core_hwmod,
2827 .slave = &omap3xxx_dss_core_hwmod,
2829 .addr = omap2_dss_addrs,
2832 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2833 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2834 .flags = OMAP_FIREWALL_L4,
2837 .user = OCP_USER_MPU | OCP_USER_SDMA,
2840 /* l4_core -> dss_dispc */
2841 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2842 .master = &omap3xxx_l4_core_hwmod,
2843 .slave = &omap3xxx_dss_dispc_hwmod,
2845 .addr = omap2_dss_dispc_addrs,
2848 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2849 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2850 .flags = OMAP_FIREWALL_L4,
2853 .user = OCP_USER_MPU | OCP_USER_SDMA,
2856 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2858 .pa_start = 0x4804FC00,
2859 .pa_end = 0x4804FFFF,
2860 .flags = ADDR_TYPE_RT
2865 /* l4_core -> dss_dsi1 */
2866 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2867 .master = &omap3xxx_l4_core_hwmod,
2868 .slave = &omap3xxx_dss_dsi1_hwmod,
2870 .addr = omap3xxx_dss_dsi1_addrs,
2873 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2874 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2875 .flags = OMAP_FIREWALL_L4,
2878 .user = OCP_USER_MPU | OCP_USER_SDMA,
2881 /* l4_core -> dss_rfbi */
2882 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2883 .master = &omap3xxx_l4_core_hwmod,
2884 .slave = &omap3xxx_dss_rfbi_hwmod,
2886 .addr = omap2_dss_rfbi_addrs,
2889 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2890 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2891 .flags = OMAP_FIREWALL_L4,
2894 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897 /* l4_core -> dss_venc */
2898 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2899 .master = &omap3xxx_l4_core_hwmod,
2900 .slave = &omap3xxx_dss_venc_hwmod,
2902 .addr = omap2_dss_venc_addrs,
2905 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2906 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2907 .flags = OMAP_FIREWALL_L4,
2910 .flags = OCPIF_SWSUP_IDLE,
2911 .user = OCP_USER_MPU | OCP_USER_SDMA,
2914 /* l4_wkup -> gpio1 */
2915 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2917 .pa_start = 0x48310000,
2918 .pa_end = 0x483101ff,
2919 .flags = ADDR_TYPE_RT
2924 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2925 .master = &omap3xxx_l4_wkup_hwmod,
2926 .slave = &omap3xxx_gpio1_hwmod,
2927 .addr = omap3xxx_gpio1_addrs,
2928 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931 /* l4_per -> gpio2 */
2932 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2934 .pa_start = 0x49050000,
2935 .pa_end = 0x490501ff,
2936 .flags = ADDR_TYPE_RT
2941 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2942 .master = &omap3xxx_l4_per_hwmod,
2943 .slave = &omap3xxx_gpio2_hwmod,
2944 .addr = omap3xxx_gpio2_addrs,
2945 .user = OCP_USER_MPU | OCP_USER_SDMA,
2948 /* l4_per -> gpio3 */
2949 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2951 .pa_start = 0x49052000,
2952 .pa_end = 0x490521ff,
2953 .flags = ADDR_TYPE_RT
2958 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2959 .master = &omap3xxx_l4_per_hwmod,
2960 .slave = &omap3xxx_gpio3_hwmod,
2961 .addr = omap3xxx_gpio3_addrs,
2962 .user = OCP_USER_MPU | OCP_USER_SDMA,
2967 * The memory management unit performs virtual to physical address translation
2968 * for its requestors.
2971 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2975 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2976 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2977 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2978 .sysc_fields = &omap_hwmod_sysc_type1,
2981 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2988 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2990 .da_end = 0xfffff000,
2991 .nr_tlb_entries = 8,
2994 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2995 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
3000 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
3002 .pa_start = 0x480bd400,
3003 .pa_end = 0x480bd47f,
3004 .flags = ADDR_TYPE_RT,
3009 /* l4_core -> mmu isp */
3010 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3011 .master = &omap3xxx_l4_core_hwmod,
3012 .slave = &omap3xxx_mmu_isp_hwmod,
3013 .addr = omap3xxx_mmu_isp_addrs,
3014 .user = OCP_USER_MPU | OCP_USER_SDMA,
3017 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3019 .class = &omap3xxx_mmu_hwmod_class,
3020 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3021 .main_clk = "cam_ick",
3022 .dev_attr = &mmu_isp_dev_attr,
3023 .flags = HWMOD_NO_IDLEST,
3026 #ifdef CONFIG_OMAP_IOMMU_IVA2
3030 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3031 .da_start = 0x11000000,
3032 .da_end = 0xfffff000,
3033 .nr_tlb_entries = 32,
3036 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3037 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3042 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3043 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3046 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3048 .pa_start = 0x5d000000,
3049 .pa_end = 0x5d00007f,
3050 .flags = ADDR_TYPE_RT,
3055 /* l3_main -> iva mmu */
3056 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3057 .master = &omap3xxx_l3_main_hwmod,
3058 .slave = &omap3xxx_mmu_iva_hwmod,
3059 .addr = omap3xxx_mmu_iva_addrs,
3060 .user = OCP_USER_MPU | OCP_USER_SDMA,
3063 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3065 .class = &omap3xxx_mmu_hwmod_class,
3066 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3067 .rst_lines = omap3xxx_mmu_iva_resets,
3068 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3069 .main_clk = "iva2_ck",
3072 .module_offs = OMAP3430_IVA2_MOD,
3075 .dev_attr = &mmu_iva_dev_attr,
3076 .flags = HWMOD_NO_IDLEST,
3081 /* l4_per -> gpio4 */
3082 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3084 .pa_start = 0x49054000,
3085 .pa_end = 0x490541ff,
3086 .flags = ADDR_TYPE_RT
3091 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3092 .master = &omap3xxx_l4_per_hwmod,
3093 .slave = &omap3xxx_gpio4_hwmod,
3094 .addr = omap3xxx_gpio4_addrs,
3095 .user = OCP_USER_MPU | OCP_USER_SDMA,
3098 /* l4_per -> gpio5 */
3099 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3101 .pa_start = 0x49056000,
3102 .pa_end = 0x490561ff,
3103 .flags = ADDR_TYPE_RT
3108 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3109 .master = &omap3xxx_l4_per_hwmod,
3110 .slave = &omap3xxx_gpio5_hwmod,
3111 .addr = omap3xxx_gpio5_addrs,
3112 .user = OCP_USER_MPU | OCP_USER_SDMA,
3115 /* l4_per -> gpio6 */
3116 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3118 .pa_start = 0x49058000,
3119 .pa_end = 0x490581ff,
3120 .flags = ADDR_TYPE_RT
3125 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3126 .master = &omap3xxx_l4_per_hwmod,
3127 .slave = &omap3xxx_gpio6_hwmod,
3128 .addr = omap3xxx_gpio6_addrs,
3129 .user = OCP_USER_MPU | OCP_USER_SDMA,
3132 /* dma_system -> L3 */
3133 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3134 .master = &omap3xxx_dma_system_hwmod,
3135 .slave = &omap3xxx_l3_main_hwmod,
3136 .clk = "core_l3_ick",
3137 .user = OCP_USER_MPU | OCP_USER_SDMA,
3140 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3142 .pa_start = 0x48056000,
3143 .pa_end = 0x48056fff,
3144 .flags = ADDR_TYPE_RT
3149 /* l4_cfg -> dma_system */
3150 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3151 .master = &omap3xxx_l4_core_hwmod,
3152 .slave = &omap3xxx_dma_system_hwmod,
3153 .clk = "core_l4_ick",
3154 .addr = omap3xxx_dma_system_addrs,
3155 .user = OCP_USER_MPU | OCP_USER_SDMA,
3158 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3161 .pa_start = 0x48074000,
3162 .pa_end = 0x480740ff,
3163 .flags = ADDR_TYPE_RT
3168 /* l4_core -> mcbsp1 */
3169 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3170 .master = &omap3xxx_l4_core_hwmod,
3171 .slave = &omap3xxx_mcbsp1_hwmod,
3172 .clk = "mcbsp1_ick",
3173 .addr = omap3xxx_mcbsp1_addrs,
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3177 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3180 .pa_start = 0x49022000,
3181 .pa_end = 0x490220ff,
3182 .flags = ADDR_TYPE_RT
3187 /* l4_per -> mcbsp2 */
3188 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3189 .master = &omap3xxx_l4_per_hwmod,
3190 .slave = &omap3xxx_mcbsp2_hwmod,
3191 .clk = "mcbsp2_ick",
3192 .addr = omap3xxx_mcbsp2_addrs,
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3196 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3199 .pa_start = 0x49024000,
3200 .pa_end = 0x490240ff,
3201 .flags = ADDR_TYPE_RT
3206 /* l4_per -> mcbsp3 */
3207 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3208 .master = &omap3xxx_l4_per_hwmod,
3209 .slave = &omap3xxx_mcbsp3_hwmod,
3210 .clk = "mcbsp3_ick",
3211 .addr = omap3xxx_mcbsp3_addrs,
3212 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3218 .pa_start = 0x49026000,
3219 .pa_end = 0x490260ff,
3220 .flags = ADDR_TYPE_RT
3225 /* l4_per -> mcbsp4 */
3226 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3227 .master = &omap3xxx_l4_per_hwmod,
3228 .slave = &omap3xxx_mcbsp4_hwmod,
3229 .clk = "mcbsp4_ick",
3230 .addr = omap3xxx_mcbsp4_addrs,
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3237 .pa_start = 0x48096000,
3238 .pa_end = 0x480960ff,
3239 .flags = ADDR_TYPE_RT
3244 /* l4_core -> mcbsp5 */
3245 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3246 .master = &omap3xxx_l4_core_hwmod,
3247 .slave = &omap3xxx_mcbsp5_hwmod,
3248 .clk = "mcbsp5_ick",
3249 .addr = omap3xxx_mcbsp5_addrs,
3250 .user = OCP_USER_MPU | OCP_USER_SDMA,
3253 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3256 .pa_start = 0x49028000,
3257 .pa_end = 0x490280ff,
3258 .flags = ADDR_TYPE_RT
3263 /* l4_per -> mcbsp2_sidetone */
3264 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3265 .master = &omap3xxx_l4_per_hwmod,
3266 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3267 .clk = "mcbsp2_ick",
3268 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3269 .user = OCP_USER_MPU,
3272 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3275 .pa_start = 0x4902A000,
3276 .pa_end = 0x4902A0ff,
3277 .flags = ADDR_TYPE_RT
3282 /* l4_per -> mcbsp3_sidetone */
3283 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3284 .master = &omap3xxx_l4_per_hwmod,
3285 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3286 .clk = "mcbsp3_ick",
3287 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3288 .user = OCP_USER_MPU,
3291 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3293 .pa_start = 0x48094000,
3294 .pa_end = 0x480941ff,
3295 .flags = ADDR_TYPE_RT,
3300 /* l4_core -> mailbox */
3301 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3302 .master = &omap3xxx_l4_core_hwmod,
3303 .slave = &omap3xxx_mailbox_hwmod,
3304 .addr = omap3xxx_mailbox_addrs,
3305 .user = OCP_USER_MPU | OCP_USER_SDMA,
3308 /* l4 core -> mcspi1 interface */
3309 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3310 .master = &omap3xxx_l4_core_hwmod,
3311 .slave = &omap34xx_mcspi1,
3312 .clk = "mcspi1_ick",
3313 .addr = omap2_mcspi1_addr_space,
3314 .user = OCP_USER_MPU | OCP_USER_SDMA,
3317 /* l4 core -> mcspi2 interface */
3318 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3319 .master = &omap3xxx_l4_core_hwmod,
3320 .slave = &omap34xx_mcspi2,
3321 .clk = "mcspi2_ick",
3322 .addr = omap2_mcspi2_addr_space,
3323 .user = OCP_USER_MPU | OCP_USER_SDMA,
3326 /* l4 core -> mcspi3 interface */
3327 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3328 .master = &omap3xxx_l4_core_hwmod,
3329 .slave = &omap34xx_mcspi3,
3330 .clk = "mcspi3_ick",
3331 .addr = omap2430_mcspi3_addr_space,
3332 .user = OCP_USER_MPU | OCP_USER_SDMA,
3335 /* l4 core -> mcspi4 interface */
3336 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3338 .pa_start = 0x480ba000,
3339 .pa_end = 0x480ba0ff,
3340 .flags = ADDR_TYPE_RT,
3345 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3346 .master = &omap3xxx_l4_core_hwmod,
3347 .slave = &omap34xx_mcspi4,
3348 .clk = "mcspi4_ick",
3349 .addr = omap34xx_mcspi4_addr_space,
3350 .user = OCP_USER_MPU | OCP_USER_SDMA,
3353 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3354 .master = &omap3xxx_usb_host_hs_hwmod,
3355 .slave = &omap3xxx_l3_main_hwmod,
3356 .clk = "core_l3_ick",
3357 .user = OCP_USER_MPU,
3360 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3363 .pa_start = 0x48064000,
3364 .pa_end = 0x480643ff,
3365 .flags = ADDR_TYPE_RT
3369 .pa_start = 0x48064400,
3370 .pa_end = 0x480647ff,
3374 .pa_start = 0x48064800,
3375 .pa_end = 0x48064cff,
3380 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3381 .master = &omap3xxx_l4_core_hwmod,
3382 .slave = &omap3xxx_usb_host_hs_hwmod,
3383 .clk = "usbhost_ick",
3384 .addr = omap3xxx_usb_host_hs_addrs,
3385 .user = OCP_USER_MPU | OCP_USER_SDMA,
3388 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3391 .pa_start = 0x48062000,
3392 .pa_end = 0x48062fff,
3393 .flags = ADDR_TYPE_RT
3398 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3399 .master = &omap3xxx_l4_core_hwmod,
3400 .slave = &omap3xxx_usb_tll_hs_hwmod,
3401 .clk = "usbtll_ick",
3402 .addr = omap3xxx_usb_tll_hs_addrs,
3403 .user = OCP_USER_MPU | OCP_USER_SDMA,
3406 /* l4_core -> hdq1w interface */
3407 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3408 .master = &omap3xxx_l4_core_hwmod,
3409 .slave = &omap3xxx_hdq1w_hwmod,
3411 .addr = omap2_hdq1w_addr_space,
3412 .user = OCP_USER_MPU | OCP_USER_SDMA,
3413 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3416 /* l4_wkup -> 32ksync_counter */
3417 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3419 .pa_start = 0x48320000,
3420 .pa_end = 0x4832001f,
3421 .flags = ADDR_TYPE_RT
3426 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3428 .pa_start = 0x6e000000,
3429 .pa_end = 0x6e000fff,
3430 .flags = ADDR_TYPE_RT
3435 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3436 .master = &omap3xxx_l4_wkup_hwmod,
3437 .slave = &omap3xxx_counter_32k_hwmod,
3438 .clk = "omap_32ksync_ick",
3439 .addr = omap3xxx_counter_32k_addrs,
3440 .user = OCP_USER_MPU | OCP_USER_SDMA,
3443 /* am35xx has Davinci MDIO & EMAC */
3444 static struct omap_hwmod_class am35xx_mdio_class = {
3445 .name = "davinci_mdio",
3448 static struct omap_hwmod am35xx_mdio_hwmod = {
3449 .name = "davinci_mdio",
3450 .class = &am35xx_mdio_class,
3451 .flags = HWMOD_NO_IDLEST,
3455 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3456 * but this will probably require some additional hwmod core support,
3457 * so is left as a future to-do item.
3459 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3460 .master = &am35xx_mdio_hwmod,
3461 .slave = &omap3xxx_l3_main_hwmod,
3463 .user = OCP_USER_MPU,
3466 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3468 .pa_start = AM35XX_IPSS_MDIO_BASE,
3469 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3470 .flags = ADDR_TYPE_RT,
3475 /* l4_core -> davinci mdio */
3477 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3478 * but this will probably require some additional hwmod core support,
3479 * so is left as a future to-do item.
3481 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3482 .master = &omap3xxx_l4_core_hwmod,
3483 .slave = &am35xx_mdio_hwmod,
3485 .addr = am35xx_mdio_addrs,
3486 .user = OCP_USER_MPU,
3489 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3490 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3491 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3492 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3493 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3497 static struct omap_hwmod_class am35xx_emac_class = {
3498 .name = "davinci_emac",
3501 static struct omap_hwmod am35xx_emac_hwmod = {
3502 .name = "davinci_emac",
3503 .mpu_irqs = am35xx_emac_mpu_irqs,
3504 .class = &am35xx_emac_class,
3506 * According to Mark Greer, the MPU will not return from WFI
3507 * when the EMAC signals an interrupt.
3508 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3510 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3513 /* l3_core -> davinci emac interface */
3515 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3516 * but this will probably require some additional hwmod core support,
3517 * so is left as a future to-do item.
3519 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3520 .master = &am35xx_emac_hwmod,
3521 .slave = &omap3xxx_l3_main_hwmod,
3523 .user = OCP_USER_MPU,
3526 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3528 .pa_start = AM35XX_IPSS_EMAC_BASE,
3529 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3530 .flags = ADDR_TYPE_RT,
3535 /* l4_core -> davinci emac */
3537 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3538 * but this will probably require some additional hwmod core support,
3539 * so is left as a future to-do item.
3541 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3542 .master = &omap3xxx_l4_core_hwmod,
3543 .slave = &am35xx_emac_hwmod,
3545 .addr = am35xx_emac_addrs,
3546 .user = OCP_USER_MPU,
3549 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3550 .master = &omap3xxx_l3_main_hwmod,
3551 .slave = &omap3xxx_gpmc_hwmod,
3552 .clk = "core_l3_ick",
3553 .addr = omap3xxx_gpmc_addrs,
3554 .user = OCP_USER_MPU | OCP_USER_SDMA,
3557 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3558 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3561 .autoidle_shift = 0,
3564 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3568 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3569 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3570 .sysc_fields = &omap3_sham_sysc_fields,
3573 static struct omap_hwmod_class omap3xxx_sham_class = {
3575 .sysc = &omap3_sham_sysc,
3578 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3579 { .irq = 49 + OMAP_INTC_START, },
3583 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3584 { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
3588 static struct omap_hwmod omap3xxx_sham_hwmod = {
3590 .mpu_irqs = omap3_sham_mpu_irqs,
3591 .sdma_reqs = omap3_sham_sdma_reqs,
3592 .main_clk = "sha12_ick",
3595 .module_offs = CORE_MOD,
3597 .module_bit = OMAP3430_EN_SHA12_SHIFT,
3599 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3602 .class = &omap3xxx_sham_class,
3605 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3607 .pa_start = 0x480c3000,
3608 .pa_end = 0x480c3000 + 0x64 - 1,
3609 .flags = ADDR_TYPE_RT
3614 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3615 .master = &omap3xxx_l4_core_hwmod,
3616 .slave = &omap3xxx_sham_hwmod,
3618 .addr = omap3xxx_sham_addrs,
3619 .user = OCP_USER_MPU | OCP_USER_SDMA,
3622 /* l4_core -> AES */
3623 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3626 .autoidle_shift = 0,
3629 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3633 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3634 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3636 .sysc_fields = &omap3xxx_aes_sysc_fields,
3639 static struct omap_hwmod_class omap3xxx_aes_class = {
3641 .sysc = &omap3_aes_sysc,
3644 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3645 { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
3646 { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
3650 static struct omap_hwmod omap3xxx_aes_hwmod = {
3652 .sdma_reqs = omap3_aes_sdma_reqs,
3653 .main_clk = "aes2_ick",
3656 .module_offs = CORE_MOD,
3658 .module_bit = OMAP3430_EN_AES2_SHIFT,
3660 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3663 .class = &omap3xxx_aes_class,
3666 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3668 .pa_start = 0x480c5000,
3669 .pa_end = 0x480c5000 + 0x50 - 1,
3670 .flags = ADDR_TYPE_RT
3675 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3676 .master = &omap3xxx_l4_core_hwmod,
3677 .slave = &omap3xxx_aes_hwmod,
3679 .addr = omap3xxx_aes_addrs,
3680 .user = OCP_USER_MPU | OCP_USER_SDMA,
3683 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3684 &omap3xxx_l3_main__l4_core,
3685 &omap3xxx_l3_main__l4_per,
3686 &omap3xxx_mpu__l3_main,
3687 &omap3xxx_l3_main__l4_debugss,
3688 &omap3xxx_l4_core__l4_wkup,
3689 &omap3xxx_l4_core__mmc3,
3690 &omap3_l4_core__uart1,
3691 &omap3_l4_core__uart2,
3692 &omap3_l4_per__uart3,
3693 &omap3_l4_core__i2c1,
3694 &omap3_l4_core__i2c2,
3695 &omap3_l4_core__i2c3,
3696 &omap3xxx_l4_wkup__l4_sec,
3697 &omap3xxx_l4_wkup__timer1,
3698 &omap3xxx_l4_per__timer2,
3699 &omap3xxx_l4_per__timer3,
3700 &omap3xxx_l4_per__timer4,
3701 &omap3xxx_l4_per__timer5,
3702 &omap3xxx_l4_per__timer6,
3703 &omap3xxx_l4_per__timer7,
3704 &omap3xxx_l4_per__timer8,
3705 &omap3xxx_l4_per__timer9,
3706 &omap3xxx_l4_core__timer10,
3707 &omap3xxx_l4_core__timer11,
3708 &omap3xxx_l4_wkup__wd_timer2,
3709 &omap3xxx_l4_wkup__gpio1,
3710 &omap3xxx_l4_per__gpio2,
3711 &omap3xxx_l4_per__gpio3,
3712 &omap3xxx_l4_per__gpio4,
3713 &omap3xxx_l4_per__gpio5,
3714 &omap3xxx_l4_per__gpio6,
3715 &omap3xxx_dma_system__l3,
3716 &omap3xxx_l4_core__dma_system,
3717 &omap3xxx_l4_core__mcbsp1,
3718 &omap3xxx_l4_per__mcbsp2,
3719 &omap3xxx_l4_per__mcbsp3,
3720 &omap3xxx_l4_per__mcbsp4,
3721 &omap3xxx_l4_core__mcbsp5,
3722 &omap3xxx_l4_per__mcbsp2_sidetone,
3723 &omap3xxx_l4_per__mcbsp3_sidetone,
3724 &omap34xx_l4_core__mcspi1,
3725 &omap34xx_l4_core__mcspi2,
3726 &omap34xx_l4_core__mcspi3,
3727 &omap34xx_l4_core__mcspi4,
3728 &omap3xxx_l4_wkup__counter_32k,
3729 &omap3xxx_l3_main__gpmc,
3733 /* GP-only hwmod links */
3734 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3735 &omap3xxx_l4_sec__timer12,
3736 &omap3xxx_l4_core__sham,
3737 &omap3xxx_l4_core__aes,
3741 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3742 &omap3xxx_l4_sec__timer12,
3743 &omap3xxx_l4_core__sham,
3744 &omap3xxx_l4_core__aes,
3748 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3749 &omap3xxx_l4_sec__timer12,
3751 * Apparently the SHA/MD5 and AES accelerator IP blocks are
3752 * only present on some AM35xx chips, and no one knows which
3754 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3755 * if you need these IP blocks on an AM35xx, try uncommenting
3756 * the following lines.
3758 /* &omap3xxx_l4_core__sham, */
3759 /* &omap3xxx_l4_core__aes, */
3763 /* 3430ES1-only hwmod links */
3764 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3765 &omap3430es1_dss__l3,
3766 &omap3430es1_l4_core__dss,
3770 /* 3430ES2+-only hwmod links */
3771 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3773 &omap3xxx_l4_core__dss,
3774 &omap3xxx_usbhsotg__l3,
3775 &omap3xxx_l4_core__usbhsotg,
3776 &omap3xxx_usb_host_hs__l3_main_2,
3777 &omap3xxx_l4_core__usb_host_hs,
3778 &omap3xxx_l4_core__usb_tll_hs,
3782 /* <= 3430ES3-only hwmod links */
3783 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3784 &omap3xxx_l4_core__pre_es3_mmc1,
3785 &omap3xxx_l4_core__pre_es3_mmc2,
3789 /* 3430ES3+-only hwmod links */
3790 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3791 &omap3xxx_l4_core__es3plus_mmc1,
3792 &omap3xxx_l4_core__es3plus_mmc2,
3796 /* 34xx-only hwmod links (all ES revisions) */
3797 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3799 &omap34xx_l4_core__sr1,
3800 &omap34xx_l4_core__sr2,
3801 &omap3xxx_l4_core__mailbox,
3802 &omap3xxx_l4_core__hdq1w,
3803 &omap3xxx_sad2d__l3,
3804 &omap3xxx_l4_core__mmu_isp,
3805 #ifdef CONFIG_OMAP_IOMMU_IVA2
3806 &omap3xxx_l3_main__mmu_iva,
3811 /* 36xx-only hwmod links (all ES revisions) */
3812 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3814 &omap36xx_l4_per__uart4,
3816 &omap3xxx_l4_core__dss,
3817 &omap36xx_l4_core__sr1,
3818 &omap36xx_l4_core__sr2,
3819 &omap3xxx_usbhsotg__l3,
3820 &omap3xxx_l4_core__usbhsotg,
3821 &omap3xxx_l4_core__mailbox,
3822 &omap3xxx_usb_host_hs__l3_main_2,
3823 &omap3xxx_l4_core__usb_host_hs,
3824 &omap3xxx_l4_core__usb_tll_hs,
3825 &omap3xxx_l4_core__es3plus_mmc1,
3826 &omap3xxx_l4_core__es3plus_mmc2,
3827 &omap3xxx_l4_core__hdq1w,
3828 &omap3xxx_sad2d__l3,
3829 &omap3xxx_l4_core__mmu_isp,
3830 #ifdef CONFIG_OMAP_IOMMU_IVA2
3831 &omap3xxx_l3_main__mmu_iva,
3836 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3838 &omap3xxx_l4_core__dss,
3839 &am35xx_usbhsotg__l3,
3840 &am35xx_l4_core__usbhsotg,
3841 &am35xx_l4_core__uart4,
3842 &omap3xxx_usb_host_hs__l3_main_2,
3843 &omap3xxx_l4_core__usb_host_hs,
3844 &omap3xxx_l4_core__usb_tll_hs,
3845 &omap3xxx_l4_core__es3plus_mmc1,
3846 &omap3xxx_l4_core__es3plus_mmc2,
3847 &omap3xxx_l4_core__hdq1w,
3849 &am35xx_l4_core__mdio,
3851 &am35xx_l4_core__emac,
3855 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3856 &omap3xxx_l4_core__dss_dispc,
3857 &omap3xxx_l4_core__dss_dsi1,
3858 &omap3xxx_l4_core__dss_rfbi,
3859 &omap3xxx_l4_core__dss_venc,
3863 int __init omap3xxx_hwmod_init(void)
3866 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
3871 /* Register hwmod links common to all OMAP3 */
3872 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3879 * Register hwmod links common to individual OMAP3 families, all
3880 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3881 * All possible revisions should be included in this conditional.
3883 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3884 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3885 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3886 h = omap34xx_hwmod_ocp_ifs;
3887 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3888 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3889 h = am35xx_hwmod_ocp_ifs;
3890 h_gp = am35xx_gp_hwmod_ocp_ifs;
3891 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3892 rev == OMAP3630_REV_ES1_2) {
3893 h = omap36xx_hwmod_ocp_ifs;
3894 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3896 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3900 r = omap_hwmod_register_links(h);
3904 /* Register GP-only hwmod links. */
3905 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3906 r = omap_hwmod_register_links(h_gp);
3913 * Register hwmod links specific to certain ES levels of a
3914 * particular family of silicon (e.g., 34xx ES1.0)
3917 if (rev == OMAP3430_REV_ES1_0) {
3918 h = omap3430es1_hwmod_ocp_ifs;
3919 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3920 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3921 rev == OMAP3430_REV_ES3_1_2) {
3922 h = omap3430es2plus_hwmod_ocp_ifs;
3926 r = omap_hwmod_register_links(h);
3932 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3933 rev == OMAP3430_REV_ES2_1) {
3934 h = omap3430_pre_es3_hwmod_ocp_ifs;
3935 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3936 rev == OMAP3430_REV_ES3_1_2) {
3937 h = omap3430_es3plus_hwmod_ocp_ifs;
3941 r = omap_hwmod_register_links(h);
3946 * DSS code presumes that dss_core hwmod is handled first,
3947 * _before_ any other DSS related hwmods so register common
3948 * DSS hwmod links last to ensure that dss_core is already
3949 * registered. Otherwise some change things may happen, for
3950 * ex. if dispc is handled before dss_core and DSS is enabled
3951 * in bootloader DISPC will be reset with outputs enabled
3952 * which sometimes leads to unrecoverable L3 error. XXX The
3953 * long-term fix to this is to ensure hwmods are set up in
3954 * dependency order in the hwmod core code.
3956 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);