arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17 #include <plat/omap_hwmod.h>
  18 #include <mach/irqs.h>
  19 #include <plat/cpu.h>
  20 #include <plat/dma.h>
  21 #include <plat/serial.h>
  22 #include <plat/l3_3xxx.h>
  23 #include <plat/l4_3xxx.h>
  24 #include <plat/i2c.h>
  25 #include <plat/gpio.h>
  26 #include <plat/mmc.h>
  27 #include <plat/mcbsp.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "smartreflex.h"
  34 #include "prm-regbits-34xx.h"
  35 #include "cm-regbits-34xx.h"
  36 #include "wd_timer.h"
  37 #include <mach/am35xx.h>
  38
  39 /*
  40  * OMAP3xxx hardware module integration data
  41  *
  42  * All of the data in this section should be autogeneratable from the
  43  * TI hardware database or other technical documentation.  Data that
  44  * is driver-specific or driver-kernel integration-specific belongs
  45  * elsewhere.
  46  */
  47
  48 /*
  49  * IP blocks
  50  */
  51
  52 /* L3 */
  53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  54         { .irq = INT_34XX_L3_DBG_IRQ },
  55         { .irq = INT_34XX_L3_APP_IRQ },
  56         { .irq = -1 }
  57 };
  58
  59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  60         .name           = "l3_main",
  61         .class          = &l3_hwmod_class,
  62         .mpu_irqs       = omap3xxx_l3_main_irqs,
  63         .flags          = HWMOD_NO_IDLEST,
  64 };
  65
  66 /* L4 CORE */
  67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  68         .name           = "l4_core",
  69         .class          = &l4_hwmod_class,
  70         .flags          = HWMOD_NO_IDLEST,
  71 };
  72
  73 /* L4 PER */
  74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  75         .name           = "l4_per",
  76         .class          = &l4_hwmod_class,
  77         .flags          = HWMOD_NO_IDLEST,
  78 };
  79
  80 /* L4 WKUP */
  81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  82         .name           = "l4_wkup",
  83         .class          = &l4_hwmod_class,
  84         .flags          = HWMOD_NO_IDLEST,
  85 };
  86
  87 /* L4 SEC */
  88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  89         .name           = "l4_sec",
  90         .class          = &l4_hwmod_class,
  91         .flags          = HWMOD_NO_IDLEST,
  92 };
  93
  94 /* MPU */
  95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  96         .name           = "mpu",
  97         .class          = &mpu_hwmod_class,
  98         .main_clk       = "arm_fck",
  99 };
 100
 101 /* IVA2 (IVA2) */
 102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 103         { .name = "logic", .rst_shift = 0 },
 104         { .name = "seq0", .rst_shift = 1 },
 105         { .name = "seq1", .rst_shift = 2 },
 106 };
 107
 108 static struct omap_hwmod omap3xxx_iva_hwmod = {
 109         .name           = "iva",
 110         .class          = &iva_hwmod_class,
 111         .clkdm_name     = "iva2_clkdm",
 112         .rst_lines      = omap3xxx_iva_resets,
 113         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 114         .main_clk       = "iva2_ck",
 115 };
 116
 117 /* timer class */
 118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 119         .rev_offs       = 0x0000,
 120         .sysc_offs      = 0x0010,
 121         .syss_offs      = 0x0014,
 122         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 123                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 124                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 125         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 126         .sysc_fields    = &omap_hwmod_sysc_type1,
 127 };
 128
 129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 130         .name = "timer",
 131         .sysc = &omap3xxx_timer_1ms_sysc,
 132         .rev = OMAP_TIMER_IP_VERSION_1,
 133 };
 134
 135 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 136         .rev_offs       = 0x0000,
 137         .sysc_offs      = 0x0010,
 138         .syss_offs      = 0x0014,
 139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 140                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 141         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 142         .sysc_fields    = &omap_hwmod_sysc_type1,
 143 };
 144
 145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 146         .name = "timer",
 147         .sysc = &omap3xxx_timer_sysc,
 148         .rev =  OMAP_TIMER_IP_VERSION_1,
 149 };
 150
 151 /* secure timers dev attribute */
 152 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 153         .timer_capability       = OMAP_TIMER_SECURE,
 154 };
 155
 156 /* always-on timers dev attribute */
 157 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 158         .timer_capability       = OMAP_TIMER_ALWON,
 159 };
 160
 161 /* pwm timers dev attribute */
 162 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 163         .timer_capability       = OMAP_TIMER_HAS_PWM,
 164 };
 165
 166 /* timer1 */
 167 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 168         .name           = "timer1",
 169         .mpu_irqs       = omap2_timer1_mpu_irqs,
 170         .main_clk       = "gpt1_fck",
 171         .prcm           = {
 172                 .omap2 = {
 173                         .prcm_reg_id = 1,
 174                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 175                         .module_offs = WKUP_MOD,
 176                         .idlest_reg_id = 1,
 177                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 178                 },
 179         },
 180         .dev_attr       = &capability_alwon_dev_attr,
 181         .class          = &omap3xxx_timer_1ms_hwmod_class,
 182 };
 183
 184 /* timer2 */
 185 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 186         .name           = "timer2",
 187         .mpu_irqs       = omap2_timer2_mpu_irqs,
 188         .main_clk       = "gpt2_fck",
 189         .prcm           = {
 190                 .omap2 = {
 191                         .prcm_reg_id = 1,
 192                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 193                         .module_offs = OMAP3430_PER_MOD,
 194                         .idlest_reg_id = 1,
 195                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 196                 },
 197         },
 198         .dev_attr       = &capability_alwon_dev_attr,
 199         .class          = &omap3xxx_timer_1ms_hwmod_class,
 200 };
 201
 202 /* timer3 */
 203 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 204         .name           = "timer3",
 205         .mpu_irqs       = omap2_timer3_mpu_irqs,
 206         .main_clk       = "gpt3_fck",
 207         .prcm           = {
 208                 .omap2 = {
 209                         .prcm_reg_id = 1,
 210                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 211                         .module_offs = OMAP3430_PER_MOD,
 212                         .idlest_reg_id = 1,
 213                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 214                 },
 215         },
 216         .dev_attr       = &capability_alwon_dev_attr,
 217         .class          = &omap3xxx_timer_hwmod_class,
 218 };
 219
 220 /* timer4 */
 221 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 222         .name           = "timer4",
 223         .mpu_irqs       = omap2_timer4_mpu_irqs,
 224         .main_clk       = "gpt4_fck",
 225         .prcm           = {
 226                 .omap2 = {
 227                         .prcm_reg_id = 1,
 228                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 229                         .module_offs = OMAP3430_PER_MOD,
 230                         .idlest_reg_id = 1,
 231                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 232                 },
 233         },
 234         .dev_attr       = &capability_alwon_dev_attr,
 235         .class          = &omap3xxx_timer_hwmod_class,
 236 };
 237
 238 /* timer5 */
 239 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 240         .name           = "timer5",
 241         .mpu_irqs       = omap2_timer5_mpu_irqs,
 242         .main_clk       = "gpt5_fck",
 243         .prcm           = {
 244                 .omap2 = {
 245                         .prcm_reg_id = 1,
 246                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 247                         .module_offs = OMAP3430_PER_MOD,
 248                         .idlest_reg_id = 1,
 249                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 250                 },
 251         },
 252         .dev_attr       = &capability_alwon_dev_attr,
 253         .class          = &omap3xxx_timer_hwmod_class,
 254 };
 255
 256 /* timer6 */
 257 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 258         .name           = "timer6",
 259         .mpu_irqs       = omap2_timer6_mpu_irqs,
 260         .main_clk       = "gpt6_fck",
 261         .prcm           = {
 262                 .omap2 = {
 263                         .prcm_reg_id = 1,
 264                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 265                         .module_offs = OMAP3430_PER_MOD,
 266                         .idlest_reg_id = 1,
 267                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 268                 },
 269         },
 270         .dev_attr       = &capability_alwon_dev_attr,
 271         .class          = &omap3xxx_timer_hwmod_class,
 272 };
 273
 274 /* timer7 */
 275 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 276         .name           = "timer7",
 277         .mpu_irqs       = omap2_timer7_mpu_irqs,
 278         .main_clk       = "gpt7_fck",
 279         .prcm           = {
 280                 .omap2 = {
 281                         .prcm_reg_id = 1,
 282                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 283                         .module_offs = OMAP3430_PER_MOD,
 284                         .idlest_reg_id = 1,
 285                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 286                 },
 287         },
 288         .dev_attr       = &capability_alwon_dev_attr,
 289         .class          = &omap3xxx_timer_hwmod_class,
 290 };
 291
 292 /* timer8 */
 293 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 294         .name           = "timer8",
 295         .mpu_irqs       = omap2_timer8_mpu_irqs,
 296         .main_clk       = "gpt8_fck",
 297         .prcm           = {
 298                 .omap2 = {
 299                         .prcm_reg_id = 1,
 300                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 301                         .module_offs = OMAP3430_PER_MOD,
 302                         .idlest_reg_id = 1,
 303                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 304                 },
 305         },
 306         .dev_attr       = &capability_pwm_dev_attr,
 307         .class          = &omap3xxx_timer_hwmod_class,
 308 };
 309
 310 /* timer9 */
 311 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 312         .name           = "timer9",
 313         .mpu_irqs       = omap2_timer9_mpu_irqs,
 314         .main_clk       = "gpt9_fck",
 315         .prcm           = {
 316                 .omap2 = {
 317                         .prcm_reg_id = 1,
 318                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 319                         .module_offs = OMAP3430_PER_MOD,
 320                         .idlest_reg_id = 1,
 321                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 322                 },
 323         },
 324         .dev_attr       = &capability_pwm_dev_attr,
 325         .class          = &omap3xxx_timer_hwmod_class,
 326 };
 327
 328 /* timer10 */
 329 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 330         .name           = "timer10",
 331         .mpu_irqs       = omap2_timer10_mpu_irqs,
 332         .main_clk       = "gpt10_fck",
 333         .prcm           = {
 334                 .omap2 = {
 335                         .prcm_reg_id = 1,
 336                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 337                         .module_offs = CORE_MOD,
 338                         .idlest_reg_id = 1,
 339                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 340                 },
 341         },
 342         .dev_attr       = &capability_pwm_dev_attr,
 343         .class          = &omap3xxx_timer_1ms_hwmod_class,
 344 };
 345
 346 /* timer11 */
 347 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 348         .name           = "timer11",
 349         .mpu_irqs       = omap2_timer11_mpu_irqs,
 350         .main_clk       = "gpt11_fck",
 351         .prcm           = {
 352                 .omap2 = {
 353                         .prcm_reg_id = 1,
 354                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 355                         .module_offs = CORE_MOD,
 356                         .idlest_reg_id = 1,
 357                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 358                 },
 359         },
 360         .dev_attr       = &capability_pwm_dev_attr,
 361         .class          = &omap3xxx_timer_hwmod_class,
 362 };
 363
 364 /* timer12 */
 365 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 366         { .irq = 95, },
 367         { .irq = -1 }
 368 };
 369
 370 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 371         .name           = "timer12",
 372         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 373         .main_clk       = "gpt12_fck",
 374         .prcm           = {
 375                 .omap2 = {
 376                         .prcm_reg_id = 1,
 377                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 378                         .module_offs = WKUP_MOD,
 379                         .idlest_reg_id = 1,
 380                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 381                 },
 382         },
 383         .dev_attr       = &capability_secure_dev_attr,
 384         .class          = &omap3xxx_timer_hwmod_class,
 385 };
 386
 387 /*
 388  * 'wd_timer' class
 389  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 390  * overflow condition
 391  */
 392
 393 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 394         .rev_offs       = 0x0000,
 395         .sysc_offs      = 0x0010,
 396         .syss_offs      = 0x0014,
 397         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 398                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 399                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 400                            SYSS_HAS_RESET_STATUS),
 401         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 402         .sysc_fields    = &omap_hwmod_sysc_type1,
 403 };
 404
 405 /* I2C common */
 406 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 407         .rev_offs       = 0x00,
 408         .sysc_offs      = 0x20,
 409         .syss_offs      = 0x10,
 410         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 411                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 412                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 413         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 414         .clockact       = CLOCKACT_TEST_ICLK,
 415         .sysc_fields    = &omap_hwmod_sysc_type1,
 416 };
 417
 418 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 419         .name           = "wd_timer",
 420         .sysc           = &omap3xxx_wd_timer_sysc,
 421         .pre_shutdown   = &omap2_wd_timer_disable,
 422         .reset          = &omap2_wd_timer_reset,
 423 };
 424
 425 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 426         .name           = "wd_timer2",
 427         .class          = &omap3xxx_wd_timer_hwmod_class,
 428         .main_clk       = "wdt2_fck",
 429         .prcm           = {
 430                 .omap2 = {
 431                         .prcm_reg_id = 1,
 432                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 433                         .module_offs = WKUP_MOD,
 434                         .idlest_reg_id = 1,
 435                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 436                 },
 437         },
 438         /*
 439          * XXX: Use software supervised mode, HW supervised smartidle seems to
 440          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 441          */
 442         .flags          = HWMOD_SWSUP_SIDLE,
 443 };
 444
 445 /* UART1 */
 446 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 447         .name           = "uart1",
 448         .mpu_irqs       = omap2_uart1_mpu_irqs,
 449         .sdma_reqs      = omap2_uart1_sdma_reqs,
 450         .main_clk       = "uart1_fck",
 451         .prcm           = {
 452                 .omap2 = {
 453                         .module_offs = CORE_MOD,
 454                         .prcm_reg_id = 1,
 455                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 456                         .idlest_reg_id = 1,
 457                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 458                 },
 459         },
 460         .class          = &omap2_uart_class,
 461 };
 462
 463 /* UART2 */
 464 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 465         .name           = "uart2",
 466         .mpu_irqs       = omap2_uart2_mpu_irqs,
 467         .sdma_reqs      = omap2_uart2_sdma_reqs,
 468         .main_clk       = "uart2_fck",
 469         .prcm           = {
 470                 .omap2 = {
 471                         .module_offs = CORE_MOD,
 472                         .prcm_reg_id = 1,
 473                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 474                         .idlest_reg_id = 1,
 475                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 476                 },
 477         },
 478         .class          = &omap2_uart_class,
 479 };
 480
 481 /* UART3 */
 482 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 483         .name           = "uart3",
 484         .mpu_irqs       = omap2_uart3_mpu_irqs,
 485         .sdma_reqs      = omap2_uart3_sdma_reqs,
 486         .main_clk       = "uart3_fck",
 487         .prcm           = {
 488                 .omap2 = {
 489                         .module_offs = OMAP3430_PER_MOD,
 490                         .prcm_reg_id = 1,
 491                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 492                         .idlest_reg_id = 1,
 493                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 494                 },
 495         },
 496         .class          = &omap2_uart_class,
 497 };
 498
 499 /* UART4 */
 500 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 501         { .irq = INT_36XX_UART4_IRQ, },
 502         { .irq = -1 }
 503 };
 504
 505 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 506         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 507         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 508         { .dma_req = -1 }
 509 };
 510
 511 static struct omap_hwmod omap36xx_uart4_hwmod = {
 512         .name           = "uart4",
 513         .mpu_irqs       = uart4_mpu_irqs,
 514         .sdma_reqs      = uart4_sdma_reqs,
 515         .main_clk       = "uart4_fck",
 516         .prcm           = {
 517                 .omap2 = {
 518                         .module_offs = OMAP3430_PER_MOD,
 519                         .prcm_reg_id = 1,
 520                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 521                         .idlest_reg_id = 1,
 522                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 523                 },
 524         },
 525         .class          = &omap2_uart_class,
 526 };
 527
 528 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 529         { .irq = INT_35XX_UART4_IRQ, },
 530 };
 531
 532 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 533         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 534         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 535 };
 536
 537 static struct omap_hwmod am35xx_uart4_hwmod = {
 538         .name           = "uart4",
 539         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 540         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 541         .main_clk       = "uart4_fck",
 542         .prcm           = {
 543                 .omap2 = {
 544                         .module_offs = CORE_MOD,
 545                         .prcm_reg_id = 1,
 546                         .module_bit = OMAP3430_EN_UART4_SHIFT,
 547                         .idlest_reg_id = 1,
 548                         .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
 549                 },
 550         },
 551         .class          = &omap2_uart_class,
 552 };
 553
 554 static struct omap_hwmod_class i2c_class = {
 555         .name   = "i2c",
 556         .sysc   = &i2c_sysc,
 557         .rev    = OMAP_I2C_IP_VERSION_1,
 558         .reset  = &omap_i2c_reset,
 559 };
 560
 561 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 562         { .name = "dispc", .dma_req = 5 },
 563         { .name = "dsi1", .dma_req = 74 },
 564         { .dma_req = -1 }
 565 };
 566
 567 /* dss */
 568 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 569         /*
 570          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 571          * driver does not use these clocks.
 572          */
 573         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 574         { .role = "tv_clk", .clk = "dss_tv_fck" },
 575         /* required only on OMAP3430 */
 576         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 577 };
 578
 579 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 580         .name           = "dss_core",
 581         .class          = &omap2_dss_hwmod_class,
 582         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 583         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 584         .prcm           = {
 585                 .omap2 = {
 586                         .prcm_reg_id = 1,
 587                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 588                         .module_offs = OMAP3430_DSS_MOD,
 589                         .idlest_reg_id = 1,
 590                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 591                 },
 592         },
 593         .opt_clks       = dss_opt_clks,
 594         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 595         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 596 };
 597
 598 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 599         .name           = "dss_core",
 600         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 601         .class          = &omap2_dss_hwmod_class,
 602         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 603         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 604         .prcm           = {
 605                 .omap2 = {
 606                         .prcm_reg_id = 1,
 607                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 608                         .module_offs = OMAP3430_DSS_MOD,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 611                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 612                 },
 613         },
 614         .opt_clks       = dss_opt_clks,
 615         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 616 };
 617
 618 /*
 619  * 'dispc' class
 620  * display controller
 621  */
 622
 623 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 624         .rev_offs       = 0x0000,
 625         .sysc_offs      = 0x0010,
 626         .syss_offs      = 0x0014,
 627         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 628                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 629                            SYSC_HAS_ENAWAKEUP),
 630         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 631                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 632         .sysc_fields    = &omap_hwmod_sysc_type1,
 633 };
 634
 635 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 636         .name   = "dispc",
 637         .sysc   = &omap3_dispc_sysc,
 638 };
 639
 640 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 641         .name           = "dss_dispc",
 642         .class          = &omap3_dispc_hwmod_class,
 643         .mpu_irqs       = omap2_dispc_irqs,
 644         .main_clk       = "dss1_alwon_fck",
 645         .prcm           = {
 646                 .omap2 = {
 647                         .prcm_reg_id = 1,
 648                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 649                         .module_offs = OMAP3430_DSS_MOD,
 650                 },
 651         },
 652         .flags          = HWMOD_NO_IDLEST,
 653         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 654 };
 655
 656 /*
 657  * 'dsi' class
 658  * display serial interface controller
 659  */
 660
 661 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 662         .name = "dsi",
 663 };
 664
 665 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 666         { .irq = 25 },
 667         { .irq = -1 }
 668 };
 669
 670 /* dss_dsi1 */
 671 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 672         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 673 };
 674
 675 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 676         .name           = "dss_dsi1",
 677         .class          = &omap3xxx_dsi_hwmod_class,
 678         .mpu_irqs       = omap3xxx_dsi1_irqs,
 679         .main_clk       = "dss1_alwon_fck",
 680         .prcm           = {
 681                 .omap2 = {
 682                         .prcm_reg_id = 1,
 683                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 684                         .module_offs = OMAP3430_DSS_MOD,
 685                 },
 686         },
 687         .opt_clks       = dss_dsi1_opt_clks,
 688         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 689         .flags          = HWMOD_NO_IDLEST,
 690 };
 691
 692 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 693         { .role = "ick", .clk = "dss_ick" },
 694 };
 695
 696 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 697         .name           = "dss_rfbi",
 698         .class          = &omap2_rfbi_hwmod_class,
 699         .main_clk       = "dss1_alwon_fck",
 700         .prcm           = {
 701                 .omap2 = {
 702                         .prcm_reg_id = 1,
 703                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 704                         .module_offs = OMAP3430_DSS_MOD,
 705                 },
 706         },
 707         .opt_clks       = dss_rfbi_opt_clks,
 708         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 709         .flags          = HWMOD_NO_IDLEST,
 710 };
 711
 712 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 713         /* required only on OMAP3430 */
 714         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 715 };
 716
 717 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 718         .name           = "dss_venc",
 719         .class          = &omap2_venc_hwmod_class,
 720         .main_clk       = "dss_tv_fck",
 721         .prcm           = {
 722                 .omap2 = {
 723                         .prcm_reg_id = 1,
 724                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 725                         .module_offs = OMAP3430_DSS_MOD,
 726                 },
 727         },
 728         .opt_clks       = dss_venc_opt_clks,
 729         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 730         .flags          = HWMOD_NO_IDLEST,
 731 };
 732
 733 /* I2C1 */
 734 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 735         .fifo_depth     = 8, /* bytes */
 736         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 737                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 738                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 739 };
 740
 741 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 742         .name           = "i2c1",
 743         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 744         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 745         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 746         .main_clk       = "i2c1_fck",
 747         .prcm           = {
 748                 .omap2 = {
 749                         .module_offs = CORE_MOD,
 750                         .prcm_reg_id = 1,
 751                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 752                         .idlest_reg_id = 1,
 753                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 754                 },
 755         },
 756         .class          = &i2c_class,
 757         .dev_attr       = &i2c1_dev_attr,
 758 };
 759
 760 /* I2C2 */
 761 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 762         .fifo_depth     = 8, /* bytes */
 763         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 764                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 765                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 766 };
 767
 768 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 769         .name           = "i2c2",
 770         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 771         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 772         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 773         .main_clk       = "i2c2_fck",
 774         .prcm           = {
 775                 .omap2 = {
 776                         .module_offs = CORE_MOD,
 777                         .prcm_reg_id = 1,
 778                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 779                         .idlest_reg_id = 1,
 780                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 781                 },
 782         },
 783         .class          = &i2c_class,
 784         .dev_attr       = &i2c2_dev_attr,
 785 };
 786
 787 /* I2C3 */
 788 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 789         .fifo_depth     = 64, /* bytes */
 790         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 791                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 792                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 793 };
 794
 795 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 796         { .irq = INT_34XX_I2C3_IRQ, },
 797         { .irq = -1 }
 798 };
 799
 800 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 801         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 802         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 803         { .dma_req = -1 }
 804 };
 805
 806 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 807         .name           = "i2c3",
 808         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 809         .mpu_irqs       = i2c3_mpu_irqs,
 810         .sdma_reqs      = i2c3_sdma_reqs,
 811         .main_clk       = "i2c3_fck",
 812         .prcm           = {
 813                 .omap2 = {
 814                         .module_offs = CORE_MOD,
 815                         .prcm_reg_id = 1,
 816                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 817                         .idlest_reg_id = 1,
 818                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 819                 },
 820         },
 821         .class          = &i2c_class,
 822         .dev_attr       = &i2c3_dev_attr,
 823 };
 824
 825 /*
 826  * 'gpio' class
 827  * general purpose io module
 828  */
 829
 830 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 831         .rev_offs       = 0x0000,
 832         .sysc_offs      = 0x0010,
 833         .syss_offs      = 0x0014,
 834         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 835                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 836                            SYSS_HAS_RESET_STATUS),
 837         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 838         .sysc_fields    = &omap_hwmod_sysc_type1,
 839 };
 840
 841 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 842         .name = "gpio",
 843         .sysc = &omap3xxx_gpio_sysc,
 844         .rev = 1,
 845 };
 846
 847 /* gpio_dev_attr */
 848 static struct omap_gpio_dev_attr gpio_dev_attr = {
 849         .bank_width = 32,
 850         .dbck_flag = true,
 851 };
 852
 853 /* gpio1 */
 854 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 855         { .role = "dbclk", .clk = "gpio1_dbck", },
 856 };
 857
 858 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 859         .name           = "gpio1",
 860         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 861         .mpu_irqs       = omap2_gpio1_irqs,
 862         .main_clk       = "gpio1_ick",
 863         .opt_clks       = gpio1_opt_clks,
 864         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 865         .prcm           = {
 866                 .omap2 = {
 867                         .prcm_reg_id = 1,
 868                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 869                         .module_offs = WKUP_MOD,
 870                         .idlest_reg_id = 1,
 871                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 872                 },
 873         },
 874         .class          = &omap3xxx_gpio_hwmod_class,
 875         .dev_attr       = &gpio_dev_attr,
 876 };
 877
 878 /* gpio2 */
 879 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 880         { .role = "dbclk", .clk = "gpio2_dbck", },
 881 };
 882
 883 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 884         .name           = "gpio2",
 885         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 886         .mpu_irqs       = omap2_gpio2_irqs,
 887         .main_clk       = "gpio2_ick",
 888         .opt_clks       = gpio2_opt_clks,
 889         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 890         .prcm           = {
 891                 .omap2 = {
 892                         .prcm_reg_id = 1,
 893                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 894                         .module_offs = OMAP3430_PER_MOD,
 895                         .idlest_reg_id = 1,
 896                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 897                 },
 898         },
 899         .class          = &omap3xxx_gpio_hwmod_class,
 900         .dev_attr       = &gpio_dev_attr,
 901 };
 902
 903 /* gpio3 */
 904 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 905         { .role = "dbclk", .clk = "gpio3_dbck", },
 906 };
 907
 908 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 909         .name           = "gpio3",
 910         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 911         .mpu_irqs       = omap2_gpio3_irqs,
 912         .main_clk       = "gpio3_ick",
 913         .opt_clks       = gpio3_opt_clks,
 914         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 915         .prcm           = {
 916                 .omap2 = {
 917                         .prcm_reg_id = 1,
 918                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 919                         .module_offs = OMAP3430_PER_MOD,
 920                         .idlest_reg_id = 1,
 921                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 922                 },
 923         },
 924         .class          = &omap3xxx_gpio_hwmod_class,
 925         .dev_attr       = &gpio_dev_attr,
 926 };
 927
 928 /* gpio4 */
 929 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 930         { .role = "dbclk", .clk = "gpio4_dbck", },
 931 };
 932
 933 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 934         .name           = "gpio4",
 935         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 936         .mpu_irqs       = omap2_gpio4_irqs,
 937         .main_clk       = "gpio4_ick",
 938         .opt_clks       = gpio4_opt_clks,
 939         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 940         .prcm           = {
 941                 .omap2 = {
 942                         .prcm_reg_id = 1,
 943                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
 944                         .module_offs = OMAP3430_PER_MOD,
 945                         .idlest_reg_id = 1,
 946                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 947                 },
 948         },
 949         .class          = &omap3xxx_gpio_hwmod_class,
 950         .dev_attr       = &gpio_dev_attr,
 951 };
 952
 953 /* gpio5 */
 954 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
 955         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
 956         { .irq = -1 }
 957 };
 958
 959 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 960         { .role = "dbclk", .clk = "gpio5_dbck", },
 961 };
 962
 963 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 964         .name           = "gpio5",
 965         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 966         .mpu_irqs       = omap3xxx_gpio5_irqs,
 967         .main_clk       = "gpio5_ick",
 968         .opt_clks       = gpio5_opt_clks,
 969         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 970         .prcm           = {
 971                 .omap2 = {
 972                         .prcm_reg_id = 1,
 973                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
 974                         .module_offs = OMAP3430_PER_MOD,
 975                         .idlest_reg_id = 1,
 976                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 977                 },
 978         },
 979         .class          = &omap3xxx_gpio_hwmod_class,
 980         .dev_attr       = &gpio_dev_attr,
 981 };
 982
 983 /* gpio6 */
 984 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
 985         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
 986         { .irq = -1 }
 987 };
 988
 989 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 990         { .role = "dbclk", .clk = "gpio6_dbck", },
 991 };
 992
 993 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 994         .name           = "gpio6",
 995         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 996         .mpu_irqs       = omap3xxx_gpio6_irqs,
 997         .main_clk       = "gpio6_ick",
 998         .opt_clks       = gpio6_opt_clks,
 999         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1000         .prcm           = {
1001                 .omap2 = {
1002                         .prcm_reg_id = 1,
1003                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1004                         .module_offs = OMAP3430_PER_MOD,
1005                         .idlest_reg_id = 1,
1006                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1007                 },
1008         },
1009         .class          = &omap3xxx_gpio_hwmod_class,
1010         .dev_attr       = &gpio_dev_attr,
1011 };
1012
1013 /* dma attributes */
1014 static struct omap_dma_dev_attr dma_dev_attr = {
1015         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1016                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1017         .lch_count = 32,
1018 };
1019
1020 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1021         .rev_offs       = 0x0000,
1022         .sysc_offs      = 0x002c,
1023         .syss_offs      = 0x0028,
1024         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1025                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1026                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1027                            SYSS_HAS_RESET_STATUS),
1028         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1029                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1030         .sysc_fields    = &omap_hwmod_sysc_type1,
1031 };
1032
1033 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1034         .name = "dma",
1035         .sysc = &omap3xxx_dma_sysc,
1036 };
1037
1038 /* dma_system */
1039 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1040         .name           = "dma",
1041         .class          = &omap3xxx_dma_hwmod_class,
1042         .mpu_irqs       = omap2_dma_system_irqs,
1043         .main_clk       = "core_l3_ick",
1044         .prcm = {
1045                 .omap2 = {
1046                         .module_offs            = CORE_MOD,
1047                         .prcm_reg_id            = 1,
1048                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1049                         .idlest_reg_id          = 1,
1050                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1051                 },
1052         },
1053         .dev_attr       = &dma_dev_attr,
1054         .flags          = HWMOD_NO_IDLEST,
1055 };
1056
1057 /*
1058  * 'mcbsp' class
1059  * multi channel buffered serial port controller
1060  */
1061
1062 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1063         .sysc_offs      = 0x008c,
1064         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1065                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1067         .sysc_fields    = &omap_hwmod_sysc_type1,
1068         .clockact       = 0x2,
1069 };
1070
1071 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1072         .name = "mcbsp",
1073         .sysc = &omap3xxx_mcbsp_sysc,
1074         .rev  = MCBSP_CONFIG_TYPE3,
1075 };
1076
1077 /* McBSP functional clock mapping */
1078 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1079         { .role = "pad_fck", .clk = "mcbsp_clks" },
1080         { .role = "prcm_fck", .clk = "core_96m_fck" },
1081 };
1082
1083 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1084         { .role = "pad_fck", .clk = "mcbsp_clks" },
1085         { .role = "prcm_fck", .clk = "per_96m_fck" },
1086 };
1087
1088 /* mcbsp1 */
1089 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1090         { .name = "common", .irq = 16 },
1091         { .name = "tx", .irq = 59 },
1092         { .name = "rx", .irq = 60 },
1093         { .irq = -1 }
1094 };
1095
1096 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1097         .name           = "mcbsp1",
1098         .class          = &omap3xxx_mcbsp_hwmod_class,
1099         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1100         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1101         .main_clk       = "mcbsp1_fck",
1102         .prcm           = {
1103                 .omap2 = {
1104                         .prcm_reg_id = 1,
1105                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1106                         .module_offs = CORE_MOD,
1107                         .idlest_reg_id = 1,
1108                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1109                 },
1110         },
1111         .opt_clks       = mcbsp15_opt_clks,
1112         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1113 };
1114
1115 /* mcbsp2 */
1116 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1117         { .name = "common", .irq = 17 },
1118         { .name = "tx", .irq = 62 },
1119         { .name = "rx", .irq = 63 },
1120         { .irq = -1 }
1121 };
1122
1123 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1124         .sidetone       = "mcbsp2_sidetone",
1125 };
1126
1127 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1128         .name           = "mcbsp2",
1129         .class          = &omap3xxx_mcbsp_hwmod_class,
1130         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1131         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1132         .main_clk       = "mcbsp2_fck",
1133         .prcm           = {
1134                 .omap2 = {
1135                         .prcm_reg_id = 1,
1136                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1137                         .module_offs = OMAP3430_PER_MOD,
1138                         .idlest_reg_id = 1,
1139                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1140                 },
1141         },
1142         .opt_clks       = mcbsp234_opt_clks,
1143         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1144         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1145 };
1146
1147 /* mcbsp3 */
1148 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1149         { .name = "common", .irq = 22 },
1150         { .name = "tx", .irq = 89 },
1151         { .name = "rx", .irq = 90 },
1152         { .irq = -1 }
1153 };
1154
1155 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1156         .sidetone       = "mcbsp3_sidetone",
1157 };
1158
1159 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1160         .name           = "mcbsp3",
1161         .class          = &omap3xxx_mcbsp_hwmod_class,
1162         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1163         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1164         .main_clk       = "mcbsp3_fck",
1165         .prcm           = {
1166                 .omap2 = {
1167                         .prcm_reg_id = 1,
1168                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1169                         .module_offs = OMAP3430_PER_MOD,
1170                         .idlest_reg_id = 1,
1171                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1172                 },
1173         },
1174         .opt_clks       = mcbsp234_opt_clks,
1175         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1176         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1177 };
1178
1179 /* mcbsp4 */
1180 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1181         { .name = "common", .irq = 23 },
1182         { .name = "tx", .irq = 54 },
1183         { .name = "rx", .irq = 55 },
1184         { .irq = -1 }
1185 };
1186
1187 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1188         { .name = "rx", .dma_req = 20 },
1189         { .name = "tx", .dma_req = 19 },
1190         { .dma_req = -1 }
1191 };
1192
1193 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1194         .name           = "mcbsp4",
1195         .class          = &omap3xxx_mcbsp_hwmod_class,
1196         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1197         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1198         .main_clk       = "mcbsp4_fck",
1199         .prcm           = {
1200                 .omap2 = {
1201                         .prcm_reg_id = 1,
1202                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1203                         .module_offs = OMAP3430_PER_MOD,
1204                         .idlest_reg_id = 1,
1205                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1206                 },
1207         },
1208         .opt_clks       = mcbsp234_opt_clks,
1209         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1210 };
1211
1212 /* mcbsp5 */
1213 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1214         { .name = "common", .irq = 27 },
1215         { .name = "tx", .irq = 81 },
1216         { .name = "rx", .irq = 82 },
1217         { .irq = -1 }
1218 };
1219
1220 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1221         { .name = "rx", .dma_req = 22 },
1222         { .name = "tx", .dma_req = 21 },
1223         { .dma_req = -1 }
1224 };
1225
1226 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1227         .name           = "mcbsp5",
1228         .class          = &omap3xxx_mcbsp_hwmod_class,
1229         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1230         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1231         .main_clk       = "mcbsp5_fck",
1232         .prcm           = {
1233                 .omap2 = {
1234                         .prcm_reg_id = 1,
1235                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1236                         .module_offs = CORE_MOD,
1237                         .idlest_reg_id = 1,
1238                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1239                 },
1240         },
1241         .opt_clks       = mcbsp15_opt_clks,
1242         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1243 };
1244
1245 /* 'mcbsp sidetone' class */
1246 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1247         .sysc_offs      = 0x0010,
1248         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1249         .sysc_fields    = &omap_hwmod_sysc_type1,
1250 };
1251
1252 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1253         .name = "mcbsp_sidetone",
1254         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1255 };
1256
1257 /* mcbsp2_sidetone */
1258 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1259         { .name = "irq", .irq = 4 },
1260         { .irq = -1 }
1261 };
1262
1263 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1264         .name           = "mcbsp2_sidetone",
1265         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1266         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1267         .main_clk       = "mcbsp2_fck",
1268         .prcm           = {
1269                 .omap2 = {
1270                         .prcm_reg_id = 1,
1271                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1272                         .module_offs = OMAP3430_PER_MOD,
1273                         .idlest_reg_id = 1,
1274                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1275                 },
1276         },
1277 };
1278
1279 /* mcbsp3_sidetone */
1280 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1281         { .name = "irq", .irq = 5 },
1282         { .irq = -1 }
1283 };
1284
1285 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1286         .name           = "mcbsp3_sidetone",
1287         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1288         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1289         .main_clk       = "mcbsp3_fck",
1290         .prcm           = {
1291                 .omap2 = {
1292                         .prcm_reg_id = 1,
1293                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1294                         .module_offs = OMAP3430_PER_MOD,
1295                         .idlest_reg_id = 1,
1296                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1297                 },
1298         },
1299 };
1300
1301 /* SR common */
1302 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1303         .clkact_shift   = 20,
1304 };
1305
1306 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1307         .sysc_offs      = 0x24,
1308         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1309         .clockact       = CLOCKACT_TEST_ICLK,
1310         .sysc_fields    = &omap34xx_sr_sysc_fields,
1311 };
1312
1313 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1314         .name = "smartreflex",
1315         .sysc = &omap34xx_sr_sysc,
1316         .rev  = 1,
1317 };
1318
1319 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1320         .sidle_shift    = 24,
1321         .enwkup_shift   = 26,
1322 };
1323
1324 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1325         .sysc_offs      = 0x38,
1326         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1327         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1328                         SYSC_NO_CACHE),
1329         .sysc_fields    = &omap36xx_sr_sysc_fields,
1330 };
1331
1332 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1333         .name = "smartreflex",
1334         .sysc = &omap36xx_sr_sysc,
1335         .rev  = 2,
1336 };
1337
1338 /* SR1 */
1339 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1340         .sensor_voltdm_name   = "mpu_iva",
1341 };
1342
1343 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1344         { .irq = 18 },
1345         { .irq = -1 }
1346 };
1347
1348 static struct omap_hwmod omap34xx_sr1_hwmod = {
1349         .name           = "sr1",
1350         .class          = &omap34xx_smartreflex_hwmod_class,
1351         .main_clk       = "sr1_fck",
1352         .prcm           = {
1353                 .omap2 = {
1354                         .prcm_reg_id = 1,
1355                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1356                         .module_offs = WKUP_MOD,
1357                         .idlest_reg_id = 1,
1358                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1359                 },
1360         },
1361         .dev_attr       = &sr1_dev_attr,
1362         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1363         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1364 };
1365
1366 static struct omap_hwmod omap36xx_sr1_hwmod = {
1367         .name           = "sr1",
1368         .class          = &omap36xx_smartreflex_hwmod_class,
1369         .main_clk       = "sr1_fck",
1370         .prcm           = {
1371                 .omap2 = {
1372                         .prcm_reg_id = 1,
1373                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1374                         .module_offs = WKUP_MOD,
1375                         .idlest_reg_id = 1,
1376                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1377                 },
1378         },
1379         .dev_attr       = &sr1_dev_attr,
1380         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1381 };
1382
1383 /* SR2 */
1384 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1385         .sensor_voltdm_name     = "core",
1386 };
1387
1388 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1389         { .irq = 19 },
1390         { .irq = -1 }
1391 };
1392
1393 static struct omap_hwmod omap34xx_sr2_hwmod = {
1394         .name           = "sr2",
1395         .class          = &omap34xx_smartreflex_hwmod_class,
1396         .main_clk       = "sr2_fck",
1397         .prcm           = {
1398                 .omap2 = {
1399                         .prcm_reg_id = 1,
1400                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1401                         .module_offs = WKUP_MOD,
1402                         .idlest_reg_id = 1,
1403                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1404                 },
1405         },
1406         .dev_attr       = &sr2_dev_attr,
1407         .mpu_irqs       = omap3_smartreflex_core_irqs,
1408         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1409 };
1410
1411 static struct omap_hwmod omap36xx_sr2_hwmod = {
1412         .name           = "sr2",
1413         .class          = &omap36xx_smartreflex_hwmod_class,
1414         .main_clk       = "sr2_fck",
1415         .prcm           = {
1416                 .omap2 = {
1417                         .prcm_reg_id = 1,
1418                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1419                         .module_offs = WKUP_MOD,
1420                         .idlest_reg_id = 1,
1421                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1422                 },
1423         },
1424         .dev_attr       = &sr2_dev_attr,
1425         .mpu_irqs       = omap3_smartreflex_core_irqs,
1426 };
1427
1428 /*
1429  * 'mailbox' class
1430  * mailbox module allowing communication between the on-chip processors
1431  * using a queued mailbox-interrupt mechanism.
1432  */
1433
1434 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1435         .rev_offs       = 0x000,
1436         .sysc_offs      = 0x010,
1437         .syss_offs      = 0x014,
1438         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1439                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1441         .sysc_fields    = &omap_hwmod_sysc_type1,
1442 };
1443
1444 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1445         .name = "mailbox",
1446         .sysc = &omap3xxx_mailbox_sysc,
1447 };
1448
1449 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1450         { .irq = 26 },
1451         { .irq = -1 }
1452 };
1453
1454 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1455         .name           = "mailbox",
1456         .class          = &omap3xxx_mailbox_hwmod_class,
1457         .mpu_irqs       = omap3xxx_mailbox_irqs,
1458         .main_clk       = "mailboxes_ick",
1459         .prcm           = {
1460                 .omap2 = {
1461                         .prcm_reg_id = 1,
1462                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1463                         .module_offs = CORE_MOD,
1464                         .idlest_reg_id = 1,
1465                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1466                 },
1467         },
1468 };
1469
1470 /*
1471  * 'mcspi' class
1472  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1473  * bus
1474  */
1475
1476 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1477         .rev_offs       = 0x0000,
1478         .sysc_offs      = 0x0010,
1479         .syss_offs      = 0x0014,
1480         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1481                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1482                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1483         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1484         .sysc_fields    = &omap_hwmod_sysc_type1,
1485 };
1486
1487 static struct omap_hwmod_class omap34xx_mcspi_class = {
1488         .name = "mcspi",
1489         .sysc = &omap34xx_mcspi_sysc,
1490         .rev = OMAP3_MCSPI_REV,
1491 };
1492
1493 /* mcspi1 */
1494 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1495         .num_chipselect = 4,
1496 };
1497
1498 static struct omap_hwmod omap34xx_mcspi1 = {
1499         .name           = "mcspi1",
1500         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1501         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1502         .main_clk       = "mcspi1_fck",
1503         .prcm           = {
1504                 .omap2 = {
1505                         .module_offs = CORE_MOD,
1506                         .prcm_reg_id = 1,
1507                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1508                         .idlest_reg_id = 1,
1509                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1510                 },
1511         },
1512         .class          = &omap34xx_mcspi_class,
1513         .dev_attr       = &omap_mcspi1_dev_attr,
1514 };
1515
1516 /* mcspi2 */
1517 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1518         .num_chipselect = 2,
1519 };
1520
1521 static struct omap_hwmod omap34xx_mcspi2 = {
1522         .name           = "mcspi2",
1523         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1524         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1525         .main_clk       = "mcspi2_fck",
1526         .prcm           = {
1527                 .omap2 = {
1528                         .module_offs = CORE_MOD,
1529                         .prcm_reg_id = 1,
1530                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1531                         .idlest_reg_id = 1,
1532                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1533                 },
1534         },
1535         .class          = &omap34xx_mcspi_class,
1536         .dev_attr       = &omap_mcspi2_dev_attr,
1537 };
1538
1539 /* mcspi3 */
1540 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1541         { .name = "irq", .irq = 91 }, /* 91 */
1542         { .irq = -1 }
1543 };
1544
1545 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1546         { .name = "tx0", .dma_req = 15 },
1547         { .name = "rx0", .dma_req = 16 },
1548         { .name = "tx1", .dma_req = 23 },
1549         { .name = "rx1", .dma_req = 24 },
1550         { .dma_req = -1 }
1551 };
1552
1553 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1554         .num_chipselect = 2,
1555 };
1556
1557 static struct omap_hwmod omap34xx_mcspi3 = {
1558         .name           = "mcspi3",
1559         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1560         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1561         .main_clk       = "mcspi3_fck",
1562         .prcm           = {
1563                 .omap2 = {
1564                         .module_offs = CORE_MOD,
1565                         .prcm_reg_id = 1,
1566                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1567                         .idlest_reg_id = 1,
1568                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1569                 },
1570         },
1571         .class          = &omap34xx_mcspi_class,
1572         .dev_attr       = &omap_mcspi3_dev_attr,
1573 };
1574
1575 /* mcspi4 */
1576 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1577         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1578         { .irq = -1 }
1579 };
1580
1581 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1582         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1583         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1584         { .dma_req = -1 }
1585 };
1586
1587 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1588         .num_chipselect = 1,
1589 };
1590
1591 static struct omap_hwmod omap34xx_mcspi4 = {
1592         .name           = "mcspi4",
1593         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1594         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1595         .main_clk       = "mcspi4_fck",
1596         .prcm           = {
1597                 .omap2 = {
1598                         .module_offs = CORE_MOD,
1599                         .prcm_reg_id = 1,
1600                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1601                         .idlest_reg_id = 1,
1602                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1603                 },
1604         },
1605         .class          = &omap34xx_mcspi_class,
1606         .dev_attr       = &omap_mcspi4_dev_attr,
1607 };
1608
1609 /* usbhsotg */
1610 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1611         .rev_offs       = 0x0400,
1612         .sysc_offs      = 0x0404,
1613         .syss_offs      = 0x0408,
1614         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1615                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1616                           SYSC_HAS_AUTOIDLE),
1617         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1618                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1619         .sysc_fields    = &omap_hwmod_sysc_type1,
1620 };
1621
1622 static struct omap_hwmod_class usbotg_class = {
1623         .name = "usbotg",
1624         .sysc = &omap3xxx_usbhsotg_sysc,
1625 };
1626
1627 /* usb_otg_hs */
1628 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1629
1630         { .name = "mc", .irq = 92 },
1631         { .name = "dma", .irq = 93 },
1632         { .irq = -1 }
1633 };
1634
1635 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1636         .name           = "usb_otg_hs",
1637         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1638         .main_clk       = "hsotgusb_ick",
1639         .prcm           = {
1640                 .omap2 = {
1641                         .prcm_reg_id = 1,
1642                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1643                         .module_offs = CORE_MOD,
1644                         .idlest_reg_id = 1,
1645                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1646                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1647                 },
1648         },
1649         .class          = &usbotg_class,
1650
1651         /*
1652          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1653          * broken when autoidle is enabled
1654          * workaround is to disable the autoidle bit at module level.
1655          */
1656         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1657                                 | HWMOD_SWSUP_MSTANDBY,
1658 };
1659
1660 /* usb_otg_hs */
1661 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1662
1663         { .name = "mc", .irq = 71 },
1664         { .irq = -1 }
1665 };
1666
1667 static struct omap_hwmod_class am35xx_usbotg_class = {
1668         .name = "am35xx_usbotg",
1669         .sysc = NULL,
1670 };
1671
1672 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1673         .name           = "am35x_otg_hs",
1674         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1675         .main_clk       = NULL,
1676         .prcm = {
1677                 .omap2 = {
1678                 },
1679         },
1680         .class          = &am35xx_usbotg_class,
1681 };
1682
1683 /* MMC/SD/SDIO common */
1684 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1685         .rev_offs       = 0x1fc,
1686         .sysc_offs      = 0x10,
1687         .syss_offs      = 0x14,
1688         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1689                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1690                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1692         .sysc_fields    = &omap_hwmod_sysc_type1,
1693 };
1694
1695 static struct omap_hwmod_class omap34xx_mmc_class = {
1696         .name = "mmc",
1697         .sysc = &omap34xx_mmc_sysc,
1698 };
1699
1700 /* MMC/SD/SDIO1 */
1701
1702 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1703         { .irq = 83, },
1704         { .irq = -1 }
1705 };
1706
1707 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1708         { .name = "tx", .dma_req = 61, },
1709         { .name = "rx", .dma_req = 62, },
1710         { .dma_req = -1 }
1711 };
1712
1713 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1714         { .role = "dbck", .clk = "omap_32k_fck", },
1715 };
1716
1717 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1718         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1719 };
1720
1721 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1722 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1723         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1724                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1725 };
1726
1727 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1728         .name           = "mmc1",
1729         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1730         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1731         .opt_clks       = omap34xx_mmc1_opt_clks,
1732         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1733         .main_clk       = "mmchs1_fck",
1734         .prcm           = {
1735                 .omap2 = {
1736                         .module_offs = CORE_MOD,
1737                         .prcm_reg_id = 1,
1738                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1739                         .idlest_reg_id = 1,
1740                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1741                 },
1742         },
1743         .dev_attr       = &mmc1_pre_es3_dev_attr,
1744         .class          = &omap34xx_mmc_class,
1745 };
1746
1747 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1748         .name           = "mmc1",
1749         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1750         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1751         .opt_clks       = omap34xx_mmc1_opt_clks,
1752         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1753         .main_clk       = "mmchs1_fck",
1754         .prcm           = {
1755                 .omap2 = {
1756                         .module_offs = CORE_MOD,
1757                         .prcm_reg_id = 1,
1758                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1759                         .idlest_reg_id = 1,
1760                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1761                 },
1762         },
1763         .dev_attr       = &mmc1_dev_attr,
1764         .class          = &omap34xx_mmc_class,
1765 };
1766
1767 /* MMC/SD/SDIO2 */
1768
1769 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1770         { .irq = INT_24XX_MMC2_IRQ, },
1771         { .irq = -1 }
1772 };
1773
1774 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1775         { .name = "tx", .dma_req = 47, },
1776         { .name = "rx", .dma_req = 48, },
1777         { .dma_req = -1 }
1778 };
1779
1780 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1781         { .role = "dbck", .clk = "omap_32k_fck", },
1782 };
1783
1784 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1785 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1786         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1787 };
1788
1789 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1790         .name           = "mmc2",
1791         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1792         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1793         .opt_clks       = omap34xx_mmc2_opt_clks,
1794         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1795         .main_clk       = "mmchs2_fck",
1796         .prcm           = {
1797                 .omap2 = {
1798                         .module_offs = CORE_MOD,
1799                         .prcm_reg_id = 1,
1800                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1801                         .idlest_reg_id = 1,
1802                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1803                 },
1804         },
1805         .dev_attr       = &mmc2_pre_es3_dev_attr,
1806         .class          = &omap34xx_mmc_class,
1807 };
1808
1809 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1810         .name           = "mmc2",
1811         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1812         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1813         .opt_clks       = omap34xx_mmc2_opt_clks,
1814         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1815         .main_clk       = "mmchs2_fck",
1816         .prcm           = {
1817                 .omap2 = {
1818                         .module_offs = CORE_MOD,
1819                         .prcm_reg_id = 1,
1820                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1821                         .idlest_reg_id = 1,
1822                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1823                 },
1824         },
1825         .class          = &omap34xx_mmc_class,
1826 };
1827
1828 /* MMC/SD/SDIO3 */
1829
1830 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1831         { .irq = 94, },
1832         { .irq = -1 }
1833 };
1834
1835 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1836         { .name = "tx", .dma_req = 77, },
1837         { .name = "rx", .dma_req = 78, },
1838         { .dma_req = -1 }
1839 };
1840
1841 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1842         { .role = "dbck", .clk = "omap_32k_fck", },
1843 };
1844
1845 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1846         .name           = "mmc3",
1847         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1848         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1849         .opt_clks       = omap34xx_mmc3_opt_clks,
1850         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1851         .main_clk       = "mmchs3_fck",
1852         .prcm           = {
1853                 .omap2 = {
1854                         .prcm_reg_id = 1,
1855                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1856                         .idlest_reg_id = 1,
1857                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1858                 },
1859         },
1860         .class          = &omap34xx_mmc_class,
1861 };
1862
1863 /*
1864  * 'usb_host_hs' class
1865  * high-speed multi-port usb host controller
1866  */
1867
1868 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1869         .rev_offs       = 0x0000,
1870         .sysc_offs      = 0x0010,
1871         .syss_offs      = 0x0014,
1872         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1873                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1874                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1875         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1876                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1877         .sysc_fields    = &omap_hwmod_sysc_type1,
1878 };
1879
1880 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1881         .name = "usb_host_hs",
1882         .sysc = &omap3xxx_usb_host_hs_sysc,
1883 };
1884
1885 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1886           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1887 };
1888
1889 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1890         { .name = "ohci-irq", .irq = 76 },
1891         { .name = "ehci-irq", .irq = 77 },
1892         { .irq = -1 }
1893 };
1894
1895 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1896         .name           = "usb_host_hs",
1897         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1898         .clkdm_name     = "l3_init_clkdm",
1899         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1900         .main_clk       = "usbhost_48m_fck",
1901         .prcm = {
1902                 .omap2 = {
1903                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1904                         .prcm_reg_id = 1,
1905                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1906                         .idlest_reg_id = 1,
1907                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1908                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1909                 },
1910         },
1911         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1912         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1913
1914         /*
1915          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1916          * id: i660
1917          *
1918          * Description:
1919          * In the following configuration :
1920          * - USBHOST module is set to smart-idle mode
1921          * - PRCM asserts idle_req to the USBHOST module ( This typically
1922          *   happens when the system is going to a low power mode : all ports
1923          *   have been suspended, the master part of the USBHOST module has
1924          *   entered the standby state, and SW has cut the functional clocks)
1925          * - an USBHOST interrupt occurs before the module is able to answer
1926          *   idle_ack, typically a remote wakeup IRQ.
1927          * Then the USB HOST module will enter a deadlock situation where it
1928          * is no more accessible nor functional.
1929          *
1930          * Workaround:
1931          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1932          */
1933
1934         /*
1935          * Errata: USB host EHCI may stall when entering smart-standby mode
1936          * Id: i571
1937          *
1938          * Description:
1939          * When the USBHOST module is set to smart-standby mode, and when it is
1940          * ready to enter the standby state (i.e. all ports are suspended and
1941          * all attached devices are in suspend mode), then it can wrongly assert
1942          * the Mstandby signal too early while there are still some residual OCP
1943          * transactions ongoing. If this condition occurs, the internal state
1944          * machine may go to an undefined state and the USB link may be stuck
1945          * upon the next resume.
1946          *
1947          * Workaround:
1948          * Don't use smart standby; use only force standby,
1949          * hence HWMOD_SWSUP_MSTANDBY
1950          */
1951
1952         /*
1953          * During system boot; If the hwmod framework resets the module
1954          * the module will have smart idle settings; which can lead to deadlock
1955          * (above Errata Id:i660); so, dont reset the module during boot;
1956          * Use HWMOD_INIT_NO_RESET.
1957          */
1958
1959         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1960                           HWMOD_INIT_NO_RESET,
1961 };
1962
1963 /*
1964  * 'usb_tll_hs' class
1965  * usb_tll_hs module is the adapter on the usb_host_hs ports
1966  */
1967 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1968         .rev_offs       = 0x0000,
1969         .sysc_offs      = 0x0010,
1970         .syss_offs      = 0x0014,
1971         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1972                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1973                            SYSC_HAS_AUTOIDLE),
1974         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1975         .sysc_fields    = &omap_hwmod_sysc_type1,
1976 };
1977
1978 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1979         .name = "usb_tll_hs",
1980         .sysc = &omap3xxx_usb_tll_hs_sysc,
1981 };
1982
1983 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1984         { .name = "tll-irq", .irq = 78 },
1985         { .irq = -1 }
1986 };
1987
1988 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1989         .name           = "usb_tll_hs",
1990         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
1991         .clkdm_name     = "l3_init_clkdm",
1992         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
1993         .main_clk       = "usbtll_fck",
1994         .prcm = {
1995                 .omap2 = {
1996                         .module_offs = CORE_MOD,
1997                         .prcm_reg_id = 3,
1998                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1999                         .idlest_reg_id = 3,
2000                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2001                 },
2002         },
2003 };
2004
2005 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2006         .name           = "hdq1w",
2007         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2008         .main_clk       = "hdq_fck",
2009         .prcm           = {
2010                 .omap2 = {
2011                         .module_offs = CORE_MOD,
2012                         .prcm_reg_id = 1,
2013                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2014                         .idlest_reg_id = 1,
2015                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2016                 },
2017         },
2018         .class          = &omap2_hdq1w_class,
2019 };
2020
2021 /*
2022  * '32K sync counter' class
2023  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2024  */
2025 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2026         .rev_offs       = 0x0000,
2027         .sysc_offs      = 0x0004,
2028         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2029         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2030         .sysc_fields    = &omap_hwmod_sysc_type1,
2031 };
2032
2033 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2034         .name   = "counter",
2035         .sysc   = &omap3xxx_counter_sysc,
2036 };
2037
2038 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2039         .name           = "counter_32k",
2040         .class          = &omap3xxx_counter_hwmod_class,
2041         .clkdm_name     = "wkup_clkdm",
2042         .flags          = HWMOD_SWSUP_SIDLE,
2043         .main_clk       = "wkup_32k_fck",
2044         .prcm           = {
2045                 .omap2  = {
2046                         .module_offs = WKUP_MOD,
2047                         .prcm_reg_id = 1,
2048                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2049                         .idlest_reg_id = 1,
2050                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2051                 },
2052         },
2053 };
2054
2055 /*
2056  * interfaces
2057  */
2058
2059 /* L3 -> L4_CORE interface */
2060 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2061         .master = &omap3xxx_l3_main_hwmod,
2062         .slave  = &omap3xxx_l4_core_hwmod,
2063         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2064 };
2065
2066 /* L3 -> L4_PER interface */
2067 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2068         .master = &omap3xxx_l3_main_hwmod,
2069         .slave  = &omap3xxx_l4_per_hwmod,
2070         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2071 };
2072
2073 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2074         {
2075                 .pa_start       = 0x68000000,
2076                 .pa_end         = 0x6800ffff,
2077                 .flags          = ADDR_TYPE_RT,
2078         },
2079         { }
2080 };
2081
2082 /* MPU -> L3 interface */
2083 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2084         .master   = &omap3xxx_mpu_hwmod,
2085         .slave    = &omap3xxx_l3_main_hwmod,
2086         .addr     = omap3xxx_l3_main_addrs,
2087         .user   = OCP_USER_MPU,
2088 };
2089
2090 /* DSS -> l3 */
2091 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2092         .master         = &omap3430es1_dss_core_hwmod,
2093         .slave          = &omap3xxx_l3_main_hwmod,
2094         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2095 };
2096
2097 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2098         .master         = &omap3xxx_dss_core_hwmod,
2099         .slave          = &omap3xxx_l3_main_hwmod,
2100         .fw = {
2101                 .omap2 = {
2102                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2103                         .flags  = OMAP_FIREWALL_L3,
2104                 }
2105         },
2106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2107 };
2108
2109 /* l3_core -> usbhsotg interface */
2110 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2111         .master         = &omap3xxx_usbhsotg_hwmod,
2112         .slave          = &omap3xxx_l3_main_hwmod,
2113         .clk            = "core_l3_ick",
2114         .user           = OCP_USER_MPU,
2115 };
2116
2117 /* l3_core -> am35xx_usbhsotg interface */
2118 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2119         .master         = &am35xx_usbhsotg_hwmod,
2120         .slave          = &omap3xxx_l3_main_hwmod,
2121         .clk            = "core_l3_ick",
2122         .user           = OCP_USER_MPU,
2123 };
2124 /* L4_CORE -> L4_WKUP interface */
2125 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2126         .master = &omap3xxx_l4_core_hwmod,
2127         .slave  = &omap3xxx_l4_wkup_hwmod,
2128         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2129 };
2130
2131 /* L4 CORE -> MMC1 interface */
2132 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2133         .master         = &omap3xxx_l4_core_hwmod,
2134         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2135         .clk            = "mmchs1_ick",
2136         .addr           = omap2430_mmc1_addr_space,
2137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2138         .flags          = OMAP_FIREWALL_L4
2139 };
2140
2141 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2142         .master         = &omap3xxx_l4_core_hwmod,
2143         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2144         .clk            = "mmchs1_ick",
2145         .addr           = omap2430_mmc1_addr_space,
2146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2147         .flags          = OMAP_FIREWALL_L4
2148 };
2149
2150 /* L4 CORE -> MMC2 interface */
2151 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2152         .master         = &omap3xxx_l4_core_hwmod,
2153         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2154         .clk            = "mmchs2_ick",
2155         .addr           = omap2430_mmc2_addr_space,
2156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2157         .flags          = OMAP_FIREWALL_L4
2158 };
2159
2160 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2161         .master         = &omap3xxx_l4_core_hwmod,
2162         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2163         .clk            = "mmchs2_ick",
2164         .addr           = omap2430_mmc2_addr_space,
2165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2166         .flags          = OMAP_FIREWALL_L4
2167 };
2168
2169 /* L4 CORE -> MMC3 interface */
2170 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2171         {
2172                 .pa_start       = 0x480ad000,
2173                 .pa_end         = 0x480ad1ff,
2174                 .flags          = ADDR_TYPE_RT,
2175         },
2176         { }
2177 };
2178
2179 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2180         .master         = &omap3xxx_l4_core_hwmod,
2181         .slave          = &omap3xxx_mmc3_hwmod,
2182         .clk            = "mmchs3_ick",
2183         .addr           = omap3xxx_mmc3_addr_space,
2184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2185         .flags          = OMAP_FIREWALL_L4
2186 };
2187
2188 /* L4 CORE -> UART1 interface */
2189 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2190         {
2191                 .pa_start       = OMAP3_UART1_BASE,
2192                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2193                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2194         },
2195         { }
2196 };
2197
2198 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2199         .master         = &omap3xxx_l4_core_hwmod,
2200         .slave          = &omap3xxx_uart1_hwmod,
2201         .clk            = "uart1_ick",
2202         .addr           = omap3xxx_uart1_addr_space,
2203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2204 };
2205
2206 /* L4 CORE -> UART2 interface */
2207 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2208         {
2209                 .pa_start       = OMAP3_UART2_BASE,
2210                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2211                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2212         },
2213         { }
2214 };
2215
2216 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2217         .master         = &omap3xxx_l4_core_hwmod,
2218         .slave          = &omap3xxx_uart2_hwmod,
2219         .clk            = "uart2_ick",
2220         .addr           = omap3xxx_uart2_addr_space,
2221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2222 };
2223
2224 /* L4 PER -> UART3 interface */
2225 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2226         {
2227                 .pa_start       = OMAP3_UART3_BASE,
2228                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2229                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2230         },
2231         { }
2232 };
2233
2234 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2235         .master         = &omap3xxx_l4_per_hwmod,
2236         .slave          = &omap3xxx_uart3_hwmod,
2237         .clk            = "uart3_ick",
2238         .addr           = omap3xxx_uart3_addr_space,
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* L4 PER -> UART4 interface */
2243 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2244         {
2245                 .pa_start       = OMAP3_UART4_BASE,
2246                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2247                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2248         },
2249         { }
2250 };
2251
2252 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2253         .master         = &omap3xxx_l4_per_hwmod,
2254         .slave          = &omap36xx_uart4_hwmod,
2255         .clk            = "uart4_ick",
2256         .addr           = omap36xx_uart4_addr_space,
2257         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2258 };
2259
2260 /* AM35xx: L4 CORE -> UART4 interface */
2261 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2262         {
2263                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2264                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2265                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2266         },
2267 };
2268
2269 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2270         .master         = &omap3xxx_l4_core_hwmod,
2271         .slave          = &am35xx_uart4_hwmod,
2272         .clk            = "uart4_ick",
2273         .addr           = am35xx_uart4_addr_space,
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276
2277 /* L4 CORE -> I2C1 interface */
2278 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2279         .master         = &omap3xxx_l4_core_hwmod,
2280         .slave          = &omap3xxx_i2c1_hwmod,
2281         .clk            = "i2c1_ick",
2282         .addr           = omap2_i2c1_addr_space,
2283         .fw = {
2284                 .omap2 = {
2285                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2286                         .l4_prot_group = 7,
2287                         .flags  = OMAP_FIREWALL_L4,
2288                 }
2289         },
2290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2291 };
2292
2293 /* L4 CORE -> I2C2 interface */
2294 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2295         .master         = &omap3xxx_l4_core_hwmod,
2296         .slave          = &omap3xxx_i2c2_hwmod,
2297         .clk            = "i2c2_ick",
2298         .addr           = omap2_i2c2_addr_space,
2299         .fw = {
2300                 .omap2 = {
2301                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2302                         .l4_prot_group = 7,
2303                         .flags = OMAP_FIREWALL_L4,
2304                 }
2305         },
2306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 /* L4 CORE -> I2C3 interface */
2310 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2311         {
2312                 .pa_start       = 0x48060000,
2313                 .pa_end         = 0x48060000 + SZ_128 - 1,
2314                 .flags          = ADDR_TYPE_RT,
2315         },
2316         { }
2317 };
2318
2319 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2320         .master         = &omap3xxx_l4_core_hwmod,
2321         .slave          = &omap3xxx_i2c3_hwmod,
2322         .clk            = "i2c3_ick",
2323         .addr           = omap3xxx_i2c3_addr_space,
2324         .fw = {
2325                 .omap2 = {
2326                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2327                         .l4_prot_group = 7,
2328                         .flags = OMAP_FIREWALL_L4,
2329                 }
2330         },
2331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2332 };
2333
2334 /* L4 CORE -> SR1 interface */
2335 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2336         {
2337                 .pa_start       = OMAP34XX_SR1_BASE,
2338                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2339                 .flags          = ADDR_TYPE_RT,
2340         },
2341         { }
2342 };
2343
2344 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2345         .master         = &omap3xxx_l4_core_hwmod,
2346         .slave          = &omap34xx_sr1_hwmod,
2347         .clk            = "sr_l4_ick",
2348         .addr           = omap3_sr1_addr_space,
2349         .user           = OCP_USER_MPU,
2350 };
2351
2352 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2353         .master         = &omap3xxx_l4_core_hwmod,
2354         .slave          = &omap36xx_sr1_hwmod,
2355         .clk            = "sr_l4_ick",
2356         .addr           = omap3_sr1_addr_space,
2357         .user           = OCP_USER_MPU,
2358 };
2359
2360 /* L4 CORE -> SR1 interface */
2361 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2362         {
2363                 .pa_start       = OMAP34XX_SR2_BASE,
2364                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2365                 .flags          = ADDR_TYPE_RT,
2366         },
2367         { }
2368 };
2369
2370 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2371         .master         = &omap3xxx_l4_core_hwmod,
2372         .slave          = &omap34xx_sr2_hwmod,
2373         .clk            = "sr_l4_ick",
2374         .addr           = omap3_sr2_addr_space,
2375         .user           = OCP_USER_MPU,
2376 };
2377
2378 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2379         .master         = &omap3xxx_l4_core_hwmod,
2380         .slave          = &omap36xx_sr2_hwmod,
2381         .clk            = "sr_l4_ick",
2382         .addr           = omap3_sr2_addr_space,
2383         .user           = OCP_USER_MPU,
2384 };
2385
2386 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2387         {
2388                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2389                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2390                 .flags          = ADDR_TYPE_RT
2391         },
2392         { }
2393 };
2394
2395 /* l4_core -> usbhsotg  */
2396 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2397         .master         = &omap3xxx_l4_core_hwmod,
2398         .slave          = &omap3xxx_usbhsotg_hwmod,
2399         .clk            = "l4_ick",
2400         .addr           = omap3xxx_usbhsotg_addrs,
2401         .user           = OCP_USER_MPU,
2402 };
2403
2404 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2405         {
2406                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2407                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2408                 .flags          = ADDR_TYPE_RT
2409         },
2410         { }
2411 };
2412
2413 /* l4_core -> usbhsotg  */
2414 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2415         .master         = &omap3xxx_l4_core_hwmod,
2416         .slave          = &am35xx_usbhsotg_hwmod,
2417         .clk            = "l4_ick",
2418         .addr           = am35xx_usbhsotg_addrs,
2419         .user           = OCP_USER_MPU,
2420 };
2421
2422 /* L4_WKUP -> L4_SEC interface */
2423 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2424         .master = &omap3xxx_l4_wkup_hwmod,
2425         .slave  = &omap3xxx_l4_sec_hwmod,
2426         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428
2429 /* IVA2 <- L3 interface */
2430 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2431         .master         = &omap3xxx_l3_main_hwmod,
2432         .slave          = &omap3xxx_iva_hwmod,
2433         .clk            = "core_l3_ick",
2434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436
2437 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2438         {
2439                 .pa_start       = 0x48318000,
2440                 .pa_end         = 0x48318000 + SZ_1K - 1,
2441                 .flags          = ADDR_TYPE_RT
2442         },
2443         { }
2444 };
2445
2446 /* l4_wkup -> timer1 */
2447 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2448         .master         = &omap3xxx_l4_wkup_hwmod,
2449         .slave          = &omap3xxx_timer1_hwmod,
2450         .clk            = "gpt1_ick",
2451         .addr           = omap3xxx_timer1_addrs,
2452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2453 };
2454
2455 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2456         {
2457                 .pa_start       = 0x49032000,
2458                 .pa_end         = 0x49032000 + SZ_1K - 1,
2459                 .flags          = ADDR_TYPE_RT
2460         },
2461         { }
2462 };
2463
2464 /* l4_per -> timer2 */
2465 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2466         .master         = &omap3xxx_l4_per_hwmod,
2467         .slave          = &omap3xxx_timer2_hwmod,
2468         .clk            = "gpt2_ick",
2469         .addr           = omap3xxx_timer2_addrs,
2470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2471 };
2472
2473 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2474         {
2475                 .pa_start       = 0x49034000,
2476                 .pa_end         = 0x49034000 + SZ_1K - 1,
2477                 .flags          = ADDR_TYPE_RT
2478         },
2479         { }
2480 };
2481
2482 /* l4_per -> timer3 */
2483 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2484         .master         = &omap3xxx_l4_per_hwmod,
2485         .slave          = &omap3xxx_timer3_hwmod,
2486         .clk            = "gpt3_ick",
2487         .addr           = omap3xxx_timer3_addrs,
2488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2489 };
2490
2491 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2492         {
2493                 .pa_start       = 0x49036000,
2494                 .pa_end         = 0x49036000 + SZ_1K - 1,
2495                 .flags          = ADDR_TYPE_RT
2496         },
2497         { }
2498 };
2499
2500 /* l4_per -> timer4 */
2501 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2502         .master         = &omap3xxx_l4_per_hwmod,
2503         .slave          = &omap3xxx_timer4_hwmod,
2504         .clk            = "gpt4_ick",
2505         .addr           = omap3xxx_timer4_addrs,
2506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2507 };
2508
2509 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2510         {
2511                 .pa_start       = 0x49038000,
2512                 .pa_end         = 0x49038000 + SZ_1K - 1,
2513                 .flags          = ADDR_TYPE_RT
2514         },
2515         { }
2516 };
2517
2518 /* l4_per -> timer5 */
2519 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2520         .master         = &omap3xxx_l4_per_hwmod,
2521         .slave          = &omap3xxx_timer5_hwmod,
2522         .clk            = "gpt5_ick",
2523         .addr           = omap3xxx_timer5_addrs,
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2528         {
2529                 .pa_start       = 0x4903A000,
2530                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2531                 .flags          = ADDR_TYPE_RT
2532         },
2533         { }
2534 };
2535
2536 /* l4_per -> timer6 */
2537 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2538         .master         = &omap3xxx_l4_per_hwmod,
2539         .slave          = &omap3xxx_timer6_hwmod,
2540         .clk            = "gpt6_ick",
2541         .addr           = omap3xxx_timer6_addrs,
2542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2543 };
2544
2545 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2546         {
2547                 .pa_start       = 0x4903C000,
2548                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2549                 .flags          = ADDR_TYPE_RT
2550         },
2551         { }
2552 };
2553
2554 /* l4_per -> timer7 */
2555 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2556         .master         = &omap3xxx_l4_per_hwmod,
2557         .slave          = &omap3xxx_timer7_hwmod,
2558         .clk            = "gpt7_ick",
2559         .addr           = omap3xxx_timer7_addrs,
2560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2561 };
2562
2563 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2564         {
2565                 .pa_start       = 0x4903E000,
2566                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2567                 .flags          = ADDR_TYPE_RT
2568         },
2569         { }
2570 };
2571
2572 /* l4_per -> timer8 */
2573 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2574         .master         = &omap3xxx_l4_per_hwmod,
2575         .slave          = &omap3xxx_timer8_hwmod,
2576         .clk            = "gpt8_ick",
2577         .addr           = omap3xxx_timer8_addrs,
2578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2582         {
2583                 .pa_start       = 0x49040000,
2584                 .pa_end         = 0x49040000 + SZ_1K - 1,
2585                 .flags          = ADDR_TYPE_RT
2586         },
2587         { }
2588 };
2589
2590 /* l4_per -> timer9 */
2591 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2592         .master         = &omap3xxx_l4_per_hwmod,
2593         .slave          = &omap3xxx_timer9_hwmod,
2594         .clk            = "gpt9_ick",
2595         .addr           = omap3xxx_timer9_addrs,
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 /* l4_core -> timer10 */
2600 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2601         .master         = &omap3xxx_l4_core_hwmod,
2602         .slave          = &omap3xxx_timer10_hwmod,
2603         .clk            = "gpt10_ick",
2604         .addr           = omap2_timer10_addrs,
2605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2607
2608 /* l4_core -> timer11 */
2609 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2610         .master         = &omap3xxx_l4_core_hwmod,
2611         .slave          = &omap3xxx_timer11_hwmod,
2612         .clk            = "gpt11_ick",
2613         .addr           = omap2_timer11_addrs,
2614         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2615 };
2616
2617 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2618         {
2619                 .pa_start       = 0x48304000,
2620                 .pa_end         = 0x48304000 + SZ_1K - 1,
2621                 .flags          = ADDR_TYPE_RT
2622         },
2623         { }
2624 };
2625
2626 /* l4_core -> timer12 */
2627 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2628         .master         = &omap3xxx_l4_sec_hwmod,
2629         .slave          = &omap3xxx_timer12_hwmod,
2630         .clk            = "gpt12_ick",
2631         .addr           = omap3xxx_timer12_addrs,
2632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2633 };
2634
2635 /* l4_wkup -> wd_timer2 */
2636 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2637         {
2638                 .pa_start       = 0x48314000,
2639                 .pa_end         = 0x4831407f,
2640                 .flags          = ADDR_TYPE_RT
2641         },
2642         { }
2643 };
2644
2645 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2646         .master         = &omap3xxx_l4_wkup_hwmod,
2647         .slave          = &omap3xxx_wd_timer2_hwmod,
2648         .clk            = "wdt2_ick",
2649         .addr           = omap3xxx_wd_timer2_addrs,
2650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2651 };
2652
2653 /* l4_core -> dss */
2654 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2655         .master         = &omap3xxx_l4_core_hwmod,
2656         .slave          = &omap3430es1_dss_core_hwmod,
2657         .clk            = "dss_ick",
2658         .addr           = omap2_dss_addrs,
2659         .fw = {
2660                 .omap2 = {
2661                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2662                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2663                         .flags  = OMAP_FIREWALL_L4,
2664                 }
2665         },
2666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2670         .master         = &omap3xxx_l4_core_hwmod,
2671         .slave          = &omap3xxx_dss_core_hwmod,
2672         .clk            = "dss_ick",
2673         .addr           = omap2_dss_addrs,
2674         .fw = {
2675                 .omap2 = {
2676                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2677                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2678                         .flags  = OMAP_FIREWALL_L4,
2679                 }
2680         },
2681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2682 };
2683
2684 /* l4_core -> dss_dispc */
2685 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2686         .master         = &omap3xxx_l4_core_hwmod,
2687         .slave          = &omap3xxx_dss_dispc_hwmod,
2688         .clk            = "dss_ick",
2689         .addr           = omap2_dss_dispc_addrs,
2690         .fw = {
2691                 .omap2 = {
2692                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2693                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2694                         .flags  = OMAP_FIREWALL_L4,
2695                 }
2696         },
2697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2698 };
2699
2700 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2701         {
2702                 .pa_start       = 0x4804FC00,
2703                 .pa_end         = 0x4804FFFF,
2704                 .flags          = ADDR_TYPE_RT
2705         },
2706         { }
2707 };
2708
2709 /* l4_core -> dss_dsi1 */
2710 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2711         .master         = &omap3xxx_l4_core_hwmod,
2712         .slave          = &omap3xxx_dss_dsi1_hwmod,
2713         .clk            = "dss_ick",
2714         .addr           = omap3xxx_dss_dsi1_addrs,
2715         .fw = {
2716                 .omap2 = {
2717                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2718                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2719                         .flags  = OMAP_FIREWALL_L4,
2720                 }
2721         },
2722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2723 };
2724
2725 /* l4_core -> dss_rfbi */
2726 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2727         .master         = &omap3xxx_l4_core_hwmod,
2728         .slave          = &omap3xxx_dss_rfbi_hwmod,
2729         .clk            = "dss_ick",
2730         .addr           = omap2_dss_rfbi_addrs,
2731         .fw = {
2732                 .omap2 = {
2733                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2734                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2735                         .flags  = OMAP_FIREWALL_L4,
2736                 }
2737         },
2738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2739 };
2740
2741 /* l4_core -> dss_venc */
2742 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2743         .master         = &omap3xxx_l4_core_hwmod,
2744         .slave          = &omap3xxx_dss_venc_hwmod,
2745         .clk            = "dss_ick",
2746         .addr           = omap2_dss_venc_addrs,
2747         .fw = {
2748                 .omap2 = {
2749                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2750                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2751                         .flags  = OMAP_FIREWALL_L4,
2752                 }
2753         },
2754         .flags          = OCPIF_SWSUP_IDLE,
2755         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2756 };
2757
2758 /* l4_wkup -> gpio1 */
2759 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2760         {
2761                 .pa_start       = 0x48310000,
2762                 .pa_end         = 0x483101ff,
2763                 .flags          = ADDR_TYPE_RT
2764         },
2765         { }
2766 };
2767
2768 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2769         .master         = &omap3xxx_l4_wkup_hwmod,
2770         .slave          = &omap3xxx_gpio1_hwmod,
2771         .addr           = omap3xxx_gpio1_addrs,
2772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2773 };
2774
2775 /* l4_per -> gpio2 */
2776 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2777         {
2778                 .pa_start       = 0x49050000,
2779                 .pa_end         = 0x490501ff,
2780                 .flags          = ADDR_TYPE_RT
2781         },
2782         { }
2783 };
2784
2785 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2786         .master         = &omap3xxx_l4_per_hwmod,
2787         .slave          = &omap3xxx_gpio2_hwmod,
2788         .addr           = omap3xxx_gpio2_addrs,
2789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2790 };
2791
2792 /* l4_per -> gpio3 */
2793 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2794         {
2795                 .pa_start       = 0x49052000,
2796                 .pa_end         = 0x490521ff,
2797                 .flags          = ADDR_TYPE_RT
2798         },
2799         { }
2800 };
2801
2802 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2803         .master         = &omap3xxx_l4_per_hwmod,
2804         .slave          = &omap3xxx_gpio3_hwmod,
2805         .addr           = omap3xxx_gpio3_addrs,
2806         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2807 };
2808
2809 /* l4_per -> gpio4 */
2810 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2811         {
2812                 .pa_start       = 0x49054000,
2813                 .pa_end         = 0x490541ff,
2814                 .flags          = ADDR_TYPE_RT
2815         },
2816         { }
2817 };
2818
2819 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2820         .master         = &omap3xxx_l4_per_hwmod,
2821         .slave          = &omap3xxx_gpio4_hwmod,
2822         .addr           = omap3xxx_gpio4_addrs,
2823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2824 };
2825
2826 /* l4_per -> gpio5 */
2827 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2828         {
2829                 .pa_start       = 0x49056000,
2830                 .pa_end         = 0x490561ff,
2831                 .flags          = ADDR_TYPE_RT
2832         },
2833         { }
2834 };
2835
2836 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2837         .master         = &omap3xxx_l4_per_hwmod,
2838         .slave          = &omap3xxx_gpio5_hwmod,
2839         .addr           = omap3xxx_gpio5_addrs,
2840         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2841 };
2842
2843 /* l4_per -> gpio6 */
2844 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2845         {
2846                 .pa_start       = 0x49058000,
2847                 .pa_end         = 0x490581ff,
2848                 .flags          = ADDR_TYPE_RT
2849         },
2850         { }
2851 };
2852
2853 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2854         .master         = &omap3xxx_l4_per_hwmod,
2855         .slave          = &omap3xxx_gpio6_hwmod,
2856         .addr           = omap3xxx_gpio6_addrs,
2857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2858 };
2859
2860 /* dma_system -> L3 */
2861 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2862         .master         = &omap3xxx_dma_system_hwmod,
2863         .slave          = &omap3xxx_l3_main_hwmod,
2864         .clk            = "core_l3_ick",
2865         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2866 };
2867
2868 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2869         {
2870                 .pa_start       = 0x48056000,
2871                 .pa_end         = 0x48056fff,
2872                 .flags          = ADDR_TYPE_RT
2873         },
2874         { }
2875 };
2876
2877 /* l4_cfg -> dma_system */
2878 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2879         .master         = &omap3xxx_l4_core_hwmod,
2880         .slave          = &omap3xxx_dma_system_hwmod,
2881         .clk            = "core_l4_ick",
2882         .addr           = omap3xxx_dma_system_addrs,
2883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2884 };
2885
2886 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2887         {
2888                 .name           = "mpu",
2889                 .pa_start       = 0x48074000,
2890                 .pa_end         = 0x480740ff,
2891                 .flags          = ADDR_TYPE_RT
2892         },
2893         { }
2894 };
2895
2896 /* l4_core -> mcbsp1 */
2897 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2898         .master         = &omap3xxx_l4_core_hwmod,
2899         .slave          = &omap3xxx_mcbsp1_hwmod,
2900         .clk            = "mcbsp1_ick",
2901         .addr           = omap3xxx_mcbsp1_addrs,
2902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2903 };
2904
2905 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2906         {
2907                 .name           = "mpu",
2908                 .pa_start       = 0x49022000,
2909                 .pa_end         = 0x490220ff,
2910                 .flags          = ADDR_TYPE_RT
2911         },
2912         { }
2913 };
2914
2915 /* l4_per -> mcbsp2 */
2916 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2917         .master         = &omap3xxx_l4_per_hwmod,
2918         .slave          = &omap3xxx_mcbsp2_hwmod,
2919         .clk            = "mcbsp2_ick",
2920         .addr           = omap3xxx_mcbsp2_addrs,
2921         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2922 };
2923
2924 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2925         {
2926                 .name           = "mpu",
2927                 .pa_start       = 0x49024000,
2928                 .pa_end         = 0x490240ff,
2929                 .flags          = ADDR_TYPE_RT
2930         },
2931         { }
2932 };
2933
2934 /* l4_per -> mcbsp3 */
2935 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2936         .master         = &omap3xxx_l4_per_hwmod,
2937         .slave          = &omap3xxx_mcbsp3_hwmod,
2938         .clk            = "mcbsp3_ick",
2939         .addr           = omap3xxx_mcbsp3_addrs,
2940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2941 };
2942
2943 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2944         {
2945                 .name           = "mpu",
2946                 .pa_start       = 0x49026000,
2947                 .pa_end         = 0x490260ff,
2948                 .flags          = ADDR_TYPE_RT
2949         },
2950         { }
2951 };
2952
2953 /* l4_per -> mcbsp4 */
2954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2955         .master         = &omap3xxx_l4_per_hwmod,
2956         .slave          = &omap3xxx_mcbsp4_hwmod,
2957         .clk            = "mcbsp4_ick",
2958         .addr           = omap3xxx_mcbsp4_addrs,
2959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2960 };
2961
2962 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2963         {
2964                 .name           = "mpu",
2965                 .pa_start       = 0x48096000,
2966                 .pa_end         = 0x480960ff,
2967                 .flags          = ADDR_TYPE_RT
2968         },
2969         { }
2970 };
2971
2972 /* l4_core -> mcbsp5 */
2973 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2974         .master         = &omap3xxx_l4_core_hwmod,
2975         .slave          = &omap3xxx_mcbsp5_hwmod,
2976         .clk            = "mcbsp5_ick",
2977         .addr           = omap3xxx_mcbsp5_addrs,
2978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2979 };
2980
2981 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2982         {
2983                 .name           = "sidetone",
2984                 .pa_start       = 0x49028000,
2985                 .pa_end         = 0x490280ff,
2986                 .flags          = ADDR_TYPE_RT
2987         },
2988         { }
2989 };
2990
2991 /* l4_per -> mcbsp2_sidetone */
2992 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2993         .master         = &omap3xxx_l4_per_hwmod,
2994         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2995         .clk            = "mcbsp2_ick",
2996         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2997         .user           = OCP_USER_MPU,
2998 };
2999
3000 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3001         {
3002                 .name           = "sidetone",
3003                 .pa_start       = 0x4902A000,
3004                 .pa_end         = 0x4902A0ff,
3005                 .flags          = ADDR_TYPE_RT
3006         },
3007         { }
3008 };
3009
3010 /* l4_per -> mcbsp3_sidetone */
3011 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3012         .master         = &omap3xxx_l4_per_hwmod,
3013         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3014         .clk            = "mcbsp3_ick",
3015         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3016         .user           = OCP_USER_MPU,
3017 };
3018
3019 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3020         {
3021                 .pa_start       = 0x48094000,
3022                 .pa_end         = 0x480941ff,
3023                 .flags          = ADDR_TYPE_RT,
3024         },
3025         { }
3026 };
3027
3028 /* l4_core -> mailbox */
3029 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3030         .master         = &omap3xxx_l4_core_hwmod,
3031         .slave          = &omap3xxx_mailbox_hwmod,
3032         .addr           = omap3xxx_mailbox_addrs,
3033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3034 };
3035
3036 /* l4 core -> mcspi1 interface */
3037 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3038         .master         = &omap3xxx_l4_core_hwmod,
3039         .slave          = &omap34xx_mcspi1,
3040         .clk            = "mcspi1_ick",
3041         .addr           = omap2_mcspi1_addr_space,
3042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3043 };
3044
3045 /* l4 core -> mcspi2 interface */
3046 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3047         .master         = &omap3xxx_l4_core_hwmod,
3048         .slave          = &omap34xx_mcspi2,
3049         .clk            = "mcspi2_ick",
3050         .addr           = omap2_mcspi2_addr_space,
3051         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3052 };
3053
3054 /* l4 core -> mcspi3 interface */
3055 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3056         .master         = &omap3xxx_l4_core_hwmod,
3057         .slave          = &omap34xx_mcspi3,
3058         .clk            = "mcspi3_ick",
3059         .addr           = omap2430_mcspi3_addr_space,
3060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3061 };
3062
3063 /* l4 core -> mcspi4 interface */
3064 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3065         {
3066                 .pa_start       = 0x480ba000,
3067                 .pa_end         = 0x480ba0ff,
3068                 .flags          = ADDR_TYPE_RT,
3069         },
3070         { }
3071 };
3072
3073 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3074         .master         = &omap3xxx_l4_core_hwmod,
3075         .slave          = &omap34xx_mcspi4,
3076         .clk            = "mcspi4_ick",
3077         .addr           = omap34xx_mcspi4_addr_space,
3078         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3079 };
3080
3081 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3082         .master         = &omap3xxx_usb_host_hs_hwmod,
3083         .slave          = &omap3xxx_l3_main_hwmod,
3084         .clk            = "core_l3_ick",
3085         .user           = OCP_USER_MPU,
3086 };
3087
3088 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3089         {
3090                 .name           = "uhh",
3091                 .pa_start       = 0x48064000,
3092                 .pa_end         = 0x480643ff,
3093                 .flags          = ADDR_TYPE_RT
3094         },
3095         {
3096                 .name           = "ohci",
3097                 .pa_start       = 0x48064400,
3098                 .pa_end         = 0x480647ff,
3099         },
3100         {
3101                 .name           = "ehci",
3102                 .pa_start       = 0x48064800,
3103                 .pa_end         = 0x48064cff,
3104         },
3105         {}
3106 };
3107
3108 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3109         .master         = &omap3xxx_l4_core_hwmod,
3110         .slave          = &omap3xxx_usb_host_hs_hwmod,
3111         .clk            = "usbhost_ick",
3112         .addr           = omap3xxx_usb_host_hs_addrs,
3113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3114 };
3115
3116 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3117         {
3118                 .name           = "tll",
3119                 .pa_start       = 0x48062000,
3120                 .pa_end         = 0x48062fff,
3121                 .flags          = ADDR_TYPE_RT
3122         },
3123         {}
3124 };
3125
3126 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3127         .master         = &omap3xxx_l4_core_hwmod,
3128         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3129         .clk            = "usbtll_ick",
3130         .addr           = omap3xxx_usb_tll_hs_addrs,
3131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3132 };
3133
3134 /* l4_core -> hdq1w interface */
3135 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3136         .master         = &omap3xxx_l4_core_hwmod,
3137         .slave          = &omap3xxx_hdq1w_hwmod,
3138         .clk            = "hdq_ick",
3139         .addr           = omap2_hdq1w_addr_space,
3140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3141         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3142 };
3143
3144 /* l4_wkup -> 32ksync_counter */
3145 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3146         {
3147                 .pa_start       = 0x48320000,
3148                 .pa_end         = 0x4832001f,
3149                 .flags          = ADDR_TYPE_RT
3150         },
3151         { }
3152 };
3153
3154 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3155         .master         = &omap3xxx_l4_wkup_hwmod,
3156         .slave          = &omap3xxx_counter_32k_hwmod,
3157         .clk            = "omap_32ksync_ick",
3158         .addr           = omap3xxx_counter_32k_addrs,
3159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3160 };
3161
3162 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3163         &omap3xxx_l3_main__l4_core,
3164         &omap3xxx_l3_main__l4_per,
3165         &omap3xxx_mpu__l3_main,
3166         &omap3xxx_l4_core__l4_wkup,
3167         &omap3xxx_l4_core__mmc3,
3168         &omap3_l4_core__uart1,
3169         &omap3_l4_core__uart2,
3170         &omap3_l4_per__uart3,
3171         &omap3_l4_core__i2c1,
3172         &omap3_l4_core__i2c2,
3173         &omap3_l4_core__i2c3,
3174         &omap3xxx_l4_wkup__l4_sec,
3175         &omap3xxx_l4_wkup__timer1,
3176         &omap3xxx_l4_per__timer2,
3177         &omap3xxx_l4_per__timer3,
3178         &omap3xxx_l4_per__timer4,
3179         &omap3xxx_l4_per__timer5,
3180         &omap3xxx_l4_per__timer6,
3181         &omap3xxx_l4_per__timer7,
3182         &omap3xxx_l4_per__timer8,
3183         &omap3xxx_l4_per__timer9,
3184         &omap3xxx_l4_core__timer10,
3185         &omap3xxx_l4_core__timer11,
3186         &omap3xxx_l4_wkup__wd_timer2,
3187         &omap3xxx_l4_wkup__gpio1,
3188         &omap3xxx_l4_per__gpio2,
3189         &omap3xxx_l4_per__gpio3,
3190         &omap3xxx_l4_per__gpio4,
3191         &omap3xxx_l4_per__gpio5,
3192         &omap3xxx_l4_per__gpio6,
3193         &omap3xxx_dma_system__l3,
3194         &omap3xxx_l4_core__dma_system,
3195         &omap3xxx_l4_core__mcbsp1,
3196         &omap3xxx_l4_per__mcbsp2,
3197         &omap3xxx_l4_per__mcbsp3,
3198         &omap3xxx_l4_per__mcbsp4,
3199         &omap3xxx_l4_core__mcbsp5,
3200         &omap3xxx_l4_per__mcbsp2_sidetone,
3201         &omap3xxx_l4_per__mcbsp3_sidetone,
3202         &omap34xx_l4_core__mcspi1,
3203         &omap34xx_l4_core__mcspi2,
3204         &omap34xx_l4_core__mcspi3,
3205         &omap34xx_l4_core__mcspi4,
3206         &omap3xxx_l4_wkup__counter_32k,
3207         NULL,
3208 };
3209
3210 /* GP-only hwmod links */
3211 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3212         &omap3xxx_l4_sec__timer12,
3213         NULL
3214 };
3215
3216 /* 3430ES1-only hwmod links */
3217 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3218         &omap3430es1_dss__l3,
3219         &omap3430es1_l4_core__dss,
3220         NULL
3221 };
3222
3223 /* 3430ES2+-only hwmod links */
3224 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3225         &omap3xxx_dss__l3,
3226         &omap3xxx_l4_core__dss,
3227         &omap3xxx_usbhsotg__l3,
3228         &omap3xxx_l4_core__usbhsotg,
3229         &omap3xxx_usb_host_hs__l3_main_2,
3230         &omap3xxx_l4_core__usb_host_hs,
3231         &omap3xxx_l4_core__usb_tll_hs,
3232         NULL
3233 };
3234
3235 /* <= 3430ES3-only hwmod links */
3236 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3237         &omap3xxx_l4_core__pre_es3_mmc1,
3238         &omap3xxx_l4_core__pre_es3_mmc2,
3239         NULL
3240 };
3241
3242 /* 3430ES3+-only hwmod links */
3243 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3244         &omap3xxx_l4_core__es3plus_mmc1,
3245         &omap3xxx_l4_core__es3plus_mmc2,
3246         NULL
3247 };
3248
3249 /* 34xx-only hwmod links (all ES revisions) */
3250 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3251         &omap3xxx_l3__iva,
3252         &omap34xx_l4_core__sr1,
3253         &omap34xx_l4_core__sr2,
3254         &omap3xxx_l4_core__mailbox,
3255         &omap3xxx_l4_core__hdq1w,
3256         NULL
3257 };
3258
3259 /* 36xx-only hwmod links (all ES revisions) */
3260 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3261         &omap3xxx_l3__iva,
3262         &omap36xx_l4_per__uart4,
3263         &omap3xxx_dss__l3,
3264         &omap3xxx_l4_core__dss,
3265         &omap36xx_l4_core__sr1,
3266         &omap36xx_l4_core__sr2,
3267         &omap3xxx_usbhsotg__l3,
3268         &omap3xxx_l4_core__usbhsotg,
3269         &omap3xxx_l4_core__mailbox,
3270         &omap3xxx_usb_host_hs__l3_main_2,
3271         &omap3xxx_l4_core__usb_host_hs,
3272         &omap3xxx_l4_core__usb_tll_hs,
3273         &omap3xxx_l4_core__es3plus_mmc1,
3274         &omap3xxx_l4_core__es3plus_mmc2,
3275         &omap3xxx_l4_core__hdq1w,
3276         NULL
3277 };
3278
3279 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3280         &omap3xxx_dss__l3,
3281         &omap3xxx_l4_core__dss,
3282         &am35xx_usbhsotg__l3,
3283         &am35xx_l4_core__usbhsotg,
3284         &am35xx_l4_core__uart4,
3285         &omap3xxx_usb_host_hs__l3_main_2,
3286         &omap3xxx_l4_core__usb_host_hs,
3287         &omap3xxx_l4_core__usb_tll_hs,
3288         &omap3xxx_l4_core__es3plus_mmc1,
3289         &omap3xxx_l4_core__es3plus_mmc2,
3290         NULL
3291 };
3292
3293 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3294         &omap3xxx_l4_core__dss_dispc,
3295         &omap3xxx_l4_core__dss_dsi1,
3296         &omap3xxx_l4_core__dss_rfbi,
3297         &omap3xxx_l4_core__dss_venc,
3298         NULL
3299 };
3300
3301 int __init omap3xxx_hwmod_init(void)
3302 {
3303         int r;
3304         struct omap_hwmod_ocp_if **h = NULL;
3305         unsigned int rev;
3306
3307         omap_hwmod_init();
3308
3309         /* Register hwmod links common to all OMAP3 */
3310         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3311         if (r < 0)
3312                 return r;
3313
3314         /* Register GP-only hwmod links. */
3315         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3316                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3317                 if (r < 0)
3318                         return r;
3319         }
3320
3321         rev = omap_rev();
3322
3323         /*
3324          * Register hwmod links common to individual OMAP3 families, all
3325          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3326          * All possible revisions should be included in this conditional.
3327          */
3328         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3329             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3330             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3331                 h = omap34xx_hwmod_ocp_ifs;
3332         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3333                 h = am35xx_hwmod_ocp_ifs;
3334         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3335                    rev == OMAP3630_REV_ES1_2) {
3336                 h = omap36xx_hwmod_ocp_ifs;
3337         } else {
3338                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3339                 return -EINVAL;
3340         };
3341
3342         r = omap_hwmod_register_links(h);
3343         if (r < 0)
3344                 return r;
3345
3346         /*
3347          * Register hwmod links specific to certain ES levels of a
3348          * particular family of silicon (e.g., 34xx ES1.0)
3349          */
3350         h = NULL;
3351         if (rev == OMAP3430_REV_ES1_0) {
3352                 h = omap3430es1_hwmod_ocp_ifs;
3353         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3354                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3355                    rev == OMAP3430_REV_ES3_1_2) {
3356                 h = omap3430es2plus_hwmod_ocp_ifs;
3357         };
3358
3359         if (h) {
3360                 r = omap_hwmod_register_links(h);
3361                 if (r < 0)
3362                         return r;
3363         }
3364
3365         h = NULL;
3366         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3367             rev == OMAP3430_REV_ES2_1) {
3368                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3369         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3370                    rev == OMAP3430_REV_ES3_1_2) {
3371                 h = omap3430_es3plus_hwmod_ocp_ifs;
3372         };
3373
3374         if (h)
3375                 r = omap_hwmod_register_links(h);
3376         if (r < 0)
3377                 return r;
3378
3379         /*
3380          * DSS code presumes that dss_core hwmod is handled first,
3381          * _before_ any other DSS related hwmods so register common
3382          * DSS hwmod links last to ensure that dss_core is already
3383          * registered.  Otherwise some change things may happen, for
3384          * ex. if dispc is handled before dss_core and DSS is enabled
3385          * in bootloader DISPC will be reset with outputs enabled
3386          * which sometimes leads to unrecoverable L3 error.  XXX The
3387          * long-term fix to this is to ensure hwmods are set up in
3388          * dependency order in the hwmod core code.
3389          */
3390         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3391
3392         return r;
3393 }