3 * HW data initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/omap.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/clock.h>
17 #include <asm/omap_gpio.h>
20 struct prcm_regs const **prcm =
21 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
22 struct dplls const **dplls_data =
23 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
24 struct vcores_data const **omap_vcores =
25 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
26 struct omap_sys_ctrl_regs const **ctrl =
27 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
30 * The M & N values in the following tables are created using the
32 * tools/omap/clocks_get_m_n.c
33 * Please use this tool for creating the table for any new frequency.
37 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
38 * OMAP4460 OPP_NOM frequency
40 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
41 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
42 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
43 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
44 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
45 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
46 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
47 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
51 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
52 * OMAP4430 OPP_TURBO frequency
53 * OMAP4470 OPP_NOM frequency
55 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
56 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
57 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
58 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
59 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
60 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
61 {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
62 {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
66 * dpll locked at 1200 MHz - MPU clk at 600 MHz
67 * OMAP4430 OPP_NOM frequency
69 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
70 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
71 {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
72 {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
73 {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
74 {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
75 {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
76 {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
79 /* OMAP4460 OPP_NOM frequency */
80 /* OMAP4470 OPP_NOM (Low Power) frequency */
81 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
82 {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
83 {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
84 {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
85 {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
86 {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
87 {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
88 {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
91 /* OMAP4430 ES1 OPP_NOM frequency */
92 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
93 {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
94 {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
95 {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
96 {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
97 {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
98 {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
99 {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
102 /* OMAP4430 ES2.X OPP_NOM frequency */
103 static const struct dpll_params
104 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
105 {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
106 {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
107 {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
108 {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
109 {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
110 {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
111 {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
114 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
115 {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
116 {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
117 {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
118 {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
119 {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
120 {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
121 {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
124 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
125 {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
126 {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
127 {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
128 {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
129 {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
130 {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
131 {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
134 /* ABE M & N values with sys_clk as source */
135 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
136 static const struct dpll_params
137 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
138 {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
139 {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
140 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
141 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
142 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
143 {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
144 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
147 /* ABE M & N values with 32K clock as source */
148 static const struct dpll_params abe_dpll_params_32k_196608khz = {
149 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
153 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
154 {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
155 {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
156 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
157 {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
158 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
159 {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
160 {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
163 struct dplls omap4430_dplls_es1 = {
164 .mpu = mpu_dpll_params_1200mhz,
165 .core = core_dpll_params_es1_1524mhz,
166 .per = per_dpll_params_1536mhz,
167 .iva = iva_dpll_params_1862mhz,
168 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
169 .abe = abe_dpll_params_sysclk_196608khz,
171 .abe = &abe_dpll_params_32k_196608khz,
173 .usb = usb_dpll_params_1920mhz,
177 struct dplls omap4430_dplls_es20 = {
178 .mpu = mpu_dpll_params_1200mhz,
179 .core = core_dpll_params_es2_1600mhz_ddr200mhz,
180 .per = per_dpll_params_1536mhz,
181 .iva = iva_dpll_params_1862mhz,
182 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
183 .abe = abe_dpll_params_sysclk_196608khz,
185 .abe = &abe_dpll_params_32k_196608khz,
187 .usb = usb_dpll_params_1920mhz,
191 struct dplls omap4430_dplls = {
192 .mpu = mpu_dpll_params_1200mhz,
193 .core = core_dpll_params_1600mhz,
194 .per = per_dpll_params_1536mhz,
195 .iva = iva_dpll_params_1862mhz,
196 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
197 .abe = abe_dpll_params_sysclk_196608khz,
199 .abe = &abe_dpll_params_32k_196608khz,
201 .usb = usb_dpll_params_1920mhz,
205 struct dplls omap4460_dplls = {
206 .mpu = mpu_dpll_params_1400mhz,
207 .core = core_dpll_params_1600mhz,
208 .per = per_dpll_params_1536mhz,
209 .iva = iva_dpll_params_1862mhz,
210 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
211 .abe = abe_dpll_params_sysclk_196608khz,
213 .abe = &abe_dpll_params_32k_196608khz,
215 .usb = usb_dpll_params_1920mhz,
219 struct dplls omap4470_dplls = {
220 .mpu = mpu_dpll_params_1600mhz,
221 .core = core_dpll_params_1600mhz,
222 .per = per_dpll_params_1536mhz,
223 .iva = iva_dpll_params_1862mhz,
224 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
225 .abe = abe_dpll_params_sysclk_196608khz,
227 .abe = &abe_dpll_params_32k_196608khz,
229 .usb = usb_dpll_params_1920mhz,
233 struct pmic_data twl6030_4430es1 = {
234 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
235 .step = 12660, /* 12.66 mV represented in uV */
236 /* The code starts at 1 not 0 */
238 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
239 .pmic_bus_init = sri2c_init,
240 .pmic_write = omap_vc_bypass_send_value,
243 /* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
244 struct pmic_data twl6030 = {
245 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
246 .step = 12660, /* 12.66 mV represented in uV */
247 /* The code starts at 1 not 0 */
249 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
250 .pmic_bus_init = sri2c_init,
251 .pmic_write = omap_vc_bypass_send_value,
254 struct pmic_data tps62361 = {
255 .base_offset = TPS62361_BASE_VOLT_MV,
256 .step = 10000, /* 10 mV represented in uV */
258 .gpio = TPS62361_VSEL0_GPIO,
260 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
261 .pmic_bus_init = sri2c_init,
262 .pmic_write = omap_vc_bypass_send_value,
265 struct vcores_data omap4430_volts_es1 = {
266 .mpu.value[OPP_NOM] = 1325,
267 .mpu.addr = SMPS_REG_ADDR_VCORE1,
268 .mpu.pmic = &twl6030_4430es1,
270 .core.value[OPP_NOM] = 1200,
271 .core.addr = SMPS_REG_ADDR_VCORE3,
272 .core.pmic = &twl6030_4430es1,
274 .mm.value[OPP_NOM] = 1200,
275 .mm.addr = SMPS_REG_ADDR_VCORE2,
276 .mm.pmic = &twl6030_4430es1,
279 struct vcores_data omap4430_volts = {
280 .mpu.value[OPP_NOM] = 1325,
281 .mpu.addr = SMPS_REG_ADDR_VCORE1,
282 .mpu.pmic = &twl6030,
284 .core.value[OPP_NOM] = 1200,
285 .core.addr = SMPS_REG_ADDR_VCORE3,
286 .core.pmic = &twl6030,
288 .mm.value[OPP_NOM] = 1200,
289 .mm.addr = SMPS_REG_ADDR_VCORE2,
293 struct vcores_data omap4460_volts = {
294 .mpu.value[OPP_NOM] = 1203,
295 .mpu.addr = TPS62361_REG_ADDR_SET1,
296 .mpu.pmic = &tps62361,
298 .core.value[OPP_NOM] = 1200,
299 .core.addr = SMPS_REG_ADDR_VCORE1,
300 .core.pmic = &twl6030,
302 .mm.value[OPP_NOM] = 1200,
303 .mm.addr = SMPS_REG_ADDR_VCORE2,
308 * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
309 * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
311 struct vcores_data omap4470_volts = {
312 .mpu.value[OPP_NOM] = 1202,
313 .mpu.addr = SMPS_REG_ADDR_SMPS1,
314 .mpu.pmic = &twl6030,
316 .core.value[OPP_NOM] = 1126,
317 .core.addr = SMPS_REG_ADDR_SMPS2,
318 .core.pmic = &twl6030,
320 .mm.value[OPP_NOM] = 1139,
321 .mm.addr = SMPS_REG_ADDR_SMPS5,
326 * Enable essential clock domains, modules and
327 * do some additional special settings needed
329 void enable_basic_clocks(void)
331 u32 const clk_domains_essential[] = {
332 (*prcm)->cm_l4per_clkstctrl,
333 (*prcm)->cm_l3init_clkstctrl,
334 (*prcm)->cm_memif_clkstctrl,
335 (*prcm)->cm_l4cfg_clkstctrl,
339 u32 const clk_modules_hw_auto_essential[] = {
340 (*prcm)->cm_l3_gpmc_clkctrl,
341 (*prcm)->cm_memif_emif_1_clkctrl,
342 (*prcm)->cm_memif_emif_2_clkctrl,
343 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
344 (*prcm)->cm_wkup_gpio1_clkctrl,
345 (*prcm)->cm_l4per_gpio2_clkctrl,
346 (*prcm)->cm_l4per_gpio3_clkctrl,
347 (*prcm)->cm_l4per_gpio4_clkctrl,
348 (*prcm)->cm_l4per_gpio5_clkctrl,
349 (*prcm)->cm_l4per_gpio6_clkctrl,
353 u32 const clk_modules_explicit_en_essential[] = {
354 (*prcm)->cm_wkup_gptimer1_clkctrl,
355 (*prcm)->cm_l3init_hsmmc1_clkctrl,
356 (*prcm)->cm_l3init_hsmmc2_clkctrl,
357 (*prcm)->cm_l4per_gptimer2_clkctrl,
358 (*prcm)->cm_wkup_wdtimer2_clkctrl,
359 (*prcm)->cm_l4per_uart3_clkctrl,
360 (*prcm)->cm_l4per_i2c1_clkctrl,
361 (*prcm)->cm_l4per_i2c2_clkctrl,
362 (*prcm)->cm_l4per_i2c3_clkctrl,
363 (*prcm)->cm_l4per_i2c4_clkctrl,
367 /* Enable optional additional functional clock for GPIO4 */
368 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
369 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
371 /* Enable 96 MHz clock for MMC1 & MMC2 */
372 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
373 HSMMC_CLKCTRL_CLKSEL_MASK);
374 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
375 HSMMC_CLKCTRL_CLKSEL_MASK);
377 /* Select 32KHz clock as the source of GPTIMER1 */
378 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
379 GPTIMER1_CLKCTRL_CLKSEL_MASK);
381 /* Enable optional 48M functional clock for USB PHY */
382 setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
383 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
385 /* Enable 32 KHz clock for USB PHY */
386 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
387 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
389 do_enable_clocks(clk_domains_essential,
390 clk_modules_hw_auto_essential,
391 clk_modules_explicit_en_essential,
395 void enable_basic_uboot_clocks(void)
397 u32 const clk_domains_essential[] = {
401 u32 const clk_modules_hw_auto_essential[] = {
402 (*prcm)->cm_l3init_hsusbotg_clkctrl,
403 (*prcm)->cm_l3init_usbphy_clkctrl,
404 (*prcm)->cm_clksel_usb_60mhz,
405 (*prcm)->cm_l3init_hsusbtll_clkctrl,
409 u32 const clk_modules_explicit_en_essential[] = {
410 (*prcm)->cm_l4per_mcspi1_clkctrl,
411 (*prcm)->cm_l3init_hsusbhost_clkctrl,
415 do_enable_clocks(clk_domains_essential,
416 clk_modules_hw_auto_essential,
417 clk_modules_explicit_en_essential,
421 void hw_data_init(void)
423 u32 omap_rev = omap_revision();
425 (*prcm) = &omap4_prcm;
430 *dplls_data = &omap4430_dplls_es1;
431 *omap_vcores = &omap4430_volts_es1;
435 *dplls_data = &omap4430_dplls_es20;
436 *omap_vcores = &omap4430_volts;
442 *dplls_data = &omap4430_dplls;
443 *omap_vcores = &omap4430_volts;
448 *dplls_data = &omap4460_dplls;
449 *omap_vcores = &omap4460_volts;
453 *dplls_data = &omap4470_dplls;
454 *omap_vcores = &omap4470_volts;
458 printf("\n INVALID OMAP REVISION ");