1 // SPDX-License-Identifier: GPL-2.0+
4 * Texas Instruments, <www.ti.com>
7 * Manikandan Pillai <mani.pillai@ti.com>
9 * Derived from Beagle Board and OMAP3 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/clocks_omap3.h>
18 #include <asm/arch/mem.h>
19 #include <asm/arch/sys_proto.h>
22 /******************************************************************************
23 * get_sys_clk_speed() - determine reference oscillator speed
24 * based on known 32kHz clock and gptimer.
25 *****************************************************************************/
26 static u32 get_osc_clk_speed(void)
28 u32 start, cstart, cend, cdiff, cdiv, val;
29 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
30 struct prm *prm_base = (struct prm *)PRM_BASE;
31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
32 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
34 val = readl(&prm_base->clksrc_ctrl);
36 if (val & SYSCLKDIV_2)
42 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
44 /* select sys_clk for GPT1 */
45 writel(val, &prcm_base->clksel_wkup);
47 /* Enable I and F Clocks for GPT1 */
48 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
49 writel(val, &prcm_base->iclken_wkup);
51 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
52 writel(val, &prcm_base->fclken_wkup);
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
57 /* enable 32kHz source, determine sys_clk via gauging */
59 /* start time in 20 cycles */
60 start = 20 + readl(&s32k_base->s32k_cr);
62 /* dead loop till start time */
63 while (readl(&s32k_base->s32k_cr) < start);
65 /* get start sys_clk count */
66 cstart = readl(&gpt1_base->tcrr);
68 /* wait for 40 cycles */
69 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
71 cdiff = cend - cstart; /* get elapsed ticks */
74 /* based on number of ticks assign speed */
77 else if (cdiff > 15200)
79 else if (cdiff > 13000)
81 else if (cdiff > 9000)
83 else if (cdiff > 7600)
89 /******************************************************************************
90 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
91 * input oscillator clock frequency.
92 *****************************************************************************/
93 static void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
115 * OMAP34XX/35XX specific functions
118 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
120 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
121 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
122 void (*f_lock_pll) (u32, u32, u32, u32);
123 int xip_safe, p0, p1, p2, p3;
125 xip_safe = is_running_in_sram();
127 /* Moving to the right sysclk and ES rev base */
128 ptr = ptr + (3 * clk_index) + sil_index;
134 clrsetbits_le32(&prcm_base->clken_pll,
135 0x00000007, PLL_FAST_RELOCK_BYPASS);
136 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
140 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
141 * work. write another value and then default value.
144 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
145 clrsetbits_le32(&prcm_base->clksel1_emu,
146 0x001F0000, (CORE_M3X2 + 1) << 16) ;
147 clrsetbits_le32(&prcm_base->clksel1_emu,
148 0x001F0000, CORE_M3X2 << 16);
150 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
151 clrsetbits_le32(&prcm_base->clksel1_pll,
152 0xF8000000, ptr->m2 << 27);
154 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
155 clrsetbits_le32(&prcm_base->clksel1_pll,
156 0x07FF0000, ptr->m << 16);
158 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
159 clrsetbits_le32(&prcm_base->clksel1_pll,
160 0x00007F00, ptr->n << 8);
162 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
163 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
166 clrsetbits_le32(&prcm_base->clksel_core,
167 0x00000F00, CORE_SSI_DIV << 8);
169 clrsetbits_le32(&prcm_base->clksel_core,
170 0x00000030, CORE_FUSB_DIV << 4);
172 clrsetbits_le32(&prcm_base->clksel_core,
173 0x0000000C, CORE_L4_DIV << 2);
175 clrsetbits_le32(&prcm_base->clksel_core,
176 0x00000003, CORE_L3_DIV);
178 clrsetbits_le32(&prcm_base->clksel_gfx,
179 0x00000007, GFX_DIV);
181 clrsetbits_le32(&prcm_base->clksel_wkup,
182 0x00000006, WKUP_RSM << 1);
183 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
184 clrsetbits_le32(&prcm_base->clken_pll,
185 0x000000F0, ptr->fsel << 4);
187 clrsetbits_le32(&prcm_base->clken_pll,
188 0x00000007, PLL_LOCK);
190 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
192 } else if (is_running_in_flash()) {
194 * if running from flash, jump to small relocated code
197 f_lock_pll = (void *) (SRAM_CLK_CODE);
199 p0 = readl(&prcm_base->clken_pll);
200 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
201 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
202 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
204 p1 = readl(&prcm_base->clksel1_pll);
205 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
206 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
207 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
208 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
209 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
210 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
211 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
212 clrbits_le32(&p1, 0x00000040);
214 p2 = readl(&prcm_base->clksel_core);
216 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
218 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
220 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
222 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
224 p3 = (u32)&prcm_base->idlest_ckgen;
226 (*f_lock_pll) (p0, p1, p2, p3);
230 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
232 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
233 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
235 /* Moving it to the right sysclk base */
236 ptr = ptr + clk_index;
238 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
239 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
240 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
243 * Errata 1.50 Workaround for OMAP3 ES1.0 only
244 * If using default divisors, write default divisor + 1
245 * and then the actual divisor value
248 clrsetbits_le32(&prcm_base->clksel1_emu,
249 0x1F000000, (PER_M6X2 + 1) << 24);
250 clrsetbits_le32(&prcm_base->clksel1_emu,
251 0x1F000000, PER_M6X2 << 24);
253 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
254 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
256 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
257 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
259 clrsetbits_le32(&prcm_base->clksel_dss,
260 0x00001F00, (PER_M3X2 + 1) << 8);
261 clrsetbits_le32(&prcm_base->clksel_dss,
262 0x00001F00, PER_M3X2 << 8);
263 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
264 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
265 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
268 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
269 clrsetbits_le32(&prcm_base->clksel2_pll,
270 0x0007FF00, ptr->m << 8);
272 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
273 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
275 /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
276 clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
278 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
279 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
280 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
283 static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
285 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
286 dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
288 /* Moving it to the right sysclk base */
289 ptr = ptr + clk_index;
291 /* PER2 DPLL (DPLL5) */
292 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
293 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
294 /* set M2 (usbtll_fck) */
295 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
296 /* set m (11-bit multiplier) */
297 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
298 /* set n (7-bit divider)*/
299 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
301 clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
303 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
304 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
307 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
309 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
310 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
312 /* Moving to the right sysclk and ES rev base */
313 ptr = ptr + (3 * clk_index) + sil_index;
315 /* MPU DPLL (unlocked already) */
317 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
318 clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
319 0x0000001F, ptr->m2);
321 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
322 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
323 0x0007FF00, ptr->m << 8);
325 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
326 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
329 /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
330 clrsetbits_le32(&prcm_base->clken_pll_mpu,
331 0x000000F0, ptr->fsel << 4);
334 static void iva_init_34xx(u32 sil_index, u32 clk_index)
336 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
337 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
339 /* Moving to the right sysclk and ES rev base */
340 ptr = ptr + (3 * clk_index) + sil_index;
343 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
344 clrsetbits_le32(&prcm_base->clken_pll_iva2,
345 0x00000007, PLL_STOP);
346 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
348 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
349 clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
350 0x0000001F, ptr->m2);
352 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
353 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
354 0x0007FF00, ptr->m << 8);
356 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
357 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
360 /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
361 clrsetbits_le32(&prcm_base->clken_pll_iva2,
362 0x000000F0, ptr->fsel << 4);
364 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
365 clrsetbits_le32(&prcm_base->clken_pll_iva2,
366 0x00000007, PLL_LOCK);
368 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
372 * OMAP3630 specific functions
375 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
377 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
378 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
379 void (*f_lock_pll) (u32, u32, u32, u32);
380 int xip_safe, p0, p1, p2, p3;
382 xip_safe = is_running_in_sram();
384 /* Moving it to the right sysclk base */
390 /* Select relock bypass: CM_CLKEN_PLL[0:2] */
391 clrsetbits_le32(&prcm_base->clken_pll,
392 0x00000007, PLL_FAST_RELOCK_BYPASS);
393 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
396 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
397 clrsetbits_le32(&prcm_base->clksel1_emu,
398 0x001F0000, CORE_M3X2 << 16);
400 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
401 clrsetbits_le32(&prcm_base->clksel1_pll,
402 0xF8000000, ptr->m2 << 27);
404 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
405 clrsetbits_le32(&prcm_base->clksel1_pll,
406 0x07FF0000, ptr->m << 16);
408 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
409 clrsetbits_le32(&prcm_base->clksel1_pll,
410 0x00007F00, ptr->n << 8);
412 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
413 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
416 clrsetbits_le32(&prcm_base->clksel_core,
417 0x00000F00, CORE_SSI_DIV << 8);
419 clrsetbits_le32(&prcm_base->clksel_core,
420 0x00000030, CORE_FUSB_DIV << 4);
422 clrsetbits_le32(&prcm_base->clksel_core,
423 0x0000000C, CORE_L4_DIV << 2);
425 clrsetbits_le32(&prcm_base->clksel_core,
426 0x00000003, CORE_L3_DIV);
428 clrsetbits_le32(&prcm_base->clksel_gfx,
429 0x00000007, GFX_DIV_36X);
431 clrsetbits_le32(&prcm_base->clksel_wkup,
432 0x00000006, WKUP_RSM << 1);
433 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
434 clrsetbits_le32(&prcm_base->clken_pll,
435 0x000000F0, ptr->fsel << 4);
437 clrsetbits_le32(&prcm_base->clken_pll,
438 0x00000007, PLL_LOCK);
440 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
442 } else if (is_running_in_flash()) {
444 * if running from flash, jump to small relocated code
447 f_lock_pll = (void *) (SRAM_CLK_CODE);
449 p0 = readl(&prcm_base->clken_pll);
450 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
451 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
452 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
454 p1 = readl(&prcm_base->clksel1_pll);
455 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
456 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
457 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
458 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
459 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
460 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
461 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
462 clrbits_le32(&p1, 0x00000040);
464 p2 = readl(&prcm_base->clksel_core);
466 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
468 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
470 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
472 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
474 p3 = (u32)&prcm_base->idlest_ckgen;
476 (*f_lock_pll) (p0, p1, p2, p3);
480 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
482 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
483 struct dpll_per_36x_param *ptr;
485 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
487 /* Moving it to the right sysclk base */
490 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
491 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
492 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
494 /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
495 clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
497 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
498 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
500 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
501 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
503 /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
504 clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
506 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
507 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
509 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
510 clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
512 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
513 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
515 /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
516 clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
518 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
519 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
520 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
523 static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
525 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
526 dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
528 /* Moving it to the right sysclk base */
529 ptr = ptr + clk_index;
531 /* PER2 DPLL (DPLL5) */
532 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
533 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
534 /* set M2 (usbtll_fck) */
535 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
536 /* set m (11-bit multiplier) */
537 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
538 /* set n (7-bit divider)*/
539 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
541 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
542 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
545 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
547 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
548 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
550 /* Moving to the right sysclk */
553 /* MPU DPLL (unlocked already */
555 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
556 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
558 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
559 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
561 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
562 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
565 static void iva_init_36xx(u32 sil_index, u32 clk_index)
567 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
568 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
570 /* Moving to the right sysclk */
574 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
575 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
576 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
578 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
579 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
581 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
582 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
584 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
585 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
587 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
588 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
590 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
593 /******************************************************************************
594 * prcm_init() - inits clocks for PRCM as defined in clocks.h
595 * called from SRAM, or Flash (using temp SRAM stack).
596 *****************************************************************************/
599 u32 osc_clk = 0, sys_clkin_sel;
600 u32 clk_index, sil_index = 0;
601 struct prm *prm_base = (struct prm *)PRM_BASE;
602 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
605 * Gauge the input clock speed and find out the sys_clkin_sel
606 * value corresponding to the input clock.
608 osc_clk = get_osc_clk_speed();
609 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
611 /* set input crystal speed */
612 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
614 /* If the input clock is greater than 19.2M always divide/2 */
615 if (sys_clkin_sel > 2) {
616 /* input clock divider */
617 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
618 clk_index = sys_clkin_sel / 2;
620 /* input clock divider */
621 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
622 clk_index = sys_clkin_sel;
625 if (get_cpu_family() == CPU_OMAP36XX) {
627 * In warm reset conditions on OMAP36xx/AM/DM37xx
628 * the rom code incorrectly sets the DPLL4 clock
629 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
630 * the AM/DM37x TRM explains that the /6.5 divider
631 * is used only when the input clock is 13MHz.
633 * If the part is in this cpu family *and* the input
634 * clock *is not* 13 MHz, then reset the DPLL4 clock
635 * input divider to /1 as it should never set to /6.5
638 if (sys_clkin_sel != 1) { /* 13 MHz */
639 /* Bit 8: DPLL4_CLKINP_DIV */
640 clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
643 /* Unlock MPU DPLL (slows things down, and needed later) */
644 clrsetbits_le32(&prcm_base->clken_pll_mpu,
645 0x00000007, PLL_LOW_POWER_BYPASS);
646 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
649 dpll3_init_36xx(0, clk_index);
650 dpll4_init_36xx(0, clk_index);
651 dpll5_init_36xx(0, clk_index);
652 iva_init_36xx(0, clk_index);
653 mpu_init_36xx(0, clk_index);
655 /* Lock MPU DPLL to set frequency */
656 clrsetbits_le32(&prcm_base->clken_pll_mpu,
657 0x00000007, PLL_LOCK);
658 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
662 * The DPLL tables are defined according to sysclk value and
663 * silicon revision. The clk_index value will be used to get
664 * the values for that input sysclk from the DPLL param table
665 * and sil_index will get the values for that SysClk for the
666 * appropriate silicon rev.
668 if (((get_cpu_family() == CPU_OMAP34XX)
669 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
670 (get_cpu_family() == CPU_AM35XX))
673 /* Unlock MPU DPLL (slows things down, and needed later) */
674 clrsetbits_le32(&prcm_base->clken_pll_mpu,
675 0x00000007, PLL_LOW_POWER_BYPASS);
676 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
679 dpll3_init_34xx(sil_index, clk_index);
680 dpll4_init_34xx(sil_index, clk_index);
681 dpll5_init_34xx(sil_index, clk_index);
682 if (get_cpu_family() != CPU_AM35XX)
683 iva_init_34xx(sil_index, clk_index);
685 mpu_init_34xx(sil_index, clk_index);
687 /* Lock MPU DPLL to set frequency */
688 clrsetbits_le32(&prcm_base->clken_pll_mpu,
689 0x00000007, PLL_LOCK);
690 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
694 /* Set up GPTimers to sys_clk source only */
695 setbits_le32(&prcm_base->clksel_per, 0x000000FF);
696 setbits_le32(&prcm_base->clksel_wkup, 1);
702 * Enable usb ehci uhh, tll clocks
704 void ehci_clocks_enable(void)
706 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
708 /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
709 setbits_le32(&prcm_base->iclken_usbhost, 1);
711 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
712 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
714 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
715 /* Enable USBTTL_ICLK */
716 setbits_le32(&prcm_base->iclken3_core, 0x00000004);
717 /* Enable USBTTL_FCLK */
718 setbits_le32(&prcm_base->fclken3_core, 0x00000004);
721 /******************************************************************************
722 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
723 *****************************************************************************/
724 void per_clocks_enable(void)
726 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
728 /* Enable GP2 timer. */
729 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
730 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
731 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
733 /* Enable GP9 timer. */
734 setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
735 setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
736 setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
738 #ifdef CONFIG_SYS_NS16550
739 /* Enable UART1 clocks */
740 setbits_le32(&prcm_base->fclken1_core, 0x00002000);
741 setbits_le32(&prcm_base->iclken1_core, 0x00002000);
743 /* Enable UART2 clocks */
744 setbits_le32(&prcm_base->fclken1_core, 0x00004000);
745 setbits_le32(&prcm_base->iclken1_core, 0x00004000);
748 setbits_le32(&prcm_base->fclken_per, 0x00000800);
749 setbits_le32(&prcm_base->iclken_per, 0x00000800);
752 #if defined(CONFIG_OMAP3_GPIO_2)
753 setbits_le32(&prcm_base->fclken_per, 0x00002000);
754 setbits_le32(&prcm_base->iclken_per, 0x00002000);
756 #if defined(CONFIG_OMAP3_GPIO_3)
757 setbits_le32(&prcm_base->fclken_per, 0x00004000);
758 setbits_le32(&prcm_base->iclken_per, 0x00004000);
760 #if defined(CONFIG_OMAP3_GPIO_4)
761 setbits_le32(&prcm_base->fclken_per, 0x00008000);
762 setbits_le32(&prcm_base->iclken_per, 0x00008000);
764 #if defined(CONFIG_OMAP3_GPIO_5)
765 setbits_le32(&prcm_base->fclken_per, 0x00010000);
766 setbits_le32(&prcm_base->iclken_per, 0x00010000);
768 #if defined(CONFIG_OMAP3_GPIO_6)
769 setbits_le32(&prcm_base->fclken_per, 0x00020000);
770 setbits_le32(&prcm_base->iclken_per, 0x00020000);
773 #ifdef CONFIG_SYS_I2C_OMAP24XX
774 /* Turn on all 3 I2C clocks */
775 setbits_le32(&prcm_base->fclken1_core, 0x00038000);
776 setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
778 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
779 setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
781 if (get_cpu_family() != CPU_AM35XX)
782 out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
784 out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
785 out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
786 out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
787 out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
788 out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
789 out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
790 out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
791 if (get_cpu_family() != CPU_AM35XX) {
792 out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
793 out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);