arch/arm/mach-omap2/mem-common.c

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *     Mansoor Ahamed <mansoor.ahamed@ti.com>
   7  *
   8  * Initial Code from:
   9  *     Manikandan Pillai <mani.pillai@ti.com>
  10  *     Richard Woodruff <r-woodruff2@ti.com>
  11  *     Syed Mohammed Khasim <khasim@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/mem.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <command.h>
  22 #include <linux/mtd/omap_gpmc.h>
  23 #include <jffs2/load_kernel.h>
  24
  25 const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
  26
  27 #if defined(CONFIG_NOR)
  28 char gpmc_cs0_flash = MTD_DEV_TYPE_NOR;
  29 #elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
  30 char gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  31 #elif defined(CONFIG_CMD_ONENAND)
  32 char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  33 #else
  34 char gpmc_cs0_flash = -1;
  35 #endif
  36
  37 #if defined(CONFIG_OMAP34XX)
  38 /********************************************************
  39  *  mem_ok() - test used to see if timings are correct
  40  *             for a part. Helps in guessing which part
  41  *             we are currently using.
  42  *******************************************************/
  43 u32 mem_ok(u32 cs)
  44 {
  45         u32 val1, val2, addr;
  46         u32 pattern = 0x12345678;
  47
  48         addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  49
  50         writel(0x0, addr + 0x400);      /* clear pos A */
  51         writel(pattern, addr);          /* pattern to pos B */
  52         writel(0x0, addr + 4);          /* remove pattern off the bus */
  53         val1 = readl(addr + 0x400);     /* get pos A value */
  54         val2 = readl(addr);             /* get val2 */
  55         writel(0x0, addr + 0x400);      /* clear pos A */
  56
  57         if ((val1 != 0) || (val2 != pattern))   /* see if pos A val changed */
  58                 return 0;
  59         else
  60                 return 1;
  61 }
  62 #endif
  63
  64 void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
  65                                 u32 base, u32 size)
  66 {
  67         writel(0, &cs->config7);
  68         sdelay(1000);
  69         /* Delay for settling */
  70         writel(gpmc_config[0], &cs->config1);
  71         writel(gpmc_config[1], &cs->config2);
  72         writel(gpmc_config[2], &cs->config3);
  73         writel(gpmc_config[3], &cs->config4);
  74         writel(gpmc_config[4], &cs->config5);
  75         writel(gpmc_config[5], &cs->config6);
  76         /* Enable the config */
  77         writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  78                 (1 << 6)), &cs->config7);
  79         sdelay(2000);
  80 }
  81
  82 void set_gpmc_cs0(int flash_type)
  83 {
  84         const u32 *gpmc_regs;
  85         u32 base, size;
  86 #if defined(CONFIG_NOR)
  87         const u32 gpmc_regs_nor[GPMC_MAX_REG] = {
  88                 STNOR_GPMC_CONFIG1,
  89                 STNOR_GPMC_CONFIG2,
  90                 STNOR_GPMC_CONFIG3,
  91                 STNOR_GPMC_CONFIG4,
  92                 STNOR_GPMC_CONFIG5,
  93                 STNOR_GPMC_CONFIG6,
  94                 STNOR_GPMC_CONFIG7
  95         };
  96 #endif
  97 #if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
  98         const u32 gpmc_regs_nand[GPMC_MAX_REG] = {
  99                 M_NAND_GPMC_CONFIG1,
 100                 M_NAND_GPMC_CONFIG2,
 101                 M_NAND_GPMC_CONFIG3,
 102                 M_NAND_GPMC_CONFIG4,
 103                 M_NAND_GPMC_CONFIG5,
 104                 M_NAND_GPMC_CONFIG6,
 105                 0
 106         };
 107 #endif
 108 #if defined(CONFIG_CMD_ONENAND)
 109         const u32 gpmc_regs_onenand[GPMC_MAX_REG] = {
 110                 ONENAND_GPMC_CONFIG1,
 111                 ONENAND_GPMC_CONFIG2,
 112                 ONENAND_GPMC_CONFIG3,
 113                 ONENAND_GPMC_CONFIG4,
 114                 ONENAND_GPMC_CONFIG5,
 115                 ONENAND_GPMC_CONFIG6,
 116                 0
 117         };
 118 #endif
 119
 120         switch (flash_type) {
 121 #if defined(CONFIG_NOR)
 122         case MTD_DEV_TYPE_NOR:
 123                 gpmc_regs = gpmc_regs_nor;
 124                 base = CONFIG_SYS_FLASH_BASE;
 125                 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
 126                       ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
 127                       ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
 128                       ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
 129                                                               GPMC_SIZE_16M)));
 130                 break;
 131 #endif
 132 #if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
 133         case MTD_DEV_TYPE_NAND:
 134                 gpmc_regs = gpmc_regs_nand;
 135                 base = CONFIG_SYS_NAND_BASE;
 136                 size = GPMC_SIZE_16M;
 137                 break;
 138 #endif
 139 #if defined(CONFIG_CMD_ONENAND)
 140         case MTD_DEV_TYPE_ONENAND:
 141                 gpmc_regs = gpmc_regs_onenand;
 142                 base = CONFIG_SYS_ONENAND_BASE;
 143                 size = GPMC_SIZE_128M;
 144                 break;
 145 #endif
 146         default:
 147                 /* disable the GPMC0 config set by ROM code */
 148                 writel(0, &gpmc_cfg->cs[0].config7);
 149                 sdelay(1000);
 150                 return;
 151         }
 152
 153         /* enable chip-select specific configurations */
 154         enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 155 }
 156
 157 /*****************************************************
 158  * gpmc_init(): init gpmc bus
 159  * Init GPMC for x16, MuxMode (SDRAM in x32).
 160  * This code can only be executed from SRAM or SDRAM.
 161  *****************************************************/
 162 void gpmc_init(void)
 163 {
 164         /* global settings */
 165         writel(0x00000008, &gpmc_cfg->sysconfig);
 166         writel(0x00000000, &gpmc_cfg->irqstatus);
 167         writel(0x00000000, &gpmc_cfg->irqenable);
 168         /* disable timeout, set a safe reset value */
 169         writel(0x00001ff0, &gpmc_cfg->timeout_control);
 170         writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ?
 171                 0x00000200 : 0x00000012, &gpmc_cfg->config);
 172
 173         set_gpmc_cs0(gpmc_cs0_flash);
 174 }