2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/omap.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/spl.h>
17 #include <linux/linkage.h>
22 ENTRY(save_boot_params)
23 ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
25 b save_boot_params_ret
26 ENDPROC(save_boot_params)
28 #if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
29 ENTRY(switch_to_hypervisor)
32 * Switch to hypervisor mode
36 adr r1, restore_from_hyp
42 MRC p15, 4, R0, c1, c0, 0
43 ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
45 MCR p15, 4, R0, c1, c0, 0
46 b switch_to_hypervisor_ret
49 ENDPROC(switch_to_hypervisor)
54 push {r4-r12, lr} @ save registers - ROM code may pollute
61 smc 0 @ SMC #0 to enter monitor mode
62 @ call ROM Code API for the service requested
67 push {r4-r12, lr} @ save registers - ROM code may pollute
69 mov r6, #0xFF @ Indicate new Task call
70 mov r12, #0x00 @ Secure Service ID in R12
74 smc 0 @ SMC #0 to enter monitor mode
76 b omap_smc_sec_end @ exit at end of the service execution
79 @ In case of IRQ happening in Secure, then ARM will branch here.
80 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
86 smc 0 @ SMC #0 to enter monitor mode