1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Board specific setup info
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
13 #include <asm/arch/omap.h>
14 #include <asm/omap_common.h>
15 #include <asm/arch/spl.h>
16 #include <linux/linkage.h>
21 ENTRY(save_boot_params)
22 ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
24 b save_boot_params_ret
25 ENDPROC(save_boot_params)
27 #if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
28 ENTRY(switch_to_hypervisor)
31 * Switch to hypervisor mode
35 adr r1, restore_from_hyp
41 MRC p15, 4, R0, c1, c0, 0
42 ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
44 MCR p15, 4, R0, c1, c0, 0
45 b switch_to_hypervisor_ret
48 ENDPROC(switch_to_hypervisor)
53 push {r4-r12, lr} @ save registers - ROM code may pollute
60 smc 0 @ SMC #0 to enter monitor mode
61 @ call ROM Code API for the service requested
66 push {r4-r12, lr} @ save registers - ROM code may pollute
68 mov r6, #0xFF @ Indicate new Task call
69 mov r12, #0x00 @ Secure Service ID in R12
73 smc 0 @ SMC #0 to enter monitor mode
75 b omap_smc_sec_end @ exit at end of the service execution
78 @ In case of IRQ happening in Secure, then ARM will branch here.
79 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
85 smc 0 @ SMC #0 to enter monitor mode